Semiconductor storage device and semiconductor storage device unit

Abstract

To provide a semiconductor storage device capable of improving heat dissipation and a semiconductor storage device unit.SOLUTION: A semiconductor storage device of one embodiment comprises a first substrate, a mold resin, a memory chip, and a controller. The memory chip is arranged between a first surface of the first substrate and the mold resin. The controller is arranged between the first surface and the mold resin, and controls the memory chip. The first substrate includes a surface layer part where a second surface of the substrate is formed. The surface layer part includes a conductive pattern including a plurality of terminals exposed to the outside, and an insulation layer covering a part of the conductive pattern. The surface layer part also includes a first non-planar part including at least a plurality of dents or a plurality of projections and alternately arranged with a first recess and a first salient in a region outside the plurality of terminals in the surface layer part.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] FIELD OF THE PRESENT EMBODIMENTS The present invention relates to a semiconductor memory device and a semiconductor memory device unit. [Background technology]

[0002] 2. Description of the Related Art A semiconductor memory device is known that has a substrate, a memory chip mounted on a first surface of the substrate, and a plurality of terminals provided on a second surface of the substrate. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2023-31558 A Summary of the Invention [Problem to be solved by the invention]

[0004] One embodiment provides a semiconductor memory device and a semiconductor memory device unit that can improve heat dissipation. [Means for solving the problem]

[0005] A semiconductor memory device according to one embodiment includes a first substrate, a molded resin, a memory chip, and a controller. The first substrate has a first surface and a second surface located on the opposite side to the first surface. The molded resin covers the first surface when viewed from a thickness direction of the first substrate. The memory chip is disposed between the first surface and the molded resin. The controller is disposed between the first surface and the molded resin and controls the memory chip. The first substrate has a surface layer portion forming the second surface. The surface layer portion includes a conductive pattern including a plurality of terminals exposed to the outside, and an insulating layer covering a portion of the conductive pattern. The surface layer portion has a first non-flat portion having at least one of a plurality of recesses and a plurality of protrusions in an area outside the plurality of terminals in the surface layer portion, in which first recesses and first protrusions are arranged alternately. [Brief description of the drawings]

[0006] [Figure 1] FIG. 2 is a diagram showing the configuration of a semiconductor memory device unit according to the first embodiment. [Diagram 2] 1 is a cross-sectional view showing a configuration of a semiconductor memory device according to a first embodiment. [Diagram 3] FIG. 2 is a diagram for explaining a surface layer portion of a substrate according to the first embodiment. [Figure 4] FIG. 2 is a cross-sectional view illustrating the thermally conductive sheet according to the first embodiment. [Diagram 5] FIG. 2 is a plan view showing a substrate of the host device according to the first embodiment. [Figure 6] FIG. 2 is a perspective view showing a first state when the semiconductor memory device according to the first embodiment is attached. [Figure 7] FIG. 13 is a perspective view showing a second state when the semiconductor memory device according to the first embodiment is attached. [Figure 8] FIG. 11 is a perspective view showing a third state when the semiconductor memory device according to the first embodiment is attached. [Figure 9] 3A to 3C are cross-sectional views showing a method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 10] FIG. 13 is a diagram showing a semiconductor memory device according to a first modified example of the first embodiment. [Figure 11] FIG. 13 is a diagram showing a semiconductor memory device according to a second modification of the first embodiment. [Figure 12] 10A to 10C are cross-sectional views showing a method for manufacturing a semiconductor memory device according to a second modification of the first embodiment. [Figure 13] FIG. 13 is a diagram showing a semiconductor memory device according to a third modified example of the first embodiment. [Figure 14] FIG. 13 is a diagram showing a semiconductor memory device according to a second embodiment. [Figure 15] FIG. 13 is a diagram showing a semiconductor memory device according to a first modified example of the second embodiment. [Figure 16] FIG. 13 is a diagram showing a semiconductor memory device according to a second modification of the second embodiment. [Figure 17] FIG. 13 is a diagram showing a semiconductor memory device according to a third embodiment. [Figure 18] FIG. 13 is a diagram showing a semiconductor memory device according to a first modified example of the third embodiment. [Figure 19] FIG. 13 is a diagram showing a semiconductor memory device according to a second modification of the third embodiment. [Figure 20] FIG. 13 is a diagram showing a semiconductor memory device according to a fourth embodiment. [Figure 21] FIG. 13 is a diagram showing a semiconductor memory device according to a first modified example of the fourth embodiment. [Figure 22] FIG. 13 is a diagram showing a semiconductor memory device according to a second modification of the fourth embodiment. [Diagram 23] FIG. 13 is a diagram showing a semiconductor memory device according to a modification of the first to fourth embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, the semiconductor memory device and the semiconductor memory device unit of the embodiment will be described with reference to the drawings. In the following description, the same reference numerals are given to configurations having the same or similar functions. Then, duplicated descriptions of those configurations may be omitted. In this application, the terms are defined as follows. "Parallel", "orthogonal", or "same" may include the cases of "substantially parallel", "substantially orthogonal", or "substantially the same", respectively. "Connection" is not limited to mechanical connection, but may include electrical connection. That is, "connection" is not limited to the case where two elements to be connected are directly connected, but may include the case where two elements to be connected are connected with another element interposed therebetween. Also, "connection" is not limited to the case where they are joined, but may include the case where they are merely in contact.

[0008] The X direction, Y direction, and Z direction are defined as follows. The X direction and Y direction are directions along a first surface 11a (see FIG. 2) of the substrate 11 described later. The X direction is a direction from a first region A1 to a second region A2 (see FIG. 1) described later. The Y direction is a direction intersecting (e.g., perpendicular to) the X direction. The Z direction is a direction intersecting (e.g., perpendicular to) the X direction and the Y direction. The Z direction is, for example, the thickness direction of the substrate 11.

[0009] In addition, in each figure described below, the content of the part accompanied by the letters "bb cross section" indicates the cross section along the bb line shown in (a) of the same figure, the content of the part accompanied by the letters "cc cross section" indicates the cross section along the cc line shown in (a) of the same figure, and the content of the part accompanied by the letters "dd cross section" indicates the cross section along the dd line shown in (a) of the same figure.

[0010] (First embodiment) <1. Configuration of Semiconductor Memory Unit> FIG. 1 is a diagram showing the configuration of a semiconductor memory device unit 1 of the first embodiment. (a) in FIG. 1 shows one surface of the semiconductor memory device unit 1. (b) in FIG. 1 shows one side of the semiconductor memory device unit 1. (c) in FIG. 1 shows the other surface of the semiconductor memory device unit 1. The semiconductor memory device unit 1 includes, for example, a semiconductor memory device 10 and a thermally conductive sheet 70.

[0011] The semiconductor memory device 10 is, for example, a semiconductor memory device such as an SSD (Solid State Drive). The semiconductor memory device 10 has, for example, a SiP (System in Package) structure. The semiconductor memory device 10 is attached to a host device and used as a storage device for the host device. The host device may be, but is not limited to, a personal computer, a mobile device, a video recorder, or an in-vehicle device. In the following, an example in which the semiconductor memory device 10 is attached to a host device HS (see FIG. 5) will be described.

[0012] The semiconductor memory device 10 is, for example, a card-type semiconductor memory device such as a memory card. For example, the semiconductor memory device 10 has a length L in the X direction, a width W in the Y direction, and a thickness T in the Z direction. The length L is greater than the width W. An example of the length L is 18 mm±0.10 mm. An example of the width W is 14 mm±0.10 mm. An example of the thickness T is 1.4 mm±0.10 mm. However, the above-mentioned specifications and numerical values ​​do not limit the contents of this embodiment.

[0013] As shown in FIG. 1, the semiconductor memory device 10 has a first main surface 10sa, a second main surface 10sb, a first end surface 10sc, a second end surface 10sd, a first side surface 10se, and a second side surface 10sf.

[0014] The first main surface 10sa and the second main surface 10sb are the widest surfaces among the six surfaces described above. The second main surface 10sb is located on the opposite side to the first main surface 10sa. The first main surface 10sa and the second main surface 10sb are spaced apart in the Z direction and extend in the X direction and the Y direction.

[0015] The first end surface 10sc and the second end surface 10sd are spaced apart in the X direction and extend in the Y and Z directions. The first end surface 10sc connects one end in the X direction of the first main surface 10sa to one end in the X direction of the second main surface 10sb. The second end surface 10sd connects the other end in the X direction of the first main surface 10sa to the other end in the X direction of the second main surface 10sb.

[0016] The first side surface 10se and the second side surface 10sf are spaced apart in the Y direction and extend in the X direction and the Z direction. The first side surface 10se connects one end of the first main surface 10sa in the Y direction to one end of the second main surface 10sb in the Y direction. The second side surface 10sf connects the other end of the first main surface 10sa in the Y direction to the other end of the second main surface 10sb in the Y direction.

[0017] <2. Configuration of Semiconductor Memory Device> Next, the configuration of the semiconductor memory device 10 will be described. 2 is a cross-sectional view showing a configuration of the semiconductor memory device 10. The semiconductor memory device 10 includes, for example, a substrate 11, one or more (e.g., a plurality of) memory chips 12, a controller 13, one or more (e.g., a plurality of) electronic components 14, and a mold resin 15.

[0018] <2.1 Substrate> The substrate 11 is a printed circuit board. The substrate 11 is in the form of a plate extending in the X and Y directions. The substrate 11 is an example of a "first substrate." The substrate 11 has a first surface 11a and a second surface 11b. The first surface 11a and the second surface 11b are spaced apart in the Z direction and extend in the X and Y directions. The first surface 11a is a surface that is covered with the molded resin 15 when viewed from the Z direction. The second surface 11b is located on the opposite side to the first surface 11a. The second surface 11b is exposed to the outside of the semiconductor memory device 10. The second surface 11b forms a second main surface 10sb of the semiconductor memory device 10.

[0019] <2.2 Memory chip> The memory chip 12 is a semiconductor memory chip that stores data in a non-volatile manner. The memory chip 12 is, for example, a NAND type flash memory. However, the "semiconductor memory" is not limited to a NAND type flash memory, and may be other types of memory such as a NOR type memory, a Magnetoresistive Random Access Memory (MRAM), or a resistive memory. The memory chip 12 generates heat when the semiconductor storage device 10 is in use.

[0020] The memory chip 12 is disposed between the first surface 11a of the substrate 11 and the mold resin 15. The multiple memory chips 12 are, for example, stacked on one another and mounted on the first surface 11a of the substrate 11. Note that instead of being mounted on the first surface 11a of the substrate 11, the memory chips 12 may be stacked above the controller 13 from the side opposite to the substrate 11. The multiple memory chips 12 are, for example, electrically connected to the first surface 11a of the substrate 11 via bonding wires BW.

[0021] <2.3 Controller> The controller 13 is a control component mounted on the substrate 11. The controller 13 controls the entire semiconductor memory device 10. The controller 13 controls write operations, read operations, and the like for the multiple memory chips 12. The controller 13 is, for example, a controller chip in which a control function unit is integrated in one semiconductor chip. The controller 13 is, for example, a semiconductor package including a SoC (System on a Chip) in which a host interface circuit that communicates with a host device, a control circuit that controls the multiple memory chips 12, and a control circuit that controls a DRAM (not shown) are integrated in one semiconductor chip. The controller 13 is disposed between the first surface 11a of the substrate 11 and the mold resin 15. The controller 13 is, for example, mounted on the first surface 11a of the substrate 11. In this embodiment, the controller 13 is disposed between the first end surface 10sc of the semiconductor memory device 10 and the memory chips 12 in the X direction. The controller 13 generates heat when the semiconductor memory device 10 is used.

[0022] <2.4 Electronic Components> The electronic component 14 is mounted on the first surface 11a of the substrate 11. The electronic component 14 is a capacitor, a resistor, or the like.

[0023] <2.5 Mold resin> The mold resin 15 is a sealing member provided on the first surface 11a of the substrate 11. The mold resin 15 is made of an insulating material. The mold resin 15 seals, for example, the memory chips 12, the controller 13, and the electronic components 14 together.

[0024] The molding resin 15 includes a first surface 15a and a second surface 15b. The first surface 15a contacts the first surface 11a of the substrate 11. The second surface 15b is located on the opposite side to the first surface 15a. The second surface 15b extends along the X direction and the Y direction. The second surface 15b forms a first main surface 10sa of the semiconductor memory device 10.

[0025] <3. Circuit board configuration> Next, the configuration of the substrate 11 will be described. 2, the substrate 11 is, for example, a multi-layer circuit board. The substrate 11 includes an insulating base material 21 and a wiring pattern 22.

[0026] The insulating substrate 21 is an insulating substrate forming the base of the substrate 11. The insulating substrate 21 is formed of a hard insulating material such as a glass epoxy material. However, the material of the insulating substrate 21 is not limited to the above example. The insulating substrate 21 may be formed of a paper phenol material, a composite material, a fluorine-based resin material, a polyimide material, or the like.

[0027] In this embodiment, the insulating base material 21 includes a core material 21A and a prepreg 21B laminated on the core material 21A. The prepreg 21B is located on the second surface 11b side of the core material 21A. The substrate 11 is not limited to a multilayer circuit board, and may be a double-sided substrate. That is, the insulating base material 21 may be formed only by the core material 21A without having the prepreg 21B. For this reason, in the following description, the "insulating base material 21" may be read as the "core material 21A", and the "surface 21s of the insulating base material 21" may be read as the "surface 21s of the core material 21A".

[0028] The wiring pattern 22 is a conductive portion provided on the substrate 11. The wiring pattern 22 includes wiring 22L provided inside the insulating base material 21 and / or on the surface of the substrate 11. The wiring pattern 22 is formed of a metal material such as copper.

[0029] <4. Composition of the surface layer of the board> Next, the surface layer 30 of the substrate 11 will be described. 3 is a diagram illustrating a surface layer portion 30 of the substrate 11. As shown in FIG. 3, the substrate 11 has a surface layer portion 30. The surface layer portion 30 is a portion that is laminated on the insulating base material 21 to form the second surface 11b of the substrate 11. The surface layer portion 30 includes a conductive pattern 31 and a solder resist layer 32.

[0030] Here, the semiconductor memory device 10 includes a first region A1 and a second region A2. The first region A1 is disposed between the center of the semiconductor memory device 10 in the X direction and a second end face 10sd. A plurality of terminals 41A and 41B, which will be described later, are disposed in the first region A1. The second region A2 is disposed between the center of the semiconductor memory device 10 in the X direction and a first end face 10sc. A plurality of terminals 41C, which will be described later, are disposed in the second region A2.

[0031] <4.1 Conductive pattern> The conductive pattern 31 is a conductive portion included in the surface layer portion 30 as a part of the wiring pattern 22. The conductive pattern 31 has a plurality of terminals 41 and a plurality of wirings .

[0032] (multiple terminals) The multiple terminals 41 are terminals exposed to the outside of the semiconductor memory device 10 in order to be electrically connected to a host device. Each terminal 41 is, for example, a pad formed in a planar shape along the X direction and the Y direction. The multiple terminals 41 are provided, for example, on the surface 21s of the insulating substrate 21. Each terminal 41 is exposed to the outside of the semiconductor memory device 10 through an opening 32h of the solder resist layer 32. Each of the multiple terminals 41 is, for example, a signal terminal, a power terminal, or a ground terminal. Note that some of the multiple terminals 41 may be test terminals.

[0033] Each terminal 41 includes a main body 45 and a protective film 46. The main body 45 is formed of a metal material such as copper. The protective film 46 is laminated on the main body 45 from the side opposite to the insulating substrate 21. The protective film 46 is, for example, a plating layer provided for rust prevention. The protective film 46 is, for example, formed of a metal material such as gold or nickel.

[0034] The multiple terminals 41 include multiple terminals 41A, 41B arranged in the first area A1 and multiple terminals 41C arranged in the second area A2.

[0035] The multiple terminals 41A are arranged in a row in the Y direction. The multiple terminals 41B are arranged between the multiple terminals 41A and the multiple terminals 41C in the X direction. The multiple terminals 41B include three terminals 41B (three terminals 41B on the first side surface side) arranged between the center in the Y direction of the semiconductor memory device 10 and the first side surface 10se, and three terminals 41B (three terminals 41B on the second side surface side) arranged between the center in the Y direction of the semiconductor memory device 10 and the second side surface 10sf. The three terminals 41B on the first side surface side and the three terminals 41B on the second side surface side are arranged in a row in the Y direction.

[0036] The multiple terminals 41C are arranged in a row in the Y direction. The distance in the X direction between the multiple terminals 41C and the multiple terminals 41B is greater than the distance in the X direction between the multiple terminals 41A and the multiple terminals 41B.

[0037] (multiple wires) The multiple wirings 42 are wirings included in the surface layer portion 30 as part of the wiring 22L. The multiple wirings 42 are provided on the surface 21s of the insulating base material 21. At least some of the multiple wirings 42 are electrically connected to the terminals 41.

[0038] <4.2 Solder resist layer> The solder resist layer 32 is an insulating protective layer that protects the conductive pattern 31. The solder resist layer 32 is an example of an "insulating layer". The solder resist layer 32 is provided, for example, on the surface 21s of an insulating base material. The solder resist layer 32 has openings 32h that expose the terminals 41, and covers a portion of the conductive pattern 31. For example, the solder resist layer 32 covers a plurality of wirings 42.

[0039] <5. Non-planar part> Next, the non-flat portion 50 of the surface layer 30 will be described. 3, the surface layer 30 has a non-planar portion 50. When viewed from the Z direction, the non-planar portion 50 is provided in a region of the surface layer 30 away from the multiple terminals 41. In this embodiment, the non-planar portion 50 is provided between the first region A1 and the second region A2 in the X direction. The non-planar portion 50 is an example of a "first non-planar portion."

[0040] In this embodiment, the non-flat portion 50 has a plurality of recesses 51. The plurality of recesses 51 are arranged in a matrix of, for example, four rows in the X direction and eight rows in the Y direction. The recesses 51 are bottomed holes provided in the solder resist layer 32. The recesses 51 reach a position closer to the insulating base material 21 than a part of the terminal 41 in the Z direction. For example, the recesses 51 reach the surface 21s (for example, the surface of the core material 21A) of the insulating base material 21. In this embodiment, by providing the above-mentioned plurality of recesses 51, the non-flat portion 50 has an uneven structure in which the recesses 61 and the protrusions 62 are alternately arranged. For example, the recesses 61 and the protrusions 62 are alternately arranged in each of the X direction and the Y direction. The recesses 61 are an example of a "first recess". The protrusions 62 are an example of a "first protrusion".

[0041] In this embodiment, the non-flat portion 50 is preferably formed in a portion of the surface layer 30 close to the controller 13 and / or the memory chip 12 which generate a large amount of heat. For example, at least a portion of the non-flat portion 50 is provided in a region of the surface layer 30 which overlaps with the controller 13 when viewed from the Z direction. Also, at least a portion of the non-flat portion 50 is provided in a region of the surface layer 30 which overlaps with the memory chip 12 when viewed from the Z direction.

[0042] <5.1 Shape of the recess> The recess 61 is formed by the depression 51. In other words, in this embodiment, the "recess 61" may be read as the "recess 51". The multiple recesses 61 are arranged at equal intervals P1 in the X direction. The width of the recess 61 in the X direction is, for example, equal to or greater than the interval P1. The width of the recess 61 in the X direction is, for example, smaller than the width of the terminal 41 in the X direction. The multiple recesses 61 are arranged at equal intervals P2 in the Y direction. The width of the recess 61 in the Y direction is, for example, equal to or greater than the interval P2. The width of the recess 61 in the Y direction is, for example, smaller than the width of the terminal 41 in the Y direction. The width of the recess 61 in the X direction may be larger than the width of the terminal 41 in the X direction. The width of the recess 61 in the Y direction may be larger than the width of the terminal 41 in the Y direction.

[0043] The recess 61 reaches a position closer to the insulating substrate 21 in the Z direction than a part of the terminal 41. For example, the recess 61 reaches the surface 21s of the insulating substrate 21 (for example, the surface of the core material 21A). The recess 61 is polygonal when viewed from the Z direction. In this embodiment, the recess 61 is quadrangular when viewed from the Z direction. However, the recess 61 may be triangular or a polygon having pentagons or more sides, or may be circular. For example, if the recess 61 is a polygon having pentagons or more sides or a circle, a part of the thermally conductive sheet 70 described later is likely to enter inside the recess 61, and it is easy to ensure a larger contact area between the non-flat portion 50 and the thermally conductive sheet 70.

[0044] <5.2 Shape of the protruding part> The protrusion 62 is a portion defined between two adjacent recesses 61 by providing a plurality of recesses 61. In the present application, the "protrusion" means a portion protruding in a direction away from the bottom of the recess. In this embodiment, the protrusion 62 is defined between two recesses 61 adjacent to each other in the X direction or the Y direction. For example, the protrusion 62 is a remaining portion of the solder resist layer 32 existing between two adjacent recesses 61. In this embodiment, the protrusion 62 is formed of the same insulating material as the solder resist layer 32. In this embodiment, the thickness (protrusion height) T1 in the Z direction of the protrusion 62 with respect to the surface 21s of the insulating substrate 21 is the same as the thickness T2 in the Z direction of the solder resist layer 32 with respect to the surface 21s of the insulating substrate 21, for example.

[0045] The Z-direction thickness T1 of the protrusions 62 (the Z-direction thickness T2 of the solder resist layer 32) is, for example, several μm to several mm. More specifically, the Z-direction thickness T1 of the protrusions 62 (the Z-direction thickness T2 of the solder resist layer 32) is, for example, 10 μm or more. The Z-direction thickness T1 of the protrusions 62 (the Z-direction thickness T2 of the solder resist layer 32) is, for example, 30 μm or less.

[0046] In this embodiment, the convex portion 62 extends in a direction parallel to the second surface 11b of the substrate 11. For example, the convex portion 62 extends linearly in the X direction or the Y direction. For example, the multiple convex portions 62 include three convex portions 62 spaced apart from each other in the X direction and extending in the Y direction, and seven convex portions 62 spaced apart from each other in the Y direction and extending in the X direction. Each of the three convex portions 62 extends so as to cross the non-flat portion 50 in the Y direction while passing next to the multiple recesses 61. Each of the seven convex portions 62 extends so as to cross the non-flat portion 50 in the X direction while passing next to the multiple recesses 61. Each of the three convex portions 62 extends to both ends of the semiconductor memory device 10 in the Y direction. Each of the seven convex portions 62 extends to the first region A1 and the second region A2 of the semiconductor memory device 10. At each of the intersections between the three protrusions 62 and the seven protrusions 62, a connection portion is formed in which a protrusion 62 extending in the X direction and a protrusion 62 extending in the Y direction are connected in a cross shape.

[0047] <6. Thermally conductive sheets> Next, returning to FIG. 1, the thermally conductive sheet 70 will be described. The thermally conductive sheet 70 is, for example, a sheet having a higher thermal conductivity than the solder resist layer 32. The thermally conductive sheet 70 has, for example, a thermal conductivity of 1.0 W / (m·K) or more. The thermally conductive sheet 70 is formed of, for example, silicone. The thermally conductive sheet 70 is disposed so as to overlap the non-flat portion 50 when viewed from the Z direction, and is in contact with the non-flat portion 50. For example, the thermally conductive sheet 70 has an outer shape that covers the entire area of ​​the non-flat portion 50 when viewed from the Z direction. Note that the thermally conductive sheet 70 does not need to be fixed to the semiconductor memory device 10, and may simply be in contact with the non-flat portion 50.

[0048] 4 is a cross-sectional view for explaining the thermally conductive sheet 70. The thermally conductive sheet 70 has flexibility, for example. A part of the thermally conductive sheet 70 enters the inside of the recess 61 when the thermally conductive sheet 70 is pressed at least toward the non-flat portion 50. The thermally conductive sheet 70 comes into contact with the inner surface of the recess 61 (the side surface of the protrusion 62) by a part of the thermally conductive sheet 70 entering the inside of the recess 61. Furthermore, the thermally conductive sheet 70 comes into contact with the bottom surface of the recess 61 (the surface 21s of the insulating substrate 21) by a part of the thermally conductive sheet 70 entering the inside of the recess 61.

[0049] <7. Host device connector> Next, the connector 90 of the host device HS will be described. FIG. 5 is a plan view showing a substrate 80 of the host device HS. For convenience of explanation, the substrate 80 of the host device HS will be referred to as the "host substrate 80" below. The host substrate 80 is an example of a "second substrate." The host substrate 80 has a socket-type connector 90 (e.g., a clamshell-type socket). The semiconductor memory device 10 can be manually attached and detached to the connector 90. For example, the semiconductor memory device 10 can be removed from the connector 90 in the event of a malfunction, and can be easily replaced. The connector 90 has, for example, a connector body 91, a plurality of terminals 92, and a holder 93 (see FIG. 6).

[0050] (Connector body) The connector body 91 is a portion that forms the main portion of the outer shape of the connector 90. The connector body 91 is fixed to the host substrate 80. The connector body 91 is electrically connected to the host substrate 80. The connector body 91 includes an accommodation section S capable of accommodating the semiconductor memory device 10. The connector body 91 is open on one side in the X direction, for example, and includes a wall section 91a that surrounds the accommodation section S from three directions.

[0051] (multiple terminals) The multiple terminals 92 are terminals exposed to the outside of the connector 90 to be connected to the multiple terminals 41 of the semiconductor memory device 10. The multiple terminals 92 are arranged at positions corresponding one-to-one to the multiple terminals 41 of the semiconductor memory device 10. Each of the terminals 92 is a pin-type terminal having a shape elongated in the X direction.

[0052] A base end of each terminal 92 is connected to the connector body 91 and supported by the connector body 91. Each terminal 92 is electrically connected to the host substrate 80 via the connector body 91. A tip end of each terminal 92 is located at a height above the host substrate 80 (see FIG. 6). Each terminal 92 is disposed at an angle with respect to the surface of the host substrate 80 so that the tip end of each terminal 92 is farther away from the host substrate 80 than the base end. Each terminal 92 is made of metal and is elastically deformable. In this embodiment, when the semiconductor memory device 10 is attached to the connector 90, each terminal 92 is pressed toward the host substrate 80 by the semiconductor memory device 10. This causes each terminal 92 to elastically deform. As a result, the tip end of each terminal 92 is brought into close contact with the terminal 41 of the semiconductor memory device 10 by the restoring force of the elastic deformation.

[0053] (holding body) 6 is a perspective view showing a first state when the semiconductor memory device 10 is attached. The holder 93 is a portion that holds the semiconductor memory device 10 when the semiconductor memory device 10 is attached to the connector 90. The holder 93 is rotatably connected to the connector main body 91. The holder 93 has, for example, a base end portion 93a, a first support portion 93b1, and a second support portion 93b2.

[0054] The base end 93a has a hinge structure and is rotatably connected to an end of the connector body 91. The first support portion 93b1 and the second support portion 93b2 are spaced apart from each other in the Y direction and extend in a direction away from the base end 93a.

[0055] The first support portion 93b1 has a first portion 94a1 (see FIG. 7) along the first main surface 10sa of the semiconductor memory device 10, a second portion 94b1 along the first side surface 10se of the semiconductor memory device 10, and a third portion 94c1 hanging over the second main surface 10sb of the semiconductor memory device 10. Similarly, the second support portion 93b2 has a first portion 94a2 (see FIG. 7) along the first main surface 10sa of the semiconductor memory device 10, a second portion 94b2 along the second side surface 10sf of the semiconductor memory device 10, and a third portion 94c2 hanging over the second main surface 10sb of the semiconductor memory device 10. The semiconductor memory device 10 is attached to the holder 93 by being inserted between the first support portion 93b1 and the second support portion 93b2.

[0056] At this time, the thermally conductive sheet 70 may be attached to the semiconductor memory device 10 or to the host substrate 80. In the following, an example in which the thermally conductive sheet 70 is attached to the host substrate 80 will be described.

[0057] Fig. 7 is a perspective view showing a second state when the semiconductor memory device 10 is attached. The second state shows a state in which the holder 93 has been rotated from the first state toward the host substrate 80. Fig. 8 is a perspective view showing a third state when the semiconductor memory device 10 is attached. The third state is a state in which the holder 93 has been further rotated from the second state toward the host substrate 80, and the semiconductor memory device 10 is accommodated in the accommodation section S (see Fig. 7) of the connector body 91.

[0058] As a result, after the semiconductor memory device 10 is attached to the holder 93, the holder 93 is rotated toward the host substrate 80, so that the semiconductor memory device 10 is removably attached to the connector 90 with the thermally conductive sheet 70 sandwiched between the non-planar portion 50 and the host substrate 80.

[0059] <8. Manufacturing method> Next, a method for manufacturing the semiconductor memory device 10 will be described. 9 is a cross-sectional view showing a manufacturing method of the semiconductor memory device 10. First, as shown in (a) of FIG. 9, a surface layer portion 30A is formed on an insulating base material 21. The surface layer portion 30A includes a conductive pattern 31A provided on the insulating base material 21 and a solder resist layer 32A covering the entire conductive pattern 31A. The conductive pattern 31A includes a main body portion 45 of a terminal 41 and a plurality of wirings 42.

[0060] Next, as shown in (b) of Fig. 9, a mask M1 is formed on the solder resist layer 32A. The mask M1 has openings M1h at positions corresponding to the openings 32h and the plurality of recesses 51 of the solder resist layer 32. Next, as shown in (c) of Fig. 9, etching is performed using the mask M1 to form the plurality of recesses 51 and the openings 32h that define the recesses 61 and the protrusions 62. As a result, the solder resist layer 32 is formed from the solder resist layer 32A.

[0061] Next, as shown in Fig. 9(d), a mask M2 is formed on the solder resist layer 32, for example, by dry film lamination. The mask M2 covers the non-flat portion 50 and has openings M2h at positions corresponding to the openings 32h of the solder resist layer 32. Next, as shown in Fig. 9(e), a plating process is performed through the openings M2h of the mask M2. As a result, the terminals 41 are formed.

[0062] <9. Advantages> As a comparative example, consider a semiconductor memory device having a flat surface, in which case the heat dissipation area is small and it is difficult to expect an increase in the amount of heat dissipation beyond a certain amount.

[0063] On the other hand, in this embodiment, the substrate 11 has a surface layer 30 that forms the second surface 11b of the substrate 11. The surface layer 30 includes a conductive pattern 31 including a plurality of terminals 41 exposed to the outside, and a solder resist layer 32 that covers a part of the conductive pattern 31. The surface layer 30 has a non-flat portion 50 having a plurality of recesses 51 and in which concave portions 61 and convex portions 62 are alternately arranged in an area outside the plurality of terminals 41. According to this configuration, the heat dissipation area of ​​the semiconductor memory device 10 is expanded by the alternating concave portions 61 and convex portions 62. This can improve the heat dissipation of the semiconductor memory device 10. The semiconductor memory device 10 can improve the heat dissipation compared to a semiconductor memory device having a flat surface, regardless of the presence or absence of the thermally conductive sheet 70.

[0064] In this embodiment, the semiconductor memory device 10 is used in combination with a thermally conductive sheet 70 that is overlaid on the non-flat portion 50. With this configuration, a part of the thermally conductive sheet 70 contacts the inner surface of the recess 61, thereby increasing the contact area between the semiconductor memory device 10 and the thermally conductive sheet 70. This can further improve the heat dissipation of the semiconductor memory device 10.

[0065] In this embodiment, the semiconductor memory device 10 can be detachably attached to the connector 90 with the thermally conductive sheet 70 sandwiched between the non-flat portion 50 and the host substrate 80. With this configuration, the heat transferred from the non-flat portion 50 to the thermally conductive sheet 70 can be dissipated through the host substrate 80. This can further improve the heat dissipation performance of the semiconductor memory device 10.

[0066] In this embodiment, the connector 90 has a connector body 91 fixed to the host substrate 80 and a holder 93 rotatable relative to the connector body 91. After the semiconductor memory device 10 is mounted on the holder 93, the holder 93 is rotated toward the host substrate 80, so that the semiconductor memory device 10 can be electrically connected to the connector 90 with the thermally conductive sheet 70 sandwiched between the non-flat portion 50 and the host substrate 80. According to this configuration, the semiconductor memory device 10 is mounted on the holder 93 of the connector 90, and the thermally conductive sheet 70 can be sandwiched between the non-flat portion 50 and the host substrate 80 by the operation of rotating the holder 93. This makes it easier to bring the non-flat portion 50 and the thermally conductive sheet 70 into close contact with each other.

[0067] In this embodiment, the substrate 11 includes an insulating base material 21. The conductive pattern 31 includes wiring 42 provided on the surface 21s of the insulating base material 21. The recess 61 reaches the surface 21s of the insulating base material 21. With this configuration, it is possible to increase the amount of heat dissipation from the surface 21s of the insulating base material 21 (for example, the core material 21A) that is closer to the heat source. This can further improve the heat dissipation of the semiconductor memory device 10. Furthermore, with the above configuration, it is possible to form a relatively deep recess as the recess 61. This can further increase the contact area between the semiconductor memory device 10 and the thermally conductive sheet 70, and further improve the heat dissipation of the semiconductor memory device 10.

[0068] In this embodiment, the protrusions 62 are formed of the same insulating material as the solder resist layer 32. With this configuration, the adhesion between the protrusions 62 and the insulating base material 21 is likely to be good, and the protrusions 62 are less likely to fall off the insulating base material 21. This can improve the reliability of the semiconductor memory device 10.

[0069] (First Modification of the First Embodiment) Next, a first modified example of the first embodiment will be described. This modified example differs from the first embodiment in that a part of the convex portion is formed of a metal material. The configuration other than that described below is the same as that of the first embodiment. In this case, "recess 61" is replaced with "recess 61A", and "convex portion 62" is replaced with "convex portion 62A". Recess 61A is an example of a "first recess". Convex portion 62A is an example of a "first convex portion".

[0070] 10 is a diagram showing a semiconductor memory device 10A according to a first modification of the first embodiment. The surface layer 30 of the semiconductor memory device 10A has a plurality of depressions 51A, thereby forming a non-planar portion 50 in which recesses 61A and protrusions 62A are alternately arranged. The recesses 61A are the same as the recesses 61 in the first embodiment. The protrusions 62A include a first portion 101 and a second portion 102.

[0071] The first portion 101 is formed of the same metal material as at least a part of the terminal 41. For example, the first portion 101 is formed of the same metal material (e.g., copper) as the main body portion 45 of the terminal 41. The first portion 101 is formed simultaneously with the main body portion 45 of the terminal 41 and the multiple wirings 42 in a process of forming the main body portion 45 of the terminal 41 and the multiple wirings 42 on the surface 21s of the insulating substrate 21. The thickness T3 of the first portion 101 is the same as the thickness T4 of the main body portion 45 of the terminal 41, for example. For example, when the thermally conductive sheet 70 is provided, a part of the thermally conductive sheet 70 that enters the recess 61A contacts the first portion 101 of the protrusion 62A.

[0072] The second portion 102 is laminated on the first portion 101 from the side opposite to the insulating base material 21. The second portion 102 is formed of the same insulating material as the solder resist layer 32. For example, the second portion 102 is formed simultaneously with the solder resist layer 32 in the process of forming the solder resist layer 32.

[0073] Other points of the protrusion 62A are the same as those of the protrusion 62 described in the first embodiment. For example, the protrusion 62A extends linearly in the X direction or the Y direction. In this embodiment, the multiple protrusions 62A include three protrusions 62A spaced apart from each other in the X direction and extending in the Y direction, and seven protrusions 62A spaced apart from each other in the Y direction and extending in the X direction. Each of the three protrusions 62A extends so as to cross the non-flat portion 50 in the Y direction while passing next to the multiple recesses 61A. In this case, each of the first portion 101 and the second portion 102 described above extends over the entire length of the protrusion 62A in the Y direction. Each of the seven protrusions 62A extends so as to cross the non-flat portion 50 in the X direction while passing next to the multiple recesses 61A. In this case, each of the first portion 101 and the second portion 102 described above extends over the entire length of the protrusion 62A in the X direction.

[0074] According to this configuration, the protrusion 62A includes the first portion 101 formed of a metal material. Therefore, heat is easily transferred from the insulating base material 21 to the protrusion 62A, and heat is easily dissipated from the protrusion 62A to the outside. This can further improve the heat dissipation of the semiconductor memory device 10A. From another perspective, a part of the thermally conductive sheet 70 that has entered the recess 61A contacts the first portion 101 of the protrusion 62A, which makes it easier for heat to be transferred from the protrusion 62A to the thermally conductive sheet 70. This can further improve the heat dissipation of the semiconductor memory device 10A.

[0075] (Second Modification of the First Embodiment) Next, a second modified example of the first embodiment will be described. This modified example differs from the first embodiment in that the entire convex portion is formed of a metal material. Note that the configuration other than that described below is the same as that of the first embodiment. In this case, "recess 61" is replaced with "recess 61B", and "convex portion 62" is replaced with "convex portion 62B". Recess 61B is an example of a "first recess". Convex portion 62B is an example of a "first convex portion".

[0076] FIG. 11 is a diagram showing a semiconductor memory device 10B according to a second modification of the first embodiment. The surface layer 30 of the semiconductor memory device 10B has a non-flat portion 50 in which concave portions 61B and convex portions 62B are alternately arranged by having a plurality of recesses 51B. The concave portions 61B are the same as the concave portions 61 of the first embodiment. The convex portions 62B are formed of the same metal material as at least a part of the terminals 41. For example, the convex portions 62B are formed of the same metal material (e.g., copper) as the main body portion 45 of the terminals 41. The convex portions 62B are formed simultaneously with the main body portion 45 of the terminals 41 and the plurality of wirings 42 in the process of forming the main body portion 45 of the terminals 41 and the plurality of wirings 42 on the surface 21s of the insulating substrate 21. The thickness T3 in the Z direction of the convex portions 62B is the same as the thickness T4 in the Z direction of the main body portion 45 of the terminals 41, for example.

[0077] In this modification, the Z-direction end face 62se of the protrusion 62B is exposed to the outside of the semiconductor memory device 10B. For example, when the thermally conductive sheet 70 is provided, a part of the thermally conductive sheet 70 contacts the end face 62se of the protrusion 62B in addition to the side face of the protrusion 62B.

[0078] Other aspects of the protrusion 62B are the same as those of the protrusion 62 described in the first embodiment. For example, the protrusion 62B extends linearly in the X direction or the Y direction. For example, the multiple protrusions 62B include three protrusions 62B spaced apart from each other in the X direction and extending in the Y direction, and seven protrusions 62B spaced apart from each other in the Y direction and extending in the X direction. Each of the three protrusions 62B extends so as to cross the non-flat portion 50 in the Y direction while passing next to the multiple recesses 61. Each of the seven protrusions 62B extends so as to cross the non-flat portion 50 in the X direction while passing next to the multiple recesses 61.

[0079] Next, a method for manufacturing the semiconductor memory device 10B will be described. Fig. 12 is a cross-sectional view showing a manufacturing method of the semiconductor memory device 10B. First, as shown in Fig. 12(a), a surface layer portion 30A is formed on an insulating base material 21. The surface layer portion 30A includes a conductive pattern 31A provided on the insulating base material 21 and a solder resist layer 32A that entirely covers the conductive pattern 31A. The conductive pattern 31A includes a main body portion 45 of the terminal 41, a plurality of wirings 42, and a plurality of protrusions 62B.

[0080] Next, as shown in (b) of Fig. 12, a mask M1 is formed on the solder resist layer 32A. The mask M1 has openings M1h at positions corresponding to the openings 32h of the solder resist layer 32 and the non-flat portion 50. The openings M1h formed at positions corresponding to the non-flat portion 50 are large openings that cover the entire area of ​​the non-flat portion 50. Next, as shown in (c) of Fig. 12, etching is performed using the mask M1, so that the solder resist layer 32 is formed from the solder resist layer 32A. As a result, a plurality of protrusions 62B are exposed to the outside.

[0081] Next, as shown in Fig. 12(d), a mask M2 is formed on the solder resist layer 32, for example, by dry film lamination. The mask M2 covers the non-flat portion 50 and has openings M2h at positions corresponding to the openings 32h of the solder resist layer 32. Next, as shown in Fig. 12(e), a plating process is performed through the openings M2h of the mask M2. As a result, the terminals 41 are formed.

[0082] According to this configuration, since the protrusions 62B are made of a metal material, heat is easily transferred from the insulating base material 21 to the protrusions 62B, and heat is easily dissipated from the protrusions 62B to the outside. This can further improve the heat dissipation of the semiconductor memory device 10B. From another perspective, since the contact area between the metal protrusions 62B and the thermally conductive sheet 70 is increased, heat is easily transferred from the protrusions 62B to the thermally conductive sheet 70. This can further improve the heat dissipation of the semiconductor memory device 10B.

[0083] (Third Modification of the First Embodiment) Next, a third modified example of the first embodiment will be described. This modified example differs from the second modified example in that a protective film is formed on the surface of the convex portion. The configuration other than that described below is the same as the second modified example. In this case, "recess 61B" is replaced with "recess 61C", and "convex portion 62B" is replaced with "convex portion 62C". Recess 61C is an example of a "first recess". Convex portion 62C is an example of a "first convex portion".

[0084] 13 is a diagram showing a semiconductor memory device 10C according to a third modified example of the first embodiment. The surface layer 30 of the semiconductor memory device 10C has a plurality of depressions 51C, thereby forming a non-planar portion 50 in which recesses 61C and protrusions 62C are alternately arranged. The recesses 61C are the same as the recesses 61B according to the second modified example of the first embodiment. The protrusions 62C are the same as the protrusions 62B according to the second modified example of the first embodiment.

[0085] In this modification, a protective film 105 is provided on the surface of the protruding portion 62C. The protective film 105 is, for example, a plating layer provided for rust prevention. The protective film 105 is formed of a metal material such as gold or nickel. For example, the protective film 105 is formed simultaneously with the protective film 46 of the terminal 41 in a process of forming the protective film 46 of the terminal 41. For example, in the process shown in (d) of FIG. 12, an opening M2h corresponding to the non-flat portion 50 is provided in the mask M2 and a plating process is performed, so that the protective film 105 is formed simultaneously with the protective film 46 of the terminal 41.

[0086] According to this configuration, as in the second modification of the second embodiment, it is possible to improve heat dissipation. Furthermore, according to the configuration of this modification, it is possible to prevent the protrusion 62C from rusting, thereby improving the reliability of the semiconductor memory device 10C.

[0087] Second embodiment Next, a second embodiment will be described. The second embodiment differs from the first embodiment in that linear recesses are provided. The configuration other than that described below is the same as that of the first embodiment. In this case, "recess 61" is replaced with "recess 61D", and "protrusion 62" is replaced with "protrusion 62D". Recess 61D is an example of a "first recess". Protrusion 62D is an example of a "first protrusion".

[0088] 14 is a diagram showing a semiconductor memory device 10D according to the second embodiment. In this embodiment, the surface layer 30 of the semiconductor memory device 10D has a plurality of depressions 51D, thereby forming a non-flat portion 50 in which recesses 61D and protrusions 62D are alternately arranged.

[0089] In this embodiment, the multiple recesses 51D are spaced apart from each other in the Y direction and extend linearly in the X direction. The recesses 51D are grooves provided in the solder resist layer 32. In the Z direction, the recesses 51D reach a position closer to the insulating base material 21 than a part of the terminal 41. For example, the recesses 51D reach the surface 21s of the insulating base material 21.

[0090] (Shape of the recess) The recess 61D is formed by the depression 51D. In other words, in this embodiment, "recess 61D" may be read as "recess 51D". The multiple recesses 61D are equally spaced apart at interval P2 in the Y direction. The width of the recess 61D in the Y direction is, for example, equal to or greater than the interval P2. The recess 61D reaches a position in the Z direction closer to the insulating substrate 21 than a portion of the terminal 41. For example, the recess 61D reaches the surface 21s of the insulating substrate 21.

[0091] (Shape of convex part) The protrusion 62D is a protrusion defined between two adjacent recesses 61D by providing a plurality of recesses 61D. In this embodiment, the protrusion 62D is defined between two recesses 61D adjacent to each other in the Y direction. For example, the protrusion 62D is a remaining portion of the solder resist layer 32 existing between two adjacent recesses 61D. In this embodiment, the protrusion 62D is formed of the same insulating material as the solder resist layer 32. In this embodiment, the thickness T1 of the protrusion 62D with respect to the surface 21s of the insulating substrate 21 is the same as the thickness T2 of the solder resist layer 32 with respect to the surface 21s of the insulating substrate 21.

[0092] In this embodiment, the convex portion 62D extends linearly in the X direction. For example, the multiple convex portions 62D are spaced apart from one another in the Y direction and each extends linearly in the X direction. Each of the seven convex portions 62D extends so as to cross the non-flat portion 50 while passing adjacent to the multiple recesses 61D. Each of the seven convex portions 62D spans the first region A1 and the second region A2 of the semiconductor memory device 10D.

[0093] According to this configuration, the heat dissipation area of ​​the semiconductor memory device 10D is expanded by the alternating recesses 61D and protrusions 62D. This can improve the heat dissipation of the semiconductor memory device 10D. Furthermore, when the thermally conductive sheet 70 is used, a part of the thermally conductive sheet 70 comes into contact with the inner surface of the recess 61D, thereby increasing the contact area between the semiconductor memory device 10D and the thermally conductive sheet 70. This can further improve the heat dissipation of the semiconductor memory device 10D.

[0094] (First modified example of the second embodiment) Next, a first modified example of the second embodiment will be described. This modified example differs from the second embodiment in that a part of the convex portion is formed of a metal material. The configuration other than that described below is the same as that of the second embodiment. In this case, "recess 61D" is replaced with "recess 61E", and "convex portion 62D" is replaced with "convex portion 62E". Recess 61E is an example of a "first recess". Convex portion 62E is an example of a "first convex portion".

[0095] 15 is a diagram showing a semiconductor memory device 10E according to a first modification of the second embodiment. The surface layer 30 of the semiconductor memory device 10E has a plurality of depressions 51E, thereby forming a non-planar portion 50 in which recesses 61E and protrusions 62E are alternately arranged. The recesses 61E are the same as the recesses 61D of the second embodiment. The protrusions 62E include a first portion 101 and a second portion 102, similar to the first modification of the first embodiment.

[0096] In this embodiment, the protrusion 62E extends linearly in the X direction. For example, the multiple protrusions 62E are spaced apart from one another in the Y direction and each extend in the X direction. Each of the multiple protrusions 62E extends so as to cross the non-planar portion 50 while passing adjacent to the multiple recesses 61E. Each of the seven protrusions 62E spans the first region A1 and the second region A2 of the semiconductor memory device 10E.

[0097] According to this configuration, for the same reason as in the first modification of the first embodiment, it is possible to improve the heat dissipation properties of the semiconductor memory device 10E.

[0098] (Second modified example of the second embodiment) Next, a second modified example of the second embodiment will be described. This modified example differs from the second embodiment in that the entire convex portion is formed of a metal material. Note that the configuration other than that described below is the same as that of the second embodiment. In this case, "recess 61D" is replaced with "recess 61F", and "convex portion 62D" is replaced with "convex portion 62F". Recess 61F is an example of a "first recess". Convex portion 62F is an example of a "first convex portion".

[0099] FIG. 16 is a diagram showing a semiconductor memory device 10F according to a second modification of the second embodiment. The surface layer 30 of the semiconductor memory device 10F has a plurality of recesses 51F, thereby forming a non-flat portion 50 in which concave portions 61F and convex portions 62F are alternately arranged. The concave portions 61F are the same as the concave portions 61D of the second embodiment. The convex portions 62F are formed of the same metal material as at least a part of the terminals 41. For example, the convex portions 62F are formed of the same metal material (e.g., copper) as the main body portion 45 of the terminals 41. The thickness T3 in the Z direction of the convex portions 62F is the same as the thickness T4 in the Z direction of the main body portion 45 of the terminals 41, for example. The convex portions 62F are formed simultaneously with the main body portion 45 of the terminals 41 and the plurality of wirings 42 in the process of forming the main body portion 45 of the terminals 41 and the plurality of wirings 42. In this embodiment, the convex portions 62F extend linearly in the X direction. For example, the multiple protrusions 62F are spaced apart from one another in the Y direction and each extend in the X direction.

[0100] According to this configuration, for the same reason as in the second modification of the first embodiment, it is possible to improve the heat dissipation performance of the semiconductor memory device 10F.

[0101] Third embodiment Next, a third embodiment will be described. The third embodiment differs from the first embodiment in that a plurality of protrusions 111 are provided. The configuration other than that described below is the same as that of the first embodiment. In this case, the "recess 61" is replaced with the "recess 61G", and the "protrusion 62" is replaced with the "protrusion 62G". The recess 61G is an example of a "first recess". The protrusion 62G is an example of a "first protrusion".

[0102] 17 is a diagram showing a semiconductor memory device 10G according to a third embodiment. In this embodiment, a surface layer 30 of the semiconductor memory device 10G has a plurality of protrusions 111, thereby forming a non-planar portion 50 in which recesses 61G and protrusions 62G are alternately arranged.

[0103] For example, the non-flat portion 50 has a recess 110 and a plurality of protrusions 111. The recess 110 is provided between the first region A1 and the second region A2. The recess 110 is recessed in a direction approaching the insulating base material 21 relative to the first region A1 and the second region A2. The recess 110 reaches a position closer to the insulating base material 21 in the Z direction than a part of the terminal 41. For example, the recess 110 reaches the surface 21s of the insulating base material 21 (e.g., the surface of the core material 21A).

[0104] The plurality of protrusions 111 are provided in the recess 110. Each protrusion 111 is a columnar protrusion protruding in the Z direction inside the recess 110. For example, each protrusion 111 protrudes from the surface 21s of the insulating substrate 21 in a direction away from the insulating substrate 21. The plurality of protrusions 111 are arranged in a matrix shape, for example, with four rows in the X direction and eight rows in the Y direction. In this embodiment, by providing the plurality of protrusions 111 described above, the non-flat portion 50 has an uneven structure in which the recesses 61G and the protrusions 62G are alternately arranged. For example, the recesses 61G and the protrusions 62G are alternately arranged in each of the X direction and the Y direction.

[0105] (Shape of convex part) The protrusion 62G is formed by the protruding portion 111. In other words, in this embodiment, the "protrusion 62G" may be read as the "protrusion 111". The multiple protrusions 62G are arranged at equal intervals P3 in the X direction. The width of the protrusion 62G in the X direction is, for example, equal to or less than the interval P3. The width of the protrusion 62G in the X direction is, for example, smaller than the width of the terminal 41 in the X direction. The multiple protrusions 62G are arranged at equal intervals P4 in the Y direction. The width of the protrusion 62G in the Y direction is, for example, equal to or less than the interval P4. The width of the protrusion 62G in the Y direction is, for example, smaller than the width of the terminal 41 in the Y direction. The width of the protrusion 62G in the X direction may be larger than the width of the terminal 41 in the X direction. The width of the protrusion 62G in the Y direction may be larger than the width of the terminal 41 in the Y direction.

[0106] In this embodiment, the entire protrusion 62G is formed of the same insulating material as the solder resist layer 32. In this embodiment, the thickness T1 of the protrusion 62 with respect to the surface 21s of the insulating substrate 21 is the same as the thickness T2 of the solder resist layer 32 with respect to the surface 21s of the insulating substrate 21. The protrusion 62G is polygonal when viewed from the Z direction. For example, the protrusion 62G is quadrangular when viewed from the Z direction. However, the protrusion 62G may be triangular or polygonal with pentagons or more, or may be circular.

[0107] (Shape of the recess) The recess 61G is a portion defined between two adjacent protrusions 62G by providing a plurality of protrusions 62G. In this application, the "recess" means a portion recessed in a direction approaching the insulating substrate 21 compared to the tip surface of the protrusion. In this embodiment, the recess 61G is defined between two protrusions G62 adjacent in the X direction or Y direction. The recess 61G reaches a position closer to the insulating substrate 21 than a part of the terminal 41. For example, the recess 61G reaches the surface 21s of the insulating substrate 21.

[0108] In this embodiment, the recess 61G is a groove provided in the solder resist layer 32. For example, the recess 61G extends linearly in the X direction or the Y direction. For example, the multiple recesses 61G include three recesses 61G spaced apart from each other in the X direction and extending in the Y direction, and seven recesses 61G spaced apart from each other in the Y direction and extending in the X direction. Each of the three recesses 61G extends so as to cross the non-flat portion 50 in the Y direction while passing adjacent to the multiple protruding portions 62G. Each of the seven recesses 61G extends so as to cross the non-flat portion 50 in the X direction while passing adjacent to the multiple protruding portions 62G.

[0109] According to this configuration, the alternating recesses 61G and protrusions 62G increase the heat dissipation area of ​​the semiconductor memory device 10G. This improves the heat dissipation of the semiconductor memory device 10G. Furthermore, when a thermally conductive sheet 70 is used, a portion of the thermally conductive sheet 70 comes into contact with the inner surface of the recess 61G, thereby increasing the contact area between the semiconductor memory device 10G and the thermally conductive sheet 70. This further improves the heat dissipation of the semiconductor memory device 10G.

[0110] (First modified example of the third embodiment) Next, a first modified example of the third embodiment will be described. This modified example differs from the third embodiment in that a part of the convex portion is formed of a metal material. The configuration other than that described below is the same as that of the third embodiment. In this case, "recess 61G" is replaced with "recess 61H", and "convex portion 62G" is replaced with "convex portion 62H". Recess 61H is an example of a "first recess". Convex portion 62H is an example of a "first convex portion".

[0111] 18 is a diagram showing a semiconductor memory device 10H according to a first modification of the third embodiment. The surface layer 30 of the semiconductor memory device 10H has a plurality of protrusions 111H, thereby forming a non-planar portion 50 in which recesses 61H and protrusions 62H are alternately arranged. The recesses 61H are the same as the recesses 61G of the third embodiment. The protrusions 62H include a first portion 101 and a second portion 102, similar to the first modification of the first embodiment.

[0112] According to this configuration, for the same reason as in the first modification of the first embodiment, it is possible to improve the heat dissipation properties of the semiconductor memory device 10H.

[0113] (Second modified example of the third embodiment) Next, a second modified example of the third embodiment will be described. This modified example differs from the third embodiment in that the entire convex portion is formed of a metal material. The configuration other than that described below is the same as that of the third embodiment. In this case, "recess 61G" is replaced with "recess 61I", and "convex portion 62G" is replaced with "convex portion 62I". Recess 61I is an example of a "first recess". Convex portion 62I is an example of a "first convex portion".

[0114] FIG. 19 is a diagram showing a semiconductor memory device 10I according to a second modification of the third embodiment. The surface layer 30 of the semiconductor memory device 10I has a plurality of protrusions 111I, thereby forming a non-flat portion 50 in which recesses 61I and protrusions 62I are alternately arranged. The recesses 61I are the same as the recesses 61G of the third embodiment. The protrusions 62I are formed of the same metal material as at least a part of the terminals 41. For example, the protrusions 62I are formed of the same metal material (e.g., copper) as the main body 45 of the terminals 41. The thickness T3 in the Z direction of the protrusions 62I is the same as the thickness T4 in the Z direction of the main body 45 of the terminals 41, for example. The protrusions 62I are formed simultaneously with the main body 45 of the terminals 41 and the plurality of wirings 42 in the process of forming the main body 45 of the terminals 41 and the plurality of wirings 42. In this modification, the protrusions 62I are arranged in a matrix in the X direction and the Y direction.

[0115] According to this configuration, for the same reason as in the first modification of the first embodiment, it is possible to improve the heat dissipation properties of the semiconductor memory device 10I.

[0116] (Fourth embodiment) Next, a fourth embodiment will be described. This embodiment differs from the third embodiment in that a linear protrusion is provided. The configuration other than that described below is the same as that of the third embodiment. In this case, the "recess 61G" is replaced with the "recess 61J", and the "protrusion 62G" is replaced with the "protrusion 62J". The recess 61J is an example of a "first recess". The protrusion 62 is an example of a "first protrusion 62J".

[0117] 20 is a diagram showing a semiconductor memory device 10J according to a fourth embodiment. In this embodiment, the surface layer 30 of the semiconductor memory device 10J has a plurality of protrusions 111J, thereby forming a non-flat portion 50 in which recesses 61J and protrusions 62J are alternately arranged.

[0118] In this embodiment, the multiple protrusions 111J are spaced apart from each other in the Y direction and extend linearly in the X direction. The protrusions 111J are columnar protrusions protruding in the Z direction inside the recess 110. For example, each protrusion 111J protrudes from the surface 21s of the insulating base material 21 in a direction away from the insulating base material 21.

[0119] (Shape of convex part) The convex portion 62J is formed by the protruding portion 111J. In other words, in this embodiment, the "convex portion 62J" may be read as the "protruding portion 111J." In this embodiment, the entire convex portion 62J is formed of the same insulating material as the solder resist layer 32. In this embodiment, the thickness T1 of the convex portion 62J with respect to the surface 21s of the insulating substrate 21 is the same as the thickness T2 of the solder resist layer 32 with respect to the surface 21s of the insulating substrate 21.

[0120] (Shape of the recess) The recess 61J is defined between two adjacent protrusions 62J by providing a plurality of protrusions 62J. The recess 61J reaches a position in the Z direction closer to the insulating base material 21 than a part of the terminal 41. For example, the recess 61J reaches the surface 21s of the insulating base material 21. In this embodiment, the recess 61J extends linearly in the X direction. For example, the plurality of recesses 61J are spaced apart from each other in the Y direction and each extends linearly in the X direction.

[0121] According to this configuration, the alternating recesses 61J and protrusions 62J increase the heat dissipation area of ​​the semiconductor memory device 10J. This improves the heat dissipation of the semiconductor memory device 10J. Furthermore, when a thermally conductive sheet 70 is used, a part of the thermally conductive sheet 70 comes into contact with the inner surface of the recess 61J, thereby increasing the contact area between the semiconductor memory device 10J and the thermally conductive sheet 70. This further improves the heat dissipation of the semiconductor memory device 10J.

[0122] (First modified example of the fourth embodiment) Next, a first modified example of the fourth embodiment will be described. This modified example differs from the fourth embodiment in that a part of the convex portion is formed of a metal material. The configuration other than that described below is the same as that of the fourth embodiment. In this case, "recess 61J" is replaced with "recess 61K", and "convex portion 62J" is replaced with "convex portion 62K". Recess 61K is an example of a "first recess". Convex portion 62K is an example of a "first convex portion".

[0123] 21 is a diagram showing a semiconductor memory device 10K according to a first modification of the fourth embodiment. The surface layer 30 of the semiconductor memory device 10K has a plurality of protrusions 111K, thereby forming a non-planar portion 50 in which recesses 61K and protrusions 62K are alternately arranged. The recesses 61K are the same as the recesses 61J of the fourth embodiment. The protrusions 62K include a first portion 101 and a second portion 102, similar to the first modification of the first embodiment.

[0124] In this embodiment, the protrusions 62K extend linearly in the X direction. For example, the multiple protrusions 62K are spaced apart from one another in the Y direction and each extend in the X direction. Each of the multiple protrusions 62K extends so as to cross the non-planar portion 50 while passing adjacent to the multiple recesses 61K. Each of the eight protrusions 62K spans the first region A1 and the second region A2 of the semiconductor memory device 10K.

[0125] According to this configuration, for the same reason as in the first modification of the first embodiment, it is possible to improve the heat dissipation performance of the semiconductor memory device 10K.

[0126] (Second modified example of the fourth embodiment) Next, a second modified example of the fourth embodiment will be described. This modified example differs from the fourth embodiment in that the entire convex portion is formed of a metal material. The configuration other than that described below is the same as that of the fourth embodiment. In this case, "recess 61J" is replaced with "recess 61L", and "convex portion 62J" is replaced with "convex portion 62L". Recess 61L is an example of a "first recess". Convex portion 62L is an example of a "first convex portion".

[0127] FIG. 22 is a diagram showing a semiconductor memory device 10L according to a second modified example of the fourth embodiment. The surface layer 30 of the semiconductor memory device 10L has a plurality of protrusions 111L, thereby forming a non-flat portion 50 in which recesses 61L and protrusions 62L are alternately arranged. The recesses 61L are the same as the recesses 61J of the fourth embodiment. The protrusions 62L are formed of the same metal material as at least a part of the terminal 41. For example, the protrusions 62L are formed of the same metal material (e.g., copper) as the main body 45 of the terminal 41. The thickness T3 of the protrusions 62L in the Z direction is the same as the thickness T4 of the main body 45 of the terminal 41 in the Z direction, for example. The protrusions 62L are formed simultaneously with the main body 45 of the terminal 41 and the plurality of wirings 42 in the process of forming the main body 45 of the terminal 41 and the plurality of wirings 42. In this embodiment, the protrusions 62L extend linearly in the X direction. For example, the multiple protrusions 62L are spaced apart from one another in the Y direction and each extend in the X direction.

[0128] According to this configuration, for the same reason as in the second modification of the first embodiment, it is possible to improve the heat dissipation properties of the semiconductor memory device 10L.

[0129] (Modifications common to the first to fourth embodiments) Next, a modified example common to the first to fourth embodiments will be described. FIG. 23 is a diagram showing a semiconductor memory device 10M according to a modification of the first to fourth embodiments. In this modification, the molded resin 15 has a second surface 15b located on the side opposite to the substrate 11. The second surface 15b has a non-planar portion 210 in which recesses 211 and protrusions 212 are alternately arranged. The recesses 211 and protrusions 212 are alternately arranged, for example, in each of the X direction and the Y direction. The non-planar portion 210 is an example of a "second non-planar portion." The recesses 211 are an example of a "second recess." The protrusions 212 are an example of a "second protrusion."

[0130] The multiple recesses 211 are arranged at equal intervals in the X direction. The multiple recesses 211 are also arranged at equal intervals in the Y direction. The multiple recesses 211 are provided so that the protrusions 212 are defined between two adjacent recesses 211. In this application, the "protrusion" refers to a portion that protrudes in a direction away from the insulating base material 21 compared to the bottom of the recess 211. In this embodiment, the protrusions 212 are formed of the same insulating material as the mold resin 15.

[0131] This configuration can further increase the heat dissipation area of ​​the semiconductor memory device 10. This can further improve the heat dissipation performance of the semiconductor memory device 10.

[0132] The first to fourth embodiments and modifications have been described above. However, the embodiments and modifications are not limited to the above examples. For example, the thermally conductive sheet 70 is not an essential component. Even if the semiconductor memory device 10 is not combined with the thermally conductive sheet 70, the non-flat portion 50 can expand the heat dissipation area, thereby improving heat dissipation.

[0133] Furthermore, the semiconductor memory device 10 is not limited to a case where the concave portion and the convex portion are formed by only one of a plurality of recesses (e.g., recesses 51 to 51F) and a plurality of protrusions (protrusions 111 to 111L). For example, the semiconductor memory device 10 may have both a plurality of recesses (e.g., recesses 51 to 51F) and a plurality of protrusions (protrusions 111 to 111L), thereby forming the concave portion and the convex portion.

[0134] Furthermore, the connector 90 is not limited to a hinge type (clamshell type) connector. For example, the connector 90 may be a push-pull type connector or a push-push type connector.

[0135] According to at least one of the embodiments described above, the surface layer of the substrate has a non-flat portion having at least one of a plurality of recesses and a plurality of protrusions in an area outside the plurality of terminals, and the recesses and protrusions are arranged alternately. With this configuration, it is possible to improve heat dissipation.

[0136] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope of the invention and its equivalents described in the claims, as well as in the scope and spirit of the invention. [Explanation of symbols]

[0137] 1...semiconductor memory device unit, 10-10L...semiconductor memory device, 11...substrate, 12...memory chip, 13...controller, 15...molding resin, 21...insulating substrate, 21s...surface of insulating substrate, 30...surface layer, 31...conductive pattern, 32...solder resist layer (insulating layer), 41...terminal, 42...wiring, 50...non-planar portion (first non-planar portion), 51-51F...depression, 61-61L...recess, 61-61L...convex portion, 111-111L...protruding portion, 210...non-planar portion (second non-planar portion), 211...recess, 212...convex portion.

Claims

1. a first substrate having a first surface and a second surface located opposite the first surface; a molding resin that covers the first surface when viewed in a thickness direction of the first substrate; a memory chip disposed between the first surface and the molding resin; a controller that is disposed between the first surface and the molding resin and that controls the memory chip; Equipped with the first substrate has a surface layer portion forming the second surface, the surface layer portion including a conductive pattern including a plurality of terminals exposed to the outside, and an insulating layer covering a portion of the conductive pattern; the surface layer portion has a first non-flat portion having at least one of a plurality of recesses and a plurality of protrusions in an area outside the plurality of terminals, and in which first recesses and first protrusions are alternately arranged; Semiconductor memory device.

2. the semiconductor memory device is detachably mountable to a socket-type connector provided on a second board of a host device; 2. The semiconductor memory device according to claim 1.

3. the semiconductor memory device is detachably attachable to the connector with a thermally conductive sheet sandwiched between the first non-flat portion and the second substrate; 3. The semiconductor memory device according to claim 2.

4. The connector has a connector body fixed to the second board and a holder rotatable relative to the connector body, the semiconductor memory device is mounted on the holder, and then the holder is rotated toward the second substrate, so that the semiconductor memory device can be electrically connected to the connector with the thermally conductive sheet sandwiched between the first non-flat portion and the second substrate.

4. The semiconductor memory device according to claim 3.

5. the first substrate includes an insulating base material; the conductive pattern includes wiring provided on a surface of the insulating base material, The first recess reaches the surface of the insulating substrate.

5. The semiconductor memory device according to claim 1, wherein the first and second memory cells are connected to each other.

6. The first convex portion is formed of the same insulating material as the insulating layer.

5. The semiconductor memory device according to claim 1, wherein the first and second memory cells are connected to each other.

7. the first protrusion includes a first portion made of the same metal material as at least a portion of the terminal, and a second portion laminated on the first portion and made of the same insulating material as the insulating layer; 5. The semiconductor memory device according to claim 1, wherein the first and second memory cells are connected to each other.

8. The first protrusion is formed of the same metal material as at least a part of the terminal.

5. The semiconductor memory device according to claim 1, wherein the first and second memory cells are connected to each other.

9. The first recess is polygonal or circular when viewed in a thickness direction of the first substrate.

5. The semiconductor memory device according to claim 1, wherein the first and second memory cells are connected to each other.

10. The first protrusion is polygonal or circular when viewed in a thickness direction of the first substrate.

5. The semiconductor memory device according to claim 1, wherein the first and second memory cells are connected to each other.

11. the molding resin has a second non-flat portion on a surface located opposite to the first substrate, the second recess portion and the second protrusion portion being arranged alternately; 5. The semiconductor memory device according to claim 1, wherein the first and second memory cells are connected to each other.

12. a first substrate having a first surface and a second surface located opposite the first surface; a molding resin that covers the first surface when viewed in a thickness direction of the first substrate; a memory chip disposed between the first surface and the molding resin; a controller that is disposed between the first surface and the molding resin and that controls the memory chip; A thermally conductive sheet; Equipped with the first substrate has a surface layer portion forming the second surface, the surface layer portion including a conductive pattern including a plurality of terminals exposed to the outside, and an insulating layer covering a portion of the conductive pattern; the surface layer portion has a first non-flat portion having at least one of a plurality of recesses and a plurality of protrusions in a region outside the plurality of terminals, and in which first recesses and first protrusions are alternately arranged, The thermally conductive sheet is in contact with the first non-planar portion. Semiconductor memory unit.

13. the thermally conductive sheet has flexibility, and a portion of the thermally conductive sheet enters inside the first recess when pressed at least toward the first non-flat portion; 13. The semiconductor memory device unit according to claim 12.

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