Memory system

Abstract

To provide a memory system which improves the reliability of data.SOLUTION: A memory system comprises: a nonvolatile memory 10 including a first memory cell MC and a second memory cell MC which are respectively configurated in a manner to store a plurality of bits of data in a nonvolatile manner; and a memory controller 20 for, when the first memory cell stores an effective first bit data as a first bit and does not store the data as a second bit and the second memory cell stores an effective second bit data as the first bit and does not store the data as the second bit, reading out the second bit data from the second memory cell according to reception of a flash command from a host, so as to write the second bit data read out from the second memory cell into the first memory cell as the second bit.SELECTED DRAWING: Figure 10

Description

[Technical field]

[0001] FIELD OF THE DISCLOSURE Embodiments of the present invention relate to a memory system. [Background technology]

[0002] 2. Description of the Related Art As a memory system, a solid state drive (SSD) equipped with a nonvolatile memory such as a NAND flash memory is known. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2022 / 0375513 [Patent Document 2] US Patent Application Publication No. 2020 / 0027514 [Patent Document 3] US Patent Application Publication No. 2015 / 0347289 Summary of the Invention [Problem to be solved by the invention]

[0004] An embodiment of the present invention provides a memory system capable of improving data reliability. [Means for solving the problem]

[0005] A memory system according to an embodiment includes a nonvolatile memory and a memory controller. The nonvolatile memory includes a plurality of memory cells each configured to nonvolatilely store a plurality of bits of data including at least a first bit and a second bit. The memory controller is electrically connected to the nonvolatile memory. The memory controller is configured to read the second bit data from the second memory cell in response to receiving a flash command from a host when a first memory cell among the plurality of memory cells stores valid first bit data as the first bit and does not store data as the second bit, and a second memory cell different from the first memory cell among the plurality of memory cells stores valid second bit data as the first bit and does not store data as the second bit. [Brief description of the drawings]

[0006] [Figure 1] 1 is a block diagram showing an example of an overall configuration of an information processing system including a memory system according to a first embodiment. [Diagram 2] 1 is a block diagram showing an example of a basic configuration of a memory chip included in a memory system according to a first embodiment. [Diagram 3] 1 is a circuit diagram showing an example of a circuit configuration of a memory cell array included in a memory system according to a first embodiment. [Figure 4] 3A and 3B are diagrams showing threshold voltage distributions and data allocations of memory cells included in the memory system according to the first embodiment. [Diagram 5] FIG. 4 is a sequence diagram showing an example of a write operation in the memory system according to the first embodiment. [Figure 6] 6 is a diagram showing a change in threshold voltage distribution of memory cells due to a first write operation in the memory system according to the first embodiment. FIG. [Figure 7] 6 is a diagram showing a change in threshold voltage distribution of memory cells due to a second write operation in the memory system according to the first embodiment. FIG. [Figure 8]4 is a diagram showing an example of the relationship between a lookup table and a write destination area included in the memory system according to the first embodiment. [Figure 9] 4 is a diagram showing an example of an order in which a first write operation and a second write operation are performed in the memory system according to the first embodiment. [Figure 10] 3A and 3B are conceptual diagrams showing an example of a write destination area before and after a protection operation in the memory system according to the first embodiment. [Figure 11] 4 is a diagram showing changes in a lookup table before and after a protection operation in the memory system according to the first embodiment. [Figure 12] 4 is a flowchart showing the overall flow of a protection operation in the memory system according to the first embodiment. [Figure 13] 11 is a flowchart showing an example of a procedure of a second write operation in the memory system according to the first embodiment. [Figure 14] 11 is a flowchart showing another example of the procedure of the second write operation in the memory system according to the first embodiment. [Figure 15] 4 is a diagram showing a specific example of an update order of read target addresses in the memory system according to the first embodiment. [Figure 16] 4A and 4B are diagrams showing a first specific example of the state of data stored in a write destination area and an MLC buffer in the memory system according to the first embodiment. [Figure 17] 11A and 11B are diagrams showing a second specific example of the state of data stored in a write destination area and an MLC buffer in the memory system according to the first embodiment. [Figure 18] 13A and 13B are diagrams showing a third specific example of the state of data stored in a write destination area and an MLC buffer in the memory system according to the first embodiment. [Figure 19] 13A and 13B are diagrams showing a fourth specific example of the state of data stored in a write destination area and an MLC buffer in the memory system according to the first embodiment. [Figure 20] 13 is a diagram showing a fifth specific example of the state of data stored in a write destination area and an MLC buffer in the memory system according to the first embodiment. [Figure 21] 13 is a diagram showing a sixth specific example of the state of data stored in a write destination area and an MLC buffer in the memory system according to the first embodiment. [Figure 22] 13 is a diagram showing a seventh specific example of the state of data stored in the write destination area and the MLC buffer in the memory system according to the first embodiment. FIG. [Diagram 23] 13 is a diagram showing an eighth specific example of the state of data stored in the write destination area and the MLC buffer in the memory system according to the first embodiment. FIG. [Figure 24] 13A and 13B are diagrams showing a ninth specific example of the state of data stored in a write destination area and an MLC buffer in the memory system according to the first embodiment. [Diagram 25] FIG. 10 is a diagram showing a tenth specific example of the state of data stored in the write destination area and the MLC buffer in the memory system according to the first embodiment. [Figure 26] 11A and 11B are conceptual diagrams showing an example of a write destination area before and after a protection operation in a memory system according to a modified example of the first embodiment. [Figure 27] 13A and 13B are diagrams showing a specific example of the state of data stored in a write destination area and an MLC buffer in a memory system according to a second embodiment. [Figure 28] 13A and 13B are diagrams showing a specific example of the state of data stored in a write destination area and an MLC buffer in a memory system according to a second embodiment. [Figure 29] 13A and 13B are diagrams showing a specific example of the state of data stored in a write destination area and an MLC buffer in a memory system according to a third embodiment. [Diagram 30] 13 is a flowchart showing the overall flow of a protection operation in a memory system according to a fourth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, an embodiment will be described with reference to the drawings. The drawings are schematic. In the following description, components having substantially the same functions and configurations are given the same reference numerals. Numbers following the letters constituting the reference numerals are used to distinguish between elements having similar configurations.

[0008] A memory system according to an embodiment will be described below.

[0009] 1 Configuration 1.1 Configuration of information processing device 1.1.1 Data Processing Device Configuration First, an example of the configuration of an information processing system 1 will be described with reference to Fig. 1. Fig. 1 is a block diagram showing an example of the overall configuration of the information processing system 1.

[0010] As shown in FIG. 1, an information processing system 1 includes a host 2 and a memory system 3.

[0011] The host 2 is an information processing device (computing device) that accesses the memory system 3. The host 2 controls the memory system 3. More specifically, for example, the host 2 requests (commands) the memory system 3 to perform a write operation or a read operation of data (hereinafter, referred to as "user data"). For example, the write request includes a write command, a logical address, and user data. The host 2 also transmits a flash command to the memory system 3. The flash command is a command that instructs the memory system 3 to guarantee (protect) valid user data that the memory system 3 has received up to the time when the flash command was received. For example, the memory system 3 executes a save operation and a protect operation as operations corresponding to the flash command. The save operation is an operation of writing (saving) data that the memory system 3 has received and that has not been stored in the nonvolatile memory 10 (for example, volatile data stored in the buffer memory 25) to the nonvolatile memory 10. The protect operation is an operation of nonvolatilizing (protecting) data that has been stored in the nonvolatile memory 10 and has not been nonvolatilized. When the backup and protection operations have completed the non-volatilization of the guaranteed data, write errors that occur during a write operation executed after completion of the operation corresponding to the flash command (after a flash command completion response) or destruction (loss) of the guaranteed data due to a power outage, etc. are suppressed.

[0012] The memory system 3 is, for example, a solid state drive (SSD). The memory system 3 includes a non-volatile memory 10 and a memory controller 20. The memory system 3 is connected to a host 2 via a host bus. The type of host bus depends on the application to which the memory system 3 is applied. When the memory system 3 is an SSD, the host bus is, for example, a PCIe TM (Peripheral Component Interconnect Express) standard.

[0013] 1.1.2 Memory System Configuration Next, an example of the configuration of the memory system 3 will be described.

[0014] The nonvolatile memory 10 is a nonvolatile storage medium. The nonvolatile memory 10 stores data received from the memory controller 20 in a nonvolatile manner. In the following, a case where the nonvolatile memory 10 is a NAND type flash memory will be described. Note that the nonvolatile memory 10 may be a nonvolatile storage medium other than a NAND type flash memory.

[0015] The memory controller 20 is, for example, a SoC (System On a Chip). The memory controller 20 manages the memory space of the nonvolatile memory 10. In response to a request (command) from the host 2, the memory controller 20 commands the nonvolatile memory 10 to perform a read operation, a write operation, and the like. When the memory controller 20 receives a flash command from the host 2, it executes a protection operation for data that has not been made nonvolatile. The protection operation will be described later. When the memory controller 20 completes the data protection operation, it transmits a response (also referred to as a "flash command completion response") to the host 2 indicating that the operation based on the flash command has been completed.

[0016] Next, an example of the internal configuration of the nonvolatile memory 10 will be described. The nonvolatile memory 10 includes one or more memory chips 11. For example, when the nonvolatile memory 10 includes multiple memory chips 11, each of the multiple memory chips 11 can operate independently. The number of memory chips 11 included in the nonvolatile memory 10 is arbitrary.

[0017] The memory chip 11 is, for example, a semiconductor chip equipped with a NAND type flash memory. The memory chip 11 includes a plurality of memory cell transistors (also written as "memory cells") that store data in a non-volatile manner. The memory chip 11 is connected to the memory controller 20 (specifically, the NAND controller 27) via a NAND bus.

[0018] Next, an example of the internal configuration of the memory controller 20 will be described. The memory controller 20 includes a host interface circuit (host I / F) 21, a CPU 22, a ROM (Read Only Memory) 23, a RAM (Random Access Memory) 24, a buffer memory 25, an ECC (Error Checking and Correcting) circuit 26, and a NAND controller 27. These circuits are connected to each other via an internal bus. Note that some or all of the functions of the host interface circuit 21, the ECC circuit 26, and the NAND controller 27 may be realized by a dedicated circuit, or the functions may be realized by the CPU 22 executing firmware.

[0019] The host interface circuit 21 is an interface circuit connected to the host 2. The host interface circuit 21 performs communication between the host 2 and the memory controller 20. The host interface circuit 21 transmits a request and user data received from the host 2 to the CPU 22 and the buffer memory 25, respectively. In addition, the host interface circuit 21 transmits user data in the buffer memory 25 to the host 2 based on an instruction from the CPU 22.

[0020] The CPU 22 is a processor. The CPU 22 controls the overall operation of the memory controller 20. For example, the CPU 22 issues commands to the non-volatile memory 10 to perform write and read operations based on requests from the host 2.

[0021] Furthermore, the CPU 22 executes a data saving operation and a data protection operation based on a flush command. Note that in the following description, a description of the saving operation will be omitted.

[0022] For example, the memory controller 20 according to the present embodiment writes multiple bits of data to a memory cell in two separate writes. Data stored in a memory cell where a first write operation has been performed but a second write operation has not been performed is data for which non-volatilization has not been completed. That is, data for which non-volatilization has not been completed is data for which some bits of the multiple bits constituting the data have been written to a memory cell and another part of the bits have not been written to the memory cell. In the protection operation, data stored in the non-volatile memory 10 and for which non-volatilization has not been completed is protected. More specifically, the CPU 22 writes valid data for which non-volatilization has not been completed to memory cells storing other data for which non-volatilization has not been completed in a memory area that includes memory cells in which data has not been written to at least some bits and is selected as a write destination, or a memory area that includes memory cells storing data for which non-volatilization has not been completed and may be selected as a write destination (hereinafter also referred to as a "write destination area"). That is, the CPU 22 moves (copies) data for which non-volatilization has not been completed within the write destination area. As a result, the CPU 22 completes the non-volatilization (protection) of the data stored in the memory cells to which the data has been copied.

[0023] The ROM 23 is a non-volatile memory. For example, the ROM 23 is an EEPROM. TM (Electrically Erasable Programmable Read-Only Memory). The ROM 23 is a non-transitory storage medium that stores firmware, programs, etc. For example, the CPU 22 loads firmware from the ROM 23 into the RAM 24 and executes it.

[0024] The RAM 24 is a volatile memory. The RAM 24 is a dynamic random access memory (DRAM) or a static random access memory (SRAM), etc. The RAM 24 stores firmware for managing the nonvolatile memory 10 and various management tables. For example, the RAM 24 stores a lookup table (LUT) as the management table. The lookup table is a table used by the memory controller 20 to manage the user data stored in the nonvolatile memory 10. The lookup table will be described later.

[0025] The buffer memory 25 is a volatile memory. The buffer memory 25 is a DRAM, an SRAM, or the like. The buffer memory 25 temporarily holds data read by the memory controller 20 from the nonvolatile memory 10, user data received from the host 2, and the like. For example, the buffer memory 25 includes an MLC buffer 251.

[0026] The MLC buffer 251 temporarily stores data read from the non-volatile memory 10 during the protection operation.

[0027] The ECC circuit 26 is a circuit that executes ECC processing. The ECC processing includes data encoding and decoding. For example, the ECC circuit 26 executes encoding processing of user data during a write operation to generate an error correction code. The ECC circuit 26 generates write data by adding an error correction code to the user data. The ECC circuit 26 also executes decoding processing during a read operation. That is, the ECC circuit 26 executes error correction of data read from the nonvolatile memory 10 using the error correction code. For example, in the case of a protection operation, the ECC circuit 26 may execute error correction of data read from the nonvolatile memory 10 and stored in the MLC buffer 251, or may execute error correction of data read from the nonvolatile memory 10 and store the error-corrected data in the MLC buffer 251.

[0028] The NAND controller 27 controls the non-volatile memory 10. For example, one NAND controller 27 can control multiple memory chips 11. The memory controller 20 includes one or more NAND controllers 27. In the example shown in FIG. 1, the memory controller 20 includes two NAND controllers 27. The NAND controller 27 transmits commands corresponding to a write operation, a read operation, an erase operation, or the like to the memory chip 11. During a read operation, the NAND controller 27 receives read data from the memory chip 11.

[0029] 1.1.3 Memory chip configuration Next, an example of the configuration of the memory chip 11 will be described with reference to Fig. 2. Fig. 2 is a block diagram showing an example of the basic configuration of the memory chip 11. In the example shown in Fig. 2, some of the connections between the components are indicated by arrows. However, the connections between the components are not limited to the example shown in Fig. 2.

[0030] 2, the memory chip 11 transmits and receives a signal DQ and timing signals DQS and DQSn to and from the memory controller 20 (more specifically, a NAND controller 27) via a NAND bus. The signal DQ is, for example, data DAT, an address ADD, or a command CMD. The timing signals DQS and DQSn are timing signals used when inputting and outputting data DAT. The timing signal DQSn is an inverted signal of the timing signal DQS.

[0031] The memory chip 11 receives various control signals from the memory controller 20 via the NAND bus. The memory chip 11 transmits a ready / busy signal RBn to the memory controller 20 via the NAND bus. The ready / busy signal RBn is a signal indicating whether the memory chip 11 is in a state in which it cannot receive a command CMD from the memory controller 20 (busy state) or in a state in which it can receive a command CMD (ready state).

[0032] Next, a description will be given of the internal configuration of the memory chip 11. The memory chip 11 includes an input / output circuit 101, a logic control circuit 102, an address register 103, a command register 104, a sequencer 105, a ready / busy circuit 106, and one or more planes PLN. Each plane PLN includes a memory cell array 111, a row decoder 112, a sense amplifier 113, a data register 114, and a column decoder 115.

[0033] The input / output circuit 101 is a circuit for inputting and outputting a signal DQ. The input / output circuit 101 is connected to the memory controller 20. The input / output circuit 101 is also connected to a logic control circuit 102, an address register 103, a command register 104, and a data register 114 of each plane PLN.

[0034] When the input signal DQ is an address ADD, the input / output circuit 101 transmits the address ADD to the address register 103. When the input signal DQ is a command CMD, the input / output circuit 101 transmits the command CMD to the command register 104.

[0035] When the input signal DQ is data DAT, the input / output circuit 101 receives the input signal DQ based on the timing signals DQS and DQSn. Then, the input / output circuit 101 transmits the data DAT to the data register 114 of the corresponding plane PLN based on the address ADD stored in the address register 103. The input / output circuit 101 also outputs the data DAT to the memory controller 20 as an output signal DQ together with the timing signals DQS and DQSn.

[0036] The logic control circuit 102 is a circuit that performs logic control based on a control signal. The logic control circuit 102 is connected to the memory controller 20. The logic control circuit 102 is also connected to the input / output circuit 101 and the sequencer 105. The logic control circuit 102 receives various control signals from the memory controller 20. The logic control circuit 102 controls the input / output circuit 101 and the sequencer 105 based on the received control signals.

[0037] The address register 103 is a register that temporarily stores an address ADD. The address register 103 is connected to the input / output circuit 101, and the row decoder 112 and column decoder 115 of each plane PLN. The address ADD includes a row address RA and a column address CA. The address register 103 transfers the row address RA to the row decoder 112. The address register 103 also transfers the column address CA to the column decoder 115.

[0038] The command register 104 is a register that temporarily stores the command CMD. The command register 104 is connected to the input / output circuit 101 and the sequencer 105. The command register 104 transfers the command CMD to the sequencer 105.

[0039] The sequencer 105 is a circuit that controls the entire memory chip 11. More specifically, for example, the sequencer 105 controls the ready / busy circuit 106, as well as the row decoder 112, the sense amplifier 113, the data register 114, and the column decoder 115 of each plane PLN. The sequencer 105 executes a write operation, a read operation, an erase operation, and the like based on a command CMD.

[0040] The ready / busy circuit 106 is a circuit that generates a ready / busy signal RBn. The ready / busy circuit 106 is connected to the memory controller 20. The ready / busy circuit 106 is also connected to the sequencer 105. The ready / busy circuit 106 transmits a ready / busy signal RBn based on the operating status of the sequencer 105 to the memory controller 20.

[0041] The plane PLN is a unit where data write and read operations are performed. In the example shown in Fig. 2, the memory chip 11 includes four planes PLN0, PLN1, PLN2, and PLN3. The number of planes PLN included in the memory chip 11 is not limited to four. The planes PLN0 to PLN3 can operate independently of each other. The planes PLN0 to PLN3 can also operate in parallel. In other words, the memory chip 11 has one or more planes PLN that can be controlled independently of each other.

[0042] Next, the internal structure of the plane PLN will be described. In the following, the case where the planes PLN0 to PLN3 have the same structure will be described. Note that the structure of each plane PLN may be different.

[0043] The memory cell array 111 is a set of multiple memory cells arranged in a matrix. The memory cell array 111 includes multiple blocks BLK. In the example shown in FIG. 2, the memory cell array 111 includes four blocks BLK0, BLK1, BLK2, and BLK3. The number of blocks BLK included in the memory cell array 111 is not limited to four. The block BLK is, for example, a set of multiple memory cells from which data is erased collectively. In other words, the block BLK is a data erasure unit. The configuration of the block BLK will be described in detail later.

[0044] The row decoder 112 is a decode circuit for a row address RA. The row decoder 112 is connected to the address register 103, the sequencer 105, and the memory cell array 111. The row decoder 112 selects one of the blocks BLK in the memory cell array 111 based on the result of decoding the row address RA. The row decoder 112 applies a voltage to the row direction wiring (word lines and select gate lines, which will be described later) of the selected block BLK.

[0045] The sense amplifier 113 is a circuit that writes and reads data DAT. The sense amplifier 113 is connected to the sequencer 105, the memory cell array 111, and the data register 114. The sense amplifier 113 reads the data DAT from the memory cell array 111 during a read operation. Moreover, the sense amplifier 113 supplies a voltage according to the data DAT to the memory cell array 111 during a write operation. The sense amplifier 113 includes a plurality of latch circuits for temporarily storing data.

[0046] The data register 114 is a register that temporarily stores data DAT. The data register 114 is connected to the input / output circuit 101, the sense amplifier 113, and the column decoder 115. The data register 114 includes a plurality of latch circuits. Each latch circuit temporarily stores data received from the input / output circuit 101 or data received from the sense amplifier 113.

[0047] The column decoder 115 is a circuit that decodes a column address CA. The column decoder 115 is connected to the address register 103 and the data register 114. The column decoder 115 receives the column address CA from the address register 103. The column decoder 115 selects a latch circuit in the data register 114 based on the decoded result of the column address CA.

[0048] 1.1.4 Memory cell array circuit configuration Next, an example of a circuit configuration of the memory cell array 111 will be described with reference to Fig. 3. Fig. 3 is a circuit diagram showing an example of a circuit configuration of the memory cell array 111.

[0049] The block BLK includes a plurality of string units SU. In the example shown in Fig. 3, the block BLK includes five string units SU0 to SU4. The number of string units SU included in the block BLK is arbitrary. The string unit SU is, for example, a collection of a plurality of NAND strings NS.

[0050] The NAND string NS is a set of multiple memory cells connected in series. Each of the multiple NAND strings NS in the string unit SU is connected to one of the bit lines BL0 to BLm (m is an integer equal to or greater than 1). Each NAND string NS includes multiple memory cells MC and selection transistors ST1 and ST2. In the example shown in FIG. 3, the NAND string NS includes eight memory cells MC0 to MC7.

[0051] The memory cell MC is a memory element that stores data in a non-volatile manner. The memory cell MC includes a control gate and a charge storage layer. The memory cell MC may be of a MONOS (Metal-Oxide-Nitride-Oxide-Silicon) type or a FG (Floating Gate) type.

[0052] The selection transistors ST1 and ST2 are switching elements and are used to select the string units SU during various operations.

[0053] The current paths of the select transistor ST2, memory cells MC0 to MC7, and select transistor ST1 in the NAND string NS are connected in series. The drain of the select transistor ST1 is connected to a bit line BL. The source of the select transistor ST2 is connected to a source line SL.

[0054] The control gates of the memory cells MC0 to MC7 in the same block BLK are connected to the word lines WL0 to WL7 in common between the string units SU. More specifically, for example, each of the string units SU0 to SU4 includes a plurality of memory cells MC0. The control gates of the plurality of memory cells MC0 in the block BLK are connected to one word line WL0. The same is true for the memory cells MC1 to MC7.

[0055] The gates of the multiple selection transistors ST1 in each string unit SU are commonly connected to one selection gate line SGD. More specifically, the gates of the multiple selection transistors ST1 in the string unit SU0 are commonly connected to a selection gate line SGD0. The gates of the multiple selection transistors ST1 in the string unit SU1 are commonly connected to a selection gate line SGD1. The gates of the multiple selection transistors ST1 in the string unit SU2 are commonly connected to a selection gate line SGD2. The gates of the multiple selection transistors ST1 in the string unit SU3 are commonly connected to a selection gate line SGD3. The gates of the multiple selection transistors ST1 in the string unit SU4 are commonly connected to a selection gate line SGD4.

[0056] The gates of the multiple selection transistors ST2 in the block BLK are commonly connected to a selection gate line SGS.

[0057] The word lines WL0 to WL7, the select gate lines SGD0 to SGD4, and the select gate line SGS are each connected to a row decoder 112.

[0058] The bit line BL is commonly connected to one NAND string NS of each of the multiple string units SU in each block BLK. Each bit line BL is connected to a sense amplifier 113.

[0059] The source line SL is shared among, for example, a plurality of blocks BLK.

[0060] A set of multiple memory cells MC connected to a common word line WL in one string unit SU is expressed as, for example, a "cell unit CU." In other words, a cell unit CU is a set of multiple memory cells MC selected collectively in a write operation or a read operation. A page is a unit of data that is collectively written (or collectively read) into a cell unit CU. For example, when a memory cell MC stores 1-bit data, the storage capacity of the cell unit CU is 1 page. In other words, the cell unit CU stores 1 page of data. Note that the cell unit CU may have a storage capacity of 2 or more pages based on the number of bits of data stored in the memory cells MC.

[0061] Hereinafter, a case where the memory cell MC is a QLC (Quad Level Cell) that stores 4-bit data will be described. Note that the memory cell MC is not limited to a QLC. For example, the memory cell MC may be a MLC (Multi Level Cell) that stores 2-bit data, a TLC (Triple Level Cell) that stores 3-bit data, or a PLC (Penta Level Cell) that stores 5-bit data.

[0062] 1.2 Threshold voltage distribution of memory cells Next, an example of the threshold voltage distribution of memory cells MC will be described with reference to Fig. 4. Fig. 4 is a diagram showing the threshold voltage distribution and data allocation when the memory cells MC are QLC.

[0063] 4, when a memory cell MC stores 4-bit data, the distribution of the threshold voltage is divided into 16. These 16 threshold voltage distributions (voltage ranges) are denoted as states S0 to S15 in order from the lowest threshold voltage.

[0064] Voltages V1 to V15 are verify voltages used in verify operations in the S0 to S15 states during a write operation. Voltage VREAD is a voltage applied to unselected word lines WL during a read operation. When voltage VREAD is applied to the gate of a memory cell MC, the memory cell MC is turned on regardless of the data stored therein. The relationship between voltages V1 to V15 and voltage VREAD is as follows: V1 <V2<V3<V4<V5<V6<V7<V8<V9<V10<V11<V12<V13<V14<V15<VREADである。

[0065] The S0 state corresponds to an erased state of the memory cell MC. The S1 to S15 states correspond to states in which charges are injected into the charge storage layer of the memory cell MC and data is written. The threshold voltage of the memory cell MC included in the S0 state is less than voltage V1. The threshold voltage of the memory cell MC included in the S1 to S14 states is greater than or equal to voltage V1 and less than voltage V2 to greater than or equal to voltage V14 and less than voltage V15, respectively. The threshold voltage of the memory cell MC included in the S15 state is greater than or equal to voltage V15 and less than voltage VREAD.

[0066] The setting value of the verify voltage and the setting value of the read voltage corresponding to each state may be the same or different. In the following, for the sake of simplicity, the case where the verify voltage and the read voltage are the same setting value will be described.

[0067] Hereinafter, the read operations using voltages V1 to V15 are referred to as read operations R1 to R15, respectively. Read operation R1 determines whether the threshold voltage of memory cell MC is less than voltage V1. Read operation R2 determines whether the threshold voltage of memory cell MC is less than voltage V2. Read operation R3 determines whether the threshold voltage of memory cell MC is less than voltage V3. The same applies below.

[0068] As described above, the threshold voltage of each memory cell MC belongs to one of 16 threshold voltage distributions. This allows each memory cell MC to take 16 different states. By assigning these states to binary data "0000" to "1111", each memory cell MC can store 4-bit data. Hereinafter, the 4-bit data will be referred to as "Lower bit", "Middle bit", "Upper bit", and "Top bit" from the least significant bit. In addition, a set of Lower bits stored in memory cells MC included in the same cell unit CU will be referred to as "Lower page data", a set of Middle bits will be referred to as "Middle page data", a set of Upper bits will be referred to as "Upper page data", and a set of Top bits will be referred to as "Top page data".

[0069] In the example shown in FIG. 4, data of "Lower bit / Middle bit / Upper bit / Top bit" is assigned to the memory cells MC included in each state as shown below.

[0070] S0 state: “1111” data S1 state: “1110” data S2 state: “1100” data S3 state: “1101” data S4 state: “1001” data S5 state: “1011” data S6 state: “0011” data S7 state: “0010” data S8 state: “1010” data S9 state: “1000” data S10 state: “0000” data S11 state: “0001” data S12 state: “0101” data S13 state: “0111” data S14 state: “0110” data S15 state: “0100” data

[0071] When reading data allocated in this way, the Lower bit is determined by read operations R6, R8, and R10. The Middle bit is determined by read operations R4 and R12. The Upper bit is determined by read operations R2, R5, R9, R13, and R15. The Top bit is determined by read operations R1, R3, R7, R11, and R14. That is, the values ​​of the Lower bit, Middle bit, Upper bit, and Top bit are determined by three, two, five, and five read operations, respectively. Hereinafter, this data allocation is referred to as the "3-2-5-5 code." Note that the allocation of data to states S0 to S15 is not limited to the 3-2-5-5 code.

[0072] 1.3 Write Operation Next, a write operation will be described. The write operation includes a program operation and a program verify operation. By repeating a combination of the program operation and the program verify operation (hereinafter referred to as a "program cycle"), the threshold voltage of the memory cell MC is raised to a target level.

[0073] The program operation is an operation for increasing the threshold voltage by injecting electrons into the charge storage layer (or forbidding the injection to maintain the threshold voltage).

[0074] The program verify operation is an operation in which data is read from the memory cells MC after the program operation to determine whether the threshold voltage of the memory cells MC has reached a target level. The memory cells MC whose threshold voltage has reached the target level are write-protected in the subsequent program cycle.

[0075] In this embodiment, the write operation to one cell unit CU is executed in two separate steps. Specifically, the write operation of four pages of data to the cell unit CU is executed in two separate steps: a first write operation (hereinafter referred to as a "first write operation") for writing Lower page data and Middle page data, and a second write operation (hereinafter referred to as a "second write operation") for writing Upper page data and Top page data. The write operation to one cell unit CU may be executed in three or more separate steps.

[0076] 1.3.1 First Write Operation First, the first write operation will be described with reference to Fig. 5 and Fig. 6. Fig. 5 is a sequence diagram showing an example of a write operation. Fig. 6 is a diagram showing a change in threshold voltage distribution of memory cells MC due to the first write operation. Note that the program verify operation is omitted in Fig. 5.

[0077] 5, the memory controller 20 causes the sequencer 105 to execute a first write operation. First, the memory controller 20 transmits lower page data and middle page data to the memory chip 11 (data in). The sequencer 105 temporarily stores the lower page data and middle page data in the latch circuit of the sense amplifier 113 (and the data register 114).

[0078] Next, the sequencer 105 executes a first write operation. More specifically, the sequencer 105 writes the Lower page data and the Middle page data to the target cell unit CU of the memory cell array 111.

[0079] As shown in Fig. 6, the threshold voltage of each memory cell MC belongs to one of four threshold voltage distributions by the first write operation. Hereinafter, the four threshold voltage distributions are referred to as M0 state, M1 state, M2 state, and M3 state from the lowest threshold voltage side. The memory cells MC included in each state are assigned "Lower bit / Middle bit" data as shown below.

[0080] M0 state: “11” data M1 state: “10” data M2 state: “00” data M3 state: “01” data

[0081] The M0 state includes memory cells MC that transition to the S0 state to the S3 state by the second write operation described below. The M1 state includes memory cells MC that transition to the S4 state, the S5 state, the S8 state, and the S9 state by the second write operation. The M2 state includes memory cells MC that transition to the S6 state, the S7 state, the S10 state, and the S11 state by the second write operation. The M3 state includes memory cells MC that transition to the S12 state to the S15 state by the second write operation.

[0082] The sequencer 105 uses voltages VM1, VM2, and VM3 as verify voltages in the first write operation. Voltage VM1 is a verify voltage used when writing the M1 state ("10" data). Voltage VM1 is equal to or greater than voltage V1 and less than voltage V4. Voltage VM2 is a verify voltage used when writing the M2 state ("00" data). Voltage VM2 is equal to or greater than voltage V4 and less than voltage V6. Voltage VM3 is a verify voltage used when writing the M3 state ("01" data). Voltage VM3 is equal to or greater than voltage V6 and less than voltage V12.

[0083] The threshold voltage of the memory cell MC included in the M0 state is less than the voltage V1. The threshold voltage of the memory cell MC included in the M1 state is equal to or greater than the voltage VM1 and less than the voltage V5. The threshold voltage of the memory cell MC included in the M2 state is equal to or greater than the voltage VM2 and less than the voltage V7. The threshold voltage of the memory cell MC included in the M3 state is equal to or greater than the voltage VM3 and less than the voltage V13.

[0084] Hereinafter, the state of the cell unit CU in which the first write operation has been performed but the second write operation has not been performed will be referred to as the "MLC state" or "intermediate stage of the write operation." Lower page data and Middle page data are written to the cell unit CU in the MLC state, and Upper page data and Top page data are not written. In this case, the Lower page data and Middle page data will be collectively referred to as "MLC data" or "intermediate data of the write operation."

[0085] 1.3.2 Second write operation Next, the second write operation will be described with reference to Figures 5 and 7. Figure 7 is a diagram showing changes in the threshold voltage distribution of memory cells MC due to the second write operation.

[0086] 5, the memory controller 20 causes the sequencer 105 to execute a second write operation. First, the memory controller 20 transmits the Upper page data and the Top page data to the memory chip 11 (data in). The sequencer 105 temporarily stores the Upper page data and the Top page data in the latch circuit of the sense amplifier 113 (and the data register 114).

[0087] Next, the sequencer 105 executes a second write operation. More specifically, first, the sequencer 105 reads out the Lower page data and the Middle page data from the corresponding cell unit CU of the memory cell array 111, and temporarily stores them in the latch circuit of the sense amplifier 113 (and the data register 114). Next, the sequencer 105 executes a write operation of the Upper page data and the Top page data in the target cell unit CU based on the Lower page data, the Middle page data, the Upper page data, and the Top page data stored in the latch circuit of the sense amplifier 113 (and the data register 114). Note that the sequencer 105 may transmit the Lower page data and the Middle page data to the memory controller 20 in order to execute error correction of the read Lower page data and the Middle page data. In this case, the memory controller 20 executes a decoding process and an encoding process of the Lower page data and the Middle page data in the ECC circuit 26. As a result, the ECC circuit 26 generates the corrected Lower page data and the Middle page data. The memory controller 20 transmits the corrected Lower page data and Middle page data to the memory chip 11 together with the Upper page data and Top page data.

[0088] As shown in FIG. 7, 16 threshold voltage distributions are formed by the second write operation. For example, by the second write operation, the memory cell MC that belonged to the threshold voltage distribution of the M0 state becomes one of the threshold voltage distributions of the S0 state to the S3 state. The memory cell MC that belonged to the threshold voltage distribution of the M1 state becomes one of the threshold voltage distributions of the S4 state, the S5 state, the S8 state, and the S9 state. The memory cell MC that belonged to the threshold voltage distribution of the M2 state becomes one of the threshold voltage distributions of the S6 state, the S7 state, the S10 state, and the S11 state. The memory cell MC that belonged to the threshold voltage distribution of the M3 state becomes one of the threshold voltage distributions of the S12 state to the S15 state.

[0089] For example, a memory cell MC that belongs to the threshold voltage distribution of the M0 state and has stored data "11" comes to belong to the threshold voltage distribution of the S3 state by the second write operation, and as a result, comes to store data "1101".

[0090] For example, a memory cell MC that belongs to the threshold voltage distribution of the M1 state and has stored data "10" comes to belong to the threshold voltage distribution of the S4 state through the second write operation, and as a result, comes to store data "1001."

[0091] For example, a memory cell MC that belongs to the threshold voltage distribution of the M2 state and has stored data "00" comes to belong to the threshold voltage distribution of the S7 state through the second write operation, and as a result, comes to store data "0010".

[0092] For example, a memory cell MC that belongs to the threshold voltage distribution of the M2 state and has stored data "01" comes to belong to the threshold voltage distribution of the S14 state by the second write operation, and as a result, comes to store data "0110".

[0093] 1.3.3 Relationship between lookup table and write destination area Next, an example of the relationship between the lookup table LUT and the write destination area will be described with reference to FIG. 8. FIG. 8 is a diagram showing an example of the relationship between the lookup table LUT and the write destination area. The upper table of FIG. 8 shows the lookup table LUT. The lower table of FIG. 8 shows a state in which data corresponding to the lookup table LUT is stored in the write destination area. In the write destination area, one square frame corresponds to one page data. WRT1 and WRT2 respectively indicate areas to be written by the first write operation and the second write operation. L, M, U, and T respectively indicate Lower page data, Middle page data, Upper page data, and Top page data.

[0094] In the following description, a cell unit CU corresponding to a word line WLi (i is an integer equal to or greater than 0) and a string unit SUj (j is an integer equal to or greater than 0) in a certain physical block (block BLK) is denoted as a "cell unit CU_WLi_SUj." For example, a cell unit CU corresponding to a word line WL0 and a string unit SU0 is denoted as a cell unit CU_WL0_SU0.

[0095] As shown in FIG. 8, the lookup table LUT includes a plurality of entries indexed by logical cluster address numbers LCAN (Logical Cluster Address Numbers). The logical cluster address numbers LCAN are identification numbers of logical cluster addresses. The logical cluster addresses are logical addresses for identifying user data in cluster units. The example shown in FIG. 8 shows a case where one cluster includes one page of data. The cluster size is arbitrary. For example, one cluster may include multiple page data. Furthermore, one page of data may be composed of multiple clusters.

[0096] Here, valid data means data associated with a certain logical cluster address number LCAN. For example, in the lookup table LUT, data associated with a logical cluster address number LCAN (more specifically, data stored in a physical address mapped to the logical cluster address number LCAN) is valid data and may be read by the host 2 later. Invalid data means data that is not associated with any logical cluster address number LCAN. Data that is not associated with any logical cluster address number LCAN is data that may no longer be read by the host 2.

[0097] Each entry stores information on a logical block number LBN, a physical block number PBN, a word line WL, a string unit SU, and a page type PT as a physical address specifying a memory area of ​​the nonvolatile memory 10.

[0098] The logical block number LBN is an identification number of the logical block.

[0099] The physical block number PBN is an identification number of a physical block, that is, a block BLK. The example shown in FIG. 8 shows a case where four physical blocks (that is, four blocks BLK) are assigned to one logical block. The number of physical blocks assigned to one logical block is arbitrary. The four physical blocks can perform a write operation in parallel. For example, in a write operation to the four physical blocks, four cell units CU corresponding to the same word line WL and the same string unit SU are selected collectively. The four page data written to the four cell units CU can also be collectively expressed as "logical page data". In this embodiment, the CPU 22 collectively writes two page data (Lower page data / Middle page data) by the first write operation or writes two page data (Upper page data / Top page data) by the second write operation in the four physical blocks (cell units CU). That is, eight page data (two logical page data) corresponding to eight logical cluster address numbers LCAN are written collectively. The execution timing of the write operation in each physical block may be different.

[0100] Multiple physical blocks corresponding to one logical block number LBN may be assigned blocks BLK included in different memory chips 11, or blocks BLK included in different planes PLN of one memory chip 11, or a combination of these.

[0101] The numbers of the word lines WL and the string units SU correspond to the cell units CU that store data.

[0102] The page type PT indicates the type of page data in the cell unit CU.

[0103] The lookup table LUT is updated when a write operation of user data is executed, and also when a trim command received from the host 2 designates valid data as invalid data.

[0104] 8, in each entry of logical cluster address numbers LCAN0 to LCAN3 in the lookup table LUT, "0" is registered in the logical block number LBN field, and "0" to "3" are registered in order in the physical block number PBN field. Furthermore, "0" (i.e., WL0) is registered in the word line WL field of each entry, "0" (i.e., SU0) is registered in the string unit SU field, and "Lower" is registered in the page type PT field. Four page data corresponding to logical cluster address numbers LCAN0 to LCAN3 constitute one logical page data.

[0105] In each entry of logical cluster address numbers LCAN4 to LCAN7 in the lookup table LUT, "0" is registered in the logical block number LBN field, and "0" to "3" are registered in order in the physical block number PBN field. Furthermore, "0" is registered in the word line WL field of each entry, "0" is registered in the string unit SU field, and "Middle" is registered in the page type PT field. The four page data corresponding to logical cluster address numbers LCAN4 to LCAN7 constitute one logical page data.

[0106] The page data to be written in the write destination area is represented as data Dx_y (x is an integer equal to or greater than 0, and y is an integer equal to or greater than 0 and equal to or less than 7). The "x" in the data Dx_y indicates the execution order of the write operation in the write destination area. The "y" in the data Dx_y indicates the order of the write data. For example, when writing eight page data represented by data D0_0 to D0_7 collectively, the CPU 22 executes a first write operation by referring to the lookup table LUT. More specifically, the CPU 22 selects the cell units CU_WL0_SU0 in the four physical blocks corresponding to the logical block number LBN0 (physical block numbers PBN0 to PBN3). Then, the CPU 22 executes the first write operation to write the data D0_0 to D0_7 into the four cell units CU_WL0_SU0. At this time, data D0_0 to D0_3 as the lower page data and data D0_4 to D0_7 as the middle page data are written to the cell unit CU_WL0_SU0 of the four physical blocks corresponding to the physical block numbers PBN0 to PBN3. More specifically, data D0_0 and D0_4 are written as the lower page data and the middle page data to the cell unit CU_WL0_SU0 of the physical block corresponding to the physical block number PBN0. Data D0_1 and D0_5 are written as the lower page data and the middle page data to the cell unit CU_WL0_SU0 of the physical block corresponding to the physical block number PBN1. Data D0_2 and D0_6 are written as the lower page data and the middle page data to the cell unit CU_WL0_SU0 of the physical block corresponding to the physical block number PBN2. Data D0_3 and D0_7 are written as Lower page data and Middle page data in the cell unit CU_WL0_SU0 of the physical block corresponding to physical block number PBN3.

[0107] 1.3.4 Execution Order of First Write Operation and Second Write Operation Next, an example of the execution order of the first write operation and the second write operation will be described with reference to FIG. 9. FIG. 9 is a diagram showing an example of the execution order of the first write operation and the second write operation. The example shown in FIG. 9 shows a case where a logical block identified by two logical block numbers LBN0 and LBN1 is selected as the write destination area. That is, two logical blocks (eight physical blocks) corresponding to logical block numbers LBN0 and LBN1 belong to the write destination area. Note that, in the example shown in FIG. 9, for the sake of simplicity, each block BLK includes two string units SU0 and SU1.

[0108] 9, first, the CPU 22 selects the cell units CU_WL0_SU0 in the four physical blocks corresponding to logical block number LBN0 (physical block numbers PBN0 to PBN3) as a write destination of the 0th data. The CPU 22 executes a first write operation to write data D0_0 to D0_3 as Lower page data and data D0_4 to D0_7 as Middle page data to the four cell units CU_WL0_SU0.

[0109] Next, the CPU 22 selects the cell units CU_WL0_SU0 in the four physical blocks corresponding to the logical block number LBN1 (physical block numbers PBN4 to PBN7) as the write destination of the first data. The CPU 22 executes a first write operation to write data D1_0 to D1_3 as Lower page data and data D1_4 to D1_7 as Middle page data to the four cell units CU_WL0_SU0.

[0110] Next, the CPU 22 selects the cell units CU_WL0_SU1 in the four physical blocks corresponding to the logical block number LBN0 (physical block numbers PBN0 to PBN3) as the write destination of the second data. The CPU 22 executes a first write operation to write data D2_0 to D2_3 as Lower page data and data D2_4 to D2_7 as Middle page data to the four cell units CU_WL0_SU1.

[0111] Next, the CPU 22 selects the cell units CU_WL0_SU1 in the four physical blocks corresponding to the logical block number LBN1 (physical block numbers PBN4 to PBN7) as the write destination of the third data. The CPU 22 executes a first write operation to write data D3_0 to D3_3 as Lower page data and data D3_4 to D3_7 as Middle page data to the four cell units CU_WL0_SU1.

[0112] Next, the CPU 22 selects the cell unit CU_WL1_SU0 in each of the four physical blocks corresponding to the logical block number LBN0 (physical block numbers PBN0 to PBN3) as a write destination of the fourth data. The CPU 22 executes a first write operation to write data D4_0 to D4_3 as Lower page data and data D4_4 to D4_7 as Middle page data to the four cell units CU_WL1_SU0.

[0113] Next, the CPU 22 selects the cell unit CU_WL1_SU0 in each of the four physical blocks corresponding to the logical block number LBN1 (physical block numbers PBN4 to PBN7) as a write destination of the fifth data. The CPU 22 executes a first write operation to write data D5_0 to D5_3 as Lower page data and data D5_4 to D5_7 as Middle page data to the four cell units CU_WL1_SU0.

[0114] Next, the CPU 22 selects the cell units CU_WL0_SU0 in the four physical blocks corresponding to the logical block number LBN0 (physical block numbers PBN0 to PBN3) as the write destination of the sixth data. The CPU 22 executes a second write operation to write data D6_0 to D6_3 as Upper page data and data D6_4 to D6_7 as Top page data to the four cell units CU_WL0_SU0.

[0115] Next, the CPU 22 selects the cell units CU_WL0_SU0 in the four physical blocks corresponding to the logical block number LBN1 (physical block numbers PBN4 to PBN7) as the write destination of the seventh data. The CPU 22 executes a second write operation to write data D7_0 to D7_3 as Upper page data and data D7_4 to D7_7 as Top page data to the four cell units CU_WL0_SU0.

[0116] Next, the CPU 22 selects the cell units CU_WL1_SU1 in the four physical blocks corresponding to the logical block number LBN0 (physical block numbers PBN0 to PBN3) as the write destination of the eighth data. The CPU 22 executes a first write operation to write data D8_0 to D8_3 as Lower page data and data D8_4 to D8_7 as Middle page data to the four cell units CU_WL1_SU1.

[0117] Next, the CPU 22 selects the cell units CU_WL1_SU1 in the four physical blocks corresponding to the logical block number LBN1 (physical block numbers PBN4 to PBN7) as the write destination of the ninth data. The CPU 22 executes a first write operation to write data D9_0 to D9_3 as Lower page data and data D9_4 to D9_7 as Middle page data to the four cell units CU_WL1_SU1.

[0118] 9, in the eight physical blocks corresponding to the physical block numbers PBN0 to PBN7, the 24 cell units CU corresponding to the combination of the word line WL0 and the string unit SU1, the combination of the word line WL1 and the string unit SU0, and the combination of the word line WL1 and the string unit SU1 are in the MLC state. That is, the 48 data D2_0 to D2_7, D3_0 to D3_7, D4_0 to D4_7, D5_0 to D5_7, D8_0 to D8_7, and D9_0 to D9_7 are MLC data.

[0119] The CPU 22 first selects logical block numbers LBN0 and LBN1 in order as a write destination, and selects a cell unit CU corresponding to the same word line WL and string unit SU of each physical block. Then, the CPU 22 selects logical block numbers LBN0 and LBN1 in order as a next write destination, and selects a cell unit CU corresponding to the next word line WL or the next string unit SU of each physical block.

[0120] Focusing on one string unit SU in one physical block, the CPU 22 executes a first write operation in a cell unit CU corresponding to a first numbered word line WL (e.g., word line WL0), and then executes a first write operation in a cell unit CU corresponding to a second numbered word line WL (e.g., word line WL1). Then, after the first write operation is completed in a cell unit CU corresponding to a second numbered word line WL (e.g., word line WL1), the CPU 22 executes a second write operation in a cell unit CU corresponding to a first numbered word line WL (e.g., word line WL0). The CPU 22 selects cell units CU in the same order from the second numbered word line WL (e.g., word line WL1) onward.

[0121] For example, the CPU 22 sets a write pointer indicating the write operation to be executed next, and manages the order of the write operations. In the example shown in Fig. 9, the CPU 22 sets the second write operation in the cell unit CU_WL0_SU1 of the physical block corresponding to the physical block number PBN0 as the target of the write pointer.

[0122] Hereinafter, in a plurality of page data, the page data that is written first in the order of writing is referred to as "first-written data", and the page data that is written later is referred to as "last-written data". For example, data D0_y is the first-written data relative to data D1_y, and data 0_y is the first-written data relative to data 6_y. Furthermore, among the eight page data for which a write operation is executed collectively, the Middle page data is referred to as the last-written data of the Lower page data, the Top page data is referred to as the last-written data of the Upper page data, and further, the data with the larger physical block number PBN is referred to as the last-written data. For example, among data D0_0 to D0_7, data D0_0 is the most first-written data, and data D0_7 is the most last-written data. Among data D6_0 to D6_7, data D6_0 is the most first-written data, and data D6_7 is the most last-written data.

[0123] The CPU 22 manages the physical address corresponding to the most recently written (latest) Middle page data in the MLC state (the last written Middle page data) as an “MLC tail address.” In the example shown in Fig. 9, in the physical block corresponding to the physical block number PBN7, the physical address of the Middle page data D9_7 written in the cell unit CU_WL1_SU1 is set as the MLC tail address.

[0124] 1.4 Protection Operation Next, the protection operation will be described with reference to Fig. 10 and Fig. 11. Fig. 10 is a conceptual diagram showing an example of a write destination area before and after the protection operation. Fig. 11 is a diagram showing changes in the lookup table LUT before and after the protection operation. Note that, in the example shown in Fig. 10 and Fig. 11, for the sake of simplicity, a case is shown in which a logical block identified by logical block number LBN0 is selected as the write destination area. In other words, the logical block (four physical blocks) corresponding to logical block number LBN0 belongs to the write destination area.

[0125] As shown in FIG. 10, for example, in a state before receiving a flash command, data D0_0 to D0_3 are written as lower page data, and data D0_4 to D0_7 are written as middle page data, in four cell units CU_WL0_SU0. Data D1_0 to D1_3 are written as lower page data, and data D1_4 to D1_7 are written as middle page data, in four cell units CU_WL0_SU1. Data D0_0 to D0_7 and D1_0 to D1_7 are MLC data. A physical address corresponding to data D1_7 (a physical address corresponding to logical cluster address number LCAN15) is set as an MLC tail address. A second write operation in cell unit CU_WL0_SU0 of a physical block corresponding to physical block number PBN0 is set as a target of the write pointer.

[0126] 11, the data D0_0 to D0_7 correspond to the logical cluster address numbers LCAN0 to LCAN7, respectively, of the lookup table LUT, and the data D1_0 to D1_7 correspond to the logical cluster address numbers LCAN8 to LCAN15, respectively, of the lookup table LUT.

[0127] In this state, when the CPU 22 receives a flash command, it executes a protection operation. The CPU 22 executes a second write operation using the MLC data in the write destination area. More specifically, the CPU 22 copies the MLC data to be written later as the Upper page data and Top page data of the cell unit CU to which the previously written MLC data has been written. This completes the non-volatilization of the previously written MLC data and the later written MLC data all at once.

[0128] In the example shown in FIG. 10, the CPU 22 executes the second write operation to write data D1_7 to D1_4 as Upper page data and data D1_3 to D1_0 as Top page data to the four cell units CU_WL0_SU0. At this time, the MLC data to be copied is read in order from data D1_7 designated by the MLC tail address toward the pre-written MLC data. In the example shown in FIG. 10, data D1_7, D1_6, D1_5, D1_4, D1_3, D1_2, and D1_0 are read in this order. Therefore, the write order of the copy destination data is the reverse of the write order of the copy source data. More specifically, data D1_7 and D1_3 are written as Upper page data and Top page data to the cell unit CU_WL0_SU0 of the physical block corresponding to the physical block number PBN0. Data D1_6 and D1_2 are written as the Upper page data and the Top page data to the cell unit CU_WL0_SU0 of the physical block corresponding to the physical block number PBN1. Data D1_5 and D1_1 are written as the Upper page data and the Top page data to the cell unit CU_WL0_SU0 of the physical block corresponding to the physical block number PBN2. Data D1_4 and D1_0 are written as the Upper page data and the Top page data to the cell unit CU_WL0_SU0 of the physical block corresponding to the physical block number PBN3.

[0129] As shown in Fig. 11, the CPU 22 updates the lookup table LUT before executing the second write operation. More specifically, the physical addresses corresponding to the data D1_0 to D1_7 (physical addresses corresponding to the logical cluster address numbers LCAN8 to LCAN15) are changed to physical addresses of the copy destination. As a result, the data D1_0 to D1_7 stored in the four cell units CU_WL0_SU1 are made invalid data. The CPU 22 executes the second write operation by referring to the lookup table LUT.

[0130] 1.4.1 Protection operation flow Next, an example of the flow of the protection operation will be described with reference to Fig. 12 to Fig. 14. Fig. 12 is a flowchart showing the overall flow of the protection operation. Fig. 13 is a flowchart showing details of step S6 in Fig. 12. Fig. 14 is a flowchart showing details of step S9 in Fig. 12.

[0131] First, the overall flow of the protection operation will be described.

[0132] As shown in FIG. 12, when the CPU 22 receives a flush command from the host 2 (S1), it starts a protection operation.

[0133] The CPU 22 checks whether there is MLC data in the write destination area (S2).

[0134] If there is no MLC data (S2_False), the CPU 22 transmits a flash command completion response to the host 2 (S10) and ends the protection operation.

[0135] If there is MLC data (S2_True), the CPU 22 sets the MLC tail address to the read target address of the MLC data (S3).

[0136] The CPU 22 reads out the page data corresponding to the read target address from the non-volatile memory 10 (S4). If the read data is valid data, the CPU 22 stores the data in the MLC buffer 251.

[0137] The CPU 22 checks whether the amount of data stored in the MLC buffer 251 has reached a data amount that allows execution of the second write operation (S5). For example, as described with reference to Figs. 8 and 9, in this embodiment, eight page data are written collectively to four cell units CU. In such a case, the MLC buffer 251 is configured to be able to store eight pages of data. The CPU 22 checks whether eight page data are stored in the MLC buffer 251.

[0138] If the amount of data stored in the MLC buffer 251 has reached the amount of data necessary to perform the second write operation (S5_True), the CPU 22 executes the second write operation using the data stored in the MLC buffer 251 as Upper page data and Top page data (S6).

[0139] If the amount of data stored in the MLC buffer 251 has not reached the amount of data necessary to perform the second write operation (S5_False), or after the second write operation of step S6 is completed, the CPU 22 checks whether there is MLC data in the write destination area that has not yet been read (S7).

[0140] If there is unread MLC data (S7_True), the CPU 22 updates the read target address (S8). More specifically, the CPU 22 changes the read target address to the physical address of the pre-written data that is one address ahead of the data at the current read target address. After updating the read target address, the CPU 22 proceeds to step S4.

[0141] If there is no unread MLC data (S7_False), the CPU 22 executes (S9) the final second write operation using the data stored in the MLC buffer 251. When the final second write operation is completed, the CPU 22 transmits a flash command completion response to the host 2 (S10) and ends the protection operation.

[0142] Next, the second write operation executed in step S6 will be described in detail.

[0143] As shown in Fig. 13, the CPU 22 first checks the write pointer (S61). As described with reference to Fig. 9, the execution order of the write operations is predetermined. Therefore, depending on the timing of receiving the flash command, the next write operation may be the first write operation. Therefore, the CPU 22 checks the write pointer to confirm whether the next write operation is the second write operation.

[0144] If the next write operation is not the second write operation (S62_False), the CPU 22 executes the first write operation using padding data (invalid data) (S63). The CPU 22 repeats the loop of steps S62 and S63 until the next write operation to be executed is the second write operation.

[0145] If the next write operation is the second write operation (S62_True), the CPU 22 executes the second write operation using the data in the MLC buffer 251 (S64). That is, the second write operation described in step S6 is executed.

[0146] After executing the second write operation, the CPU 22 updates the lookup table LUT (S65).

[0147] Next, the final second write operation executed in step S9 will be described in detail.

[0148] As shown in FIG. 14, the CPU 22 first checks whether or not there is any unwritten data remaining in the MLC buffer 251 (S91).

[0149] When there is no data remaining in the MLC buffer 251 (S92_False), the CPU 22 ends the last second write operation, that is, the last second write operation of step S9 is skipped.

[0150] If data remains in the MLC buffer 251 (S92_True), the CPU 22 checks the write pointer to determine whether the next write operation is the second write operation (S93).

[0151] If the next write operation is not the second write operation (S93_False), the CPU 22 executes the first write operation using padding data (invalid data) (S94). The CPU 22 repeats the loop of steps S93 and S94 until the next write operation to be executed is the second write operation.

[0152] If the next write operation is the second write operation (S93_True), the CPU 22 checks whether the amount of data stored in the MLC buffer 251 has reached the amount of data that allows the second write operation to be executed (S95).

[0153] If the amount of data stored in the MLC buffer 251 has not reached the amount of data that allows the second write operation to be executed (S95_False), the CPU 22 fills the MLC buffer 251 with padding data so that the sum of the amount of data stored in the MLC buffer 251 and the amount of padding data reaches the amount of data that allows the second write operation to be executed (S96). That is, the CPU 22 inserts the padding data into the free area of ​​the MLC buffer 251.

[0154] When the amount of data stored in the MLC buffer 251 reaches the amount of data that allows the second write operation to be executed (S95_True), or after filling the MLC buffer 251 with padding data (S96), the CPU 22 executes the final second write operation using the data in the MLC buffer 251 (S97). That is, the final second write operation described in step S9 is executed.

[0155] After executing the second write operation, the CPU 22 updates the lookup table LUT (S98).

[0156] 1.4.2 Example of read target address update order Next, a specific example of the update order of the read target addresses will be described with reference to Fig. 15. Fig. 15 is a diagram showing a specific example of the update order of the read target addresses. The example shown in Fig. 15 shows a case where the read target addresses are set for the data write state shown in Fig. 9.

[0157] As shown in Fig. 15, the read target addresses are set in order from the most recently written MLC data to the most recently written MLC data. In the example shown in Fig. 15, there are 48 MLC data (Lower page data or Middle page data) for which read target addresses are set.

[0158] In this state, first, the MLC tail address is set to the 0th (initial position) read target address. In the example shown in Fig. 15, the physical address of the Middle page data stored in the cell unit CU_WL1_SU1 of the physical block corresponding to the physical block number PBN7 is set to the 0th read target address.

[0159] Next, in the other three physical blocks selected collectively during the write operation, the physical addresses of the Middle page data stored in the cell unit CU_WL1_SU1 are set to the first to third read target addresses in the order of physical block numbers PBN6 to PBN4. Similarly, in the four physical blocks corresponding to physical block numbers PBN7 to PBN4, the physical addresses of the Lower page data stored in the cell unit CU_WL1_SU1 are set to the fourth to seventh read target addresses in the order of physical block numbers PBN7 to PBN4.

[0160] Similarly, the 8th to 15th read target addresses are set in sequence in the cell unit CU_WL1_SU1 of the four physical blocks corresponding to the physical block numbers PBN3 to PBN0. The 16th to 47th read target addresses are set in sequence in the same manner. However, since the later-written MLC data is written by the second write operation to the cell unit CU in which the previously-written MLC data is written, not all 48 data are necessarily set as read target addresses. The CPU 22 may end the update of the read target addresses when there is no more MLC data to be read.

[0161] 1.4.3 Specific examples of protective operations Next, a specific example of the protection operation will be described with reference to Fig. 16 to Fig. 25. Fig. 16 to Fig. 25 are diagrams showing a specific example of the write destination area and the state of data stored in the MLC buffer 251.

[0162] As shown in FIG. 16, for example, data D0_0 to D3_7 are stored in the write destination area. In this case, data D0_0 to D0_7, D1_0 to D1_7, D2_0 to D2_7, and D3_0 to D3_7 are MLC data. As the MLC tail address, the physical address of data D3_7 stored in cell unit CU_WL0_SU1 of the physical block corresponding to physical block number PBN7 is set. As the write pointer, the first write operation in cell unit CU_WL1_SU0 of the physical block corresponding to physical block number PBN0 is set. In the example shown in FIG. 16, data D0_2, D1_3, D2_2, D2_5, D2_6, and D3_5 are invalid data.

[0163] When the CPU 22 receives a flush command in this state, the CPU 22 starts a protection operation and sets the MLC tail address as the read target address.

[0164] As shown in FIG. 17, the CPU 22 reads data corresponding to the read target address in order while moving the read target address. The CPU 22 stores valid data among the read data in the MLC buffer 251. In the example shown in FIG. 17, the CPU 22 reads data D3_7 to D3_0 and D2_7 in order. The CPU 22 stores the valid data D3_7, D3_6, D3_4, D3_3, D3_2, D3_1, D3_0, and D2_7 in the MLC buffer 251 in the order in which they were read. More specifically, first, the data D3_7, D3_6, D3_4, and D3_3 are stored in order in the buffers 0 to 3 corresponding to the Upper page data of the MLC buffer 251. Next, the data D3_2, D3_1, D3_0, and D2_7 are stored in order in the buffers 0 to 3 corresponding to the Top page data of the MLC buffer 251.

[0165] When the eight page data are stored in the MLC buffer 251 and the second write operation is ready to be executed, the CPU 22 checks the write pointer. In the example shown in Fig. 17, the write pointer is set to the first write operation in the cell unit CU_WL1_SU0 of the physical block corresponding to the physical block number PBN0.

[0166] As shown in Fig. 18, the CPU 22 executes a first write operation using padding data PD until the write operation to be executed next becomes the second write operation. In the example shown in Fig. 18, the CPU 22 executes the first write operation to write padding data PD as lower page data and middle page data to the cell unit CU_WL1_SU0 of the eight physical blocks corresponding to the physical block numbers PBN0 to PBN7. As a result, the second write operation in the cell unit CU_WL0_SU0 of the physical block corresponding to the physical block number PBN0 is set as the next write pointer.

[0167] As shown in Fig. 19, the CPU 22 executes a second write operation to write data of the MLC buffer 251 as Upper page data and Top page data to the cell unit CU_WL0_SU0 of the four physical blocks corresponding to the physical block numbers PBN0 to PBN3. In the example shown in Fig. 19, data D3_7 and D3_2 are written as Upper page data and Top page data to the CU_WL0_SU0 of the physical block corresponding to the physical block number PBN0. Data D3_6 and D3_1 are written as Upper page data and Top page data to the cell unit CU_WL0_SU0 corresponding to the physical block number PBN1. Data D3_4 and D3_0 are written as Upper page data and Top page data to the cell unit CU_WL0_SU0 of the physical block corresponding to the physical block number PBN2. Data D3_3 and D2_7 are written as Upper page data and Top page data in the cell unit CU_WL0_SU0 of the physical block corresponding to physical block number PBN3.

[0168] After the second write operation is completed, the CPU 22 updates the lookup table LUT so that the data D3_7, D3_6, D3_4, D3_3, D3_2, D3_1, D3_0, and D2_7 stored in the cell unit CU_WL0_SU1 of the five physical blocks corresponding to the physical block numbers PBN3 to PBN7 are invalidated. The data in the MLC buffer 251 is invalidated. The second write operation in the cell unit CU_WL0_SU0 of the physical block corresponding to the physical block number PBN4 is set as the next write pointer.

[0169] As shown in Fig. 20, when valid MLC data that has not yet been read remains in the write destination area, the CPU 22 moves the read target address and sequentially reads data corresponding to the read target address. The CPU 22 stores valid data from the read data in the MLC buffer 251. In the example shown in Fig. 20, the CPU 22 sequentially reads data D2_6 to D2_0 and D1_7 to D1_4. The CPU 22 stores valid data from the read data, that is, data D2_4, D2_3, D2_1, D2_0, D1_7, D1_6, D1_5, and D1_4, in the MLC buffer 251 in the order in which they were read.

[0170] When the eight page data are stored in the MLC buffer 251 and the second write operation is ready to be performed, the CPU 22 checks the write pointer. In the example shown in Fig. 20, the write pointer is set to the second write operation in the cell unit CU_WL0_SU0 of the physical block corresponding to the physical block number PBN4.

[0171] As shown in Fig. 21, the CPU 22 executes a second write operation to write data of the MLC buffer 251 as Upper page data and Top page data to the cell unit CU_WL0_SU0 of the four physical blocks corresponding to the physical block numbers PBN4 to PBN7. In the example shown in Fig. 21, data D2_4 and D1_7 are written as Upper page data and Top page data to the cell unit CU_WL0_SU0 of the physical block corresponding to the physical block number PBN4. Data D2_3 and D1_6 are written as Upper page data and Top page data to the cell unit CU_WL0_SU0 of the physical block corresponding to the physical block number PBN5. Data D2_1 and D1_5 are written as Upper page data and Top page data to the cell unit CU_WL0_SU0 of the physical block corresponding to the physical block number PBN6. Data D2_0 and D1_4 are written as Upper page data and Top page data in the cell unit CU_WL0_SU0 of the physical block corresponding to physical block number PBN7.

[0172] After the second write operation is completed, the CPU 22 updates the lookup table LUT so that the data D2_4, D2_3, D2_1, D2_0, D1_7, D1_6, D1_5, and D1_4 in the write destination area are invalidated. The data in the MLC buffer 251 is invalidated. The first write operation in the cell unit CU_WL1_SU1 of the physical block corresponding to the physical block number PBN1 is set as the next write pointer.

[0173] Since there is no valid MLC data that has not yet been read out in the write destination area, the CPU 22 transmits a flash command completion response to the host 2 and ends the protection operation.

[0174] Next, a specific example of the final second write operation will be described.

[0175] 22, for example, the CPU 22 executes a first write operation after the example shown in FIG 21 to write data D8_0 to D8_3 as Lower page data and data D8_4 to D8_7 as Middle page data to cell units CU_WL1_SU1 of four physical blocks corresponding to physical block numbers PBN0 to PBN3, respectively. Next, the CPU 22 executes a first write operation to write data D9_0 to D9_3 as Lower page data and data D9_4 to D9_7 as Middle page data to cell units CU_WL1_SU1 of four physical blocks corresponding to physical block numbers PBN4 to PBN7, respectively. Furthermore, the CPU 22 executes a second write operation to write data D10_0 to D10_3 as Upper page data and data D10_4 to D10_7 as Top page data to the cell units CU_WL0_SU1 of the four physical blocks corresponding to the physical block numbers PBN0 to PBN3, respectively.

[0176] In this state, the data D10_0 to D10_7, D8_0 to D8_7, D9_0 to D9_7, and the padding data PD of the eight cell units CU_WL1_SU0 are MLC data. As the MLC tail address, the physical address of the data D9_7 of the cell unit CU_WL1_SU1 of the physical block corresponding to the physical block number PBN7 is set. As the write pointer, the second write operation in the cell unit CU_WL0_SU1 of the physical block corresponding to the physical block number PBN4 is set. In the example shown in FIG. 22, the data D0_2, D1_3 to D1_7, D2_0 to D2_7, D3_0 to D3_7, D8_0 to D8_7, D9_0 to D9_3, and the padding data PD are invalid data.

[0177] When the CPU 22 receives a flush command in this state, the CPU 22 starts a protection operation and sets the MLC tail address as the read target address.

[0178] As shown in FIG. 23, the CPU 22 reads out data corresponding to the read target address in order while moving the read target address. The CPU 22 stores valid data among the read data in the MLC buffer 251. In the example shown in FIG. 23, the data D3_0 to D3_7, the 16 padding data PD of the cell unit CU_WL1_SU0, the data D8_0 to D8_7, and the data D9_0 to D9_7 are MLC data. Among them, the data D3_0 is the most pre-written MLC data, and the data D9_7 is the most post-written MLC data. The CPU 22 executes read operations in order from the data D9_7, which is the most post-written MLC data, to the data D3_0, which is the most pre-written MLC data. The CPU 22 stores the valid data among them, the data D9_7, D9_6, D9_5, and D9_4, in the MLC buffer 251 in the order in which the data was read out. In this case, the MLC buffer 251 stores four pages of data.

[0179] As shown in FIG. 24, the CPU 22 fills the MLC buffer 251 with padding data PD because the amount of data stored in the MLC buffer 251 has not reached the amount of data that allows the second write operation to be executed.

[0180] As shown in Fig. 25, the CPU 22 executes a second write operation to write data of the MLC buffer 251 as Upper page data and Top page data to the cell unit CU_WL0_SU1 of the four physical blocks corresponding to the physical block numbers PBN4 to PBN7. In the example shown in Fig. 25, data D9_7 and padding data PD are written as Upper page data and Top page data to the cell unit CU_WL0_SU1 of the physical block corresponding to the physical block number PBN4. Data D9_6 and padding data PD are written as Upper page data and Top page data to the cell unit CU_WL0_SU1 of the physical block corresponding to the physical block number PBN5. Data D9_5 and padding data PD are written as Upper page data and Top page data to the cell unit CU_WL0_SU1 of the physical block corresponding to the physical block number PBN6. Data D9_4 and padding data PD are written as Upper page data and Top page data in the cell unit CU_WL0_SU1 of the physical block corresponding to physical block number PBN7.

[0181] After the second write operation is completed, the CPU 22 updates the lookup table LUT so that the data D9_4 to D9_7 stored in the cell units CU_WL1_SU1 of the four physical blocks corresponding to the physical block numbers PBN4 to PBN7 are invalidated. The data in the MLC buffer 251 is invalidated.

[0182] After completing the final second write operation, the CPU 22 transmits a flash command completion response to the host 2 and ends the protection operation.

[0183] 1.5 Effects of this embodiment The configuration according to this embodiment can provide a memory system that can improve data reliability.

[0184] When writing multiple bits of data to a memory cell, there is a method of executing the write operation in multiple steps. For example, in a write operation to a QLC, a first write operation is executed to write Lower page data and Middle page data, and a second write operation is executed to write Upper page data and Top page data. In this case, if a write failure occurs in the second write operation or if the power supply to the memory system is stopped during the second write operation, the MLC data (Lower page data and Middle page data) stored in the cell unit CU during the second write operation may be destroyed.

[0185] For example, the host sends a flush command to the memory system to ensure the latest value of the data. When the memory system receives the flush command from the host, it executes a process to protect the MLC data. For example, to protect the MLC data, a method is conceivable in which padding data is written as Upper page data and Top page data to the cell unit CU that stores the MLC data, and the write operation (second write operation) is completed. However, in this case, the amount of invalid data written to the memory cell increases, and the write amplification factor (WAF) increases.

[0186] In contrast, in the configuration according to this embodiment, the memory system 3 can execute a protection operation when it receives a flash command. In the protection operation, the memory system 3 can write the later written MLC data of a certain cell unit CU in the write destination area as Upper page data and Top page data to other cell units CUs in the same write destination area that store previously written MLC data. That is, the memory system 3 can execute a second write operation using the later written MLC data. This makes it possible to make the MLC data non-volatile (protect it). Therefore, the memory system 3 can improve the reliability of the data.

[0187] Furthermore, with the configuration according to this embodiment, it is possible to write later-written MLC data to the cell unit CU that stores the previously-written MLC data. That is, the non-volatilization of the later-written MLC data and the previously-written MLC data can be completed at the same time. This makes it possible to reduce the amount of MLC data to be copied (moved). This makes it possible to suppress an increase in the number of times the write operation is performed in the protection operation. That is, it is possible to suppress an increase in the processing time of the protection operation. This makes it possible to improve the processing capacity of the memory system 3.

[0188] Furthermore, with the configuration according to this embodiment, the memory system 3 can reduce the amount of MLC data to be moved. This makes it possible to suppress an increase in invalid data written to memory cells. In other words, it is possible to suppress an increase in WAF.

[0189] 1.6 Modification of the first embodiment Next, a modified example of the first embodiment will be described with reference to Fig. 26. Fig. 26 is a conceptual diagram showing an example of a write destination area before and after a protection operation. Note that, in the example shown in Fig. 26, for the sake of simplicity, a case is shown in which a logical block identified by logical block number LBN0 is selected as the write destination area, as in the explanation using Fig. 10.

[0190] As shown in FIG. 26, similarly to the explanation using FIG. 10, data D0_0 to D0_7 and D1_0 to D1_7 are written to the write destination area.

[0191] In this state, when the CPU 22 receives a flash command, it executes a protection operation. The CPU 22 executes a second write operation to copy the Lower page data to the Upper page data in the same cell unit CU, and copy the Middle page data to the Top page data in the same cell unit CU. At this time, the CPU 22 updates the lookup table LUT and sets the Lower page data and Middle page data, which are the copy sources, as invalid data. Note that the copied Upper page data and Top page data may also be invalid data. In this case, the update of the lookup table LUT is omitted.

[0192] 2. Second embodiment Next, a second embodiment will be described. In the second embodiment, the order of data stored in the MLC buffer 251 is different from that of the first embodiment. The following description will focus on the differences from the first embodiment.

[0193] 2.1 Example of MLC buffer A specific example of the MLC buffer 251 will be described with reference to Fig. 27 and Fig. 28. Fig. 27 and Fig. 28 are diagrams showing a specific example of a write destination area and a state of data stored in the MLC buffer 251. Fig. 27 corresponds to Fig. 17 described in the first embodiment. Fig. 28 corresponds to Fig. 19 described in the first embodiment.

[0194] In this embodiment, the CPU 22 stores the MLC data read from the write destination area in the order of buffers 3 to 0 corresponding to the Top page data of the MLC buffer 251. Next, the CPU 22 stores the MLC data read from the write destination area in the order of buffers 3 to 0 corresponding to the Upper page data of the MLC buffer 251.

[0195] As shown in FIG. 27, the CPU 22 reads out the data D3_7 to D3_0 and D2_7 in order. The CPU 22 stores the data D3_7, D3_6, D3_4, D3_3, D3_2, D3_1, D3_0, and D2_7, which are valid data, in the MLC buffer 251. At this time, the buffer selection order in the MLC buffer 251 is reversed from the order described in the first embodiment. More specifically, first, the data D3_7, D3_6, D3_4, and D3_3 are stored in order from the buffer 3 corresponding to the Top page data of the MLC buffer 251 toward the buffer 0. Next, the data D3_2, D3_1, D3_0, and D2_7 are stored in order from the buffer 3 corresponding to the Upper page data of the MLC buffer 251 toward the buffer 0. As a result, the eight page data stored in the MLC buffer 251 can be selected as write data in order from the pre-written data.

[0196] As shown in Fig. 28, the CPU 22 executes a second write operation to write data of the MLC buffer 251 as Upper page data and Top page data to the cell unit CU_WL0_SU0 of the four physical blocks corresponding to the physical block numbers PBN0 to PBN3. In the example shown in Fig. 28, data D2_7 and D3_3 are written as Upper page data and Top page data to the CU_WL0_SU0 of the physical block corresponding to the physical block number PBN0. Data D3_0 and D3_4 are written as Upper page data and Top page data to the cell unit CU_WL0_SU0 corresponding to the physical block number PBN1. Data D3_1 and D3_6 are written as Upper page data and Top page data to the cell unit CU_WL0_SU0 of the physical block corresponding to the physical block number PBN2. Data D3_2 and D3_7 are written as Upper page data and Top page data in the cell unit CU_WL0_SU0 of the physical block corresponding to physical block number PBN3.

[0197] The data storage order in the MLC buffer 251 may be the same as that in the first embodiment. In this case, the CPU 22 can select write data in order starting from the first written data by reversing the order in which data is read from the MLC buffer 251 to that in the first embodiment.

[0198] 2.2 Effects of this embodiment With the configuration according to this embodiment, the same effects as those of the first embodiment can be obtained.

[0199] Furthermore, with the configuration according to this embodiment, the order in which buffers for storing data in the MLC buffer 251 are selected can be reversed from that in the first embodiment.

[0200] For example, the data written to the destination area before receiving the flash command may be arranged optimally for sequential reads, and if the protection operation rearranges the order of the data, this may reduce the throughput of read operations.

[0201] In contrast, in the configuration according to the present embodiment, the multiple page data stored in the MLC buffer 251 can be selected as write data in order starting from the data written first. Therefore, it is possible to suppress a decrease in processing power caused by changing the data writing order.

[0202] The modified example of the first embodiment may be combined with this embodiment.

[0203] 3. Third embodiment Next, a third embodiment will be described. In the third embodiment, a case where a physical block includes a defective block will be described. Below, the differences from the first and second embodiments will be mainly described.

[0204] 3.1 Example of MLC buffer A specific example of the MLC buffer 251 will be described with reference to Fig. 29. Fig. 29 is a diagram showing a specific example of a write destination area and a state of data stored in the MLC buffer 251. The following description focuses on a second write operation using the MLC buffer 251.

[0205] In this embodiment, the amount of data stored in the MLC buffer 251 is changed depending on the status of the physical block to which the second write operation is next executed. That is, if the physical block is a defective block BLK (unused block BLK), the corresponding buffer of the MLC buffer 251 is also unused.

[0206] 29, for example, the physical block corresponding to the physical block number PBN7 is a defective block BLK. The CPU 22 does not execute a write operation or a read operation on the defective block BLK.

[0207] When the CPU 22 executes a second write operation to logical block number LBN1 (physical block numbers PBN4 to PBN7) including defective block BLK in the protection operation, the CPU 22 sets the buffer of the MLC buffer 251 corresponding to the defective block BLK as unused. Then, the CPU 22 stores six page data to be written to three physical blocks corresponding to physical block numbers PBN4 to PBN6 in the remaining buffer of the MLC buffer 251.

[0208] More specifically, when the CPU 22 executes the second write operation for logical block number LBN1 (physical block numbers PBN4 to PBN7), it sets buffer 3 of the MLC buffer 251 corresponding to the defective block BLK as unused. Then, the CPU 22 sequentially reads data D9_6 to D9_4 and D9_2 to D9_0 of cell units CU_WL1_SU1 of three physical blocks corresponding to physical block numbers PBN4 to PBN6, for example. At this time, the CPU 22 sequentially stores data D9_6, D9_5, and D9_4 in buffers 0 to 2 corresponding to the Upper page data of the MLC buffer 251. Next, the CPU 22 sequentially stores data D9_2, D9_1, and D9_0 in buffers 0 to 2 corresponding to the Top page data of the MLC buffer 251. The CPU 22 executes the second write operation to write the data D9_6 to D9_4 and D9_2 to D9_0 in the MLC buffer 251 to the cell unit CU_WL0_SU1 of the three physical blocks corresponding to the physical block numbers PBN4 to PBN6.

[0209] On the other hand, when the CPU 22 executes a second write operation for logical block number LBN0 (physical block numbers PBN0 to PBN3), the CPU 22 sets buffer 3 of the MLC buffer 251 to an in-use state. Then, the CPU 22 sequentially reads data D8_7 to D8_0 from cell units CU_WL1_SU1 of four physical blocks corresponding to physical block numbers PBN0 to PBN3, for example. The CPU 22 sequentially stores data D8_7, D8_6, D8_5, and D8_4 in buffers 0 to 3 corresponding to the Upper page data of the MLC buffer 251. Next, the CPU 22 sequentially stores data D8_3, D8_2, D8_1, and D8_0 in buffers 0 to 3 corresponding to the Top page data of the MLC buffer 251. The CPU 22 executes the second write operation to write the data D8_7 to D8_0 in the MLC buffer 251 to the cell unit CU_WL1_SU0 of the four physical blocks corresponding to the physical block numbers PBN0 to PBN3.

[0210] 3.2 Effects of this embodiment With the configuration according to this embodiment, the same effects as those of the first embodiment can be obtained.

[0211] Furthermore, with the configuration according to this embodiment, when the write destination area includes a defective block BLK, it is possible to appropriately use the buffer of the MLC buffer 251. Note that the modified example of the first embodiment or the second embodiment may be combined with this embodiment.

[0212] 4. Fourth embodiment Next, a fourth embodiment will be described. In the fourth embodiment, an overall flow of a protection operation different from that of the first embodiment will be described. The following mainly describes the differences from the first to third embodiments.

[0213] 4.1 Protection operation flow Next, an example of the flow of the protection operation will be described with reference to Fig. 30. Fig. 30 is a flowchart showing the overall flow of the protection operation.

[0214] As shown in FIG. 30, the CPU 22 executes the operations from step S1 to step S3 in the same manner as described with reference to FIG. 12 in the first embodiment.

[0215] After setting the MLC tail address as the read target address of the MLC data (S3), the CPU 22 checks whether the data corresponding to the read target address is valid data (S101). More specifically, the CPU 22 refers to the lookup table LUT to check whether the same physical address as the read target address is registered.

[0216] If the data corresponding to the read target address is valid data (S101_True), the CPU 22 reads the page data corresponding to the read target address from the non-volatile memory 10 (S4). The CPU 22 stores the read valid data in the MLC buffer 251.

[0217] If the data corresponding to the read target address is not valid data (S101_False), the CPU 22 updates the read target address (S8).

[0218] The operation from step S5 onwards is similar to that described with reference to FIG. 12 in the first embodiment.

[0219] 4.2 Effects of this embodiment With the configuration according to this embodiment, the same effects as those of the first embodiment can be obtained.

[0220] Furthermore, with the configuration according to this embodiment, the operation of reading invalid data can be omitted, thereby suppressing an increase in the processing time of the read operation in the protection operation.

[0221] The present embodiment may be combined with the modified example of the first embodiment, the second embodiment, or the third embodiment.

[0222] 5. Modifications, etc. The memory system according to the above embodiment includes a nonvolatile memory (10) including a plurality of memory cells (MC), each configured to nonvolatilely store a plurality of bits of data including at least a first bit (lower bit) and a second bit (upper bit); and a memory controller (20) electrically connected to the nonvolatile memory, configured to, in response to receiving a flash command from a host (2), read the second bit data from the second memory cell and write the second bit data read from the second memory cell to the first memory cell as the second bit when a first memory cell of the plurality of memory cells stores valid first bit data (FIG. 10, D0_0) as the first bit and does not store data as the second bit, and when a second memory cell different from the first memory cell of the plurality of memory cells stores valid second bit data (FIG. 10, D1_3) as the first bit and does not store data as the second bit.

[0223] According to the above embodiment, it is possible to provide a memory system with improved data reliability.

[0224] The embodiment is not limited to the above-described embodiment, and various modifications are possible. In addition, the above-described embodiments can be combined as much as possible.

[0225] Furthermore, in the above embodiments, "connection" also includes a state in which something else, such as a transistor or a resistor, is interposed between them and indirectly connected.

[0226] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0227] 1...information processing system, 2...host, 3...memory system, 10...non-volatile memory, 11...memory chip, 20...memory controller, 21...host interface circuit, 22...CPU, 23...ROM, 24...RAM, 25...buffer memory, 26...ECC circuit, 27...NAND controller, 101...input / output circuit, 102...logic control circuit, 103...address register, 104...command register, 105...sequencer, 106...ready / busy circuit, 111...memory cell array, 112...row decoder, 113...sense amplifier, 114...data register, 115...column decoder, 251...MLC buffer, BL...bit line, MC0 to MC7...memory cell, PLN0 to PLN3...plane, SGD0 to SGD4...selection gate line, SL...source line, ST1, ST2...selection transistor, SU0 to SU4...string unit, WL0 to WL7...word line.

Claims

1. a non-volatile memory including a plurality of memory cells each configured to store a plurality of bits of data including at least a first bit and a second bit in a non-volatile manner; electrically connected to the non-volatile memory; in response to receiving a flash command from a host, when a first memory cell of the plurality of memory cells stores valid first bit data as the first bit and does not store data as the second bit, and a second memory cell of the plurality of memory cells different from the first memory cell stores valid second bit data as the first bit and does not store data as the second bit, reading the second bit of data from the second memory cell; The second bit data read from the second memory cell is written to the first memory cell as the second bit. a memory controller configured to A memory system comprising:

2. a memory region to which the first memory cell and the second memory cell belong includes at least a memory cell among the plurality of memory cells that does not store data as the second bit; 2. The memory system of claim 1.

3. the memory controller further writes the second bit of data to the second memory cell as the first bit after writing the first bit of data to the first memory cell; In response to receiving the flush command from the host, reading the second bit of data from the second memory cell; The second bit data read from the second memory cell is written to the first memory cell as the second bit.

2. The memory system according to claim 1, configured as follows.

4. The nonvolatile memory includes a plurality of cell units, each of the plurality of cell units includes one or more of the memory cells, and the plurality of cell units includes at least a first cell unit including the first memory cell and a second cell unit including the second memory cell; The memory controller further comprises: reading valid data stored as the first bit in each of the one or more memory cells of the second cell unit including at least the second memory cell; writing the second bit data read as the first bit from the second memory cell to the first memory cell in response to a total amount of valid data read from each of the one or more memory cells of the second cell unit after receiving the flash command from the host reaching a data amount capable of executing a write operation to the first cell unit; 2. The memory system according to claim 1, configured as follows.

5. the memory controller further writes padding data to at least one of the memory cells included in the first cell unit when a total amount of the valid data stored as the first bits in each of the one or more memory cells of the second cell unit at the time of receiving the flash command from the host is less than the amount of data required to execute the write operation to the first cell unit; 5. The memory system according to claim 4, configured as follows.

6. Further comprising a buffer; The nonvolatile memory includes a plurality of cell units, each of the plurality of cell units includes one or more of the memory cells, and the plurality of cell units includes at least a first cell unit including the first memory cell and a second cell unit including the second memory cell; The memory controller further comprises: storing data read from the second cell unit and including at least the second bit data in the buffer; writing the second bit of data stored in the buffer to the first memory cell when the amount of data stored in the buffer reaches a data amount that allows a write operation to be performed on the first cell unit; 2. The memory system according to claim 1, configured as follows.

7. the memory controller further stores padding data in the buffer when the amount of the data stored in the buffer does not reach the amount of data required to execute the write operation to the first cell unit, and executes the write operation to the first cell unit using the data stored in the buffer and the padding data stored in the buffer.

7. The memory system according to claim 6, configured as follows.

8. The memory controller further comprises: after writing the first bit data to the first memory cell, writing a valid third bit data as the first bit to a third memory cell of the plurality of memory cells; after writing the third bit data to the third memory cell, writing a valid fourth bit data as the first bit to a fourth memory cell of the plurality of memory cells; after writing the fourth bit data to the fourth memory cell, writing the second bit data to the second memory cell as the first bit; when the first memory cell stores the first bit of data as the first bit and has not stored data as the second bit, the second memory cell stores the second bit of data as the first bit and has not stored data as the second bit, the third memory cell stores the third bit of data as the first bit and has not stored data as the second bit, and the fourth memory cell stores the fourth bit of data as the first bit and has not stored data as the second bit, in response to receiving the flash command from the host, reading the second bit of data from the second memory cell; The second bit data read from the second memory cell is written to the first memory cell as the second bit, reading the fourth bit of data from the fourth memory cell; writing the fourth bit data read from the fourth memory cell to the third memory cell as the second bit; 2. The memory system according to claim 1, configured as follows.

9. The memory controller further comprises: after writing the first bit data to the first memory cell, writing a valid third bit data as the first bit to a third memory cell of the plurality of memory cells; after writing the third bit data to the third memory cell, writing a valid fourth bit data as the first bit to a fourth memory cell of the plurality of memory cells; after writing the fourth bit data to the fourth memory cell, writing the second bit data to the second memory cell as the first bit; when the first memory cell stores the first bit of data as the first bit and has not stored data as the second bit, the second memory cell stores the second bit of data as the first bit and has not stored data as the second bit, the third memory cell stores the third bit of data as the first bit and has not stored data as the second bit, and the fourth memory cell stores the fourth bit of data as the first bit and has not stored data as the second bit, in response to receiving the flash command from the host, reading the second bit of data from the second memory cell; reading the fourth bit of data from the fourth memory cell; The fourth bit data read from the fourth memory cell is written to the first memory cell as the second bit, and then The second bit data read from the second memory cell is written to the third memory cell as the second bit.

2. The memory system according to claim 1, configured as follows.

10. The memory controller further comprises: managing the second bit data stored in the second memory cell as the first bit as invalid data; 2. The memory system according to claim 1, configured as follows:

11. each of the plurality of memory cells is configured to non-volatilely store four bits of data including the first bit, the second bit, a third bit, and a fourth bit; The memory controller further comprises: a first write operation to write data as the first bit and the third bit of the first memory cell; performing a second write operation to write data to the second bit and the fourth bit of the second memory cell based on the data read from the first bit and the third bit of the first memory cell; 2. The memory system according to claim 1, configured as follows.

12. each of the plurality of memory cells is configured to store data in a non-volatile manner according to a threshold voltage; Each of the plurality of memory cells includes: storing first data including at least the first bit in response to the threshold voltage being in a first voltage range; storing second data including at least the first bit and the second bit in response to the threshold voltage being in a second voltage range narrower than the first voltage range; 2. The memory system according to claim 1, configured as follows.

Images