Gate driving circuit, power source control device, power source device, and vehicle

Abstract

To achieve low ringing and low switching loss.SOLUTION: A gate driving circuit (20) is configured to drive a gate of a power transistor (M1). The gate driving circuit includes a switching unit (200) configured to switch output current capability. The switching unit is configured to switch the output current capability from a first capability to a second capability which is higher than the first capability, in the middle of shifting the power transistor from off to fully on.SELECTED DRAWING: Figure 7

Description

[Technical field]

[0001] The invention disclosed in this specification relates to a gate drive circuit, a power supply control device, a power supply device, and a vehicle. [Background technology]

[0002] Conventionally, step-down DC / DC converters are known. For example, a synchronous rectification type step-down DC / DC converter converts an input voltage into a lower output voltage by switching a high-side switch element and a low-side switch element.

[0003] In a synchronous rectification type step-down DC / DC converter, a high-side switch element and a low-side switch element are connected in series between an input voltage application terminal and a ground potential application terminal. A switch voltage is generated at a node where the high-side switch element and the low-side switch element are connected. Conventionally, in a step-down DC / DC converter, it is known that ringing occurs in the switch voltage when the high-side switch element is turned on (switched from an off state to an on state) due to the influence of the inductor component and the resistance component of the bonding wire. This ringing becomes a voltage in the high frequency region, and is a factor that adversely affects EMI (Electromagnetic Interference) characteristics.

[0004] Patent Document 1 proposes a power supply control device that can automatically adjust the ringing of a switch voltage. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2023-82752 A

[0006] [overview] However, with the power supply control device proposed in Patent Document 1, it is difficult to achieve both low ringing and low switching loss.

[0007] The gate drive circuit disclosed in this specification is a gate drive circuit configured to drive a gate of a power transistor, and includes a switching unit configured to switch an output current capability, the switching unit configured to switch the output current capability from a first capability to a second capability greater than the first capability during a transition of the power transistor from off to full on.

[0008] The power supply control device disclosed in this specification includes a gate drive circuit having the above-described configuration, and a control circuit configured to control the gate drive circuit.

[0009] The power supply device disclosed in this specification includes a power supply control device having the above-described configuration and the power transistor.

[0010] The vehicle disclosed in this specification is equipped with a power supply device having the above-described configuration. [Brief description of the drawings]

[0011] [Figure 1] FIG. 1 is an overall configuration diagram showing the configuration of a switching power supply device according to an embodiment of the present disclosure. [Diagram 2] FIG. 2 is a diagram showing an example of the appearance of a power supply IC. [Diagram 3] FIG. 3 is a diagram showing the relationship between the signals SET, RST, G1 and G2. [Figure 4A] FIG. 4A is a diagram illustrating an example of the configuration of the slope voltage generating unit. [Figure 4B] FIG. 4B is a diagram showing example waveforms of current and voltage related to the slope voltage. [Diagram 5] FIG. 5 is a diagram showing an example of waveforms of a clock signal and a set signal. [Figure 6] FIG. 6 is a timing chart showing an example of basic switching control. [Figure 7] FIG. 7 is a diagram showing a first configuration example of the high-side pre-driver. [Figure 8] FIG. 8 is a diagram illustrating a first configuration example of the switching unit. [Figure 9] FIG. 9 is a diagram illustrating a second configuration example of the switching unit. [Figure 10] FIG. 10 is a diagram illustrating a third configuration example of the switching unit. [Figure 11] FIG. 11 is a waveform diagram of the switch voltage and the gate-source voltage of the high-side switch element. [Figure 12] FIG. 12 is a diagram showing a second configuration example of the high-side pre-driver. [Figure 13] FIG. 13 is a diagram showing an example of a configuration of a low-side pre-driver. [Figure 14] FIG. 14 is an external view of the vehicle.

[0012] [Detailed Description] In this specification, MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) refers to a field effect transistor whose gate structure is composed of at least three layers: "a layer made of a conductor or a semiconductor such as polysilicon with a low resistance value," "an insulating layer," and "a P-type, N-type, or intrinsic semiconductor layer." In other words, the gate structure of a MOSFET is not limited to a three-layer structure of a metal, an oxide, and a semiconductor.

[0013] In this specification, the reference voltage means a voltage that is constant under ideal conditions, but in reality, it is a voltage that may fluctuate slightly due to temperature changes and the like.

[0014] <Switching power supply unit> Fig. 1 is an overall configuration diagram showing the configuration of a switching power supply device according to an embodiment of the present disclosure. The switching power supply device AA in Fig. 1 is configured as a synchronous rectification type step-down DC / DC converter that generates an output voltage Vout lower than an input voltage Vin from an input voltage Vin. The input voltage Vin and the output voltage Vout are positive DC voltages. The switching power supply device AA includes a power supply IC1 as a power supply control device, and an inductor L1, an output capacitor C1, a feedback resistor R1, and a feedback resistor R2 that are provided outside the power supply IC1.

[0015] Figure 2 shows an example of the appearance of power supply IC1. Power supply IC1 is an electronic component (semiconductor device) formed by encapsulating a semiconductor integrated circuit in a housing (package) made of resin, and each circuit constituting power supply IC1 is integrated with semiconductors. The housing of the electronic component serving as power supply IC1 has multiple external terminals exposed from the housing to the outside of IC1. Note that the number of external terminals shown in Figure 2 is merely an example.

[0016] As part of the multiple external terminals provided in the power supply IC1, external terminals TM1 to TM4 are shown in FIG. 1. The external terminal TM1 is connected to an application terminal for an input voltage Vin. The external terminal TM2 is connected to a node ND1 described later. The external terminal TM3 is connected to an application terminal for a ground potential. The external terminal TM4 is connected to an application terminal for a feedback voltage V FB is applied.

[0017] The power supply IC1 includes a high-side switch element M1 as an output transistor, a low-side switch element M2 as a synchronous rectification transistor, a control unit 10, and an internal power supply circuit 30. The high-side switch element M1 and the low-side switch element M2 are power transistors. The power supply IC1 may further include blocks (such as a reset circuit and a protection circuit) that do not belong to the control unit 10 and are different from the internal power supply circuit 30, but illustrations and functional descriptions of these blocks are omitted here unless necessary. The high-side switch element M1 and the low-side switch element M2 are configured as NMOS transistors (N-channel MOSFETs (metal-oxide-semiconductor field-effect transistors)). However, a modification in which the high-side switch element M1 is configured as a PMOS transistor (P-channel MOSFET) is also possible. The high-side switch element M1 and the low-side switch element M2 may be provided outside the power supply IC1. When an NMOS transistor is used for the high-side switch element M1, the switching power supply device AA includes a bootstrap circuit not shown in FIG. 1.

[0018] Furthermore, the switching power supply AA is not limited to a synchronous rectification type, and may be an asynchronous rectification type. When the switching power supply AA is configured as an asynchronous rectification type, a rectifier diode is used instead of the low-side switch element M2. The low-side switch element or the rectifier diode is an example of a rectifier element.

[0019] The switching power supply device AA performs DC-DC conversion by synchronous rectification using a high-side switch element M1 and a low-side switch element M2. Note that, for any transistor including the high-side switch element M1 and the low-side switch element M2, a section in which the transistor is in an on state may be referred to as an on section, and a section in which the transistor is in an off state may be referred to as an off section.

[0020] The drain of the high-side switch element M1 is connected to the external terminal TM1, and therefore receives the input voltage Vin. The source of the high-side switch element M1 and the drain of the low-side switch element M2 are connected to a node ND1. The source of the low-side switch element M2 is connected to a ground potential application terminal via an external terminal TM3. The voltage generated at the node ND1 is called a switch voltage and is represented by the symbol "Vsw". The external terminal TM2 is connected to the node ND1. One end of the inductor L1 is connected to the external terminal TM2, and the other end of the inductor L1 is connected to the node ND2. An output voltage Vout is generated at the node ND2. An output capacitor C1 is connected between the node ND2 and the ground potential application terminal. In addition, a series circuit of feedback resistors R1 and R2 is provided between the node ND2 and the ground potential application terminal. Therefore, a feedback voltage Vfb, which is a divided voltage of the output voltage Vout, is generated at the connection node between the feedback resistors R1 and R2. The connection node between the feedback resistors R1 and R2 is connected to the external terminal TM4, and the feedback voltage Vfb is applied to the external terminal TM4. When the high-side switch element M1 is configured as a PMOS transistor, the relationship between the source and drain of the transistor is reversed (that is, the source and drain of the high-side switch element M1 are connected to the external terminal TM1 and the node ND1, respectively).

[0021] In FIG. 1, "LD" represents a load connected between the node ND2 and the application terminal of the ground potential. The load LD is any load (such as a microcomputer) that is driven based on the output voltage Vout. The consumption current of the load LD that flows from the node ND2 to the load LD is called the load current and is represented by the symbol "I LD The current flowing through the inductor L1 is called the inductor current and is represented by the symbol "I L " is used.

[0022] The control unit 10 controls the gate voltages of the high-side switch element M1 and the low-side switch element M2 based on a feedback voltage Vfb and a slope voltage Vslp (described later) corresponding to the current flowing through the high-side switch element M1, thereby controlling the on / off of the high-side switch element M1 and the low-side switch element M2, thereby stabilizing the output voltage Vout to a predetermined target voltage (e.g., 5V). The control unit 10 in FIG. 1 is capable of driving the high-side switch element M1 and the low-side switch element M2 by a so-called current mode control method. The internal power supply circuit 30 generates a predetermined internal power supply voltage Vreg from the input voltage Vin. Each circuit in the control unit 10 is driven based on the internal power supply voltage Vreg.

[0023] The following describes the internal configuration of the control unit 10. The control unit 10 includes an error amplifier 11, a reference voltage source 12, a resistor 13, a capacitor 14, a slope voltage generation unit 15, a main comparator 16, a clock generation unit 17, a set signal generation unit 18, a control logic unit 19, a high-side pre-driver 20, a low-side pre-driver 21, and a slew rate control unit 22.

[0024] The error amplifier 11 is a current output type transconductance amplifier. The inverting input terminal (-) of the error amplifier 11 is supplied with a feedback voltage Vfb applied to an external terminal TM4. A reference voltage source 12 generates a reference voltage Vref, which is a predetermined positive DC voltage. The reference voltage Vref is input to the non-inverting input terminal (+) of the error amplifier 11. The output terminal of the error amplifier 11 is connected to a line LN1, which is a wiring within the power supply IC1. Note that if the power supply IC1 is provided with a soft start function, the soft start voltage is also input to the error amplifier 11, but this function will be ignored here.

[0025] The error amplifier 11 generates an error voltage Verr according to the difference between the negative target voltage and the positive target voltage. When the soft start function is ignored, the negative target voltage and the positive target voltage are the feedback voltage Vfb and the reference voltage Vref, respectively. The error amplifier 11 generates an error voltage Vcmp on the line LN1 by inputting and outputting charges based on an error current signal based on the difference between the negative target voltage and the positive target voltage to and from the line LN1. Specifically, when the positive target voltage is higher than the negative target voltage, the error amplifier 11 outputs a current based on the error current signal to the line LN1 so that the error voltage Verr becomes higher, and when the negative target voltage is higher than the positive target voltage, the error amplifier 11 draws a current based on the error current signal from the line LN1 to the error amplifier 11 so that the error voltage Verr becomes lower. As the absolute value of the difference between the negative target voltage and the positive target voltage increases, the magnitude of the current based on the error current signal also increases.

[0026] A series circuit of a resistor 13 and a capacitor 14 is connected between the line LN1 and a terminal to which the ground potential is applied. This series circuit functions as a phase compensation unit, and generates an error voltage Verr on the line LN1 in cooperation with the error amplifier 11. Specifically, one end of the resistor 13 is connected to the line LN1, and the other end of the resistor 13 is connected to the terminal to which the ground potential is applied via the capacitor 14. By appropriately setting the resistance value of the resistor 13 and the capacitance value of the capacitor 14, it is possible to compensate the signal phase of the error voltage Verr and prevent oscillation of the output feedback loop. Note that both or one of the resistor 13 and the capacitor 14 may be provided outside the power supply IC1 and externally connected to the power supply IC1.

[0027] The slope voltage generating unit 15 generates a slope voltage Vslp according to the current flowing through the high-side switch element M1 in an on-interval of the high-side switch element M1 (that is, a period in which the high-side switch element M1 is in an on-state).

[0028] The main comparator 16 compares the slope voltage Vslp and the error voltage Verr and outputs a signal RST indicating the comparison result. Of the output signals RST from the main comparator 16, only the high-level signal RST functions as a reset signal, and the low-level signal RST does not correspond to the reset signal. Hereinafter, the output of the high-level signal RST from the main comparator 16 may be expressed as the issuance or output of a reset signal. The main comparator 16 functions as a reset signal generating unit that issues a reset signal based on the slope voltage Vslp and the error voltage Verr.

[0029] The set signal generating unit 18 outputs a signal SET to the control logic unit 19. Of the output signals SET from the set signal generating unit 18, only a high-level signal SET functions as a set signal, and a low-level signal SET does not correspond to a set signal. Hereinafter, the output of a high-level signal SET from the set signal generating unit 18 may be expressed as issuing or outputting a set signal. The set signal generating unit 18 can periodically issue a set signal, which will be described in detail later.

[0030] The control logic unit 19 is composed of logic circuits such as flip-flops, and generates control signals for specifying the on / off states of the high-side switch element M1 and the low-side switch element M2 based on the signal SET from the set signal generation unit 18 and the signal RST from the main comparator 16, and outputs the control signals to the high-side pre-driver 20 and the low-side pre-driver 21. The high-side pre-driver 20 generates and outputs a gate signal G1 for the high-side switch element M1 based on the control signal from the control logic unit 19. The low-side pre-driver 21 generates and outputs a gate signal G2 for the low-side switch element M2 based on the control signal from the control logic unit 19.

[0031] The relationship between the signals SET, RST, G1, and G2 is shown in Fig. 3. Each of the signals SET, RST, G1, and G2 is a binary signal that takes either a high level or a low level.

[0032] When a high-level signal SET is input to the control logic unit 19 while the signal RST is at a low level (i.e., when a set signal is issued), the gate signal G1 becomes high and the gate signal G2 becomes low, and these states are maintained thereafter until a high-level signal RST is input to the control logic unit 19 (i.e., until a reset signal is issued).

[0033] When a high-level signal RST is input to the control logic unit 19 while the signal SET is at a low level (i.e., when a reset signal is issued), the gate signal G1 becomes low level and the gate signal G2 becomes high level, and these states are maintained thereafter until a high-level signal SET is input to the control logic unit 19 (i.e., until a set signal is issued).

[0034] In the section where the signals SET and RST are both at low level, the levels of the gate signals G1 and G2 are maintained. Note that in the control unit 10, the signals SET and RST are never at high level at the same time.

[0035] For convenience, a block consisting of the high-side switch element M1 and the low-side switch element M2 is referred to as the output stage. The state of the output stage (i.e., the state of the switch voltage Vsw) is either an output high state, an output low state, or a Hi-Z state. In the output high state, M1 and M2 are in the on state and off state, respectively. In the output low state, M1 and M2 are in the off state and on state, respectively. In the Hi-Z state, M1 and M2 are both in the off state.

[0036] The control unit 10 configured as described above performs a switching operation of alternately turning on and off the high-side switch element M1 and the low-side switch element M2 (i.e., switching the output stage between an output high state and an output low state) based on the feedback voltage Vfb and the slope voltage Vslp, thereby stabilizing the output voltage Vout to a target voltage according to the reference voltage Vref, and using current information based on the slope voltage Vslp to improve load responsiveness. A method of controlling the high-side switch element M1 and the low-side switch element M2 using current information in addition to information on the output voltage Vout (i.e., in addition to the feedback voltage Vfb) is called a current mode control method, and this control is called current mode control.

[0037] In addition, in the switching operation, when the state of the output stage is switched between the output high state and the output low state, a dead time may be inserted in which the high-side switch element M1 and the low-side switch element M2 are simultaneously turned off in order to prevent the generation of a through current through the high-side switch element M1 and the low-side switch element M2.

[0038] The switching operation produces a square-wave voltage Vsw whose level fluctuates between the level of the input voltage Vin and the level of the ground potential, but the switch voltage Vsw is smoothed by the inductor L1 and the output capacitor C1 to obtain a DC output voltage Vout.

[0039] The slope voltage Vslp will be explained in more detail. The current flowing through the high-side switch element M1 during the ON period of the high-side switch element M1 is the inductor current I L Therefore, the slope voltage Vslp is equal to the inductor current I during the on-period of the high-side switch element M1. LThat is, the slope voltage Vslp includes current information of the high-side switch element M1 or the inductor L1 during the ON section of the high-side switch element M1. Any known method can be used as a method for generating the slope voltage Vslp including the current information.

[0040] 4A shows an example of the configuration of the slope voltage generating unit 15, and FIG. 4B shows waveforms of current and voltage related to the slope voltage Vslp. The slope voltage generating unit 15 in FIG. 4A includes an IV converting unit 15A, a ramp voltage generating unit 15B, and an adding unit 15C. The IV converting unit 15A converts the current flowing through the high-side switch element M1 during the ON period of the high-side switch element M1 (i.e., the inductor current I L ) into a voltage to generate a sense voltage Vsns proportional to the current. The ramp voltage generation unit 15B generates a sawtooth ramp voltage Vrmp that gradually increases from 0V during the on-section of the high-side switch element M1. The adder 15C generates the sum of the sense voltage Vsns and the ramp voltage Vrmp as a slope voltage Vslp. In sections other than the on-section of the high-side switch element M1, the slope voltage Vslp is 0V (however, it may have a predetermined bias voltage value). As is well known, the addition of the ramp voltage Vrmp can suppress oscillation of the output feedback loop in current mode control.

[0041] <Basic switching control> Next, the load current I LD Next, a basic switching control that can be performed by the control unit 10 when is relatively large will be described.

[0042] As shown in FIG. 1, the control unit 10 controls a predetermined reference frequency f CLK The clock signal CLK has a reference frequency f CLKA pulse occurs in the clock signal CLK, and a pulse that is at a high level for a very short time occurs in the clock signal CLK every period of the clock signal CLK. In the clock signal CLK, the interval between high-level sections is a time T P1 , i.e. the reference frequency f CLK When the signal SET is generated based on the clock signal CLK, the signal SET goes high for a predetermined short time at the falling edge of the clock signal CLK. In other words, when the signal SET is generated based on the clock signal CLK, the signal SET is a signal obtained by shifting the clock signal CLK in the time delay direction by the above-mentioned short time.

[0043] In this example, the signal SET is generated from the clock signal CLK, but in basic switching control, the clock signal CLK itself may be supplied as the signal SET to the set signal generating unit 18. In addition, in basic switching control, the occurrence of a falling edge of the clock signal CLK may be considered to correspond to the issuance of a set signal.

[0044] FIG. 6 shows a timing chart of the basic switching control. At a timing t A0 The basic switching control will be explained starting from the timing t A0 At time t A1 When a pulse occurs in the clock signal CLK, the falling edge of the clock signal CLK triggers the signal SET to go high for a very short period of time, i.e., a set signal is issued. In response to the issuance of the set signal, the output stage switches from an output low state to an output high state. During the section in which the output stage is in the output high state, the inductor current I L The slope voltage Vslp, which was less than the error voltage Verr, gradually increases at the timing t A2When the error voltage Vcmp is reached at , the output signal RST of the main comparator 16 switches from low to high, i.e., a reset signal is issued. In response to the issuance of the reset signal, the output stage switches from an output high state to an output low state. When the output stage goes into an output low state, the slope voltage Vslp quickly drops to 0V, and the signal RST returns to a low level. Thereafter, the same operation is repeated.

[0045] In this way, in basic switching control, the reference frequency f CLK Since the set signal is issued in response to the falling edge of the clock signal CLK having the reference frequency f CLK In other words, in basic switching control, the input voltage Vin is PWM-controlled at a reference frequency f CLK The output voltage Vout is obtained by pulse width modulation at "PWM." "PWM" is an abbreviation for pulse width modulation.

[0046] <High side pre-driver> The high-side pre-driver 20 includes a switching unit configured to switch an output current capacity from a first capacity to a second capacity larger than the first capacity during a transition of the high-side switch element M1 from off to full on (a state in which the high-side switch element M1 can pass a maximum current).

[0047] The high-side pre-driver 20 suppresses the output current capacity until the high-side switch element M1 is partway through transition from off to full on, and therefore the ringing of the switch voltage Vsw can be reduced. This is because the ringing of the switch voltage Vsw can be reduced by reducing the output current capacity of the high-side pre-driver 20 until the gate-source voltage Vgs of the high-side switch element M1 becomes a plateau voltage.

[0048] In addition, the high-side pre-driver 20 increases the output current capacity during the period from midway through the transition of the high-side switch element M1 from off to full on until it becomes fully on. This increases the slew rate of the high-side switch element M1 during the period from midway through the transition of the high-side switch element M1 from off to full on until it becomes fully on, thereby reducing the switching loss in the high-side switch element M1.

[0049] Fig. 7 is a diagram showing a first configuration example of the high-side pre-driver 20. The high-side pre-driver 20 according to this configuration example includes a switching unit 200 and a plurality of drivers 201-203. In the configuration shown in Fig. 7, the number of drivers is three, but the number of drivers may be two or four or more. The drivers 201-203 each receive a control signal CNT from the control logic unit 19. The output terminals of the drivers 201-203 are commonly connected to the gate of the high-side switch element M1.

[0050] The switching unit 200 outputs driver control signals DRSEL1-DRSEL3 to the drivers 201-203, respectively. The driver control signals DRSEL1-DRSEL3 are signals for selecting the on / off operation of each of the drivers 201-203. When the driver control signal selects the on operation, the corresponding driver goes into a high level output state or a low level output state according to the level of the control signal CNT. On the other hand, when the driver control signal selects the off operation, the corresponding driver goes into a Hi-Z output state regardless of the level of the control signal CNT.

[0051] As a result, the current capability (output current capability) of the driver in the high-level output state to supply current to the gate of the high-side switch element M1 changes according to the number of drivers 201-203 selected to be turned on by the driver control signals DRSEL1-DRSEL3. By varying the current capability, the slew rate of the switch voltage Vsw when the high-side switch element M1 is turned on changes. More specifically, the greater the number of drivers selected to be turned on, the greater the current capability and the greater the slew rate of the switch voltage Vsw.

[0052] FIG. 8 is a diagram showing a first configuration example of the switching unit 200. The switching unit 200 according to this configuration example includes a delay circuit 200A and a signal generating circuit 200B. The delay circuit 200A generates a delay signal DLY by delaying the control signal CNT. The signal generating circuit 200B generates driver control signals DRSEL1 to DRSEL3 such that the number of drivers 201 to 203 selected to be turned on changes from one to three when a predetermined time has elapsed from the start of a transition operation for transitioning the high-side switch element M1 from off to full on, based on the delay signal DLY. The above-mentioned predetermined time can be set by setting the delay time in the delay circuit 200A. Note that the timing at which the above-mentioned predetermined time has elapsed is preferably a timing at which the gate-source voltage Vgs of the high-side switch element M1 and the plateau voltage of the high-side switch element M1 approximately match.

[0053] Since the delay circuit 200A can be realized by a circuit with a simple configuration such as a CR circuit, the switching section 200 according to this configuration example can be made smaller and less expensive.

[0054] 9 is a diagram showing a second configuration example of the switching unit 200. The switching unit 200 according to this configuration example includes a signal generating circuit 200C. The signal generating circuit 200C obtains a gate-source voltage Vgs of the high-side switch element M1 from the gate signal G1 and the switch voltage Vsw, and generates driver control signals DRSEL1-DRSEL3 such that the number of drivers 201-203 selected to be turned on changes from one to three when the gate-source voltage Vgs of the high-side switch element M1 reaches a predetermined value. Note that the predetermined value is preferably approximately equal to the plateau voltage of the high-side switch element M1.

[0055] FIG. 10 is a diagram showing a third configuration example of the switching unit 200. The switching unit 200 according to this configuration example includes a differentiation circuit 200D and a signal generation circuit 200E. The differentiation circuit 200D obtains the gate-source voltage Vgs of the high-side switch element M1 from the gate signal G1 and the switch voltage Vsw, and generates a differentiation signal DIFF, which is a signal obtained by differentiating the gate-source voltage Vgs of the high-side switch element M1. The signal generation circuit 200E generates driver control signals DRSEL1 to DRSEL3 such that the number of drivers 201 to 203 selected to be turned on is switched from one to three when the rate of change of the gate-source voltage Vgs of the high-side switch element M1 becomes a predetermined value based on the differentiation signal DIFF. Note that the predetermined value is preferably approximately zero. This is because the rate of change of the gate-source voltage Vgs of the high-side switch element M1 becomes approximately zero when the gate-source voltage Vgs of the high-side switch element M1 becomes the plateau voltage of the high-side switch element M1.

[0056] FIG. 11 is a waveform diagram of the switch voltage Vsw and the gate-source voltage Vgs of the high-side switch element M1.

[0057] The voltage V1 is the switch voltage Vsw when the number of drivers 201 to 203 selected to be turned on changes from one to three during the transition of the high-side switch element M1 from off to full on, as in the high-side pre-driver 20 of this configuration example.

[0058] Unlike the high-side pre-driver 20 according to this configuration example, the voltage V2 is the switch voltage Vsw when only one of the drivers 201 to 203 is selected to be turned on during the period in which the high-side switch element M1 is transitioned from off to full on.

[0059] Unlike the high-side pre-driver 20 according to this configuration example, the voltage V2 is the switch voltage Vsw when three of the drivers 201 to 203 are selected to be turned on during the period in which the high-side switch element M1 is transitioned from off to full on.

[0060] As is clear from the comparison between the voltages V1 and V2, the high-side pre-driver 20 according to this configuration example can increase the slew rate of the high-side switch element M1 during the period in which the high-side switch element M1 transitions from off to full on, compared to the case in which only one of the drivers 201 to 203 is selected to be turned on.

[0061] As is clear from the comparison between the voltages V1 and V3, the high-side pre-driver 20 according to this configuration example can suppress ringing of the switch voltage Vsw during the period in which the high-side switch element M1 transitions from off to full on, compared to the case in which three of the drivers 201 to 203 are selected to be turned on.

[0062] The voltage V4 is the gate-source voltage Vgs of the high-side switch element M1 when the number of drivers 201-203 selected to be turned on changes from one to three during the transition of the high-side switch element M1 from off to full on, as in the high-side pre-driver 20 of this configuration example.

[0063] Unlike the high-side pre-driver 20 in this configuration example, the voltage V5 is the gate-source voltage Vgs of the high-side switch element M1 when the number of drivers 201-203 selected to be turned on is one during the period in which the high-side switch element M1 is transitioned from off to full on.

[0064] Unlike the high-side pre-driver 20 in this configuration example, the voltage V6 is the gate-source voltage Vgs of the high-side switch element M1 when the number of drivers 201-203 selected to be turned on during the period in which the high-side switch element M1 is transitioned from off to fully on is three among the drivers 201-203.

[0065] In addition, the magnitude of the high-frequency noise component contained in the switch voltage Vsw in the high-side pre-driver 20 according to this configuration example is between the case where one driver among the drivers 201 to 203 is selected to be turned on and the case where three drivers among the drivers 201 to 203 are selected to be turned on during the period in which the high-side switch element M1 is transitioned from off to full on.

[0066] FIG. 12 is a diagram showing a second configuration example of the high-side pre-driver 20. The high-side pre-driver 20 according to this configuration example includes a switching unit 204 and a driver including a variable resistor 205, a PMOS transistor 206, and an NMOS transistor 207. The switching unit 204 controls the resistance value of the variable resistor 205. The variable resistor 205 is a variable current source. A boost voltage Vboot output from a bootstrap circuit is applied to a first terminal of the variable resistor 205. A source of the PMOS transistor 206 is connected to a second terminal of the variable resistor 205. The drains of the PMOS transistor 206 and the NMOS transistor 207 are connected to the gate of the high-side switch element M1. A switch voltage Vsw is applied to the source of the NMOS transistor 207. The gates of the PMOS transistor 206 and the NMOS transistor 207 receive a control signal CNT from the control logic unit 19.

[0067] For example, the switching unit 204 switches (decreases) the resistance value of the variable resistor 205 when a predetermined time has elapsed since the start of the transition operation of transitioning the high-side switch device M1 from off to full on.

[0068] Furthermore, for example, the switching unit 204 switches (decreases) the resistance value of the variable resistor 205 when the gate-source voltage Vgs of the high-side switch element M1 reaches a predetermined value.

[0069] Also, for example, the switching unit 204 switches (decreases) the resistance value of the variable resistor 205 when the rate of change of the gate-source voltage Vgs of the high-side switch element M1 reaches a predetermined value.

[0070] <Reducing dead time> FIG. 13 is a diagram showing an example of the configuration of the low-side pre-driver 21. As shown in FIG.

[0071] A power supply voltage VDD is applied to the positive power supply terminal of the control logic unit 19. A ground potential is applied to the negative power supply terminal of the control logic unit 19. A boosted voltage Vboot is applied to each of the positive power supply terminals of the drivers 201 to 203. A switch voltage Vsw is applied to each of the negative power supply terminals of the drivers 201 to 203. The high side pre-driver 20 includes a level shifter 208. A power supply voltage VDD is applied to a first positive power supply terminal of the level shifter 208. A ground potential is applied to a first negative power supply terminal of the level shifter 208. A boosted voltage Vboot is applied to a second positive power supply terminal of the level shifter 208. A switch voltage Vsw is applied to a second negative power supply terminal of the level shifter 208. The level shifter 208 shifts the level of the control signal CNT, which becomes the power supply voltage VDD when at a high level and the ground potential when at a low level, to generate a signal which becomes the boost voltage Vboot when at a high level and the switch voltage Vsw when at a low level, and supplies the signal to the drivers 201 to 203. Note that although the description of the level shifter 208 is omitted in the first and second configuration examples of the high side pre-driver 20, the high side pre-driver 20 also includes the level shifter 208 in the first and second configuration examples of the high side pre-driver 20.

[0072] The inverter IV1 generates an inverted signal of the control signal CNT and supplies the inverted signal to the low-side pre-driver 21.

[0073] The low-side pre-driver 21 of the configuration example shown in FIG. 13 includes a level shifter 210 and a driver 211. The level shifter 210 has the same circuit configuration as the level shifter 208. A power supply voltage VDD is applied to a first positive power supply terminal and a second positive power supply terminal of the level shifter 210. A ground potential is applied to a first negative power supply terminal and a second negative power supply terminal of the level shifter 208. The level shifter 208 level-shifts an inverted signal of a control signal CNT that becomes the power supply voltage VDD when at a high level and becomes the ground potential when at a low level, generates a signal that becomes the power supply voltage VDD when at a high level and becomes the ground potential when at a low level, and supplies the signal to the driver 211. That is, the level shift amount in the level shifter 210 is zero.

[0074] In the low-side pre-driver 21 of the configuration example shown in FIG. 13, a level shifter 210, which is not actually necessary on the low side, is intentionally provided, and the level shifter 210 is used as a delay circuit.

[0075] Since the delay in the inverter IV1 can be considered to be zero, the length of the delay from when the control logic unit 19 issues a turn-on command to when the switch elements (high-side switch element M1, low-side switch element M2) are actually turned on can be matched between the high side and the low side by providing the level shifter 210 that pairs with the level shifter 208. This allows the design value of the dead time to be shortened even if the dead time is extended by switching the output current capacity of the high-side pre-driver during the transition of the high-side switch element M1 from off to full on.

[0076] Furthermore, by making the level shifter 210 and the level shifter 208 have the same circuit configuration, it is possible to improve robustness against manufacturing variations.

[0077] <Application Examples> 14 is an external view of a vehicle X. The vehicle X of this configuration example is equipped with various electronic devices X11 to X18 that operate by receiving a supply of voltage output from a battery (not shown). Note that the mounting positions of the electronic devices X11 to X18 in this figure may differ from the actual positions for convenience of illustration.

[0078] The electronic device X11 is an engine control unit that performs engine-related controls (such as injection control, electronic throttle control, idling control, oxygen sensor heater control, and auto-cruise control).

[0079] The electronic device X12 is a lamp control unit that controls the turning on and off of HID [high intensity discharged lamp] and DRL [daytime running lamp].

[0080] The electronic device X13 is a transmission control unit that performs control related to the transmission.

[0081] The electronic device X14 is a braking unit that performs control related to the motion of the vehicle X (ABS [anti-lock brake system] control, EPS [electric power steering] control, electronic suspension control, etc.).

[0082] The electronic device X15 is a security control unit that controls the operation of door locks, burglar alarms, and the like.

[0083] The electronic device X16 is an electronic device that is installed in the vehicle X at the factory as a standard equipment or a manufacturer's option, such as a wiper, an electric door mirror, a power window, a damper (shock absorber), an electric sunroof, and an electric seat.

[0084] The electronic device X17 is an electronic device that is optionally installed in the vehicle X as a user option, such as an in-vehicle A / V (audio / visual) device, a car navigation system, and an ETC (electronic toll collection system).

[0085] The electronic device X18 is an electronic device equipped with a high-voltage resistant motor, such as an in-vehicle blower, oil pump, water pump, or battery cooling fan.

[0086] The switching power supply device AA described above can be incorporated in any of the electronic devices X11 to X18. Furthermore, the application of the switching power supply device AA described above is not limited to a power supply mounted on the vehicle X, and may be, for example, a power supply mounted on industrial equipment.

[0087] <Other> In addition to the above-described embodiment, various modifications can be made to the configuration of the invention without departing from the spirit of the invention. The above-described embodiment should be considered to be illustrative in all respects and not restrictive, and the technical scope of the present invention is indicated by the claims, not the description of the above-described embodiment, and should be understood to include all modifications that fall within the meaning and scope of the claims.

[0088] <Additional Notes> Regarding the present disclosure, specific configuration examples of which have been shown in the above-mentioned embodiments, additional notes will be provided.

[0089] A gate drive circuit (20) of the present disclosure is a gate drive circuit configured to drive the gate of a power transistor (M1), and includes a switching unit (200) configured to switch an output current capacity, the switching unit being configured to switch the output current capacity from a first capacity to a second capacity greater than the first capacity during a transition of the power transistor from off to full on (first configuration).

[0090] According to the gate drive circuit of the first configuration, it is possible to achieve both low ringing and low switching loss.

[0091] In the gate drive circuit of the first configuration, a configuration (second configuration) may be provided that includes a plurality of drivers (201, 202, 203) configured to drive the gates of the power transistors, and the switching unit is configured to switch the number of drivers to be operated among the plurality of drivers.

[0092] In the gate drive circuit of the first configuration, a configuration (third configuration) may be provided in which the gate drive circuit is provided with a driver (205, 206, 207) configured to drive the gate of the power transistor, the driver including a variable current source (205), and the switching unit is configured to control the variable current source.

[0093] In the gate drive circuit of any of the above first to third configurations, the switching unit may be configured to switch the output current capacity from the first capacity to the second capacity when a predetermined time has elapsed from the start of a transition operation that transitions the power transistor from off to fully on (fourth configuration).

[0094] In the gate drive circuit of any of the above first to third configurations, the switching unit may be configured to switch the output current capacity from the first capacity to the second capacity when the gate-source voltage of the power transistor reaches a predetermined value (fifth configuration).

[0095] In the gate drive circuit of any of the above first to third configurations, the switching unit may be configured to switch the output current capacity from the first capacity to the second capacity when a rate of change of the gate-source voltage of the power transistor reaches a predetermined value (sixth configuration).

[0096] A power supply control device (1) of the present disclosure has a configuration (seventh configuration) including a gate drive circuit of any of the first to sixth configurations described above, and a control circuit (19) configured to control the gate drive circuit.

[0097] The power supply control device of the seventh configuration may further include a low-side gate drive circuit (21) configured to drive a gate of a low-side power transistor (M2) that is connected in series with the power transistor and is provided on a lower potential side than the power transistor, the low-side gate drive circuit including a delay circuit (210) configured to delay a signal based on an output signal of the control circuit, and the low-side gate drive circuit may be configured to turn on the low-side power transistor based on the output signal of the delay circuit, and to turn off the low-side power transistor based on the output signal of the delay circuit (eighth configuration).

[0098] The power supply device (AA) of the present disclosure has a configuration (ninth configuration) including the power supply control device of the seventh or eighth configuration and the power transistor.

[0099] A vehicle (X) of the present disclosure has a configuration (tenth configuration) that includes the power supply device of the ninth configuration described above. [Explanation of symbols]

[0100] 1 Power IC 10 Control section 11 Error Amplifier 12 Reference Voltage Source 13 Resistance 14 Capacitor 15 Slope voltage generator 15A IV conversion unit 15B Lamp voltage generator 15C Addition section 16 Main Comparator 17 Clock Generation Unit 18 Set signal generator 19 Control logic section 20 High side pre-driver 200, 204 Switching section 200A delay circuit 200B, 200C, 200E signal generation circuit 200D Differential Circuit 201~203 Driver 205 Variable Resistor 206 PMOS Transistor 207 NMOS Transistor 208 Level Shifter 21 Low side pre-driver 210 Level Shifter 211 Driver 30 Internal power circuit AA Switching Power Supply C1 Output capacitor IV1 Inverter L1 Inductor LD load LN1 Line M1 High side switch element M2 Low-side switch element R1, R2 Feedback resistors TM1~TM4 external terminals X Vehicle X11~X18 Electronic equipment

Claims

1. 1. A gate drive circuit configured to drive a gate of a power transistor, comprising: A switching unit configured to switch an output current capability, The switching unit is configured to switch the output current capacity from a first capacity to a second capacity greater than the first capacity during a transition of the power transistor from off to full on.

2. a plurality of drivers configured to drive gates of the power transistors; The gate drive circuit according to claim 1 , wherein the switching unit is configured to switch the number of drivers to be operated among the plurality of drivers.

3. a driver configured to drive a gate of the power transistor; The driver includes a variable current source; The gate drive circuit of claim 1 , wherein the switching unit is configured to control the variable current source.

4. 2. The gate drive circuit according to claim 1, wherein the switching unit is configured to switch the output current capacity from the first capacity to the second capacity when a predetermined time has elapsed from the start of a transition operation that transitions the power transistor from off to full on.

5. 2. The gate drive circuit according to claim 1, wherein the switching unit is configured to switch the output current capacity from the first capacity to the second capacity when a gate-source voltage of the power transistor reaches a predetermined value.

6. 2. The gate drive circuit according to claim 1, wherein the switching unit is configured to switch the output current capacity from the first capacity to the second capacity when a rate of change of a gate-source voltage of the power transistor reaches a predetermined value.

7. A gate drive circuit according to any one of claims 1 to 6; a control circuit configured to control the gate drive circuit; A power supply control device comprising:

8. a low-side gate drive circuit configured to drive a gate of a low-side power transistor that is connected in series with the power transistor and is provided on a lower potential side than the power transistor; the low-side gate drive circuit includes a delay circuit configured to delay a signal based on an output signal of the control circuit; 8. The power supply control device according to claim 7, wherein the low-side gate drive circuit is configured to turn on the low-side power transistor based on an output signal of the delay circuit, and to turn off the low-side power transistor based on the output signal of the delay circuit.

9. A power supply control device according to claim 7 ; The power transistor; A power supply device comprising:

10. A vehicle comprising the power supply device according to claim 9.

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