Semiconductor device

Abstract

To provide a semiconductor device whose reverse recovery characteristic at diode operation is improved.SOLUTION: An embodiment includes a first electrode, a second electrode, a semiconductor part, a gate electrode, and a first part with an insulating property. The first electrode and the second electrode are provided in a first region, a second region, and a third region. The semiconductor part is provided between the first electrode and the second electrode. In the first region, the gate electrode is provided in the semiconductor part. The first part is provided on the first electrode in the third region. The first region is an IGBT region, and the second region is a diode region. The third region separates the first region and the second region between the first region and the second region. In the third region, a bottom surface of the first part is in contact with the first electrode, an upper surface of the first part is in contact with a fourth semiconductor layer, and a side surface of the first part is in contact with the third semiconductor layer.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The embodiments relate to a semiconductor device. [Background technology]

[0002] IGBTs (Insulated Gate Bipolar Transistors) are widely used as semiconductor elements for power control. Among them, there is the reverse conductive IGBT (RC-IGBT), which is integrated with diodes connected in antiparallel.

[0003] In such RC-IGBTs, there is a strong demand for improving the reverse recovery characteristics of the integrated diode. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent No. 5332376 Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the embodiments is to provide a semiconductor device with improved reverse recovery characteristics during diode operation. [Means for solving the problem]

[0006] The semiconductor device of the embodiment comprises a first electrode provided across a first region, a second region, and a third region between the first region and the second region, a second electrode provided across the first region, the second region, and the third region, a semiconductor portion provided between the first electrode and the second electrode, a gate electrode extending into the semiconductor portion between the second electrode and the semiconductor portion in the first region and electrically isolated from the semiconductor portion, and an insulating first portion provided on the first electrode in the third region. the semiconductor section includes: a first semiconductor layer of a first conductivity type provided on the first electrode in the first region and electrically connected to the first electrode; a second semiconductor layer of a second conductivity type provided on the first electrode in the second region and electrically connected to the first electrode; a third semiconductor layer of the second conductivity type provided on the first semiconductor layer and the second semiconductor layer in the first region and the second region; a fourth semiconductor layer of the second conductivity type provided on the third semiconductor layer and on the first portion in the first region, the second region, and the third region; a fifth semiconductor layer of the first conductivity type provided on the fourth semiconductor layer in the first region and electrically connected to the second electrode; a sixth semiconductor layer of the second conductivity type selectively provided on the fifth semiconductor layer and electrically connected to the second electrode; The gate electrode faces the fifth semiconductor layer via a gate insulating film. A bottom surface of the first portion contacts the first electrode. A top surface of the first portion contacts the fourth semiconductor layer. A side surface of the first portion contacts the third semiconductor layer. [Brief description of the drawings]

[0007] [Figure 1] 1 is a schematic cross-sectional view illustrating a semiconductor device according to an embodiment; [Diagram 2]5A to 5C are schematic cross-sectional views for explaining the operation of the semiconductor device according to the embodiment. [Diagram 3] 11 is a schematic cross-sectional view for explaining the operation of a semiconductor device of a comparative example. FIG. [Figure 4] 11A and 11B are schematic cross-sectional views illustrating semiconductor devices according to modified examples. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as those in reality. Even when the same part is shown, the dimensions and ratios of each part may be different depending on the drawing. In this specification and each drawing, elements similar to those already explained are given the same reference numerals and detailed explanations are omitted as appropriate.

[0009] In the following description and drawings, n + , n - and p + The notation "p" indicates the relative level of each impurity concentration. In other words, a notation with "+" indicates a relatively higher impurity concentration than a notation with neither "+" nor "-" and a notation with "-" indicates a relatively lower impurity concentration than a notation with neither. When both p-type and n-type impurities are contained in each region, these notations indicate the relative level of the net impurity concentration after the impurities compensate for each other. In each embodiment described below, the p-type and n-type of each semiconductor region may be reversed to implement each embodiment.

[0010] FIG. 1 is a schematic cross-sectional view illustrating a semiconductor device according to an embodiment. 1, a semiconductor device 100 according to the embodiment includes a collector electrode 1, an emitter electrode 2, a semiconductor portion 10, a gate electrode 21, and an insulator 61. The semiconductor portion 10 is provided between the collector electrode 1 and the emitter electrode 2. The insulator 61 is provided on the collector electrode 1 and extends from the collector electrode 1 into the semiconductor portion 10.

[0011] A collector electrode (first electrode) 1 is provided on the back surface of the semiconductor portion 10 and functions as one of the main electrodes of the RC-IGBT. An emitter electrode (second electrode) 2 is provided on the front surface side of the semiconductor portion 10 and functions as one of the main electrodes of the RC-IGBT. The gate electrode 21 faces the semiconductor portion 10 via a gate insulating film 31.

[0012] The semiconductor device 100 includes a first region I, a second region II, and a third region III. The third region III is provided between the first region I and the second region II.

[0013] In the first region I, the semiconductor device 100 mainly operates as an IGBT. The operation as an IGBT means that, in an n-type IGBT, the IGBT turns on when a voltage sufficiently higher than the gate threshold voltage is applied to the gate electrode 21, and turns off when a voltage sufficiently lower than the gate threshold voltage is applied to the gate electrode 21.

[0014] In the second region II, the semiconductor device 100 mainly operates as a diode. In the case of an n-type IGBT, operation as a diode refers to an operation in which, when the IGBT is off, a current flows into the emitter electrode 2 and a current flows out from the collector electrode 1. Hereinafter, the operation of the semiconductor device as an IGBT may be referred to as IGBT operation, and the operation of the semiconductor device as a diode may be referred to as diode operation.

[0015] The third region III electrically separates the first region I and the second region II. A distance W3 is the width of the third region III and is the distance between the first region I and the second region II.

[0016] The collector electrode 1, the semiconductor portion 10 and the emitter electrode 2 are provided across the first region I, the second region II and the third region III.

[0017] Hereinafter, the configuration of the semiconductor device 100 may be described using an XYZ coordinate system. The description will be made assuming that the direction from the collector electrode 1 toward the emitter electrode 2 is the direction of the Z axis. The first region I, the third region III, and the second region II are arranged in this order in the direction of the X axis perpendicular to the Z axis. For example, the first region I and the second region II are arranged alternately with the third region III therebetween. That is, in the specific example of FIG. 1, the first region I may be arranged on the positive side of the second region II along the X axis with the third region III therebetween. Also, the second region II may be arranged on the negative side of the first region I along the X axis with the third region III therebetween. The repetition of the arrangement of the first region I to the third region III may be applied in the Y axis direction.

[0018] The longer the distance W3, the smaller the interference between the operation in the first region I and the operation in the second region II. On the other hand, the longer the distance W3, the larger the area of ​​the semiconductor device 100 in a plan view, and the lower the cost performance.

[0019] In the semiconductor device 100 according to the embodiment, the insulator (first portion) 61 is provided in the third region III. The width W0 of the insulator 61 is equal to or shorter than the distance W3. By including the insulator 61, the semiconductor device 100 can suppress interference between the operation in the first region I and the operation in the second region II even when the distance W3 is short.

[0020] The interference between the operation in the first region I and the operation in the second region II means that minority carriers injected into the first region I move to the second region II when the semiconductor device 100 operates as a diode. When the minority carriers injected into the first region I move to the second region II, the charge amount of the minority carriers in the second region II becomes excessive, and the reverse recovery time becomes long. The insulator 61 is provided in the third region III to restrict the movement of minority carriers from the first region I to the second region II.

[0021] The configuration of the semiconductor device 100 will be described in more detail. In the following, the semiconductor device 100 will be described as an n-type RC-IGBT. When the semiconductor device 100 operates as a diode, the collector electrode 1 functions as a cathode electrode of the diode, and the emitter electrode 2 functions as an anode electrode of the diode.

[0022] The semiconductor portion 10 is - A drift layer 11 and a p - a p-type base layer 12a, a p-type anode layer 12b, and + A source layer 13 and a p + collector layer 14, and + A cathode layer 15 and a n + A buffer layer 16 and a p + The semiconductor portion 10 includes a p-type emitter layer 17. + The semiconductor portion 10 further includes an n-type contact layer 18 and an n-type barrier layer 19. The semiconductor portion 10 includes, for example, Si.

[0023] p + The collector layer (first semiconductor layer) 14 is provided on the collector electrode 1 in the first region I and is electrically connected to the collector electrode 1. + The collector layer 14 is not provided in the second region II and the third region III.

[0024] n + The cathode layer (second semiconductor layer) 15 is provided on the collector electrode 1 in the second region II and is electrically connected to the collector electrode 1. + The cathode layer 15 is not provided in the first region I and the third region III.

[0025] n + The buffer layer (third semiconductor layer) 16 has a p + The collector layer 14 is provided on the + The second region II of the buffer layer 16 is + The cathode layer 15 is provided on the cathode layer 15. +The n-type buffer layer 16 is provided on the collector electrode 1 in the third region III. + The shape buffer layer 16 surrounds the insulator 61 in the third region III.

[0026] n - The n-type drift layer (fourth semiconductor layer) 11 is formed in the first region I and the second region II. + The buffer layer 16 is provided on the - The n-type drift layer 11 is provided on the insulator 61 in the third region III. - The drift layer 11 is + The insulating layer 16 is provided on the insulating film 16 .

[0027] The n-type barrier layer 19 has a first region I. - The n-type barrier layer 19 is provided on the n-type drift layer 11. The n-type barrier layer 19 is not provided in the second region II and the third region III.

[0028] p - The n-type base layer (fifth semiconductor layer) 12a is provided on the n-type barrier layer 19 in the first region I. - The shape base layer 12a is not provided in the second region II and the third region III.

[0029] The p-type anode layer (seventh semiconductor layer) 12b has n - The p-type anode layer 12b is provided on the first region I.

[0030] n + The source layer (sixth semiconductor layer) 13 has a p - The shape is selectively provided on the base layer 12a. + The source layer 13 is not provided in the second region II and the third region III.

[0031] p + The eighth semiconductor layer 17 has a p -The shape is selectively provided on the base layer 12a. + The p-type emitter layer 17 is provided on the p-type anode layer 12b in the second region II and the third region III.

[0032] p + The contact layer 18 has a p - In the first region I, p + The contact layer 18 is a p + The emitter layer 17 is provided at a position where it is not provided. + The contact layer 18 is not provided in the second region II and the third region III.

[0033] n - The impurity concentration of the drift layer 11 is n + Shaped cathode layer 15, n + The buffer layer 16 and the n + The impurity concentration of each of the n-type source layers is lower than that of the n-type source layers. - The impurity concentration of the n-type drift layer 11 is lower than the impurity concentration of the n-type barrier layer 19. - Drift layer 11 and p - When a reverse bias is applied between the n-type base layer 12a and the n-type base layer 12b, the depletion layer - The n-type drift layer 11 extends into the n-type drift layer 11, and the desired breakdown voltage is realized. - When a reverse bias is applied between the n-type drift layer 11 and the p-type anode layer 12b, the depletion layer - The MOSFET's 14 extend into drift layer 11 and achieve a desired breakdown voltage.

[0034] p + The impurity concentration of the emitter layer 17 is p - The impurity concentration of the p-type base layer 12a is higher than that of the p-type base layer 12b. + The impurity concentration of the p-type emitter layer 17 is higher than the impurity concentration of the p-type anode layer 12b.

[0035] The insulator 61 is provided in the third region III, and preferably provided over the entire third region III. The insulator 61 is provided on the collector electrode 1, and a lower surface 61B of the insulator 61 is in contact with the collector electrode 1. The insulator 61 is provided on a side surface 61S of the insulator 61. + The insulator 61 is in contact with the n-type buffer layer 16. + The insulator 61 is disposed to separate the n-type buffer layer 16. Preferably, as in the embodiment of FIG. - The insulator 61 extends into the drift layer 11. - The insulator 61 is in contact with the drift layer 11 and has an upper side surface 61S of n - The semiconductor device is in contact with the drift layer 11 .

[0036] The insulator 61 includes an insulating material such as a silicon oxide or silicon nitride, and includes, for example, SiO2. The insulator 61 may be any other insulating material as long as it can block the movement of holes, and may include, for example, an insulating material such as rubber or other resin. The inside of the insulator 61 does not have to be entirely filled with an insulating material, and may include voids, etc.

[0037] The insulator 61 can be formed, for example, as follows. That is, in the third region III, + The n-type buffer layer 16 is penetrated. - A recess is formed so as to reach the drift layer 11, and a SiO2 film is formed in the recess. The recess has a bottom surface facing the top surface 61T of the insulator 61, and a side surface that is continuous with the bottom surface and faces the side surface 61S of the insulator 61. The recess can be formed by, for example, an anisotropic etching method such as reactive ion etching (RIE). The SiO2 film can be formed by, for example, chemical vapor deposition (CVD).

[0038] The gate electrode 21 extends from the surface of the semiconductor portion 10 toward the inside in the first region I, and is electrically isolated from the semiconductor portion 10. The gate electrode 21 is connected to a p -The gate electrode 21 faces the n-type base layer 12a through a gate insulating film 31. The gate electrode 21 faces the n-type barrier layer 19 through the gate insulating film 31. - The shaped drift layer 11 faces a part of the shaped drift layer 11 .

[0039] 1, the conductor 41 is provided between two gate electrodes 21 aligned in the X-axis direction. The conductor 41 extends from the surface of the semiconductor portion 10 toward the inside, and is electrically isolated from the semiconductor portion 10.

[0040] In the first region I, the conductor 41 is connected to the insulating film 51 via a p - The conductor 41 faces the base layer 12a in the first region I. + The conductor 41 faces the emitter layer 17. In the first region I, the conductor 41 is connected to the p + The conductor 41 faces the n-type contact layer 18 in the first region I. The conductor 41 faces the n-type barrier layer 19 in the first region I. - The shaped drift layer 11 faces a part of the shaped drift layer 11 .

[0041] The conductor 41 extends from the surface of the semiconductor portion 10 toward the inside in each of the second region II and the third region III, and is electrically isolated from the semiconductor portion 10.

[0042] The conductor 41 faces the p-type anode layer 12b through the insulating film 51 in each of the second region II and the third region III. + The conductor 41 faces the n-type emitter layer 17 in each of the second region II and the third region III via the insulating film 51. - The shaped drift layer 11 faces a part of the shaped drift layer 11 .

[0043] Although not shown, the gate electrode 21 and the conductor 41 extend in the Y-axis direction and are provided in a stripe shape in a plan view. The gate electrode 21 and the conductor 41 include, for example, polycrystalline Si.

[0044] The emitter electrode 2 has n + On the source layer 13, p + On the emitter layer 17, p + The emitter electrode 2 is provided on the contact layer 18 and the conductor 41. In the first region I, the emitter electrode 2 has an n + Shape source layer 13, p + Emitter layer 17, p + The contact layer 18 and the conductor 41 are electrically connected.

[0045] The emitter electrode 2 is provided on the gate electrode 21 in the first region I. The emitter electrode 2 is electrically isolated from the gate electrode 21 by an interlayer insulating film 32 provided between the emitter electrode 2 and the gate electrode 21.

[0046] The emitter electrode 2 has p + The emitter electrode 2 is provided on the emitter layer 17 and the conductor 41. The emitter electrode 2 is provided on the p + The emitter layer 17 and the conductor 41 are electrically connected.

[0047] The operation of the semiconductor device 100 according to the embodiment will be described. FIG. 2 is a schematic cross-sectional view for explaining the operation of the semiconductor device according to the embodiment. In FIG. 2, the paths and directions of hole movement when the semiconductor device 100 operates as a diode are indicated by arrows A11 to A21.

[0048] First, the case where the semiconductor device 100 operates as an IGBT will be described. In the IGBT operation, when the semiconductor device 100 is turned on, a sufficiently high voltage exceeding the gate threshold is applied to the gate electrode 21 relative to the emitter electrode 2. - An inversion layer is formed on the surface of the base layer 12a. + Electrons supplied from the n-type source layer 13 pass through the inversion layer, - Drift layer 11 and n + The ions flow into the buffer layer 16.

[0049] A higher voltage is applied to the collector electrode 1 than to the emitter electrode 2, so p + The collector layer 14 is a n-type + The buffer layer 16 and the n - The ions are injected into the drift layer 11. This turns on the IGBT.

[0050] In the IGBT operation, when the semiconductor device 100 is turned off, a sufficiently low voltage lower than the gate threshold is applied to the gate electrode 21 with respect to the emitter electrode 2. For example, by applying a negative voltage with respect to the voltage of the emitter electrode 2, p - An accumulation layer is formed on the base layer 12a.

[0051] n - The holes in the drift layer 11 form an accumulation layer and a p - The electrons are collected on the emitter electrode 2 side through the base layer 12a. A sufficiently low voltage is applied to the emitter electrode 2 to - When an accumulation layer is formed in the base layer 12a, excess holes are collected, and the turn-off speed of the semiconductor device 100 is improved.

[0052] Next, a case where the semiconductor device 100 operates as a diode will be described. As shown in FIG. 2, in the diode operation, a voltage higher than that applied to the collector electrode 1 is applied to the emitter electrode 2, so that the p + Holes are emitted from the emitter layer 17. -The electrons are injected into the n-type drift layer 11. Depending on the amount of charge of the injected holes, + Electrons are supplied from the cathode layer 15 , and a current flows from the emitter electrode 2 to the collector electrode 1 .

[0053] In the first region I, the holes are p + Emitter layer 17 and p + From the n-type contact layer 18, through the n-type barrier layer 19, - The ions are injected into the drift layer 11.

[0054] n in the first region I - The holes injected into the drift layer 11 are - There are two paths leading to drift layer 11: a first path indicated by arrows A11, A12, and A13, and a second path indicated by arrow A21.

[0055] Each of the arrows A11, A12, and A13 constitutes a part of the first path. - Drift layer 11 to n + The arrow A12 indicates a part of the path leading to the crystalline buffer layer 16. + The n-type buffer layer 16 of the third region III + The arrow A13 indicates a part of the path leading to the n-type buffer layer 16 of the third region III. + The n-type buffer layer 16 of the second region II + 1 shows a portion of the path leading to the shape buffer layer 16.

[0056] In the second path, the arrow A21 points to the n - From the drift layer 11, the n - The n-type drift layer 11 of the second region II - 1 represents a path leading to the drift layer 11.

[0057] In the semiconductor device 100 according to the embodiment, an insulator 61 is provided on the collector electrode 1 in the third region III. The insulator 61 has a thickness of n +The n-type buffer layer 16 is formed between the first region I and the second region II. + Therefore, as shown by the dashed arrow A13, in the first path, the n-type buffer layer 16 of the first region I - The movement of holes injected into the drift layer 11 to the second region II is blocked by the insulator 61 in the third region III.

[0058] In the first route, n - The n-type drift layer 11 has a sheet resistance lower than that of the n-type drift layer 11. + The shaped buffer layer 16 is included as a part of the path. As a result, the resistance value of the first path consisting of the arrows A11, A12, and A13 in FIG. 2 is lower than the resistance value of the second path consisting of the arrow A21. - Most of the holes injected into the drift layer 11 are supposed to reach the second region II via the first path, but because their movement is blocked by the insulator 61, they are unable to reach the second region II, thereby suppressing the deterioration of the reverse recovery characteristics in the second region II.

[0059] FIG. 3 is a schematic cross-sectional view for explaining the operation of the semiconductor device 100a of the comparative example. As shown in FIG. 3, in the semiconductor device 100a of the comparative example, instead of the insulator 61 provided in the third region III, the distance W3a of the third region III is set sufficiently long.

[0060] Each of the arrows A11a and A12a constitutes a part of the first path. The arrow A21a constitutes the second path. In either path, the resistance value of the path can be substantially increased by making the length of the path sufficiently long. This allows the n - This can suppress the holes injected into the drift layer 11 from moving to the second region II.

[0061] On the other hand, the distance W3a of the third region III becomes longer, and the area of ​​the region that does not contribute to either the IGBT operation or the diode operation increases, which reduces the cost performance of the semiconductor device 100a.

[0062] (Modification) FIG. 4 is a schematic cross-sectional view illustrating a semiconductor device according to a modified example. 4, the semiconductor device 200 according to this modification has a high resistance portion (second portion) 71 in the third region III. - The high resistance portion 71 is provided in the n-type drift layer 11. The high resistance portion 71 is provided on the upper surface 61T of the insulator 61. The n-type impurity concentration of the high resistance portion 71 is - The n-type impurity concentration of the n-type drift layer 11 is lower than that of the n-type drift layer 11.

[0063] The high resistance portion 71 is formed in the third region III as follows: - The second region II has a sheet resistance lower than that of drift layer 11. As a result, the movement of holes through the first path shown in FIG. 2 can be more reliably blocked, and the movement of holes through the second path can be suppressed, thereby more reliably preventing the deterioration of the reverse recovery characteristics in second region II.

[0064] The high resistance portion 71 can be formed, for example, as follows. That is, after forming a recess for forming the insulator 61, the n - The high resistance portion 71 can be formed by introducing p-type impurities into the drift layer 11. The p-type impurities can be introduced by, for example, ion implantation.

[0065] The effects of the semiconductor device 100 according to the embodiment and the semiconductor device 200 according to the modification will be described. In the semiconductor devices 100 and 200, when a reverse bias is applied between the collector electrode 1 and the emitter electrode 2, n - In order to prevent the depletion layer formed in the n-type drift layer 11 from extending to the collector electrode 1, +A buffer layer 16 is provided. + When the semiconductor device 100 or 200 operates as a diode, the n-type buffer layer 16 can be a path through which holes injected into the first region I move to the second region II. In the semiconductor device 100 or 200 according to the embodiment, in the third region III between the first region I and the second region II, + An insulator 61 is provided to divide the n-type buffer layer 16. + The movement of holes to the second region II via the buffer layer 16 is blocked, the amount of charge of excess holes in the second region II is reduced, and the reverse recovery characteristic is improved.

[0066] By making the width W0 of the insulator 61 sufficient, the movement of holes from the first region I to the second region II can be blocked more reliably. + Shape buffer layer 16 to n - By extending the insulating film 14 sufficiently into the drift layer 11, the movement of holes from the first region I to the second region II can be blocked more reliably.

[0067] In the semiconductor device 200 according to the modified example, the high resistance portion 71 is provided on the insulator 61, so that the movement of holes from the first region I to the second region II can be blocked more reliably.

[0068] In each of the embodiments described above, the relative level of the impurity concentration between each semiconductor region can be confirmed, for example, by using a scanning capacitance microscope (SCM). The carrier concentration in each semiconductor region can be considered to be equal to the concentration of the activated impurities in each semiconductor region. Therefore, the relative level of the carrier concentration between each semiconductor region can also be confirmed by using the SCM. The impurity concentration in each semiconductor region can also be measured, for example, by SIMS (secondary ion mass spectrometry).

[0069] Although some embodiments of the present invention have been illustrated above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, modifications, etc. can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are included in the scope of the invention and its equivalents described in the claims. In addition, the above-mentioned embodiments can be implemented in combination with each other.

[0070] The embodiments include the following aspects.

[0071] (Appendix 1) a first electrode provided across a first region, a second region, and a third region between the first region and the second region; a second electrode provided across the first region, the second region, and the third region; A semiconductor portion provided between the first electrode and the second electrode; a gate electrode extending into the semiconductor portion between the second electrode and the semiconductor portion in the first region and electrically isolated from the semiconductor portion; a first portion having insulating properties and provided on the first electrode in the third region; Equipped with The semiconductor portion is a first semiconductor layer of a first conductivity type provided on the first electrode in the first region and electrically connected to the first electrode; a second semiconductor layer of a second conductivity type provided on the first electrode in the second region and electrically connected to the first electrode; a third semiconductor layer of the second conductivity type provided on the first semiconductor layer and the second semiconductor layer in the first region and the second region; a fourth semiconductor layer of the second conductivity type provided on the third semiconductor layer and on the first portion in the first region, the second region, and the third region; a fifth semiconductor layer of the first conductivity type provided on the fourth semiconductor layer in the first region and electrically connected to the second electrode; a sixth semiconductor layer of the second conductivity type selectively provided on the fifth semiconductor layer and electrically connected to the second electrode; a seventh semiconductor layer of the first conductivity type provided on the fourth semiconductor layer in the second region and the third region and electrically connected to the second electrode; an eighth semiconductor layer of the first conductivity type selectively provided on the fifth semiconductor layer, provided on the seventh semiconductor layer, and electrically connected to the second electrode; Including, the gate electrode faces the fifth semiconductor layer via a gate insulating film, A semiconductor device in which a bottom surface of the first portion is in contact with the first electrode, a top surface of the first portion is in contact with the fourth semiconductor layer, and a side surface of the first portion is in contact with the third semiconductor layer.

[0072] (Appendix 2) 2. The semiconductor device according to claim 1, wherein a side surface of the first portion contacts the fourth semiconductor layer at an upper portion of the first portion.

[0073] (Appendix 3) 3. The semiconductor device according to claim 1, further comprising, in the third region, a first portion on the first portion, the first portion having a carrier concentration lower than a carrier concentration of the fourth semiconductor layer.

[0074] (Appendix 4) 4. The semiconductor device according to claim 3, wherein the first portion is in contact with an upper surface of the first portion.

[0075] (Appendix 5) the third semiconductor layer is provided on the first electrode, 5. The semiconductor device according to claim 1, wherein a side surface of the first portion is in contact with the third semiconductor layer.

[0076] (Appendix 6) 6. The semiconductor device according to claim 1, wherein the first portion is provided so as to separate the third semiconductor layer in the first region from the third semiconductor layer in the second region.

[0077] (Appendix 7) 7. The semiconductor device according to claim 1, wherein the first portion contains a Si oxide or a Si nitride. [Explanation of symbols]

[0078] 1...collector electrode, 2...emitter electrode, 10...semiconductor portion, 11...n - Shape drift layer, 12a…p - p-type base layer, 12b...p-type anode layer, 13...n + Shape source layer, 14...p + Collector layer, 15...n + Shape cathode layer, 16...n + Shape buffer layer, 17...p + Emitter layer, 18...p + n-type contact layer, 19... n-type barrier layer, 21... gate electrode, 31... gate insulating film, 32... interlayer insulating film, 41... conductor, 51... insulating film, 61... insulator, 61B... bottom surface, 61S... side surface, 61T... upper surface, 71... high resistance portion, 100, 200... semiconductor device

Claims

1. a first electrode provided across a first region, a second region, and a third region between the first region and the second region; a second electrode provided across the first region, the second region, and the third region; A semiconductor portion provided between the first electrode and the second electrode; a gate electrode extending in the semiconductor portion between the second electrode and the semiconductor portion in the first region and electrically isolated from the semiconductor portion; a first portion having insulating properties and provided on the first electrode in the third region; Equipped with The semiconductor portion is a first semiconductor layer of a first conductivity type provided on the first electrode in the first region and electrically connected to the first electrode; a second semiconductor layer of a second conductivity type provided on the first electrode in the second region and electrically connected to the first electrode; a third semiconductor layer of the second conductivity type provided on the first semiconductor layer and the second semiconductor layer in the first region and the second region; a fourth semiconductor layer of the second conductivity type provided on the third semiconductor layer and on the first portion in the first region, the second region, and the third region; a fifth semiconductor layer of the first conductivity type provided on the fourth semiconductor layer in the first region and electrically connected to the second electrode; a sixth semiconductor layer of the second conductivity type selectively provided on the fifth semiconductor layer and electrically connected to the second electrode; a seventh semiconductor layer of the first conductivity type provided on the fourth semiconductor layer in the second region and the third region and electrically connected to the second electrode; an eighth semiconductor layer of the first conductivity type selectively provided on the fifth semiconductor layer, provided on the seventh semiconductor layer, and electrically connected to the second electrode; Including, the gate electrode faces the fifth semiconductor layer via a gate insulating film, A semiconductor device, wherein a bottom surface of the first portion is in contact with the first electrode, a top surface of the first portion is in contact with the fourth semiconductor layer, and a side surface of the first portion is in contact with the third semiconductor layer.

2. The semiconductor device according to claim 1 , wherein a side surface of the first portion contacts the fourth semiconductor layer at an upper portion of the first portion.

3. 2. The semiconductor device of claim 1, further comprising a second portion, in the third region, above the first portion, the second portion having a carrier concentration lower than a carrier concentration of the fourth semiconductor layer.

4. The semiconductor device according to claim 3 , wherein the second portion is in contact with an upper surface of the first portion.

5. The third semiconductor layer is provided on the first electrode, The semiconductor device according to claim 1 , wherein a side surface of the first portion is in contact with the third semiconductor layer.

6. The semiconductor device according to claim 1 , wherein the first portion is provided so as to separate the third semiconductor layer in the first region from the third semiconductor layer in the second region.

7. 7. The semiconductor device according to claim 1, wherein the first portion includes a silicon oxide or a silicon nitride.

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