processor

Abstract

To provide a processor that suppresses memory access latency.SOLUTION: A processor includes a plurality of core circuits CORE, and a cache unit $_UNIT having a plurality of caches from a primary cache L1$ and a secondary cache L2$ to an Nth-order cache (N is an integer equal to or greater than 3). The primary cache includes a move-in buffer MIB having plurality of entries for storing a memory access instruction that has resulted in a cache miss in the primary cache. When the move-in buffer issues, to the secondary cache, a memory request RQ to perform memory access of the memory access instruction that has resulted in a cache miss, the move-in buffer parallelly issues, to caches from the tertiary cache to the Nth-order cache, a pseudo memory request P_RQ to perform memory access, and receives a pseudo data response having data for which coherency is not secured from any of caches where the pseudo memory request has resulted in a cache hit.SELECTED DRAWING: Figure 9

Description

[Technical field]

[0001] The present invention relates to a processor. [Background technology]

[0002] The arithmetic processing device is a processor or a CPU (Central Processing Unit) chip. Hereinafter, the arithmetic processing device will be referred to as a processor. Recent processors have a problem of increased latency (number of clocks from memory request to data response) for memory access due to increased functionality and miniaturization. In particular, the increase in the scale of circuits due to miniaturization makes it possible to increase the number of cores and the cache hierarchy, but it is necessary to suppress the increase in latency that accompanies this.

[0003] The following patent documents describe speculatively storing data in a cache in response to a speculative execution instruction. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Special Publication No. 2014-503929 [Patent Document 2] JP 2009-64471 A Summary of the Invention [Problem to be solved by the invention]

[0005] On the other hand, with the advent of multi-core processing and multi-hierarchical caches, it becomes necessary to ensure cache coherency, which means the consistency of data in a cache. A cache has a data memory for storing data and a tag memory for storing the state of each cache line in the data memory or the state of data in the cache line, and determines whether or not the data is coherent based on the state. For example, in the MESI protocol, four states are used for this state: I (cache line is invalid), S (the contents of the cache line are the same as the memory and can be shared by the caches of other cores), E (the contents of the cache line are the same as the memory and do not exist in the caches of other cores), and M (the contents of the cache line are changed by writing and do not match the memory).

[0006] An example of a procedure for ensuring cache coherency is described below. When a core 0 attempts to read memory at a certain address, but a cache miss occurs in that cache, the latest data that has been rewritten may be present in the cache of another core 1, and the contents of the memory may remain old. Therefore, core 0 broadcasts to the caches of other cores, including core 1, and requests that they write back (Copy Back) to memory if they have a cache line in M ​​state for that address. In response to this, the cache of core 1 writes back the contents of the cache line in M ​​state to memory, changes the M state to S state, and responds to core 0 that it has a cache line in S state. After that, core 0 reads the latest data of that address from memory and stores it in its own cache, and puts the cache line in S state. Also, in response to a write back request from core 0, if the cache of core 1 does not have a cache line of that address, it responds to core 0 that it does not have a cache line of that address. In response to this, core 0 reads the data of that address from memory and stores it in its own cache, and puts the cache line in E state.

[0007] The procedure for ensuring cache coherency in this way is one in which data consistency is achieved between the caches of multiple cores, and the original data, i.e., the latest data, can be read. If cache coherency is not ensured, the above-mentioned procedure for ensuring cache coherency must be implemented.

[0008] Therefore, the procedure for ensuring cache coherency may result in increased latency. The processor then locks out subsequent memory requests that depend on the memory request until the procedure for ensuring cache coherency is completed. Therefore, if the latency is long, subsequent memory requests cannot be started, reducing the processor's processing efficiency.

[0009] In order to avoid the above-mentioned decrease in processing efficiency, a branch prediction mechanism for a branch instruction or a prefetch mechanism is used to speculatively execute memory access to an address predicted to be executed next. However, in the case of a speculative execution, it is necessary to rewind the circuit to the state before the speculative execution when the speculation fails. The speculative execution area that can be rewound is limited to, for example, the decoder to the arithmetic unit and the register file, and it is prohibited to store data that has not been speculatively executed in the cache area. Therefore, during the procedure for ensuring coherency of a memory request of an instruction to be speculatively executed, the execution of subsequent memory requests that depend on the memory request is locked, and the subsequent memory requests cannot be executed speculatively. As a result, the improvement of program execution efficiency by the speculative execution of instructions is suppressed.

[0010] Therefore, one object of this embodiment is to provide a processor capable of suppressing the latency of memory access. [Means for solving the problem]

[0011] A first aspect of this embodiment includes a plurality of core circuits each having an arithmetic circuit that executes an issued instruction, a load / store unit that executes an issued memory access instruction, a primary cache, and a reorder buffer that controls instruction execution completion processing of the arithmetic circuit and the load / store unit, and a cache unit having a plurality of caches from a secondary cache to an Nth (N is an integer of 3 or more)th cache, the primary cache has a move-in buffer having a plurality of entries that store a memory access instruction that has resulted in a cache miss in the primary cache, the move-in buffer issues a normal memory request to the secondary cache to perform memory access of the memory access instruction that has resulted in a cache miss, the normal memory request is issued serially from the secondary cache to the Nth cache, and the normal memory request is transferred from the secondary cache that has a cache hit to the Nth cache. and when the normal memory request is issued to the secondary cache, a pseudo memory request for performing the memory access is issued to a tertiary cache if N is 3, and is issued in parallel from the tertiary cache to the Nth cache if N is 4 or more, the move-in buffer receives a pseudo data response having data for which coherency is not ensured from any of the caches in which the pseudo memory request has hit, the reorder buffer executes normal instruction execution completion processing based on the normal data response and executes pseudo instruction execution completion processing based on the pseudo data response, and if the pseudo data response is unsuccessful, rewinds the arithmetic circuit that speculatively executed an instruction following the memory access instruction that resulted in the cache miss based on the pseudo instruction execution completion processing to a state before the speculative execution. Effect of the Invention

[0012] According to a first aspect, a processor capable of suppressing memory access latency is provided. [Brief description of the drawings]

[0013] [Figure 1] FIG. 2 is a diagram illustrating an example of a configuration of a processor according to the present embodiment. [Diagram 2] FIG. 1 illustrates an example of the configuration of a multi-core processor. [Diagram 3] 11 is a diagram illustrating an example of an instruction sequence in which processing for ensuring coherency in a cache suppresses speculative execution. [Figure 4] 1A and 1B are diagrams illustrating a cache structure and a procedure for reading the latest data in response to a memory request. [Diagram 5] 1A and 1B are diagrams illustrating a cache structure and a procedure for reading the latest data in response to a memory request. [Figure 6] FIG. 1 is a diagram illustrating an example of the configuration of a conventional processor for explaining a conventional memory request operation. [Figure 7] FIG. 13 is a timing chart showing the operation of a load instruction. [Figure 8] FIG. 2 is a diagram showing the operation between circuits within a processor in response to a load instruction. [Figure 9] FIG. 2 is a diagram illustrating an example of a configuration of a processor according to the present embodiment. [Figure 10] FIG. 13 is a timing chart showing the operation of a load instruction. [Figure 11] FIG. 1 is a diagram showing the operation (1) between circuits in a processor in response to a load instruction. [Figure 12] FIG. 13 is a diagram showing the operation (2) between circuits in a processor in response to a load instruction. [Figure 13] 13 is a diagram illustrating an example of a buffer configuration of a move-in buffer MIB. [Figure 14] FIG. 13 is a flowchart illustrating an example of the operation of the move-in buffer MIB. [Figure 15] FIG. 2 is a diagram illustrating an example of a buffer configuration of a reorder buffer ROB in the present embodiment. [Figure 16] FIG. 13 is a flowchart illustrating an example of the operation of the reorder buffer ROB. [Figure 17]FIG. 4 is a diagram showing an example of an instruction sequence different from that shown in FIG. 3. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] Fig. 1 is a diagram showing an example of the configuration of a processor in this embodiment. The processor in Fig. 1 has, as an instruction issuing unit, an instruction fetch address generator I_F_ADD_GEN, a first instruction cache L1_ICACHE, a second instruction cache L2_ICACHE, an instruction buffer I_BUF, an instruction decoder I_DEC, and reservation stations RSA, RSE, and RSF which are instruction issuing units that issue a plurality of instructions to arithmetic units. The instruction issuing unit also has a reservation station RSBR for branch instructions, and a reorder buffer ROB.

[0015] The processor further includes a storage unit SU, a fixed-point arithmetic unit FX_EXC, and a floating-point arithmetic unit FL_EXC as a plurality of arithmetic units. The processor may include one or more of each of these arithmetic units.

[0016] The storage unit SU has an operand address generator OP_ADD_GEN including an adder / subtractor circuit for address calculation, a first data cache L1$, and a second data cache L2$. In addition to a data memory, the first data cache has a first cache control unit L1$_CNT that controls the cache memory. The first cache control unit is composed of, for example, a pipeline circuit. The second data cache is similar.

[0017] The fixed-point arithmetic unit FX_EXC and the floating-point arithmetic unit FL_EXC each have, for example, an adder / subtractor circuit, a logical arithmetic unit, and a multiplier. The floating-point arithmetic unit has, for example, arithmetic units corresponding to the SIMD width so that SIMD (Single Instruction Multiple Data) arithmetic can be performed. The processor has a fixed-point register file FX_REG and a floating-point register file FL_REG that store the processing results of these arithmetic units. These register files have multiple registers, some of which are renaming registers in which the processing results are stored before an instruction is completed, and architectural registers in which the processing results are stored when an instruction is completed. The architectural registers are general-purpose registers that can be accessed by software.

[0018] The above is the configuration of the cores in the processor. The processor further has a third-level data cache L3$ shared by multiple cores, and is connected to the main memory M_MEM via a memory controller (not shown). The second-level instruction cache L2_ICACHE is also connected to the main memory M_MEM via a memory controller.

[0019] The overall processor configuration is explained below along with the flow of instruction processing. The instruction fetch address generator I_F_ADD_GEN generates a fetch address, reads the fetch instruction from the primary instruction cache L1_ICACHE in the execution order of the program (in-order), and temporarily stores it in the instruction buffer I_BUF. The instruction decoder I_DEC then inputs the fetch instruction in the instruction buffer in-order, decodes it, and generates an executable instruction (execution instruction) with the information required for execution added.

[0020] Next, the execution instructions generated by the instruction decoder are queued in-order in a storage with a queue structure called a reservation station. The reservation station is an execution queue that accumulates execution instructions in a queue, and is provided for each arithmetic unit that executes instructions.

[0021] The reservation station includes, for example, an RSA (Reservation Station for Address generation) provided in a storage unit SU including a first-level data cache L1$, an RSE (Reservation Station for Execution) provided in a fixed-point arithmetic unit FX_EXC, and an RSF (Reservation Station for Floating point) provided in a floating-point arithmetic unit FL_EXC. It also includes an RSBR (Reservation Station for Branch) corresponding to the branch prediction unit BR_PRD. Hereinafter, the reservation station will be abbreviated to RS as appropriate.

[0022] The execution instructions queued in each RS are issued to the arithmetic unit in random order (out of order) and executed by the arithmetic unit, starting with those whose execution conditions are met, such as whether the input operands required for instruction execution can be read from the general-purpose register file by the completion processing of the previous instruction's calculation process (whether the read-after-write (RAW) constraint is satisfied) and whether the circuit resources of the arithmetic unit can be used.

[0023] On the other hand, the instruction decoder I_DEC assigns an instruction identifier (IID) to the executable instruction generated by decoding the fetch instruction in the order of execution in the program, and transmits the executable instruction in order to the re-order buffer ROB (Re-order Buffer). The re-order buffer ROB has a queue-structured storage that stores the transmitted executable instruction in order, and an instruction commit processing unit that performs a commit process (completion process) of each instruction based on information in the queue in response to a processing completion report of the instruction from the pipeline circuit of the arithmetic unit. In other words, the ROB executes the completion process of an instruction that was executed out of order (non-program order) in order (program order).

[0024] Furthermore, the reorder buffer ROB stores speculatively executed speculative execution instructions in a queue-structured storage, and if the speculative execution fails, executes a process of rewinding the retryable area (speculative execution area) to the state before the speculative execution. Therefore, the reorder buffer ROB has a buffer (storage with the queue structure) that stores information necessary for re-executing an instruction that has failed in speculation, such as the instruction sequence being speculatively executed, its flags, parameters, data, etc. The speculative execution area is, for example, a circuit from the instruction fetch address generation circuit I_F_ADD_GEN to the arithmetic unit and registers.

[0025] The ROB stores execution instructions in a queue within the ROB in order and waits for a report of completion of instruction processing from each arithmetic unit. Then, each RS sends the instructions that are ready for execution out of order to the arithmetic unit, and the instructions are executed by the arithmetic unit. After that, when a report of completion of instruction processing is sent from the arithmetic unit to the ROB, the instruction commit processing unit of the ROB completes (commits) the oldest instruction in program order among the instructions stored in the queue waiting for a report of completion in order, and updates circuit resources such as registers and caches. In the completion process, the ROB releases the circuit resources used in the execution of the completed instruction, releases the entries in the ROB, and increments the program counter PC.

[0026] Branch instructions queued in the reservation station RSBR for branch processing are predicted by the branch prediction unit BR_PRD, and the instruction fetch address generator I_F_ADD_GEN generates the branch destination address based on the prediction result. As a result, the instruction based on the branch prediction is read from the instruction cache, and is speculatively executed by the arithmetic unit via the instruction buffer and instruction decoder. RSBR executes branch instructions in order, but predicts the branch destination before the branch destination of the branch instruction is determined, and speculatively executes the instruction at the predicted branch destination. If the branch prediction is correct, processing efficiency increases, but if it is incorrect, the speculatively executed instruction is canceled in the pipeline, decreasing processing efficiency.

[0027] FIG. 2 is a diagram showing a configuration example of a multi-core processor. In the example of FIG. 2, the number of cores is n (n is a positive integer). The configuration of the core CORE_0 is the same as that of the other cores CORE_1 to n. The configuration of each core is the same as that of FIG. 1, but in FIG. 2, it has an instruction buffer I_BUF, a decoder I_DEC, a reservation station RS, a register file RF including an architectural register, a reorder buffer ROB, a load store unit LD / ST, a first cache L1$, and a second cache L2$. However, the instruction fetch address generation circuit I_F_ADD_GEN, the branch prediction unit BR_PRD, the corresponding branch reservation station RSBR, etc. shown in FIG. 1 are omitted in FIG. 2.

[0028] The multi-core processor further includes a tertiary cache L3$ shared by multiple cores, and a memory access controller MAC that controls access to the memory. The primary cache L1$ includes a data cache D$, an instruction cache I$, a pipeline circuit EX_PIPE that controls the primary cache, a write buffer WB, a move-out buffer MOB, and a move-in buffer MIB. The write buffer WB stores write data of a store command. The move-out buffer MOB stores data to be purged when data in the primary cache is purged to a secondary cache or the like. The move-in buffer MIB stores data acquired by a memory request issued to a secondary cache or lower when a cache miss occurs in the primary cache. For this purpose, a signal path is provided for data response from the tertiary cache L3$ to the move-in buffer MIB in the primary cache L1$. See FIG. 6 and FIG. 9. However, this signal path is omitted in FIG. 2.

[0029] The multi-core processor in FIG. 2 has a first cache L1$, a second cache L2$, and a third cache L3$, but may also have a fourth, fifth, or higher cache.

[0030] FIG. 3 is a diagram showing an example of an instruction sequence in which processing for ensuring coherency in a cache suppresses speculative execution. The line numbers of the instruction sequence are shown on the left side. Line number 01 is a load instruction to read data at address A in memory. Line number 02 is an arbitrary instruction that performs a calculation that depends on the result of the load instruction of line number 01. Line number 03 is a non-cache load instruction that reads data from a device other than a cache, and is an example of an instruction to check the status of the load instruction of line numbers 06 to 10 as to whether the data can be read. The non-cache load instruction does not depend on the instructions of line numbers 01 and 02. Line number 04 is an instruction to monitor the above status to become readable. Line number 05 is a barrier instruction that monitors whether the previous instruction has been completed, and allows the issuance of a subsequent instruction when it has been completed. Line numbers 06 to 08 are load instructions to read data at addresses B to D in memory. Line number 09 is an instruction sequence that performs a calculation that depends on the results of the above three load instructions. Line number 10 is a store instruction that writes the calculation result of the instruction on line number 09 to address E in memory, and is executed after the instruction on line number 09 is completed. In the instruction sequence of Figure 3, one challenge is to speed up the completion of the store instruction on line number 09.

[0031] The following description of this embodiment will show how the problem of the process of ensuring coherency in the cache for the load instruction in the instruction sequence of Figure 3 inhibiting improvement in program execution efficiency through speculative execution of instructions following the load instruction is solved.

[0032] 4 and 5 are diagrams for explaining the structure of a cache and a procedure for reading the latest data in response to a memory request, which will be explained as background art for the processor of the present embodiment.

[0033] Figure 4 shows the structure of a cache called an inclusion cache. In this example, two cores CORE_0 and CORE_1 each have a load / store unit LD / ST, a first cache L1$, a second cache L2$, and share a third cache L3$. The third cache L3$ is connected to a memory access controller MAC, which controls access to the memory MEM.

[0034] In an inclusion cache, for example, the load / store unit LD / ST of core CORE_0 stores data read from memory MEM in the tertiary cache L3$, secondary cache L2$, and primary cache L1$ in the order of proximity to the memory. The same is true for core CORE_1. In an inclusion cache, cache control is performed so that the contents of the primary cache L1$ are stored in the secondary cache L2$, and the contents of the secondary cache L2$ are also stored in the tertiary cache L3$. The dashed line in the figure indicates the range in which certain data is commonly registered in the inclusion cache.

[0035] The table on the right side of the figure shows an example of the transition over time of data stored in three levels of caches L1$ to L3$. At time t1, for example, as a result of a load command executed by the load store unit of core CORE_0, data D1 read from memory is stored in all caches L1$ to L3$. Then, at time t2, as a result of a load store unit of core CORE_0 executing another load command, data D1 is evicted from cache L1$ to cache L2$ and other data is stored in cache L1$, so data D1 is not stored in cache L1$ (NA).

[0036] After time t1, at time t3, the load-store unit of core CORE_0 executes a store instruction, and as a result, data D1 in cache L1$ is changed to data D2. Then, at time t4, just like at time t2, data D2 is evicted from cache L1$ to cache L2$, and other data is stored in cache L1$, so data D2 is not stored in cache L1$ (NA).

[0037] In the above cache state, in the cases of time t1 to t2, time t1 to t3, and time t4, in order for the core to search for the latest data with coherency maintained, it is necessary to execute a memory request so that cache judgment is performed in order from the primary cache L1$ on the core side of the cache to the secondary cache L2$, the tertiary cache L3$, and so on toward the memory.

[0038] FIG. 5 shows the structure of a cache called a victim cache. It has the same structure as FIG. 4, and in the figure, the dashed line indicates the range of the cache that stores the data first read from the memory. That is, the memory access controller stores the data read from the memory MEM in the first cache L1$, which is closest to the core, instead of storing it in the third cache L3$ and the second cache L2$. When a cache line of data stored in the first cache is evicted to store another cache line, the evicted cache line is stored in the second cache. In this way, in a victim cache, the contents of the first cache are not necessarily stored in the second cache, and the contents of the second cache are not necessarily stored in the third cache.

[0039] The table on the right side of the figure shows an example of the transition of data stored in three levels of cache L1$ to L3$ over time. The memory access from time t1 to t2 and from time t1 to t3 and t4 are the same as in Figure 4. In the case of Figure 5, at time t2, data D1 in L1$ is evicted to L2$, and data D1 is stored in L2$. Similarly, at time t3, rewritten data D2 in L1$ is evicted to L2$ at time t4, and data D2 is stored in L2$.

[0040] Even in the above cache state, in the case of times t1 to t2, t1 to t3, and t4, in order for the core to search for the latest data with coherency maintained, it is necessary to execute a memory request so that cache judgment is performed in order from the primary cache L1$ on the core side of the cache to the secondary cache L2$, the tertiary cache L3$, and so on toward the memory.

[0041] As described above, in both the inclusion cache and the victim cache, data search within the cache is performed serially from the first cache, the highest cache on the core side, to the lower caches on the memory side, the second cache, and the third cache.

[0042] [Issues caused by long latency in traditional memory requests] 6 is a diagram showing an example of the configuration of a conventional processor for explaining the operation of a conventional memory request. In the diagram, the processor configuration includes a core CORE, caches L1$, L2$, and L3$, and a memory access controller MAC. The core CORE shows a part of the configuration inside the core shown in FIG. 1 and FIG. 2. That is, the core CORE shows an instruction decoder DEC, a reservation station RS, an arithmetic logic circuit ALU, a register file RF, a reorder buffer ROB, and a load store unit LD / ST. Data in the register file RF is input to the arithmetic logic circuit.

[0043] 6 includes a first cache L1$ to a third cache L3$. The second cache L2$ and the third cache L3$, excluding the first cache L1$, may be referred to as a cache unit $_UNIT. The cache unit may include a first cache to an Nth cache (N is an integer equal to or greater than 3).

[0044] The primary cache L1$ of the cache has a data cache D$ and its tag TAG, a pipeline circuit EX_PIPE that checks the tag TAG of the data cache D$ for a memory access instruction MA_INST issued by the load / store unit LD / ST to determine whether or not there is a cache hit, and a response circuit CPLT that responds to the load / store unit with the processing result of the memory access instruction MA_INST. The primary cache L1$ also has a move-in buffer MIB that issues a memory request RQ to the secondary cache in the event of a cache miss and has a buffer that stores data read by the memory request.

[0045] The second level cache L2$ and the third level cache L3$ of the cache have a request FIFO (RQ_FIFO) that stores memory requests RQ issued by higher level caches, a data cache D$ and its tag TAG, a pipeline circuit EX_PIPE that performs cache hit determination for memory requests, and a response circuit CPLT that responds to the move-in buffer MIB with the processing result of the memory request. In the case of a cache miss, the response circuit CPLT of the second and third level caches issues the memory request RQ to a lower level cache or a memory access controller MAC.

[0046] The memory access controller MAC has a request FIFO that stores memory requests RQ issued by the third-level cache L3$, a pipeline circuit EX_PIPE that controls memory access, a read and write circuit READ_WRITE that issues a read or write request for the memory request to the memory MEM, and a response circuit CPLT that responds to the MIB with the processing result of the memory request.

[0047] Next, the operation when the load instruction on line number 01 in FIG. 3 is executed in the processor in FIG. 6 will be described.

[0048] FIG. 7 is a timing chart of the operation of the instruction sequence of FIG. 3. In FIG. 7, the line numbers of the instruction sequence of FIG. 3 are shown. The horizontal direction is the time axis t. The load instruction Load MEM[A] of line number 01 misses in the second cache, then hits in the third cache and is completed. As described above, the instruction of line number 02 is an instruction that depends on the result of the load instruction of line number 01, so it is completed after the completion of the load instruction. The non-cache load instruction of line number 03 does not depend on the result of line number 01, so it is completed before the completion time t10 of line numbers 01 and 02. On the other hand, the barrier instruction of line number 05 inhibits the execution of the instructions after it until the instructions before it are completed. Therefore, at the time t10 when all the instructions before it are completed, the barrier instruction causes the load instructions of lines 06-08 after it to start execution. After these load instructions are completed, the store instruction of line number 10 starts execution.

[0049] 8 is a diagram showing the operation between circuits in the processor in response to the load instruction on line number 01. The execution operation of the load instruction will be described with reference to FIGS.

[0050] 8, when the address A of the operand of the load instruction Load MEM[A] is prepared, the reservation station RS issues the load instruction to the load store unit LD / ST (S50). The load store unit issues a memory access instruction MA_INST to the primary cache L1$ (S51), and in response, the pipeline circuit of the primary cache checks the tag of the data cache D$, resulting in a cache miss (S52). In response to the cache miss, the move-in buffer MIB secures an entry for the load instruction and issues a memory request RQ_1 to the secondary cache L2$ (S53).

[0051] The secondary cache L2$ performs a cache check in response to the memory request RQ_1, resulting in a cache miss (S54). Therefore, the secondary cache issues a memory request RQ_2 to the tertiary cache L3$ (S55). The tertiary cache performs a cache check, resulting in a cache hit (S56), and returns a data response D_RPL to the move-in buffer MIB (S57). The tertiary cache L3$ also transmits a data response D_RPL to the secondary cache L2$ (S57), and may also execute a move-in D_REG to register the data in the cache. The move-in buffer MIB stores the data of the data response in the entry of the load command (S58), and a data registration D_REG is performed to store the read data in the data cache D$ in the primary cache (S59). In addition, the move-in buffer MIB notifies the load / store unit LD / ST of the data response. In response to this notification, the load store unit LD / ST stores the read data in a register in the register file RF (S60). The load store unit LD / ST also notifies the reorder buffer ROB of the completion CMP of the load instruction (S61), and in response to this notification, the reorder buffer ROB performs a commit process CMT of the load instruction (S62). The completion of the commit process CMT is notified to the reservation station RS, and the RS issues an instruction that depends on the completed load instruction to the arithmetic unit (S63).

[0052] As shown in FIG. 7, the load store unit executes a load instruction Load MEM[A] (line number 01) and reads data with coherency secured by the cache. Since the data read by the load instruction in line number 01 is prepared, an instruction that has a dependency on the result of the load instruction (line number 02) is executed by the arithmetic unit ALU. Furthermore, a non-cache load instruction NC_Load (line number 03) and a barrier instruction Sync(FENCE) (line number 05) are executed. The barrier instruction Sync(FENCE) permits the execution of the instruction after it at t10, when the execution of the previous load instruction Load MEM[A] (line number 01), the next instruction (line number 02), and the NC load instruction (line number 03) is completed. Therefore, the timing t10 ​​of the completion of the execution of the barrier instruction Sync is the timing of starting the execution of the instruction after it. Also, the execution of the barrier instruction Sync is completed after the instruction before the barrier instruction, i.e., the load instruction Load MEM[A], is completed and the instruction that depends on the result of the load instruction is completed. In order to advance the execution start timing t10 ​​of the subsequent instruction, it is necessary to advance the completion of the instruction (line numbers 01-04) before the barrier instruction.

[0053] In the relationship between the load instruction Load MEM[A] and the barrier instruction Sync(FENCE) shown in Figure 3, if the latency of the read process of data with coherency secured in the cache based on the load instruction Load MEM[A] is long, the barrier instruction will delay the start of execution of the subsequent instruction at time t10. In particular, even if the three load instructions (line numbers 06, 07, and 08) in Figure 3 can be speculatively executed, the barrier instruction will delay their speculative execution until time t10. This situation reduces the efficiency of program execution of the processor.

[0054] [Processor of this embodiment] FIG. 9 is a diagram showing an example of the configuration of a processor in this embodiment. The circuitry constituting the processor in FIG. 9 is the same as that in FIG. 6. However, in the processor in FIG. 9, firstly, when a cache miss occurs in the primary cache, when the move-in buffer MIB issues a memory request RQ to the secondary cache, which is the cache one level lower, it issues a pseudo memory request P_RQ to the tertiary cache, which is the cache further lower. P stands for pseudo. Instead of the move-in buffer MIB issuing the pseudo memory request P_RQ, the request FIFO of the secondary cache L2$ may issue a pseudo memory request P_RQ to the tertiary cache in response to receiving the memory request RQ from the move-in buffer MIB. In short, in addition to issuing sequential memory requests RQ from the move-in buffer MIB to multiple lower caches (secondary cache, tertiary cache), the move-in buffer MIB issues pseudo memory requests in parallel to all lower caches.

[0055] Secondly, in a conventional memory request issued sequentially to multiple lower caches (hereinafter referred to as a normal memory request), each level of cache responds with data to the move-in buffer MIB with the latest data that has undergone a coherency check. This is referred to as a normal data response. On the other hand, in a pseudo memory request issued in parallel to multiple lower caches, each level of cache responds with data to the move-in buffer MIB as pseudo data P_Data for cache-hit data without performing a coherency check process. This is referred to as a pseudo data response. In this sense, a pseudo state (P state), which means a state where coherency has not been checked, is added to the state of the cache line or data in the cache.

[0056] Thirdly, when the move-in buffer MIB receives the pseudo data response, it notifies the reorder buffer ROB of the pseudo completion of the load instruction. In response to this, the reorder buffer ROB notifies the reservation station, etc. of the pseudo completion of the load instruction. In response to the pseudo completion of the load instruction, the arithmetic unit that executes the barrier instruction in FIG. 3 determines that the barrier is released, and enables speculative execution of subsequent instructions.

[0057] Fourth, the move-in buffer MIB compares the pseudo data P_Data received in the pseudo data response to the pseudo memory request with the normal data for which coherency has been ensured received in the normal data response to the normal memory request, and determines whether the pseudo completion by the pseudo memory request is successful or not. If the pseudo data matches the normal data, it determines that the pseudo completion by the pseudo memory request is successful, and if they do not match, it determines that it is unsuccessful.

[0058] Fifth, when the reorder buffer ROB receives a notification that the pseudo completion of the pseudo memory request has failed, it executes a process of rewinding the circuit state in the retryable area to the time before the start of the instruction following the load instruction. In addition, the load / store unit LD / ST registers (move-in) the normal data received in the normal data response to the load instruction in the primary cache and overwrites and saves (move-in bypass) it in the register file of the arithmetic unit. The retryable area refers to the circuits excluding the load / store unit LD / ST in the core CORE shown in Figures 6 and 9.

[0059] Sixth, when the move-in buffer MIB receives a pseudo data response, it does not register the pseudo data in the primary cache (move-in processing). Since the cache is a circuit outside the retry-enabled area, the pseudo data is not registered in the cache. Instead, the pseudo data is written to a register file within the retry-enabled area (move-in bypass processing). This differs from the case where data in a normal data response is registered in the cache (move-in processing) and written to a register file in the arithmetic unit (move-in bypass processing).

[0060] Fig. 9 is a diagram showing an example of the configuration of a processor in this embodiment. As in Fig. 6, Fig. 9 shows a core CORE, caches L1$, L2$, L3$, and a memory access controller MAC as the configuration of the processor. The core CORE shows an instruction decoder DEC, a reservation station RS, an arithmetic logic circuit ALU, a register file RF, a reorder buffer ROB, and a load store unit LD / ST. Data in the register file RF is input to the arithmetic logic circuit.

[0061] The configurations of the primary to tertiary caches L1$, L2$, and L3$ and the memory access controller MAC are the same as those in Fig. 6. However, the move-in buffer MIB in the primary cache L1$ issues a normal memory request RQ to the secondary cache L2$ and also issues a pseudo memory request P_RQ to the tertiary cache L3$. Alternatively, as described above, the request FIFO of the secondary cache L2$ may issue a pseudo memory request to the tertiary cache in response to the normal memory request RQ issued by the move-in buffer MIB.

[0062] [Move-in buffer and reorder buffer] Before describing the operation of a load command by the processor of FIG. 9 according to this embodiment, an example of the configuration and operation of the move-in buffer MIB and the reorder buffer ROB will be described.

[0063] Fig. 13 is a diagram showing an example of a buffer configuration of the move-in buffer MIB. Here, the buffer configuration and simple operation of the move-in buffer MIB of this embodiment will be described. Fig. 13 shows a buffer having four entries (rows). Each entry stores information on a memory access command that has caused a cache miss, information on a normal memory request (R memory request) issued to the cache, information on a pseudo memory request (P memory request), information on a normal data response (R data response), information on a pseudo data response (P data response), and a success flag for the pseudo memory request.

[0064] When a cache miss occurs in the primary cache L1$, the move-in buffer MIB secures an entry as shown in Fig. 13 and stores the corresponding memory access command information (e.g., command ID, command type (LD, ST, etc.), address ADD, etc.). It then stores normal memory request information R_RQ# (# is 1 to 4) (ID and address of the R memory request, etc.) and pseudo memory request information P_RQ# (# is 1 to 4) (ID, address, and destination cache ID of the P memory request, etc.), and issues the R memory request and P memory request to the secondary cache and tertiary cache, respectively.

[0065] When the move-in buffer MIB receives a normal data response (R data response) to an R memory request and a pseudo data response (P data response) to a P memory request, it stores the information of each data response (cache ID, normal data D, pseudo data PD) and the completion status R_CMP, P_CMP in the corresponding entry. Since each data response has the ID of the original memory request, the move-in buffer MIB can store the above information in the entry corresponding to the received data response.

[0066] 14 is a diagram showing a flowchart of an operation example of the move-in buffer MIB. When the first cache performs a cache hit judgment for a memory access command and a cache miss occurs (YES in S10), if there is a free entry in the buffer (YES in S11), the move-in buffer MIB registers in the entry the memory access command information that has resulted in a cache miss, information R_RQ# of a normal memory request to be issued to the second cache L2$, and information P_RQ# of a pseudo memory request to be issued to the third cache L3$ (S12). Then, the move-in buffer MIB issues a normal memory request R_RQ to the second cache L2$ and a pseudo memory request P_RQ to the third cache L3$ (S13). As described above, the pseudo memory request may be issued from the request FIFO of the second cache.

[0067] When the move-in buffer MIB receives the pseudo data response P_D_RPL (YES in S14), it registers the information of the pseudo data response P_D_RPL (the cache ID of the responder (e.g. L3), the pseudo data PD, and the pseudo response completion flag P_CMP) in the corresponding entry of the buffer in FIG. 13, notifies the load store unit LD / ST of the pseudo data response, registers the pseudo data PD in the register file RF, and notifies the reorder buffer ROB of the pseudo completion P_CMP (S15). The load store unit LD / ST may also notify the reorder buffer ROB of the pseudo completion P_CMP.

[0068] When the move-in buffer MIB receives the normal data response R_D_RPL (S16), it registers the information of the normal data response R_D_RPL (the cache ID of the response source, the data D, and the normal completion flag R_CMP) in the corresponding entry of the buffer (S17). In this case, if the pseudo data response P_D_RPL has already been received (YES in S18), the move-in buffer MIB compares the pseudo data PD stored in the buffer with the data D of the normal data response to determine whether the pseudo data response was successful or unsuccessful (S20). If the pseudo data PD of the pseudo data response matches the data D of the normal data response, the move-in buffer MIB determines that the pseudo data response by the pseudo memory request P_RQ is successful, and if they do not match, it determines that it is unsuccessful.

[0069] If successful (YES in S21), the MIB notifies the load / store unit LD / ST that the pseudo memory request was successful, registers the pseudo data of the pseudo data response (or data D of the normal data response) in the data cache D$, and notifies the reorder buffer ROB of the success of the pseudo data response (S22).

[0070] If it fails (NO in S21), the MIB registers the failure as a pseudo memory request success flag in the corresponding entry of the buffer, notifies the load store unit LD / ST that the pseudo memory request failed, and notifies the reorder buffer ROB of the failure of the pseudo data response (S23). The notification of the success or failure of the pseudo data response may be given by the load store unit LD / ST to the reorder buffer ROB. Furthermore, if it fails, the MIB registers data D of the already received normal data response in the primary cache (move-in processing) (S23), and further the load store unit LD / ST overwrites and registers data D in the register file RF of the arithmetic unit (move-in bypass processing).

[0071] On the other hand, if the pseudo data response has not been received before receiving the normal data response (NO in S18), the move-in buffer MIB notifies the load / store unit LD / ST of the R data response, registers the response data D in the data cache D$, and notifies the reorder buffer ROB of normal completion R_CMP (S19). The notification to the reorder buffer described above may be performed by the load / store unit instead of the MIB. The response data D is also registered in the register file RF of the arithmetic unit in the core.

[0072] [Reorder buffer] 15 is a diagram showing an example of the buffer configuration of the reorder buffer ROB in this embodiment. When the instruction decoder decodes a fetched instruction and issues the decoded instruction to the reservation station RS of the arithmetic unit, it also notifies the reorder buffer ROB of the instruction. In response to this notification, the reorder buffer ROB stores information (instruction information) of the instruction issued by the decoder in each entry of the buffer. This is as shown in the first column from the left in the figure. The instruction information is, for example, the instruction ID (IID) of a program and its instruction INST.

[0073] Furthermore, the reorder buffer records, in each entry of the buffer, instruction re-execution information REXC_INF for rewinding the retryable area to a state before the speculative execution of the instruction and re-executing the instruction when the speculative execution of the instruction fails. This is shown in the second column from the left in the figure. Specifically, the instruction re-execution information includes state information of the circuits and registers in the retryable area before the speculative execution of the instruction, and information on the storage location of flags, parameters, and data of the instruction being speculatively executed. Also, in each entry of the buffer, a normal completion flag (R completion flag) R_CMP (shown in the third column from the left in the figure) indicating whether or not the completion of the instruction has been notified from the arithmetic unit, success / failure information (success or failure) indicating whether or not the speculative execution of the instruction was successful, and information REXC (shown in the sixth column from the left in the figure) indicating whether or not the circuit in the retryable area is rewound and the instruction is being re-executed when it fails, etc. are recorded.

[0074] The reorder buffer ROB executes a commit process (completion process) from the instruction issued by the decoder oldest among the instructions of the entry in which the normal completion flag R_CMP, which indicates the completion notification of the instruction received from each arithmetic unit, is recorded. In other words, when all instructions in the program order prior to the instruction in which the normal completion flag is recorded have been committed, the reorder buffer ROB executes a commit process for the instruction in which the normal completion flag is recorded. The commit process includes the release of circuit resources used in the execution of the instruction and the increment of the program counter. In other words, the reorder buffer ROB executes a commit process for the instruction sequence executed in the order of the instructions that the reservation station of each arithmetic unit is ready to execute, that is, in the out-of-order order, which is not the instruction order of the program, in the in-order order, which is the instruction order of the program.

[0075] In this embodiment, the reorder buffer records in each entry of the buffer a pseudo-completion flag P_CMP notified when a pseudo-data response to a pseudo-memory request is received from the move-in buffer MIB or the load / store unit LD / ST. This is the fourth column from the left in the figure. Furthermore, in response to receiving the pseudo-completion flag (P completion flag) P_CMP, the reorder buffer records in the entry a pseudo-commit flag (P commit flag) P_CMT indicating whether or not a pseudo-commit process has been performed for the speculative execution of the corresponding instruction. This is the fifth column from the left in the figure. Note that INV in the entry in FIG. 15 means that the data or flag is invalid data or an invalid flag.

[0076] 16 is a diagram showing a flowchart of an operation example of the reorder buffer ROB. When the decoder issues an instruction (YES in S30), the reorder buffer ROB registers instruction information and re-execution information of the issued instruction in a free entry of the buffer (S31). When a pseudo-completion notification P_CMP is received from the move-in buffer MIB or the load store unit LD / ST (YES in S32), the reorder buffer ROB registers a pseudo-completion flag P_CMP in the entry, executes a pseudo-commit (P-commit) of the pseudo-completed instruction, registers a pseudo-commit flag P_CMT, and notifies each reservation station RS of the pseudo-commit P_CMT (S33). The pseudo-commit is a process in which pseudo data is stored in the register file RF in the retryable area, but the pseudo data is not registered in the cache in the non-retryable area, and is a process of changing or releasing a minimum number of circuit resources to enable speculative execution of an instruction following the pseudo-committed instruction.

[0077] Furthermore, when a normal completion notification R_CMP is received from the move-in buffer MIB or the load / store unit LD / ST (YES in S36), the reorder buffer ROB registers a normal completion flag R_CMP in the entry (S35), and checks the pseudo-completion flag in the entry for that instruction to check whether the pseudo-completion flag P_CMP is being registered (S36).

[0078] If the pseudo-completion flag P_CMP is being registered (YES in S36), and if the move-in buffer MIB or the like has notified the user that the execution of the pseudo-memory request that was responded to with pseudo-data has been successful (YES in S38), the reorder buffer performs normal commit processing, such as releasing the circuit resources of the instruction that was responded to with pseudo-data, and notifies each reservation station RS of a normal commit R_CMT (S39).

[0079] On the other hand, if it is notified that it has failed (NO in S38), the reorder buffer ROB rewinds the retryable area to the state before the speculative execution of the instruction following the load instruction, and notifies each reservation station RS that the state of the retryable area has been rewound and that the speculatively executed instruction following the failed load instruction will be re-executed (S40). Since the instruction following the failed load instruction was speculatively executed based on the load data of the failed load instruction, the reservation station RS responds to this failure notification by rewinding the state of the retryable area to the state before the speculative execution of the speculatively executed instruction. Then, as described above, normal data is registered (moved in) in the primary cache L1$, and the normal data is overwritten (moved in bypassed) in the register file RF of the arithmetic unit.

[0080] If the pseudo-completion flag P_CMP is not being registered (NO in S36), the reorder buffer performs normal commit processing such as releasing the circuit resources of the instruction that has been notified of normal completion, and notifies each reservation station RS of a normal commit R_CMT (S37).Then, the operation returns to the beginning of the flowchart (S41).

[0081] [Example of processor operation when executing a load instruction (1)] Next, the operation when the load instruction on line number 01 in FIG. 3 is executed in the processor in FIG. 9 will be described.

[0082] Fig. 10 is a timing chart of the operation of the load instruction. Fig. 11 and Fig. 12 are diagrams showing the operation between circuits in the processor when the load instruction is executed. The operation (1) of the load instruction will be described with reference to Figs. 9, 10 and 11.

[0083] In the operation (1) of the load command, the move-in buffer MIB compares the data of the P data response with the data of the R data response and determines (S86_FLT) whether the pseudo-completion of the P memory request was successful or not. This is the operation that occurs when the two data match and the pseudo-completion of the P memory request is successful.

[0084] When the address A of the operand of the load command Load MEM[A] is prepared, the reservation station RS issues the load command to the load store unit LD / ST (S70). The load store unit LD / ST executes the load command and issues a memory access command MA_INST to the primary cache L1$ (S71). In response to this, the pipeline circuit EX_PIPE of the primary cache L1$ checks the tag of the data cache D$ and a cache miss occurs (S72). In response to the cache miss, the move-in buffer MIB secures an entry for the memory access command in the buffer and issues a normal memory request R_RQ_1 to the secondary cache L2$ (S73). Here, the normal memory request is a name to distinguish it from a pseudo memory request described later, and is a conventional memory request. Therefore, the normal memory request is serially propagated from the primary cache to the secondary cache and further to the last level cache, and the latest data with coherency secured is obtained from the cache or memory, and the acquired data is responded to the move-in buffer as data.

[0085] At this time, the move-in buffer MIB that issued the normal memory request issues a pseudo memory request P_RQ_1 to preferably all caches on the last level cache side of the second cache, i.e., the third cache L3$ (S74). This pseudo memory request (P memory request) P_RQ_1 may be issued to the third cache L3$ by the request FIFO in the second cache in response to receiving the normal memory request R_RQ_1. In this embodiment, the last level cache is the third cache, but if the last level cache is the fourth cache, the pseudo memory request is issued in parallel to the third cache and the fourth cache. As a result, the move-in buffer MIB issues pseudo memory requests P_RQ# in parallel to all caches below the third cache.

[0086] Assume that the tertiary cache L3$ performs a cache check in response to the P memory request P_RQ_1 and a cache hit occurs for a cache line whose state is S(share) (S75). At this time, the tertiary cache L3$ returns a P data response P_D_RPL to the move-in buffer MIB without performing a coherency check of the data (cache line) whose state is S that has been hit (S76).

[0087] Generally, when processor A gets a cache hit on a cache line in state S, there is a possibility that the cache line with the same address may also be present in the cache of other processor B. This is different from the case of a cache hit on a cache line in state E. When there is a cache hit in state S, there is a possibility that processor B has written data to that cache line and its state has become M. Therefore, processor A requests other processors, including processor B, to write the cache line to memory and change its state to I (invalidated) if they have the same cache line in state M. Then, when processor A receives an invalidation completion notification from processor B, processor A reads the latest data from memory, registers it in the cache in state E, and responds with the data to the move-in buffer MIB.

[0088] In this specification, the process by which a processor obtains the latest data from a cache as described above is called a coherency assurance procedure. The coherency assurance procedure includes a coherency check (or snoop process) that inquires about the state of the cache of another processor.

[0089] In this embodiment, when the cache unit of the tertiary cache L3$ hits data (cache line) in state S (S75), it sends a pseudo data response P_D_RPL to the move-in buffer MIB with the hit data without performing the above-mentioned coherency check (S76). This makes it possible to shorten the latency of the pseudo memory request. However, since no coherency check is performed, there is no guarantee that the hit data is the latest data with coherency ensured. The latest data may be stored in the secondary cache in state M, or may be stored in the cache of another processor in state M.

[0090] Now, in response to this P data response, the move-in buffer MIB stores the information of the P data response in an already reserved entry in the buffer, and notifies the load / store unit LD / ST and the reorder buffer ROB of pseudo-completion P_CMP without registering the response data in the data cache D$ of the primary cache (i.e., without performing the move-in process) (S77, S78). The load / store unit stores the pseudo data response data in a register in the register file RF (i.e., performs the move-in bypass process) (S79). The register file RF is in a retryable area, so it can store the P data response data. If the P memory access is unsuccessful, the P data response data will not be correct. For this reason, the P data response data may be registered in a retryable area where rewinding is possible, but the P data response data is not registered in a cache where rewinding is not possible.

[0091] In addition, the reorder buffer ROB performs pseudo-completion P_CMT processing for the load instruction in response to the pseudo-completion P_CMP (S80). In response to this, the barrier state of the barrier instruction Sync (FENSE) is released, and the reservation station RS issues SP_ISSUE (S81) to the arithmetic unit for speculative execution of the instructions following the barrier instruction, that is, the three load instructions addressed to addresses B, C, and D in the example of FIG. 3.

[0092] Thereafter, the secondary cache L2$ performs a cache check in response to the R memory request R_RQ_1, resulting in a cache miss (S82). Therefore, the secondary cache issues an R memory request R_RQ_2 to the tertiary cache L3$ (S83). The tertiary cache L3$ performs a cache check in response to the R memory request R_RQ_2. If the tertiary cache has a cache hit in state S in this cache check, then after a coherency assurance procedure, the coherency-checked data becomes a cache hit (S84), and an R data response R_D_RPL is returned to the move-in buffer MIB (S85).

[0093] As mentioned above, when the tertiary cache gets a cache hit in state S, it snoops on the caches of other processors, and if another processor owns the same cache line in state M, it writes it back to memory. The processor then reads the latest data from memory and responds with the data to the move-in buffer MIB. This is the procedure for ensuring coherency, and it means that there is a cache hit with the above coherency-checked data.

[0094] The move-in buffer MIB stores the data of the R data response in the entry of the load instruction, and compares the data of the P data response with the data of the R data response to determine whether the pseudo-completion of the P memory request is successful or not (S86). If they match, the pseudo-completion of the P memory request is successful, and the load store unit LD / ST performs data registration (i.e., move-in) D_REG in the primary cache L1$ (S87). In data registration, the load store unit stores the data of the P data response or R data response that matches in the above-mentioned comparison operation in the data cache D$ in the primary cache (S87). Then, the move-in buffer MIB or the load store unit LD / ST notifies the reorder buffer ROB of the normal completion R_CMP of the load instruction (S88). In response to this notification of normal completion R_CMP, the reorder buffer ROB performs normal commit processing R_CMT of the load instruction and the speculatively executed instruction following it (S89). Completion of the normal commit process R_CMT is notified to the reservation station RS, and the RS issues an instruction that depends on the completed speculatively executed instruction to the arithmetic unit (S90).

[0095] The operation example of FIG. 10 and FIG. 11 is an example in which the P data response from the third level cache L3$ in response to the P memory request is successful, that is, the P data in the P data response is the latest data for which coherency has been ensured. As shown in FIG. 10 and FIG. 11, the reorder buffer ROB pseudo-commits (pseudo-completes) the load instruction P_CMT in response to the P data response, so that the barrier instruction can release the barrier state and can start speculative execution of the instruction following the barrier instruction. In other words, as shown in FIG. 10, the pseudo-completion time t11 of the barrier instruction is earlier than the completion time t10 in FIG. 7. Therefore, even if the latency until the memory request is completed is extended due to the coherency check process, the speculative execution of the subsequent instruction can be started based on the pseudo data response of the pseudo memory request. This can improve the processing efficiency of the processor.

[0096] [Example of processor operation when executing a load instruction (2)] Next, an example of operation when the processor in FIG. 9 executes the load instruction on line number 01 in FIG. 3, that is, operation (2) of the load instruction, will be described with reference to FIG. 9, FIG. 10, and FIG.

[0097] In the operation (2) of the load command, the move-in buffer MIB compares the data of the P data response with the data of the R data response and determines (S86_FLT) whether the pseudo-completion of the P memory request was successful or unsuccessful, and as a result, the two pieces of data do not match, so the pseudo-completion of the P memory request fails.

[0098] 12, the move-in buffer MIB judges that the pseudo-completion of the P memory request is a failure (S86_FLT), registers failure in the memory request success flag of the entry, registers (i.e., moves in) the data of the R data response in the primary cache D_REG (S87), and further notifies the load / store unit LD / ST of the failure FLT of the P memory request (S88_FLT). Then, when the load / store unit notifies the reorder buffer ROB of the failure FLT (S88_FLT), the reorder buffer ROB registers "failure" in the success / failure flag of the entry, and rewinds (flushes) the state of the retryable area of ​​the arithmetic unit ALU to the state before the speculative execution of the instruction following the load instruction (S89_FLSH).

[0099] This rewind rewinds the state of the retryable area due to the speculative execution of the barrier instruction, which is the instruction after the load instruction, and the speculative execution of the three load instructions after the barrier instruction, to the state before the speculative execution. Along with the rewind FLSH, and preferably after the rewind FLSH, the load store unit LD / ST registers the correct R data in the register of the register file RF of the arithmetic unit ALU (i.e., move-in bypass) RF_REG. As a result, the correct R data of the failed load instruction is registered in L1$ (move-in) D_REG (S87) and registered in the register file RF of the ALU (move-in bypass) RF_REG (S91), completing the execution of the load instruction. The reorder buffer ROB requests the reservation station RS to reissue the instruction that has failed to be speculatively executed to the arithmetic unit (S92). The other operations are the same as those of the load instruction (1).

[0100] [Status of data that hits the cache in a pseudo memory request] In the operation (1) of the load instruction in Figure 11, the pseudo memory request hits a cache line (or data) in state S in the tertiary cache, the tertiary cache responds with pseudo data for the data in state S to the move-in buffer MIB, and then the data in the pseudo data response matches the latest data for the coherency-guaranteed data.

[0101] In the MESI protocol, the state of a cache line (data state) of a cache can be state I, state E, or state M in addition to state S. First, if a pseudo memory request hits a cache line in state E in the tertiary cache, in the MESI protocol, a cache line in state E is held by only one cache, so the data in the hit cache line becomes the latest data for which coherency has been ensured. In the first case, it is faster for a pseudo memory request to hit the tertiary cache and respond with pseudo data to the move-in buffer than for a normal memory request to hit the tertiary cache and respond with normal data to the move-in buffer after a cache miss in the secondary cache.

[0102] Second, if a pseudo memory request hits a cache line in state M in the tertiary cache, the data in the hit cache line will be the latest data with coherency ensured, since only one cache holds cache lines in state M in the MESI protocol. Therefore, as in the first state E described above, the pseudo data from a pseudo memory request will be returned faster than the normal data from a normal memory request.

[0103] Thirdly, if the pseudo memory request does not detect a cache line with the same address in the tertiary cache, a cache miss occurs in the tertiary cache. In this embodiment, as a first method, the tertiary cache does not notify the move-in buffer of the pseudo data response, and does not execute memory access. In the first method, the move-in buffer acquires the latest data for which coherency has been secured in a normal data response to a normal memory request. As a second method, the tertiary cache executes memory access, acquires data for which coherency has been secured from the memory, and responds to the move-in buffer with the data acquired from the memory in a normal data response. This may allow the move-in buffer to receive the normal data response earlier than the normal data response of the data acquired from the memory in response to the normal memory request.

[0104] [Example of behavior when a move-in buffer receives multiple pseudo data responses] In this embodiment, when multiple tertiary or lower caches are provided, the move-in buffer MIB issues pseudo memory requests to multiple tertiary or lower caches in parallel. Therefore, the move-in buffer may receive multiple pseudo data responses corresponding to multiple pseudo memory requests. In this embodiment, the move-in buffer MIB registers the received multiple pseudo data in the move-in buffer with a predetermined priority.

[0105] An example of the predetermined priority is that a first pseudo data response from a first cache closer to the processor core has a higher priority than a second pseudo data response from a second cache farther from the processor core. Furthermore, regardless of the above priority, the pseudo data response of data in state M has the highest priority. Based on such priority, the move-in buffer determines whether or not to overwrite the pseudo data of the received pseudo data response in the move-in buffer. Overwriting means overwriting pseudo data with a higher priority over pseudo data with a lower priority.

[0106] As a result, when the normal data response is received, the move-in buffer stores the pseudo data of the pseudo data response with the highest priority among the multiple pseudo data responses received before receiving the normal data response.The move-in buffer then compares the pseudo data stored in the move-in buffer with the normal data of the normal data response to determine whether the pseudo memory request is successful or unsuccessful.The comparison with the pseudo data with the highest priority increases the probability that the pseudo memory request will be determined to be successful.

[0107] [Another example of an instruction sequence in which cache coherency suppresses speculative execution] Fig. 17 is a diagram showing an example of an instruction sequence different from that in Fig. 3. In the example in Fig. 17, the instruction ldr is a load instruction, and the instruction add is an add instruction. The instruction ldr on line number 01 is an instruction to load data at address x9 into register x0. The instruction add on line number 02 is an instruction to add 8 to the data in register x0 and store the result in register X1. The instruction ldr on line number 03 is an instruction to load data at address x1 into register x2.

[0108] In the case of the above simple instruction sequence, the instruction add in line number 02 cannot start execution until the load instruction ldr in line number 01 is completed, so the instruction add in line number 02 has a relationship of being dependent on the result of the instruction ldr in line number 01. The instruction ldr in line number 03 cannot start execution until the add instruction add in line number 02 is completed, so the instruction ldr in line number 03 has a relationship of being dependent on the result of the instruction add in line number 02. In such a case of multiple instructions having a dependency relationship, the latency of the previous load instruction can be shortened in a pseudo manner using a pseudo memory request, so that the speculative execution of the subsequent instruction having a dependency relationship with the load instruction can be accelerated. Therefore, the processor of this embodiment is effective even in the instruction sequence shown in FIG. 17.

[0109] As described above, in this embodiment, for a memory access instruction from a load store, a move-in buffer in a primary cache issues pseudo memory requests in parallel to multiple lower caches, in addition to normal memory requests that are sequentially propagated to multiple lower caches. Then, when the move-in buffer receives data acquired by the pseudo memory request in a pseudo data response, it notifies the reorder buffer of pseudo completion and causes the reorder buffer to speculatively commit the memory access instruction. This makes it possible to speed up the speculative execution of subsequent memory. [Explanation of symbols]

[0110] CORE: Processor core, core, core circuit DEC: Decoder RS: Reservation Station ALU: Arithmetic circuit, arithmetic unit, logical arithmetic unit RF: Register File, Architectural Register LD / ST: Load store unit, load store circuit ROB: Reorder buffer MIB: Move-in buffer L1$, L2$, L3$: 1st level cache, 2nd level cache, 3rd level cache D$: Data cache, data cache memory TAG: Tag, tag memory CMPT: Response circuit REQ_FIFO: Memory request FIFO buffer LD: Load instruction M_INST: Memory access instruction RQ: Memory request R_RQ: Normal memory request R_D_RPL: Normal data response P_RQ: Pseudo memory request P_D_RPL: Pseudo data response R_CMT: Normal instruction execution completed P_CMT: Pseudo instruction execution completed

Claims

1. a plurality of core circuits each including an arithmetic circuit for executing an issued instruction, a load / store unit for executing an issued memory access instruction, a primary cache, and a reorder buffer for controlling instruction execution completion processing of the arithmetic circuit and the load / store unit; a cache unit having a plurality of caches from a second cache to an Nth cache (N is an integer of 3 or more); the primary cache has a move-in buffer having a plurality of entries for storing memory access instructions that have resulted in a cache miss in the primary cache; The move-in buffer includes: issue a normal memory request to the second cache to perform memory access of the memory access instruction resulting in a cache miss, the normal memory request being issued serially from the second cache to the Nth level cache, and receiving a normal data response having coherency-guaranteed data from any one of the caches from the second cache to the Nth level cache in which the normal memory request has been hit; when the normal memory request is issued to the second level cache, a pseudo memory request for performing the memory access is issued to a third level cache if N is 3, and is issued in parallel from the third level cache to the Nth level cache if N is 4 or more; The move-in buffer includes: receiving a pseudo data response having non-coherent data from any of the caches in which the pseudo memory request hits; The reorder buffer comprises: Executing a normal command execution completion process based on the normal data response; Executing a pseudo command execution completion process based on the pseudo data response; If the pseudo data response is unsuccessful, the processor rewinds the arithmetic circuit that speculatively executed the instruction following the memory access instruction that resulted in the cache miss based on the pseudo instruction execution completion process to a state before the speculative execution.

2. The primary cache is storing data of the normal data response in a cache memory in the primary cache based on the normal data response; The processor of claim 1 , further comprising: based on the pseudo data response, not storing data of the pseudo data response in a cache memory within the primary cache.

3. data of the normal data response is stored in a register in the core circuit based on the normal data response; data of the pseudo data response is stored in a register in the core circuit based on the pseudo data response; The processor of claim 2 , wherein if the pseudo data response is unsuccessful, data of the normal data response is overwritten in a register in the core circuit.

4. The move-in buffer includes: When receiving the normal data response after receiving the pseudo data response, determining whether or not the data of the pseudo data response matches the data of the normal data response, and if they match, determining that the pseudo data response was successful, and if they do not match, determining that the pseudo data response was unsuccessful; The processor of claim 1 , wherein the success or failure of the pseudo data response is notified to the reorder buffer.

5. The arithmetic circuit executes the issued instructions in an out-of-order order different from a program order; the reorder buffer executes the normal instruction execution completion process for the instructions executed by the arithmetic circuit in an in-order order that is the program order; 2. The processor of claim 1, wherein the arithmetic circuit executes a first instruction having a dependency and a second instruction following the first instruction, executes the second instruction after the normal instruction execution completion processing of the first instruction, and further speculatively executes the second instruction after the pseudo instruction execution completion processing of the first instruction.

6. The processor of claim 1 , wherein the pseudo memory request is issued by the move-in buffer.

7. 2. The processor according to claim 1, wherein the pseudo memory request is issued by the second level cache when the normal memory request is issued.

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