Connection structure of semiconductor switching element and power conversion device

Abstract

To arrange and connect a semiconductor switching element of a power converter at low ESL.SOLUTION: A three-phase inverter which is a power conversion device includes: semiconductor switching elements 14A on an upper arm-side, which are connected to a DC capacitor; semiconductor switching elements 14B on a lower arm-side, which are connected to the capacitor; and a gate substrate 11 having patterns 20 connecting emitter terminals E of the semiconductor switching elements 14A and collector terminals C of the elements 14B. The elements 14A and 14B include center collector terminals C, the emitter terminals E on one end side, and gate terminals G on the other end side. The terminals C, E and G extend vertically to the gate substrate 11. The elements 14A and 14B are mounted offset on an opposite face of a cooler 15. The emitter terminals C of the elements 14A and the collector terminals C of the elements 14B are confronted each other and are connected by a wiring pattern in an approximately shortest distance on the gate substrate 11.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present invention relates to a terminal connection structure for a three-terminal discrete-type semiconductor switching element and a power conversion device including the connection structure. [Background technology]

[0002] 1 and 2 show the three-phase inverter described in Patent Document 1. Here, a three-terminal discrete type is used for the semiconductor switching elements 14A, 14B of each phase, and the elements 14A, 14B are mounted on the front and back surfaces of a heat sink 83.

[0003] Figures 3(a) and (b) show an application example of the configuration of Figure 2. Here, a configuration is proposed in which the element 14A on the upper arm side and the element 14B on the lower arm side of Figure 1 are disposed on opposite sides of the cooler.

[0004] In this case, the gate substrate 11 that connects the terminals of the elements 14A and 14B is provided at the top of FIG. 2, and the emitter terminal E of the element 14A and the collector terminal C of the element 14B are connected by a wiring pattern in the gate substrate 11. This connection point is connected to an output terminal block in the gate substrate 11, and the output terminal block and the inverter load are connected by wires or the like. In addition, the P-side bus bar 16 connects the emitter terminal C of the element 14A and the P-terminal of the DC capacitor shown in FIG. 1. Similarly, the N-side bus bar 17 connects the emitter terminal E of the element 14B and the N-terminal of the DC capacitor. Note that FIG. 3 shows an example in which the elements 14A and 14B are IGBTs (insulated gate bipolar transistors). If the elements are MOSFETs, the names of the terminals are changed from collector terminal to drain terminal and emitter terminal to source terminal. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Patent Publication No. 2018-73884 Summary of the Invention [Problem to be solved by the invention]

[0006] As shown in FIG. 3(a), the three-terminal discrete type elements 14A and 14B often have a collector terminal (drain terminal) C located in the center, an emitter terminal (source terminal) E located at one end, and a gate terminal G located at the other end.

[0007] As a result, when the element 14A arranged on the front side of the cooler 15 and the element 14B arranged on the back side are mounted with their positions aligned in the XX' direction, as shown in Figure 3(b), the wiring pattern 20 of the gate substrate 11 connecting the emitter terminal E of the element 14A and the collector terminal C of the element 14B becomes slanted.

[0008] This increases the pattern distance between the terminals E and C, and increases the ESL (wiring impedance, inductance) between the elements 14A, 14B and the capacitor PN terminal, which may cause the following problems.

[0009] (1) The surge voltage generated during switching of the elements 14A and 14B increases, making the elements 14A and 14B more susceptible to overvoltage breakdown.

[0010] (2) The switching speed of the elements 14A and 14B becomes slower, resulting in increased switching loss.

[0011] The present invention has been made to solve such problems in the conventional technology, and has as its object to arrange and connect semiconductor switching elements of a power converter with low ESL. [Means for solving the problem]

[0012] (1) The present invention comprises a semiconductor switching element on an upper arm side connected to a DC capacitor; a lower arm semiconductor switching element connected to the DC capacitor; A structure for connecting terminals of the elements of a power conversion device having one or more arms of DC connections, Each of the elements is configured as a three-terminal discrete type, and includes a collector terminal or drain terminal disposed in the center and an emitter terminal or source terminal disposed on one end side; a substrate that connects the terminals of the elements; the element on the upper arm side and the element on the lower arm side are mounted on opposite sides of a cooler, The device is characterized in that the emitter terminal or drain terminal of the element on the upper arm side and the collector terminal or source terminal of the element on the lower arm side are connected on the substrate by a wiring pattern of approximately the shortest distance.

[0013] (2) In one embodiment, each of the elements is provided offset with the cooler in between, and an emitter terminal of the element on the upper arm side is arranged to face a collector terminal of the element on the lower arm side. In addition, in one embodiment, each of the terminals is formed perpendicular to the substrate. The present invention can also be configured as a power conversion device having a structure for connecting the terminals of the elements. Effect of the Invention

[0014] According to the present invention, it is possible to arrange and connect semiconductor switching elements of a power converter with low ESL. [Brief description of the drawings]

[0015] [Figure 1] FIG. 1 is a circuit diagram of an inverter device disclosed in Patent Document 1. [Diagram 2] FIG. 4 is a perspective view showing a state in which a semiconductor switching element is attached to the heat sink of the same. [Diagram 3] (a) is a layout diagram of the application example in Figure 2, and (b) is a diagram of the connection pattern between the emitter terminal and the collector terminal of (a). [Figure 4]4A is a layout diagram showing the connection structure of a semiconductor switching element according to an embodiment of the present invention, FIG. 4B is a terminal structure diagram of FIG. 4A, and FIG. 4C is a connection pattern diagram of the emitter terminal and collector terminal of FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] A connection structure of semiconductor switching elements according to an embodiment of the present invention will now be described with reference to Fig. 4. This connection structure is used, for example, in a power conversion device that drives a three-phase AC motor mounted in an automobile.

[0017] Here, three-terminal discrete type IGBTs (insulated gate bipolar transistors) are used for the semiconductor switching elements 14A and 14B of each phase of the three-phase inverter, similarly to Fig. 3. Note that MOSFETs may be used instead of the IGBTs.

[0018] That is, as shown in Figures 4(a) and (b), it comprises an upper arm semiconductor switching element 14A that is DC-connected to the P terminal of the DC capacitor via a P-side bus bar 16, and a lower arm semiconductor switching element 14B that is DC-connected to the N terminal of the same capacitor via an N-side bus bar 17, and a gate substrate 11 that connects the terminals of the elements 14A, 14B is provided at the top (lower side in Figure 4(b)).

[0019] The elements 14A and 14B are mounted on the surface opposite to the cooler 15 via an insulating plate 22, and include an element body 21 vertically provided on the gate substrate 11, and an emitter terminal (source terminal) E, a collector terminal (drain terminal) C, and a gate terminal G provided in this order from the right end on one side of the element body 21. Here, as shown in Figs. 4(b) and (c), the collector terminal C is provided in the center of the side, the emitter terminal E is provided on one end (right end), and the gate terminal is provided on the other end (left end). In the case of an insulated element in which the cooling surface (surface on the cooler 15 side) of the elements 14A and 14B is insulated from each terminal, the insulating plate 22 may be omitted.

[0020] The gate substrate 11 is provided with a wiring pattern (not shown) that connects the P-side bus bar 16 and the collector terminal C of the element 14A, a wiring pattern (not shown) that connects the N-side bus bar 17 and the emitter terminal E of the element 14B, and a wiring pattern 20 that connects the emitter terminal E of the element 14A and the collector terminal C of the element 14B. The bus bars 16 and 17 are connected to the P and N terminals of a DC capacitor, respectively. An insulating plate 23 is sandwiched between the bus bars 16 and 17 to insulate them from each other. In the arrangement shown in Fig. 4(b), a gap is generated between the bus bars 16, 17 and the gate substrate 11 in the vertical direction (YY' direction). Therefore, the P-side bus bar 16 is connected to a wiring pattern in the gate substrate 11 having the same potential as the collector terminal C of the element 14A by a wiring member or the like (not shown). The same is true for the N-side bus bar 17. If the bus bars 16, 17 and the gate substrate 11 can be arranged at approximately the same height position (YY' direction position) unlike Fig. 4(b), a PN terminal block connected to the wiring pattern instead of the wiring member may be provided in the gate substrate 11, and the bus bars 16, 17 may be directly connected to this PN terminal block. Furthermore, a wiring pattern 20 connecting the emitter terminal E of the element 14A and the collector terminal C of the element 14B is connected to an output terminal block provided in the gate substrate 11. Furthermore, this output terminal block is connected to an inverter load by an electric wire or the like.

[0021] However, the connection structure in Fig. 4 differs from that in Fig. 3 in that the elements 14A and 14B are disposed offset with the cooler 15 in between. That is, in Fig. 3, the elements 14A and 14B are mounted with their positions aligned in the XX' direction, so that a positional deviation occurs between the emitter terminal E of the element 14A and the collector terminal C of the element 14B, and the wiring pattern 20 of the gate substrate 11 connecting between the terminals E and C becomes inclined.

[0022] In contrast to this, in FIG. 4, the element 14A is mounted offset in the X direction relative to the element 14B, so that the positional deviation between the emitter terminal E of the element 14A and the collector terminal C of the element 14B is absorbed, and the two terminals E and C are disposed opposite each other, as shown in FIG. 4(c).

[0023] This allows the wiring pattern 20 on the gate substrate 11 connecting the emitter terminal E of the element 14A and the collector terminal C of the element 14B to be approximately the shortest distance, making it possible to reduce the ESL between the elements 14A, 14B and the DC capacitor PN terminal.

[0024] At this time, since each of the terminals C and E is extended perpendicularly to the gate substrate 11, the ESL can be further reduced compared to the case where the terminals are formed (bent). In this way, the ESL can be minimized by making the wiring pattern 20 approximately the shortest distance without forming each of the terminals C and E.

[0025] As a result, according to the connection structure of FIG. 4, it is possible to suppress overvoltage breakdown of the elements 14A and 14B due to a reduction in surge voltage, and it is also possible to increase the switching speed and reduce switching loss.

[0026] The present invention is not limited to the above embodiment, and can be modified and implemented within the scope of the claims. For example, the present invention can be applied not only to a three-phase inverter having six discrete semiconductor switching elements, i.e., the elements 14A and 14B, as shown in Fig. 4, but also to a single-phase inverter having four discrete semiconductor switching elements or a chopper having two discrete semiconductor switching elements. In addition, a power conversion device such as an inverter device having the connection structure of Fig. 4 naturally constitutes the present invention. [Explanation of symbols]

[0027] 11...Gate substrate 14A, 14B...Discrete type semiconductor switching element 15...Cooler 16…P side busbar 17…N side busbar 20...A pattern connecting the emitter terminal E of the semiconductor switching element 14A and the collector terminal C of the same element 14B 21...Element body 22, 23...Insulating plate G…Gate terminal C: Collector terminal E: Emitter terminal

Claims

1. An upper arm semiconductor switching element connected to a DC capacitor; a lower arm semiconductor switching element connected to the DC capacitor; A structure for connecting terminals of the elements of a power conversion device having one or more arms of DC connections, Each of the elements is configured as a three-terminal discrete type, and includes a collector terminal or drain terminal disposed in the center and an emitter terminal or source terminal disposed on one end side, a substrate that connects the terminals of the elements; the element on the upper arm side and the element on the lower arm side are mounted on opposite sides of a cooler, The emitter terminal or the drain terminal of the element on the upper arm side and the collector terminal or the source terminal of the element on the lower arm side are connected by a wiring pattern of approximately the shortest distance on the substrate. A connection structure for a semiconductor switching element.

2. The elements are offset from each other across the cooler, The emitter terminal of the element on the upper arm side and the collector terminal of the element on the lower arm side are disposed opposite to each other.

2. The connection structure of claim 1, wherein the semiconductor switching element is a semiconductor switching element.

3. 2. The connection structure of a semiconductor switching element according to claim 1, wherein each of said terminals is formed perpendicular to said substrate.

4. A power conversion device comprising the connection structure for semiconductor switching elements according to any one of claims 1 to 3.

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