Semiconductor device, method for manufacturing semiconductor device, inverter circuit, drive device, vehicle, and elevator

Abstract

To provide a semiconductor device capable of reducing on-resistance.SOLUTION: A semiconductor device includes a silicon carbide layer having a first surface and a second surface, a first trench and a second trench extending in a first direction, a gate electrode, a gate insulating layer, an n-type first silicon carbide region, a p-type second silicon carbide region that is located between the first silicon carbide region and the first surface and shallower than the trench, a plurality of n-type third silicon carbide regions and a plurality of p-type fourth silicon carbide regions that are located between the second silicon carbide region and the first surface and alternately formed in the first direction, an n-type fifth silicon carbide region that is located between the first trench and the second trench and between the second silicon carbide region and the third silicon carbide region and the fourth silicon carbide region, is in contact with the first trench and extends in the first direction, and an n-type sixth silicon carbide region that is located in a second direction perpendicular to the first direction to be away from the fifth silicon carbide region, is in contact with the second trench, and extends in the first direction.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] An embodiment of the present disclosure relates to a semiconductor device, a method for manufacturing a semiconductor device, an inverter circuit, a drive device, a vehicle, and an elevator. [Background technology]

[0002] Silicon carbide (SiC) is expected to be a material for next-generation semiconductor devices. Compared to silicon, silicon carbide has excellent physical properties, such as a band gap about three times larger, a breakdown electric field strength about ten times larger, and a thermal conductivity about three times larger. By utilizing these physical properties, it is possible to realize semiconductor devices that are low-loss and capable of operating at high temperatures.

[0003] In vertical metal oxide semiconductor field effect transistors (MOSFETs) using silicon carbide, a trench gate structure in which a gate electrode is provided inside a trench is applied to achieve low on-resistance. By applying the trench gate structure, the channel area per unit area is increased, and the on-resistance is reduced. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2021-150406 A Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present disclosure is to provide a semiconductor device capable of reducing the on-resistance. [Means for solving the problem]

[0006] A semiconductor device according to an embodiment includes a silicon carbide layer having a first surface parallel to a first direction and a second direction perpendicular to the first direction, and a second surface parallel to the first surface, a first trench provided in the silicon carbide layer, provided on a side of the first surface of the silicon carbide layer and extending in the first direction, a first gate electrode provided in the first trench, a first gate insulating layer provided between the first gate electrode and the silicon carbide layer, and a second gate insulating layer provided in the silicon carbide layer, provided on a side of the first surface of the silicon carbide layer and extending in the first direction. a second trench, a second gate electrode provided in the second trench, a second gate insulating layer provided between the second gate electrode and the silicon carbide layer, an n-type first silicon carbide region provided in the silicon carbide layer and at least a portion of which is provided between the first trench and the second trench, a p-type second silicon carbide region provided in the silicon carbide layer, between the first trench and the second trench, and between the first silicon carbide region and the first surface, and a p-type second silicon carbide region provided in the silicon carbide layer and between the first trench and the second trench. a plurality of n-type third silicon carbide regions and a plurality of p-type fourth silicon carbide regions are provided between the first trench and the second trench, the plurality of n-type third silicon carbide regions are provided between the second silicon carbide region and the first surface, and are alternately arranged in the first direction; an n-type fifth silicon carbide region is provided in the silicon carbide layer, between the first trench and the second trench, contacts the first trench, is provided between the second silicon carbide region and the third silicon carbide region and between the second silicon carbide region and the fourth silicon carbide region, and extends in the first direction; an n-type sixth silicon carbide region provided in the silicon carbide layer, between the first trench and the second trench, in contact with the second trench, spaced apart from the fifth silicon carbide region, between the second silicon carbide region and the third silicon carbide region and between the second silicon carbide region and the fourth silicon carbide region, and extending in the first direction; a first electrode provided on a side of the silicon carbide layer facing the first surface, in contact with the third silicon carbide region and the fourth silicon carbide region; and a second electrode provided on a side of the silicon carbide layer facing the second surface.and an interlayer insulating layer provided between the first gate electrode and the first electrode and between the second gate electrode and the first electrode. [Brief description of the drawings]

[0007] [Figure 1] 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. [Diagram 2] 1 is a schematic top view of a semiconductor device according to a first embodiment. [Diagram 3] 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. [Figure 4] 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. [Diagram 5] 3A to 3C are schematic cross-sectional views showing an example of a manufacturing method of the semiconductor device according to the first embodiment. [Figure 6] 3A to 3C are schematic cross-sectional views showing an example of a manufacturing method of the semiconductor device according to the first embodiment. [Figure 7] 3A to 3C are schematic cross-sectional views showing an example of a manufacturing method of the semiconductor device according to the first embodiment. [Figure 8] 3A to 3C are schematic cross-sectional views showing an example of a manufacturing method of the semiconductor device according to the first embodiment. [Figure 9] 3A to 3C are schematic cross-sectional views showing an example of a manufacturing method of the semiconductor device according to the first embodiment. [Figure 10] 3A to 3C are schematic cross-sectional views showing an example of a manufacturing method of the semiconductor device according to the first embodiment. [Figure 11] 3A to 3C are schematic cross-sectional views showing an example of a manufacturing method of the semiconductor device according to the first embodiment. [Figure 12] 3A to 3C are schematic cross-sectional views showing an example of a manufacturing method of the semiconductor device according to the first embodiment. [Figure 13] 3A to 3C are schematic cross-sectional views showing an example of a manufacturing method of the semiconductor device according to the first embodiment. [Figure 14] 3A to 3C are schematic cross-sectional views showing an example of a manufacturing method of the semiconductor device according to the first embodiment. [Figure 15] 3A to 3C are schematic cross-sectional views showing an example of a manufacturing method of the semiconductor device according to the first embodiment. [Figure 16] FIG. 2 is a schematic cross-sectional view of a semiconductor device according to a first comparative example. [Figure 17]FIG. 4 is an explanatory diagram of a problem of the semiconductor device of the first comparative example. [Figure 18] FIG. 11 is a schematic cross-sectional view of a semiconductor device according to a second comparative example. [Figure 19] FIG. 11 is an explanatory diagram of a problem of the semiconductor device of the second comparative example. [Figure 20] 5A to 5C are explanatory diagrams illustrating the operation and effects of the semiconductor device according to the first embodiment. [Figure 21] FIG. 5 is a schematic cross-sectional view of a semiconductor device according to a second embodiment. [Figure 22] FIG. 5 is a schematic cross-sectional view of a semiconductor device according to a second embodiment. [Diagram 23] FIG. 11 is a schematic cross-sectional view of a semiconductor device according to a modified example of the second embodiment. [Figure 24] FIG. 13 is a schematic diagram of a drive device according to a third embodiment. [Diagram 25] FIG. 13 is a schematic diagram of a vehicle according to a fourth embodiment. [Figure 26] FIG. 13 is a schematic diagram of a vehicle according to a fifth embodiment. [Figure 27] FIG. 13 is a schematic diagram of an elevator according to a sixth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In the following description, the same reference numerals will be used to designate the same or similar components, and the description of components that have already been described will be omitted as appropriate.

[0009] In the following description, n + , n, n - And, p + , p, p - When the notations are used, these notations indicate the relative high and low impurity concentrations in each conductivity type. + has a relatively higher n-type impurity concentration than n, - indicates that the n-type impurity concentration is relatively lower than that of n. + has a relatively higher p-type impurity concentration than p, - indicates that the p-type impurity concentration is relatively lower than that of p. + type, n -The types are simply n-type and p-type. + type, p - The type is sometimes simply referred to as p-type.

[0010] The impurity concentration can be measured by, for example, Secondary Ion Mass Spectrometry (SIMS). The relative level of the impurity concentration can also be determined from the level of the carrier concentration obtained by, for example, Scanning Capacitance Microscopy (SCM). Distances such as the width and depth of the impurity region can be obtained by, for example, SIMS. Distances such as the width and depth of the impurity region can also be obtained from, for example, an SCM image.

[0011] The trench width, trench interval, trench depth, insulating layer thickness, etc. can be measured on an image taken with a Transmission Electron Microscope (TEM), for example.

[0012] In this specification, unless otherwise defined, the impurity concentration of a particular region is represented by the impurity concentration at the center of the region.

[0013] (First embodiment) A semiconductor device of a first embodiment includes a silicon carbide layer having a first surface parallel to a first direction and a second direction perpendicular to the first direction, and a second surface parallel to the first surface, a first trench provided in the silicon carbide layer, on the side of the first surface of the silicon carbide layer, and extending in the first direction, a first gate electrode provided in the first trench, a first gate insulating layer provided between the first gate electrode and the silicon carbide layer, a second trench provided in the silicon carbide layer, on the side of the first surface of the silicon carbide layer, and extending in the first direction, a second gate electrode provided in the second trench; a second gate insulating layer provided between the second gate electrode and the silicon carbide layer; an n-type first silicon carbide region provided in the silicon carbide layer and at least a portion of which is provided between the first trench and the second trench; a p-type second silicon carbide region provided in the silicon carbide layer, between the first trench and the second trench, and between the first silicon carbide region and the first surface; a plurality of n-type third silicon carbide regions and a plurality of p-type fourth silicon carbide regions provided between the silicon carbide region and the first surface and alternately arranged in a first direction; an n-type fifth silicon carbide region provided in the silicon carbide layer, provided between the first trench and the second trench, in contact with the first trench, provided between the second silicon carbide region and the third silicon carbide region and between the second silicon carbide region and the fourth silicon carbide region, and extending in the first direction; and a fifth silicon carbide region provided in the silicon carbide layer, provided between the first trench and the second trench, the sixth silicon carbide region of n-type contacting the trench and separated from the fifth silicon carbide region, and provided between the second silicon carbide region and the third silicon carbide region and between the second silicon carbide region and the fourth silicon carbide region, and extending in the first direction; a first electrode provided on the first surface side of the silicon carbide layer and in contact with the third silicon carbide region and the fourth silicon carbide region; a second electrode provided on the second surface side of the silicon carbide layer; and an interlayer insulating layer provided between the first gate electrode and the first electrode and between the second gate electrode and the first electrode.

[0014] 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. The semiconductor device according to the first embodiment is a trench-gate vertical MOSFET 100 using silicon carbide. The MOSFET 100 is an n-channel MOSFET that uses electrons as carriers.

[0015] Fig. 2 is a schematic top view of the semiconductor device of the first embodiment. Fig. 2 is a top view of the first face F1 of Fig. 1. Fig. 1 is a cross section taken along line AA' of Fig. 2.

[0016] 3 is a schematic cross-sectional view of the semiconductor device according to the first embodiment, taken along line BB' of FIG.

[0017] 4 is a schematic cross-sectional view of the semiconductor device according to the first embodiment, taken along line CC' in FIGS.

[0018] The MOSFET 100 includes a silicon carbide layer 10, a first trench 11, a first gate electrode 12, a first gate insulating layer 13, a second trench 21, a second gate electrode 22, a second gate insulating layer 23, a source electrode 41 (first electrode), a drain electrode 42 (second electrode), and an interlayer insulating layer 43.

[0019] Hereinafter, the first trench 11 and the second trench 21 may be collectively referred to as trenches. The first gate electrode 12 and the second gate electrode 22 may be collectively referred to as gate electrodes. The first gate insulating layer 13 and the second gate insulating layer 23 may be collectively referred to as gate insulating layers.

[0020] In the silicon carbide layer 10, n + 50, n-type drain region - a p-type drift region 51 (first silicon carbide region), a p-type body region 52 (second silicon carbide region), + an upper source region 53 (third silicon carbide region) of p + type contact region 54 (fourth silicon carbide region), + a first lower source region 55a (fifth silicon carbide region) of the n-type +a second lower source region 55b (sixth silicon carbide region) of type n + The third lower source region 55c, n + A fourth lower source region 55d of the type, and + A field relief region 56 of the mold is provided.

[0021] Hereinafter, the first lower source region 55a, the second lower source region 55b, the third lower source region 55c, and the fourth lower source region 55d may be collectively referred to as lower source region 55.

[0022] The silicon carbide layer 10 is made of single crystal SiC, for example, 4H—SiC.

[0023] Silicon carbide layer 10 has a first surface (F1 in FIG. 1) and a second surface (F2 in FIG. 1). First surface F1 and second surface F2 face each other. First surface F1 and second surface F2 are parallel to each other. Hereinafter, first surface F1 will also be referred to as the front surface, and second surface F2 will also be referred to as the back surface. Note that, hereinafter, "depth" refers to the depth in the direction toward second surface F2 with first surface F1 as the reference.

[0024] 1 to 4, the first direction and the second direction are parallel to the first plane F1, and the second direction is perpendicular to the first direction.

[0025] 1 to 4, the third direction is a direction perpendicular to the first direction and the second direction. The third direction is a direction from the first face F1 to the second face F2. The third direction is a direction perpendicular to the first face F1. Hereinafter, the third direction may be referred to as a depth direction.

[0026] The first face F1 is, for example, a face inclined at 0 to 8 degrees with respect to the (0001) face. That is, the normal is a face inclined at 0 to 8 degrees with respect to the c-axis in the

[0001] direction. In other words, the off angle with respect to the (0001) face is 0 to 8 degrees. The second face F2 is, for example, a face inclined at 0 to 8 degrees with respect to the (000-1) face.

[0027] The (0001) plane is called a silicon plane. The (000-1) plane is called a carbon plane. The tilt direction of the first plane F1 and the second plane F2 is, for example, the [11-20] direction. The [11-20] direction is the a-axis direction. In FIG. 2, for example, the first direction shown in the figure is the a-axis direction.

[0028] The first trench 11 and the second trench 21 are present in the silicon carbide layer 10. The first trench 11 and the second trench 21 are provided on the front surface side of the silicon carbide layer 10. The first trench 11 and the second trench 21 extend in a first direction as shown in FIG. 2. The first trench 11 and the second trench 21 are grooves formed in the silicon carbide layer 10.

[0029] The widths of the first trench 11 and the second trench 21 in the second direction are, for example, smaller than the distance between the first trench 11 and the second trench 21.

[0030] The width of the first trench 11 and the second trench 21 in the second direction is, for example, not less than 0.3 μm and not more than 1 μm. The distance between the first trench 11 and the second trench 21 is, for example, not less than 0.5 μm and not more than 2 μm. The depth of the first trench 11 and the second trench 21 is, for example, not less than 1 μm and not more than 3 μm.

[0031] A plurality of trenches including the first trench 11 and the second trench 21 are repeatedly arranged in the second direction. The repeat pitch of the plurality of trenches in the second direction is, for example, not less than 1 μm and not more than 5 μm.

[0032] The first gate electrode 12 is provided in the first trench 11. The first gate electrode 12 is provided between the source electrode 41 and the drain electrode 42. The first gate electrode 12 extends in a first direction.

[0033] The distance in the third direction perpendicular to the first face F1 from the first face F1 to the first gate electrode 12 is, for example, greater than the distance from the first face F1 to the interface between the contact region 54 and the first lower source region 55a. Also, the distance in the third direction perpendicular to the first face F1 from the first face F1 to the first gate electrode 12 is, for example, smaller than the distance from the first face F1 to the interface between the first lower source region 55a and the body region 52.

[0034] The second gate electrode 22 is provided in the second trench 21. The second gate electrode 22 is provided between the source electrode 41 and the drain electrode 42. The second gate electrode 22 extends in a first direction.

[0035] The distance from the first face F1 to the second gate electrode 22 in the third direction perpendicular to the first face F1 is, for example, greater than the distance from the first face F1 to the interface between the contact region 54 and the second lower source region 55b. Also, the distance from the first face F1 to the second gate electrode 22 in the third direction perpendicular to the first face F1 is, for example, smaller than the distance from the first face F1 to the interface between the second lower source region 55b and the body region 52.

[0036] The first gate electrode 12 and the second gate electrode 22 are conductive layers, and are, for example, polycrystalline silicon containing p-type impurities or n-type impurities.

[0037] The first gate insulating layer 13 is provided between the first gate electrode 12 and the silicon carbide layer 10. The first gate insulating layer 13 is provided between the first gate electrode 12 and each of the first lower source region 55a, the third lower source region 55c, the body region 52, the drift region 51, and the electric field relaxation region 56.

[0038] The second gate insulating layer 23 is provided between the second gate electrode 22 and the silicon carbide layer 10. The second gate insulating layer 23 is provided between the second gate electrode 22 and each of the second lower source region 55b, the fourth lower source region 55d, the body region 52, the drift region 51, and the electric field relaxation region 56.

[0039] The first gate insulating layer 13 and the second gate insulating layer 23 are, for example, silicon oxide films. For example, a high-k insulating film (a high dielectric constant insulating film such as HfSiON, ZrSiON, or AlON) can be used for the first gate insulating layer 13 and the second gate insulating layer 23. Also, for example, a stacked film of a silicon oxide film (SiO2) and a high-K insulating film can be used for the first gate insulating layer 13 and the second gate insulating layer 23.

[0040] The interlayer insulating layer 43 is provided on the first gate electrode 12 and on the second gate electrode 22. The interlayer insulating layer 43 is provided between the first gate electrode 12 and the source electrode 41, and between the second gate electrode 22 and the source electrode 41.

[0041] The interlayer insulating layer 43 is, for example, a silicon oxide film.

[0042] The source electrode 41 is provided on the surface side of the silicon carbide layer 10. The source electrode 41 is provided on the surface of the silicon carbide layer 10. The source electrode 41 is electrically connected to the body region 52, the upper source region 53, the lower source region 55, and the contact region 54. The source electrode 41 is in contact with the upper source region 53 and the contact region 54.

[0043] The source electrode 41 includes a metal. The metal forming the source electrode 41 is, for example, a laminated structure of titanium (Ti) and aluminum (Al). The source electrode 41 may include a metal silicide or a metal carbide in contact with the silicon carbide layer 10.

[0044] The drain electrode 42 is provided on the back surface side of the silicon carbide layer 10. The drain electrode 42 is provided on the back surface of the silicon carbide layer 10. The drain electrode 42 is in contact with the drain region 50.

[0045] The drain electrode 42 is, for example, a metal or a metal-semiconductor compound, and includes, for example, a material selected from the group consisting of nickel silicide (NiSi), titanium (Ti), nickel (Ni), silver (Ag), and gold (Au).

[0046] n + The n-type drain region 50 is provided on the back surface side of the silicon carbide layer 10. The drain region 50 contains, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration of the drain region 50 is, for example, 1×10 18 cm -3 More than 1×10 21 cm -3 The following is the result.

[0047] n - A type drift region 51 is provided on the drain region 50. The drift region 51 is provided between the drain region 50 and a surface of the silicon carbide layer 10. A portion of the drift region 51 is provided between the first trench 11 and the second trench 21.

[0048] The drift region 51 contains, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration of the drift region 51 is, for example, 4×10 14 cm -3 More than 1×10 18 cm -3 The thickness of the drift region 51 in the third direction is, for example, not less than 4 μm and not more than 150 μm.

[0049] The p-type body region 52 is provided between the drift region 51 and the surface of the silicon carbide layer 10. The body region 52 is provided between the first trench 11 and the second trench 21. The body region 52 contacts a side surface of the first trench 11 and a side surface of the second trench 21.

[0050] The body region 52 functions as a channel region of the MOSFET 100. For example, when the MOSFET 100 is in an on-state, a channel through which electrons flow is formed in a region of the body region 52 in contact with the gate insulating layer.

[0051] The depth of body region 52 is shallower than the depth of first trench 11 from the surface of silicon carbide layer 10. First trench 11 penetrates body region 52. The depth of body region 52 is shallower than the depth of second trench 21 from the surface of silicon carbide layer 10. Second trench 21 penetrates body region 52. The depth of body region 52 is, for example, not less than 0.8 μm and not more than 2.0 μm.

[0052] The body region 52 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration of the body region 52 is, for example, 5×10 16 cm -3 5×10 or more 18 cm -3 The following is the result.

[0053] n + The upper source region 53 and the p + A type contact region 54 is provided between the first trench 11 and the second trench 21. The upper source region 53 and the contact region 54 are provided between the body region 52 and the surface of the silicon carbide layer 10.

[0054] 2, the multiple upper source regions 53 and the multiple contact regions 54 are alternately arranged in a first direction. The upper source regions 53 and the contact regions 54 contact each other.

[0055] An upper source region 53 extends in the second direction intersecting the trench. A contact region 54 extends in the second direction intersecting the trench.

[0056] The width (Wn in FIG. 4) of the upper source region 53 in the first direction is, for example, not less than 0.3 μm and not more than 30 μm. The width (Wp in FIG. 4) of the contact region 54 in the first direction is, for example, not less than 0.3 μm and not more than 30 μm. The width Wn of the upper source region 53 in the first direction is, for example, not less than 0.5 times and not more than 2 times the width Wp of the contact region 54 in the first direction.

[0057] The arrangement ratio (Wp / (Wn+Wp)) of the contact region 54 in the first direction is, for example, not less than 0.1 and not more than 50. In other words, the ratio (Wp / (Wn+Wp)) of the width Wp of the contact region 54 in the first direction to the sum of the width Wn of the upper source region 53 in the first direction and the width Wp of the contact region 54 in the first direction is, for example, not less than 0.1 and not more than 50.

[0058] The upper source region 53 contacts a side surface of a trench. The upper source region 53 contacts, for example, a side surface of the first trench 11. The upper source region 53 contacts, for example, a side surface of the second trench 21.

[0059] The upper source region 53 is in contact with the source electrode 41. The upper source region 53 is in contact with the source electrode 41 on the surface of the silicon carbide layer 10, for example.

[0060] The depth of the upper source region 53 is shallower than the depth of the body region 52. The depth of the upper source region 53 is, for example, not less than 0.2 μm and not more than 0.6 μm.

[0061] The upper source region 53 contains nitrogen (N) or phosphorus (P) as an n-type impurity. The n-type impurity concentration of the upper source region 53 is higher than the n-type impurity concentration of the drift region 51. The n-type impurity concentration of the upper source region 53 is, for example, 1×10 19 cm -3 More than 1×10 21 cm -3 The following is the result.

[0062] p +The mold contact region 54 contacts the side surface of the trench. For example, the contact region 54 contacts the side surface of the first trench 11. For example, the contact region 54 contacts the side surface of the second trench 21.

[0063] The contact region 54 is in contact with the source electrode 41. The contact region 54 is in contact with the source electrode 41 on the surface of the silicon carbide layer 10, for example.

[0064] The depth of the contact region 54 is shallower than the depth of the body region 52. The depth of the contact region 54 is, for example, not less than 0.2 μm and not more than 0.6 μm.

[0065] The contact region 54 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration of the contact region 54 is higher than the p-type impurity concentration of the body region 52.

[0066] The p-type impurity concentration of the contact region 54 is, for example, 1×10 18 cm -3 More than 1×10 21 cm -3 The p-type impurity concentration of the contact region 54 in the contact portion with the source electrode 41 is, for example, 1×10 19 cm -3 More than 1×10 21 cm -3 The following is the result.

[0067] n + A first lower source region 55a of the same type is provided between the body region 52 and the upper source region 53. The first lower source region 55a is provided between the body region 52 and the contact region .

[0068] The first lower source region 55a contacts the body region 52. The first lower source region 55a contacts the upper source region 53. The first lower source region 55a contacts the contact region .

[0069] The first lower source region 55a extends in a first direction.

[0070] The first lower source region 55a is provided between the first trench 11 and the second trench 21. The first lower source region 55a contacts the side surface of the second trench 21.

[0071] n + A second lower source region 55b of the same type is provided between the body region 52 and the upper source region 53. The second lower source region 55b is provided between the body region 52 and the contact region .

[0072] The second lower source region 55b contacts the body region 52. The second lower source region 55b contacts the upper source region 53. The second lower source region 55b contacts the contact region .

[0073] The second lower source region 55b extends in the first direction.

[0074] The second lower source region 55b is spaced apart from the first lower source region 55a in the second direction. The body region 52 is provided between the first lower source region 55a and the second lower source region 55b.

[0075] n + A third lower source region 55c of the same type is provided between the body region 52 and the upper source region 53. The third lower source region 55c is provided between the body region 52 and the contact region .

[0076] The third lower source region 55c contacts the body region 52. The third lower source region 55c contacts the upper source region 53. The third lower source region 55c contacts the contact region .

[0077] The third lower source region 55c extends in the first direction.

[0078] Between the first lower source region 55a and the third lower source region 55c, the first trench 11 is provided. The third lower source region 55c contacts the side surface of the first trench 11.

[0079] n + A fourth lower source region 55d of the type is provided between the body region 52 and the upper source region 53. The fourth lower source region 55d is provided between the body region 52 and the contact region .

[0080] The fourth lower source region 55d contacts the body region 52. The fourth lower source region 55d contacts the upper source region 53. The fourth lower source region 55d contacts the contact region .

[0081] The fourth lower source region 55d extends in the first direction.

[0082] The second trench 21 is provided between the second lower source region 55b and the fourth lower source region 55d. The fourth lower source region 55d contacts the side surface of the second trench 21.

[0083] The depth of the lower source region 55 is shallower than the depth of the body region 52. The depth of the lower source region 55 is deeper than the depth of the upper source region 53 and the depth of the contact region 54. The depth of the lower source region 55 is, for example, not less than 0.4 μm and not more than 1.0 μm.

[0084] The width of the lower source region 55 in the third direction is, for example, not less than 0.2 μm and not more than 0.6 μm.

[0085] The lower source region 55 contains nitrogen (N) or phosphorus (P) as an n-type impurity. The n-type impurity concentration of the lower source region 55 is higher than the n-type impurity concentration of the drift region 51. The n-type impurity concentration of the lower source region 55 is, for example, 1×10 19 cm -3 More than 1×10 21 cm -3 The following is the result.

[0086] The n-type impurity concentration of the lower source region 55 is, for example, 0.1 to 10 times the n-type impurity concentration of the upper source region 53.

[0087] p + The electric field relaxation region 56 of the mold is provided between the drift region 51 and the trench. The electric field relaxation region 56 is provided, for example, between the drift region 51 and the first trench 11. The electric field relaxation region 56 is provided, for example, between the drift region 51 and the second trench 21.

[0088] The electric field relaxation region 56 contacts the first trench 11. The electric field relaxation region 56 contacts the second trench 21.

[0089] The electric field buffer region 56 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration of the electric field buffer region 56 is higher than the p-type impurity concentration of the body region 52. The p-type impurity concentration of the electric field buffer region 56 is, for example, 1×10 17 cm -3 More than 1×10 20 cm -3 The following is the result.

[0090] The potential of the electric field relaxation region 56 is fixed, for example, to the potential of the source electrode 41. The potential of the electric field relaxation region 56 is fixed, for example, to the source potential. The electric field relaxation region 56 has a function of relaxing the electric field applied to the gate insulating layer at the bottom of the trench.

[0091] A method for manufacturing a semiconductor device according to a first embodiment includes the steps of: preparing a silicon carbide layer having a first surface parallel to a first direction and a second direction perpendicular to the first direction, and a second surface parallel to the first surface, the silicon carbide layer including an n-type first region, a p-type second region provided between the first region and the first surface, and a plurality of n-type third regions and a plurality of p-type fourth regions provided between the second region and the first surface, alternately arranged in the first direction, and extending in the second direction; A first mask material having an extending first opening is formed, n-type impurities are ion-implanted from the first opening using the first mask material as a mask to form an n-type fifth region that is deeper than the third region and the fourth region and shallower than the second region, a sidewall is formed in the first opening, a trench penetrating the second region, the third region, the fourth region, and the fifth region is formed using the first mask material and the sidewall as a mask, a gate insulating layer is formed in the trench, and a gate electrode is formed on the gate insulating layer in the trench.

[0092] An example of a method for manufacturing the semiconductor device of the first embodiment will be described below.

[0093] Figures 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, and 15 are schematic cross-sectional views showing an example of a method for manufacturing the semiconductor device of the first embodiment. Figures 5, 7, 9, 10, 11, 12, 13, 14, and 15 are cross-sectional views corresponding to Figure 1. Figures 6 and 8 are top views corresponding to Figure 2.

[0094] First, a silicon carbide layer 10 is prepared (FIGS. 5 and 6). The silicon carbide layer 10 has a first surface (F1 in FIG. 5) parallel to a first direction and a second direction perpendicular to the first direction, and a second surface (F2 in FIG. 5) parallel to the first surface F1.

[0095] The silicon carbide layer 10 is + 50, n-type drain region - A p-type drift region 51 (first region), a p-type body region 52 (second region), and a plurality of n + A top source region 53 (third region) of type p +The mold contact region 54 (fourth region) is included.

[0096] The body region 52 is provided between the drain region 50 and the first face F1. The upper source region 53 and the contact region 54 are provided between the body region 52 and the first face F1.

[0097] The upper source regions 53 and the contact regions 54 are alternately arranged in a first direction as shown in Figure 6. The upper source regions 53 and the contact regions 54 extend in a second direction as shown in Figure 6.

[0098] The drift region 51 is formed, for example, by epitaxial growth on the drain region 50. The body region 52, the upper source region 53, and the contact region 54 are formed, for example, by ion implantation of impurities from the surface of the silicon carbide layer 10.

[0099] Next, a first mask material 61 is formed on the silicon carbide layer 10 (FIGS. 7 and 8). The first mask material 61 has a first opening 61a. The first opening 61a extends in a first direction. In the first opening 61a, the upper source region 53 and the contact region 54 are exposed.

[0100] The first mask material 61 is formed by, for example, depositing a film by a chemical vapor deposition method (CVD method), and patterning the film by a lithography method and a reactive ion etching method (RIE method). The first mask material 61 is, for example, a silicon oxide film.

[0101] Next, using the first mask material 61 as a mask, n-type impurities are ion-implanted into the silicon carbide layer 10 through the first openings 61a. + Then, an n-type lower source region 55 (fifth region) is formed (FIG. 9). The n-type impurity is, for example, phosphorus (P) or nitrogen (N).

[0102] The lower source region 55 is shallower than the body region 52. The lower source region 55 is deeper than the upper source region 53 and the contact region .

[0103] Next, a sidewall 62 is formed in the first opening 61a of the first mask material 61 (FIG. 10). The sidewall 62 is, for example, a silicon oxide film.

[0104] Next, using the first mask material 61 and the sidewall 62 as a mask, a trench 71 is formed (FIG. 11). The trench 71 penetrates the upper source region 53, the contact region 54, the lower source region 55, and the body region 52. The trench 71 is formed by, for example, the RIE method.

[0105] The upper source region 53, the contact region 54, and the lower source region 55 are divided into left and right regions by a trench 71. The lower source region 55 is divided into two regions with the trench 71 sandwiched therebetween.

[0106] Next, a sidewall film 63 is formed on the side surface of the trench 71. The sidewall film 63 is, for example, a silicon oxide film.

[0107] Next, p-type impurities are ion-implanted using the first mask material 61 and the sidewall 62 as a mask. + A p-type electric field relaxation region 56 is formed (FIG. 12). The electric field relaxation region 56 is formed in the bottom of the trench 71. The p-type impurity is, for example, aluminum (Al). The sidewall film 63 suppresses the introduction of the p-type impurity into the silicon carbide layer 10 from the side surface of the trench 71.

[0108] Next, the first mask material 61, the sidewall 62, and the sidewall film 63 are peeled off. The first mask material 61, the sidewall 62, and the sidewall film 63 are peeled off by, for example, a wet etching method.

[0109] Next, a gate insulating layer 73 is formed in the trench 71. Next, a gate electrode 74 is formed on the gate insulating layer 73 in the trench 71. The gate insulating layer 73 is, for example, a silicon oxide film. The gate electrode 74 is, for example, polycrystalline silicon containing p-type impurities or n-type impurities. The gate insulating layer 73 and the gate electrode 74 are formed by, for example, a CVD method.

[0110] Next, the gate insulating layer 73 and the gate electrode 74 in the upper part of the trench 71 are removed (FIG. 13). The gate insulating layer 73 and the gate electrode 74 are removed by, for example, a wet etching method or a dry etching method. The upper surface of the gate electrode 74 is located in the trench 71.

[0111] Next, the trench 71 is filled with a buried insulating layer 75. The buried insulating layer 75 is an example of an insulating layer. The buried insulating layer 75 is, for example, a silicon oxide film. The buried insulating layer 75 is formed by, for example, a CVD method.

[0112] Next, a second opening 75a is formed in the buried insulating layer 75 (FIG. 14). In the second opening 75a, the upper source region 53 and the contact region 54 are exposed on the upper surface of the silicon carbide layer 10. The second opening 75a is formed by using, for example, a photolithography method and an RIE method.

[0113] Next, the source electrode 41 is formed (FIG. 15). The source electrode 41 is formed by depositing a metal film by, for example, a sputtering method or a CVD method.

[0114] Thereafter, a drain electrode 42 is formed on the back surface of the silicon carbide layer 10 using a known process technology.

[0115] By the above manufacturing method, the MOSFET 100 shown in FIGS. 1 to 4 is manufactured.

[0116] Next, the operation and effects of the semiconductor device of the first embodiment will be described.

[0117] According to the MOSFET 100 of the first embodiment, it is possible to reduce both the switching loss and the on-resistance, as will be described in detail below.

[0118] Fig. 16 is a schematic cross-sectional view of a semiconductor device of a first comparative example, which corresponds to Fig. 4 of the first embodiment.

[0119] The semiconductor device of the first comparative example is a trench-gate vertical MOSFET 901 using silicon carbide. The MOSFET 901 is an n-channel MOSFET in which electrons serve as carriers.

[0120] In the MOSFET 901, the silicon carbide layer 10 is + The MOSFET 100 differs from the MOSFET 100 of the first embodiment in that it does not include a lower source region 55 of the same type.

[0121] In the MOSFET 901, the width Wn of the upper source region 53 in the first direction is larger than the width Wp of the contact region 54 in the first direction.

[0122] 17 is an explanatory diagram of the problem of the semiconductor device of the first comparative example, and corresponds to FIG.

[0123] The right half of Fig. 17 shows a schematic diagram of a current flowing through body region 52 when MOSFET 901 is in the on state. The left half of Fig. 17 shows a schematic diagram of a current flowing through body region 52 during a turn-off operation of MOSFET 901. In other words, the left half of Fig. 17 shows a schematic diagram of a current flowing through body region 52 when MOSFET 901 transitions from an on state to an off state. The current is indicated by an arrow.

[0124] When MOSFET 901 is in the on state, a current flows through an inversion layer formed in body region 52 from drift region 51 toward upper source region 53. At this time, the body region 52 between contact region 54 and drift region 51 becomes an ineffective region (X in FIG. 17) through which a current does not easily flow.

[0125] The presence of the invalid region X in the body region 52 increases the channel resistance of the MOSFET 901. Therefore, the on-resistance of the MOSFET 901 increases.

[0126] During the turn-off operation of the MOSFET 901, the inversion layer formed in the body region 52 disappears, and the current does not flow, and the MOSFET 901 transitions from the on state to the off state. As shown in FIG. 17, the body region 52 between the center of the upper source region 53 and the drift region 51 is far from the contact region 54. Therefore, the apparent resistance of the body region 52 between the center of the upper source region 53 and the drift region 51 is high, and the change in potential during the turn-off operation is delayed. Therefore, the disappearance of the inversion layer in the body region 52 is delayed, and the transition from the on state to the off state is delayed. The delay in the transition from the on state to the off state increases the turn-off loss of the MOSFET 901. In other words, the switching loss of the MOSFET 901 increases.

[0127] Fig. 18 is a schematic cross-sectional view of a semiconductor device of a second comparative example, which corresponds to Fig. 16 of the first comparative example.

[0128] The semiconductor device of the second comparative example is a trench-gate vertical MOSFET 902 using silicon carbide. The MOSFET 902 is an n-channel MOSFET in which electrons serve as carriers.

[0129] MOSFET 902 differs from MOSFET 901 in that the width Wn of upper source region 53 in the first direction is smaller than that of MOSFET 901 of the first comparative example, and the layout ratio (Wp / (Wn+Wp)) of contact region 54 in the first direction is higher.

[0130] Fig. 19 is an explanatory diagram of the problem of the semiconductor device of the second comparative example. Fig. 19 is a diagram corresponding to Fig. 18. Fig. 19 is a diagram corresponding to Fig. 17 of the first comparative example.

[0131] 19 shows a schematic diagram of a current flowing through the body region 52 when the MOSFET 902 is in the on state. The left half of Fig. 19 shows a schematic diagram of a current flowing through the body region 52 when the MOSFET 902 is turned off.

[0132] In the MOSFET 902, the width Wn of the upper source region 53 in the first direction is smaller than that of the MOSFET 901 of the first comparative example. Therefore, the distance from the contact region 54 of the body region 52 between the center of the upper source region 53 and the drift region 51 is closer than that of the MOSFET 901 of the first comparative example. Therefore, in the body region 52 between the center of the upper source region 53 and the drift region 51, the apparent resistance of the body region 52 is lower, and the change in potential during the turn-off operation is promoted. Therefore, compared with the MOSFET 901 of the first comparative example, the disappearance of the inversion layer is promoted, and the transition from the on state to the off state is promoted. The promotion of the transition from the on state to the off state reduces the turn-off loss of the MOSFET 902. In other words, the switching loss of the MOSFET 902 is reduced.

[0133] When the MOSFET 902 is in an on state, a current flows through an inversion layer formed in the body region 52 from the drift region 51 toward the upper source region 53. At this time, the body region 52 between the contact region 54 and the drift region 51 becomes an ineffective region X through which a current does not easily flow.

[0134] The presence of the invalid region X in the body region 52 increases the channel resistance of the MOSFET 902. Therefore, the on-resistance of the MOSFET 902 increases.

[0135] The MOSFET 902 has a higher arrangement ratio of the contact region 54 than the MOSFET 901 of the first comparative example. Therefore, the proportion of the invalid region X, through which current does not easily flow, in the body region 52 is higher than that of the MOSFET 901 of the first comparative example. Therefore, the channel resistance of the MOSFET 902 is higher than that of the MOSFET 901 of the first comparative example. Therefore, the on-resistance of the MOSFET 902 is higher than that of the MOSFET 901 of the first comparative example.

[0136] 20 is an explanatory diagram of the operation and effect of the semiconductor device of the first embodiment, and corresponds to FIG.

[0137] 20 shows a schematic diagram of a current flowing through the body region 52 in the on-state of the MOSFET 100. The current is indicated by an arrow.

[0138] The MOSFET 100 of the first embodiment has n + The MOSFET 100 of the first embodiment differs from the MOSFET 902 of the second comparative example in that it includes a lower source region 55 having a type I-type. The MOSFET 100 of the first embodiment includes the lower source region 55 between the contact region 54 and the body region 52. This reduces the resistance below the contact region 54, making it easier for a current to flow. As a result, there is almost no ineffective region in the body region 52 through which a current does not easily flow. This reduces the on-resistance of the MOSFET 100.

[0139] According to the MOSFET 100 of the first embodiment, it is possible to reduce both the switching loss and the on-resistance.

[0140] In the case of a MOSFET not including the lower source region 55, the larger the layout ratio (Wp / (Wn+Wp)) of the contact region 54 in the first direction, the larger the proportion of the ineffective region occupied by the body region 52, and the higher the channel resistance. Therefore, providing the lower source region 55 is effective especially when the layout ratio (Wp / (Wn+Wp)) of the contact region 54 in the first direction is large. In other words, the layout ratio (Wp / (Wn+Wp)) of the contact region 54 in the first direction is the ratio (Wp / (Wn+Wp)) of the width Wp of the contact region 54 in the first direction to the sum of the width Wn of the upper source region 53 in the first direction and the width Wp of the contact region 54 in the first direction.

[0141] From the above viewpoints, the arrangement ratio (Wp / (Wn+Wp)) of the contact regions 54 in the first direction is preferably 0.1 or more, more preferably 1 or more, and further preferably 10 or more.

[0142] From the viewpoint of reducing the electrical resistance of the lower source region 55 and reducing the on-resistance of the MOSFET 100, the n-type impurity concentration of the lower source region 55 is, for example, 1×10 19 cm -3 It is preferable that the value is 5×10 or more. 19 cm -3 More preferably, it is 1×10 20 cm -3 More preferably, it is equal to or greater than this.

[0143] From the viewpoint of reducing the electrical resistance in the vertical direction (third direction) of the lower source region 55 and reducing the on-resistance of the MOSFET 100, the width of the lower source region 55 in the third direction is preferably 0.6 μm or less.

[0144] From the viewpoint of reducing the electrical resistance in the lateral direction (first direction) of the lower source region 55 and reducing the on-resistance of the MOSFET 100, the width of the lower source region 55 in the third direction is preferably 0.2 μm or more.

[0145] The n-type impurity concentration of the lower source region 55 is preferably 0.1 to 10 times, more preferably 0.2 to 5 times, and further preferably 0.5 to 2 times, the n-type impurity concentration of the upper source region 53.

[0146] From the viewpoint of increasing the arrangement ratio of the upper source region 53 in the first direction and reducing the on-resistance, the arrangement ratio (Wp / (Wn+Wp)) of the contact region 54 in the first direction is preferably 50 or less, more preferably 5 or less, and even more preferably 2 or less.

[0147] As described above, according to the first embodiment, a MOSFET that can achieve both reduced switching loss and reduced on-resistance can be realized.

[0148] Second Embodiment The semiconductor device of the second embodiment differs from the semiconductor device of the first embodiment in that the first electrode contacts the side surface of the first trench and the side surface of the second trench. In the following, some of the contents that overlap with the first embodiment may be omitted.

[0149] 21 and 22 are schematic cross-sectional views of a semiconductor device according to a second embodiment. The semiconductor device according to the second embodiment is a trench-gate vertical MOSFET 200 using silicon carbide. The MOSFET 200 is an n-channel MOSFET that uses electrons as carriers.

[0150] Fig. 21 is a diagram corresponding to Fig. 1 of the first embodiment, and Fig. 22 is a diagram corresponding to Fig. 3 of the first embodiment.

[0151] The MOSFET 200 includes a silicon carbide layer 10, a first trench 11, a first gate electrode 12, a first gate insulating layer 13, a second trench 21, a second gate electrode 22, a second gate insulating layer 23, a source electrode 41 (first electrode), a drain electrode 42 (second electrode), and an interlayer insulating layer 43.

[0152] In the silicon carbide layer 10, n + 50, n-type drain region - a p-type drift region 51 (first silicon carbide region), a p-type body region 52 (second silicon carbide region), + an upper source region 53 (third silicon carbide region) of p + type contact region 54 (fourth silicon carbide region), + a first lower source region 55a (fifth silicon carbide region) of the n-type + a second lower source region 55b (sixth silicon carbide region) of type n + The third lower source region 55c, n + A fourth lower source region 55d of the type, and + A field relief region 56 of the mold is provided.

[0153] The source electrode 41 is provided on the front surface side of the silicon carbide layer 10. The source electrode 41 contacts the side surface of the first trench 11. The source electrode 41 contacts the upper source region 53 and the contact region 54 on the side surface of the first trench 11.

[0154] The source electrode 41 contacts the side surface of the second trench 21. The source electrode 41 contacts the upper source region 53 and the contact region 54 on the side surface of the second trench 21.

[0155] The source electrode 41 is in contact with the upper source region 53 and the contact region 54 on the surface of the silicon carbide layer 10 .

[0156] The MOSFET 200 of the second embodiment can be manufactured by the method for manufacturing the semiconductor device of the first embodiment, in which the buried insulating layer 75 filled in the trench 71 is etched so that a part of the side surface of the trench 71 is exposed before the source electrode 41 is formed.

[0157] According to the MOSFET 200 of the second embodiment, the contact resistance of the source electrode 41 is reduced compared to the MOSFET 100 of the first embodiment. Therefore, according to the MOSFET 200 of the second embodiment, the on-resistance can be reduced compared to the MOSFET 100.

[0158] (Modification) Fig. 23 is a schematic cross-sectional view of a semiconductor device according to a modification of the second embodiment, which corresponds to Fig. 21 of the second embodiment.

[0159] The MOSFET 201 of the modification differs from the MOSFET 200 of the second embodiment in that a part of the interlayer insulating layer 43 is located above the first face F1 of the silicon carbide layer 10.

[0160] As described above, according to the second embodiment and its modification, a MOSFET that can achieve both reduced switching loss and reduced on-resistance can be realized.

[0161] (Third embodiment) The inverter circuit and the drive device of the third embodiment are a drive device including the semiconductor device of the first embodiment.

[0162] 24 is a schematic diagram of a driving device of the third embodiment. The driving device 1000 includes a motor 140 and an inverter circuit 150.

[0163] The inverter circuit 150 is composed of three semiconductor modules 150a, 150b, and 150c, which use the MOSFET 100 of the first embodiment as a switching element. By connecting the three semiconductor modules 150a, 150b, and 150c in parallel, a three-phase inverter circuit 150 having three AC voltage output terminals U, V, and W is realized. The motor 140 is driven by the AC voltage output from the inverter circuit 150.

[0164] According to the third embodiment, the MOSFET 100 with improved characteristics is provided, and thus the characteristics of the inverter circuit 150 and the driving device 1000 are improved.

[0165] (Fourth embodiment) The vehicle of the fourth embodiment is a vehicle equipped with the semiconductor device of the first embodiment.

[0166] 25 is a schematic diagram of a vehicle according to the fourth embodiment. A vehicle 1100 according to the fourth embodiment is a railcar. The vehicle 1100 includes a motor 140 and an inverter circuit 150.

[0167] The inverter circuit 150 is composed of three semiconductor modules using the MOSFET 100 of the first embodiment as a switching element. By connecting the three semiconductor modules in parallel, a three-phase inverter circuit 150 having three AC voltage output terminals U, V, and W is realized. The AC voltage output from the inverter circuit 150 drives the motor 140. The wheels 90 of the vehicle 1100 are rotated by the motor 140.

[0168] According to the fourth embodiment, the vehicle 1100 is provided with the MOSFET 100 having improved characteristics, thereby improving the characteristics of the vehicle 1100.

[0169] Fifth embodiment The vehicle of the fifth embodiment is a vehicle equipped with the semiconductor device of the first embodiment.

[0170] 26 is a schematic diagram of a vehicle according to the fifth embodiment. The vehicle 1200 according to the fifth embodiment is an automobile. The vehicle 1200 includes a motor 140 and an inverter circuit 150.

[0171] The inverter circuit 150 is composed of three semiconductor modules using the MOSFET 100 of the first embodiment as a switching element. By connecting the three semiconductor modules in parallel, a three-phase inverter circuit 150 having three AC voltage output terminals U, V, and W is realized.

[0172] The motor 140 is driven by the AC voltage output from the inverter circuit 150. The motor 140 causes the wheels 90 of the vehicle 1200 to rotate.

[0173] According to the fifth embodiment, the vehicle 1200 is provided with the MOSFET 100 having improved characteristics, thereby improving the characteristics of the vehicle 1200.

[0174] Sixth embodiment The elevator of the sixth embodiment is an elevator including the semiconductor device of the first embodiment.

[0175] 27 is a schematic diagram of an elevator according to the sixth embodiment. The elevator 1300 according to the sixth embodiment includes a car 610, a counterweight 612, a wire rope 614, a hoist 616, a motor 140, and an inverter circuit 150.

[0176] The inverter circuit 150 is composed of three semiconductor modules using the MOSFET 100 of the first embodiment as a switching element. By connecting the three semiconductor modules in parallel, a three-phase inverter circuit 150 having three AC voltage output terminals U, V, and W is realized.

[0177] The motor 140 is driven by the AC voltage output from the inverter circuit 150. The motor 140 rotates the hoist 616, causing the car 610 to rise and fall.

[0178] According to the sixth embodiment, the elevator 1300 has improved characteristics by including the MOSFET 100 with improved characteristics.

[0179] In the above, the first and second embodiments have been described using an example of 4H—SiC as the crystal structure of silicon carbide, but the present disclosure can also be applied to silicon carbide with other crystal structures, such as 6H—SiC and 3C—SiC.

[0180] In the first and second embodiments, a MOSFET is used as an example of a semiconductor device, but the present disclosure may also be applied to an Insulated Gate Bipolar Transistor (IGBT). For example, an IGBT can be realized by replacing the region corresponding to the drain region 50 of the MOSFET 100 from n-type to p-type.

[0181] Furthermore, in the third to sixth embodiments, the semiconductor device of the first embodiment has been described as an example, but the semiconductor device of the second embodiment or a modified example thereof may also be applied.

[0182] In addition, in the third to sixth embodiments, the semiconductor device of the present disclosure has been described as being applied to vehicles and elevators, but the semiconductor device of the present disclosure can also be applied to, for example, a power conditioner of a solar power generation system.

[0183] Although some embodiments of the present disclosure have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. For example, components of one embodiment may be replaced or changed with components of another embodiment. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0184] 10 Silicon carbide layer 11 First Trench 12 First gate electrode 13 First gate insulating layer 21 Second Trench 22 Second gate electrode 23 Second gate insulating layer 41 source electrode (first electrode, electrode) 42 Drain electrode (second electrode) 43 Interlayer insulation layer 51 drift region (first silicon carbide region, first region) 52 body region (second silicon carbide region, second region) 53 upper source region (third silicon carbide region, third region) 54 contact region (fourth silicon carbide region, fourth region) 55 Lower source region (fifth region) 55a first lower source region (fifth silicon carbide region) 55b second lower source region (sixth silicon carbide region) 61 First mask material 61a First opening 62 Side wall 71 Trench 73 Gate Insulation Layer 74 Gate electrode 75 Buried insulating layer (insulating layer) 100 MOSFET (semiconductor device) 150 Inverter circuit 200 MOSFET (semiconductor device) 1000 Drive Unit 1100 vehicles 1200 vehicles 1300 Elevator F1 First Side F2 Second Face

Claims

1. a silicon carbide layer having a first surface parallel to a first direction and a second direction perpendicular to the first direction, and a second surface parallel to the first surface; a first trench provided in the silicon carbide layer, the first trench being provided on a side of the first surface of the silicon carbide layer and extending in the first direction; a first gate electrode disposed in the first trench; a first gate insulating layer provided between the first gate electrode and the silicon carbide layer; a second trench provided in the silicon carbide layer, on a side of the first surface of the silicon carbide layer, and extending in the first direction; a second gate electrode disposed in the second trench; a second gate insulating layer provided between the second gate electrode and the silicon carbide layer; an n-type first silicon carbide region provided in the silicon carbide layer, at least a portion of which is provided between the first trench and the second trench; a p-type second silicon carbide region provided in the silicon carbide layer, between the first trench and the second trench, and between the first silicon carbide region and the first surface; a plurality of n-type third silicon carbide regions and a plurality of p-type fourth silicon carbide regions provided in the silicon carbide layer, between the first trench and the second trench, between the second silicon carbide region and the first surface, and alternately arranged in the first direction; an n-type fifth silicon carbide region provided in the silicon carbide layer, between the first trench and the second trench, in contact with the first trench, between the second silicon carbide region and the third silicon carbide region and between the second silicon carbide region and the fourth silicon carbide region, and extending in the first direction; a sixth silicon carbide region of n-type provided in the silicon carbide layer, between the first trench and the second trench, in contact with the second trench, separated from the fifth silicon carbide region, provided between the second silicon carbide region and the third silicon carbide region and between the second silicon carbide region and the fourth silicon carbide region, and extending in the first direction; a first electrode provided on a side of the silicon carbide layer facing the first surface and in contact with the third silicon carbide region and the fourth silicon carbide region; a second electrode provided on a side of the silicon carbide layer facing the second surface; an interlayer insulating layer provided between the first gate electrode and the first electrode and between the second gate electrode and the first electrode; A semiconductor device comprising:

2. The semiconductor device according to claim 1 , wherein said third silicon carbide region and said fourth silicon carbide region contact said first trench and said second trench.

3. the fifth silicon carbide region is in contact with the third silicon carbide region and the fourth silicon carbide region; The semiconductor device according to claim 1 , wherein said sixth silicon carbide region contacts said third silicon carbide region and said fourth silicon carbide region.

4. The semiconductor device according to claim 1 , wherein said second silicon carbide region is provided between said fifth silicon carbide region and said sixth silicon carbide region.

5. 2 . The semiconductor device according to claim 1 , wherein a p-type impurity concentration of said fourth silicon carbide region is higher than a p-type impurity concentration of said second silicon carbide region.

6. 2 . The semiconductor device according to claim 1 , wherein an n-type impurity concentration of said fifth silicon carbide region and an n-type impurity concentration of said sixth silicon carbide region are 0.1 to 10 times an n-type impurity concentration of said third silicon carbide region.

7. 2. The semiconductor device according to claim 1, wherein a distance in a third direction perpendicular to the first surface from the first surface to the first gate electrode is greater than a distance in the third direction from the first surface to an interface between the fourth silicon carbide region and the fifth silicon carbide region.

8. The semiconductor device according to claim 1 , wherein said first electrode contacts a side surface of said first trench and a side surface of said second trench.

9. 2. The semiconductor device according to claim 1, wherein a ratio of a width in the first direction of said fourth silicon carbide region to a sum of a width in the first direction of said third silicon carbide region and a width in the first direction of said fourth silicon carbide region is 0.1 or more and 50 or less.

10. An inverter circuit comprising the semiconductor device according to claim 1.

11. A driving device comprising the semiconductor device according to claim 1.

12. A vehicle comprising the semiconductor device according to claim 1.

13. An elevator comprising the semiconductor device according to claim 1.

14. A silicon carbide layer having a first surface parallel to a first direction and a second direction perpendicular to the first direction, and a second surface parallel to the first surface, preparing a silicon carbide layer including: an n-type first region; a p-type second region provided between the first region and the first surface; and a plurality of n-type third regions and a plurality of p-type fourth regions provided between the second region and the first surface, alternately arranged in the first direction, and extending in the second direction; forming a first mask material having a first opening extending in the first direction on the silicon carbide layer; using the first mask material as a mask, ion-implanting an n-type impurity through the first opening to form an n-type fifth region that is deeper than the third region and the fourth region and shallower than the second region; forming a sidewall at the first opening; forming a trench penetrating the second region, the third region, the fourth region, and the fifth region using the first mask material and the sidewall as a mask; forming a gate insulating layer in the trench; A method of manufacturing a semiconductor device further comprising forming a gate electrode on the gate insulating layer in the trench.

15. The method for manufacturing a semiconductor device according to claim 14 , wherein an upper surface of the gate electrode is located within the trench.

16. After forming the gate electrode, filling the trench above the gate electrode with an insulating layer; Etching the insulating layer so as to expose at least a portion of a side surface of the trench; 15. The method for manufacturing a semiconductor device according to claim 14, further comprising forming an electrode on a side surface of said trench so as to contact said third region and said fourth region.

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