Semiconductor device

Abstract

To provide a semiconductor device capable of recording the amount of voltage change (dV / dt) over time when the voltage changes suddenly.SOLUTION: A semiconductor device includes: a main element that has a first semiconductor region, a first electrode, a second electrode, a first gate electrode, and a first insulating member located between the first gate electrode and the first semiconductor region, and in which a gate voltage of the first gate electrode controls a current flowing between the first electrode and the second electrode via the first semiconductor region; and a recording element electrically connected to the first electrode and recording a maximum value of a change amount dV / dt in voltage of the first electrode over time as analog data.SELECTED DRAWING: Figure 1A

Description

[Technical field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] For example, in power semiconductor devices, there is a demand for a function to predict degradation and life span due to use. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 6400545 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the embodiment of the present invention is to provide a semiconductor device capable of recording the amount of voltage change dV / dt with respect to time when the voltage changes suddenly. [Means for solving the problem]

[0005] According to an embodiment of the present invention, a semiconductor device has a first semiconductor region, a first electrode, a second electrode, a first gate electrode, and a first insulating member located between the first gate electrode and the first semiconductor region, and is provided with a main element in which a gate voltage of the first gate electrode controls a current flowing between the first electrode and the second electrode via the first semiconductor region, and a recording element electrically connected to the first electrode and recording a maximum value of a change in voltage of the first electrode over time, dV / dt, as analog data. [Brief description of the drawings]

[0006] [Figure 1A] 1 is a schematic diagram illustrating a configuration of a semiconductor device according to an embodiment; [Figure 1B] 1 is a schematic diagram illustrating a configuration of a semiconductor device according to an embodiment; [Diagram 2] 1 is a schematic diagram illustrating a configuration of a semiconductor device according to an embodiment; [Diagram 3] FIG. 2A is a schematic cross-sectional view of a main element of the embodiment, and FIG. 2B is a schematic cross-sectional view of a recording element of the embodiment. [Figure 4] FIG. 13 is a schematic diagram showing a configuration of a semiconductor device according to another embodiment. [Diagram 5] FIG. 2 is a schematic cross-sectional view of a main element and a recording element according to the embodiment. [Figure 6] FIG. 2 is a schematic perspective view of a main element according to the embodiment. [Figure 7] FIG. 2 is a schematic perspective view of a main element according to the embodiment. [Figure 8] FIG. 2 is a schematic cross-sectional view of a main element according to an embodiment. [Figure 9] 1A and 1B are schematic perspective views of a main element of an embodiment. [Figure 10] FIG. 2 is a schematic perspective view of a recording element according to the embodiment. [Figure 11] FIG. 2 is a schematic cross-sectional view of a recording element according to an embodiment. [Figure 12] FIG. 2 is a schematic cross-sectional view of a recording element according to an embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Each embodiment will be described below with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as those in reality. Even when the same part is shown, the dimensions and ratios of each part may be different depending on the drawing. Furthermore, the same reference numbers are used to refer to the same or similar elements.

[0008] 1A, 1B, and 2, the semiconductor device of the embodiment includes a main element 210 and a recording element 220. The main element 210 is, for example, a power semiconductor element that controls or converts power. The main element 210 has, for example, a vertical MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) structure.

[0009] As shown in Figure 3(a), the main element 210 has a first semiconductor region 211, a first electrode 221, a second electrode 222, and a first gate electrode 231, and the gate voltage of the first gate electrode 231 controls the current flowing between the first electrode 221 and the second electrode 222 via the first semiconductor region 211.

[0010] The main element 210 may further include a substrate 201. The first semiconductor region 211 is provided on the first surface 201A of the substrate 201. A direction parallel to the first surface 201A of the substrate 201 is defined as the X-axis direction. A direction parallel to the first surface 201A and perpendicular to the X-axis direction is defined as the Y-axis direction. A direction perpendicular to the X-axis direction and the Y-axis direction is defined as the Z-axis direction. For example, in the main element, the direction along the Y-axis is defined as the first direction Y, the direction along the X-axis is defined as the second direction X, and the direction along the Z-axis is defined as the third direction Z. In addition, in the third direction Z, the direction in which the arrow of the Z-axis points is defined as "upward" or "upper surface side".

[0011] The first semiconductor region 211 has a first semiconductor portion 211A of a first conductivity type provided on the first surface 201A of the substrate 201, a second semiconductor portion 211B of a second conductivity type provided on the first semiconductor portion 211A, and a third semiconductor portion 211C of the first conductivity type provided on the second semiconductor portion 211B. In this specification, for example, the first conductivity type is n-type and the second conductivity type is p-type. The first conductivity type may also be p-type and the second conductivity type may also be n-type.

[0012] The substrate 201 is, for example, n-type, and functions as a drain layer. The n-type impurity concentration of the substrate 201 is higher than the n-type impurity concentration of the first semiconductor portion 211A. The first semiconductor portion 211A functions as a drift layer. The second semiconductor portion 211B functions as a base layer. The third semiconductor portion 211C functions as a source layer. The n-type impurity concentration of the third semiconductor portion 211C is higher than the n-type impurity concentration of the first semiconductor portion 211A.

[0013] The main element 210 has, for example, a trench gate structure. On the upper surface side of the first semiconductor region 211, a plurality of first gate electrodes 231 are arranged in the second direction X. A side surface of the first gate electrode 231 faces the second semiconductor portion 211B. In one trench formed on the upper surface side of the first semiconductor region 211, for example, two first gate electrodes 231 are positioned apart from each other in the second direction X.

[0014] The first electrode 221 is provided on a second surface 201B located on the opposite side to the first surface 201A of the substrate 201. The first electrode 221 is electrically connected to the substrate (drain layer) 201. The first electrode 221 functions as a drain electrode.

[0015] The second electrode 222 is provided on the upper surface of the first semiconductor region 211 and is electrically connected to the third semiconductor portion 211C. The second electrode 222 functions as a source electrode. The second electrode 222 is in contact with the second semiconductor portion 211B.

[0016] The main element 210 may further include a first insulating member 241. The first insulating member 241 is provided between the two first gate electrodes 231 in one trench, between the first gate electrode 231 and the first semiconductor region 211, and between the first gate electrode 231 and the second electrode 222. In the first insulating member 241, a portion provided between the first gate electrode 231 and the second semiconductor portion 211B functions as a first gate insulating film. When a gate voltage equal to or higher than a threshold is applied to the first gate electrode 231, a channel (inversion layer) is formed in a portion of the second semiconductor portion 211B facing the first gate electrode 231. In the on state of the main element 210, a current flows between the first electrode 221 and the second electrode 222 via the substrate (drain layer) 201, the first semiconductor portion (drift layer) 211A, the channel, and the third semiconductor portion (source layer) 211C.

[0017] The main element 210 may further have a field plate electrode 251 provided below the first gate electrode 231. The first insulating member 241 is also provided between the field plate electrode 251 and the first semiconductor region 211, and between the field plate electrode 251 and the first gate electrode 231. For example, the potential (source potential) of the second electrode 222 is applied to the field plate electrode 251. The source potential is, for example, a ground potential. The field plate electrode 251 can reduce the electric field (vertical electric field) applied in the third direction Z, and can improve the withstand voltage.

[0018] The first electrode 221 of the main element 210 is electrically connected to a power supply 1000, and a voltage Vd is applied to the first electrode 221 from the power supply 1000. The second electrode 222 of the main element 210 is grounded. The first gate electrode 231 of the main element 210 is electrically connected to a gate driver 300, and a gate voltage Vg is applied to the first gate electrode 231 from the gate driver 300.

[0019] The recording element 220 has a vertical MOSFET structure similar to that of the main element 210. As shown in FIG. 3(b), the recording element 220 has a substrate 202, a second semiconductor region 212, a third electrode 223, a fourth electrode 224, and at least a pair of second gate electrodes 232. A direction parallel to the first surface 202A of the substrate 202 is defined as the X-axis direction. A direction parallel to the first surface 202A and perpendicular to the X-axis direction is defined as the Y-axis direction. A direction perpendicular to the X-axis direction and the Y-axis direction is defined as the Z-axis direction. In the recording element 220, a direction along the Y-axis is defined as the fourth direction Y, a direction along the X-axis is defined as the fifth direction X, and a direction along the Z-axis is defined as the sixth direction Z. The orientations of the main element 210 and the recording element 220 are independent of each other and do not necessarily match, but for simplicity, the following description will be given assuming that the X-axis direction, Y-axis direction, and Z-axis direction defined by the main element 210 match the X-axis direction, Y-axis direction, and Z-axis direction defined by the recording element 220.

[0020] The second semiconductor region 212 has a fourth semiconductor portion 212A of a first conductivity type provided on the first surface 202A of the substrate 202, a fifth semiconductor portion 212B of a second conductivity type provided on the fourth semiconductor portion 212A, and a sixth semiconductor portion 212C of the first conductivity type provided on the fifth semiconductor portion 212B.

[0021] The substrate 202 functions as a drain layer, similar to the main element 210. The n-type impurity concentration of the substrate 202 is higher than the n-type impurity concentration of the fourth semiconductor portion 212A. The fourth semiconductor portion 212A functions as a drift layer. The fifth semiconductor portion 212B functions as a base layer. The sixth semiconductor portion 212C functions as a source layer. The n-type impurity concentration of the sixth semiconductor portion 212C is higher than the n-type impurity concentration of the fourth semiconductor portion 212A.

[0022] At least a pair of second gate electrodes 232 are arranged side by side in the fifth direction X on the upper surface side of the second semiconductor region 212. Of the pair of second gate electrodes 232, a side surface of one second gate electrode 232 facing the other second gate electrode 232 and a side surface of the other second gate electrode 232 facing the one second gate electrode 232 each face the fifth semiconductor portion 212B.

[0023] The third electrode 223 is provided on a second surface 202B located opposite to the first surface 202A of the substrate 202. The third electrode 223 is electrically connected to the substrate (drain layer) 202, and functions as a drain electrode.

[0024] The fourth electrode 224 is provided on the upper surface of the second semiconductor region 212 and is electrically connected to the sixth semiconductor portion 212C. The fourth electrode 224 functions as a source electrode. The fourth electrode 224 is in contact with the fifth semiconductor portion 212B.

[0025] The recording element 220 can further include a second insulating member 244. The second insulating member 244 is provided between the second gate electrode 232 and the second semiconductor region 212, and between the second gate electrode 232 and the fourth electrode 224. In the second insulating member 244, a portion provided between the second gate electrode 232 and the fifth semiconductor portion 212B functions as a second gate insulating film.

[0026] The recording element 220 is electrically connected to the first electrode 221 of the main element 210, and records the maximum value of the amount of change dV / dt of the voltage of the first electrode 221 over time as analog data.

[0027] For example, the recording element 220 has a capacitor 502 that holds an amount of charge proportional to the dV / dt of the voltage of the first electrode 221. In the example shown in Fig. 3(b), the capacitor 502 has a pair of second gate electrodes 232 facing each other in the fifth direction X, and a part of the second semiconductor region 212 (a fifth semiconductor portion 212B) located between the pair of second gate electrodes 232.

[0028] When the capacitor 502 is charged with a charge corresponding to a gate voltage equal to or higher than a threshold value, a channel (inversion layer) is formed in a portion of the fifth semiconductor portion 212B facing the second gate electrode 232. When a voltage is applied between the third electrode 223 and the fourth electrode 224, the magnitude of the current flowing between the third electrode 223 and the fourth electrode 224 via the substrate (drain layer) 202, the fourth semiconductor portion (drift layer) 212A, the channel, and the sixth semiconductor portion (source layer) 212C changes depending on the amount of charge in the capacitor 502.

[0029] In the example shown in FIG. 1A, the recording element 220 is electrically connected to the first electrode 221 of the main element 210 via a differentiation circuit 400 and a peak hold circuit 500.

[0030] 1B, the differentiation circuit 400 is, for example, a CR circuit including a capacitor 401 and a resistor 402. The differentiation circuit 400 outputs the time differentiation (dV / dt) of the voltage of the first electrode 221.

[0031] The peak hold circuit 500 includes, for example, a first diode 501 and a capacitor 502. In the example shown in FIG. 1, the recording element 220 records the maximum value of the positive dV / dt when the main element 210 is turned on. In this case, the anode of the first diode 501 is connected to the differentiation circuit 400, and the cathode of the first diode 501 is connected to the capacitor 502. In addition, the cathode of the second diode 601 is connected between the cathode of the first diode 501 and the capacitor 502. The anode of the second diode 601 is connected to ground.

[0032] When the output dV / dt of the differentiation circuit 400, which is the input voltage to the peak hold circuit 500, is greater than the voltage charged to the capacitor 502 (the potential of the second gate electrode 232), a current flows in the forward direction through the first diode 501, charging the capacitor 502. When the input voltage to the peak hold circuit 500 (the output dV / dt of the differentiation circuit 400) becomes equal to the voltage charged to the capacitor 502, no current flows through the first diode 501. Therefore, the capacitor 502 holds the maximum value of dV / dt applied to the first electrode 221 of the main element 210 in an analog manner as an amount of charge.

[0033] When a voltage is applied between the third electrode 223 and the fourth electrode 224 of the recording element 220, the magnitude of the current (read current) flowing between the third electrode 223 and the fourth electrode 224 through the second semiconductor region 212 changes depending on the amount of charge held by the capacitor 502 (the potential of the second gate electrode 232). The amount of charge held by the capacitor 502 can be determined from the magnitude of this read current, and the maximum value of dV / dt applied to the first electrode 221 of the main element 210 can be determined from the amount of charge held by the capacitor 502. The maximum value of dV / dt makes it possible to predict the deterioration and lifespan of the main element 210 due to use. For example, the main element 210 can be replaced before its performance deteriorates due to its service life or before it breaks down.

[0034] The recording element 220 records the maximum value of dV / dt of the voltage of the first electrode 221 of the main element 210 as a continuously changing charge amount, i.e., analog data. Therefore, compared to the case where digital recording is performed using, for example, a CMOS circuit and a non-volatile counter, this embodiment does not require a large-scale configuration, and costs can be reduced.

[0035] A voltage needs to be applied to the third electrode 223 and the fourth electrode 224 of the recording element 220 independently of the first electrode 221 and the second electrode 222 of the main element 210. For this reason, for example, the main element 210 and the recording element 220 can be formed on a substrate of the same wafer or a different wafer by the same process, and then diced into individual chips. Alternatively, the main element 210 and the recording element 220 can be integrated into a single chip. In this case, the third electrode 223 and the fourth electrode 224 of the recording element 220 need to be electrically isolated from the first electrode 221 and the second electrode 222 of the main element 210.

[0036] 2 shows an example of a circuit in which the recording element 220 records the maximum value of negative dV / dt when the main element 210 is turned off. The orientations of the first diode 501 and the second diode 601 are opposite to those in the circuit of FIG. 1B. In the example of FIG. 2, the cathode of the first diode 501 is connected to the differentiation circuit 400, and the anode of the first diode 501 is connected to the capacitor 502. In addition, the anode of the second diode 601 is connected between the anode of the first diode 501 and the capacitor 502. The cathode of the second diode 601 is connected to ground.

[0037] As shown in FIG. 4, the semiconductor device may include a plurality of recording elements 220 whose electrical connection with the first electrode 221 of the main element 210 is switched in sequence.

[0038] Each of the recording elements 220 is connected to a corresponding peak hold circuit 500. Each of the peak hold circuits 500 is connected to the differentiation circuit 400 via a corresponding switching element 802. Each of the switching elements 802 is turned on and off by a Q output signal of a corresponding flip-flop 801. The flip-flops 801 form a ring counter, and the output of the final-stage flip-flop 801 is provided to the input of the first-stage flip-flop 801.

[0039] A rising edge of the gate voltage (gate signal) output by the gate driver 300 causes the flip-flop 801 to turn on the corresponding switching element 802, and the recording element 220 corresponding to the switching element 802 in the ON state is electrically connected to the differentiation circuit 400 and the peak hold circuit 500. The reset circuit 803 provides the gate potential of the recording element 220 to the D input of the first-stage flip-flop 801. The recording elements 220 connected to the differentiation circuit 400 are switched in sequence, so that it is possible to record the maximum value of dV / dt for several times immediately before the main element 210 breaks down, for example.

[0040] According to other examples of the main element and the recording element which will be described below with reference to FIGS. 5 to 11, the main element and the recording element having independent electrodes can be easily formed within the same chip.

[0041] As shown in Fig. 6, the main element 110 is provided on the support 100. As shown in Fig. 10, the recording element 120 is provided on the support 100. The support 100 has a first surface 100A. A first direction Y and a second direction X are parallel to the first surface 100A.

[0042] 6 to 9(b), the main element 110 will be described. In Fig. 7, the main element 110 is illustrated in a state in which the second conductive portion 22b and the second insulating member 42 have been removed.

[0043] The support 100 has a substrate 101. The substrate 101 extends in a first direction Y and a second direction X. For example, a silicon substrate can be used as the substrate 101. The main element 110 has a first semiconductor region 11 provided on the substrate 101 in the third direction Z. The support 100 may further have an insulating layer 102 provided between the substrate 101 and the first semiconductor region 11 in the third direction Z. In this example, the upper surface of the insulating layer 102 becomes the first surface 100A of the support 100. For example, a silicon oxide layer can be used as the insulating layer 102.

[0044] The conductivity type of the first semiconductor region 11 is a first conductivity type. The first conductivity type is one of n-type and p-type. Hereinafter, the first conductivity type is defined as n-type. The first semiconductor region 11 is, for example, a silicon layer. The first semiconductor region 11 may be a silicon carbide layer or a gallium nitride layer.

[0045] The main element 110 further includes a first electrode 21 and a second electrode 22. The first electrode 21 and the second electrode 22 are located apart from each other in the first direction Y. The first semiconductor region 11 is provided between the first electrode 21 and the second electrode 22 in the first direction Y, and is electrically connected to the first electrode 21 and the second electrode 22. The first electrode 21, the second electrode 22, and the first semiconductor region 11 extend in the third direction Z above the first surface 100A. With this configuration, the density of the main elements 110 on the first surface 100A of the support 100 can be increased, and for example, the on-resistance per unit area can be reduced.

[0046] The first electrode 21 may include, for example, at least one selected from the group consisting of Al, Cu, Mo, W, Ta, Co, Ru, Ti, and Pt.

[0047] The second electrode 22 has a first conductive portion 22a and a second conductive portion 22b. The first conductive portion 22a is in contact with the first semiconductor region 11. The first semiconductor region 11 and the first conductive portion 22a form a first Schottky junction S1. The first conductive portion 22a is located between the first semiconductor region 11 and the second conductive portion 22b in the first direction Y. The second conductive portion 22b is electrically connected to the first conductive portion 22a.

[0048] The first conductive portion 22a may include at least one selected from the group consisting of, for example, Ti, W, Mo, Ta, Zr, Al, Sn, V, Re, Os, Ir, Pt, Pd, Rh, Ru, Nb, Sr, and Hf. The second conductive portion 22b may include at least one selected from the group consisting of, for example, Al, Cu, Mo, W, Ta, Co, Ru, Ti, and Pt.

[0049] The main element 110 further includes a first gate electrode 31. A plurality of first gate electrodes 31 are arranged in the second direction X. The first gate electrode 31 faces the first Schottky junction S1 in the second direction X. For example, polycrystalline silicon can be used as the material of the first gate electrode 31. As shown in FIG. 7, the first gate electrode 31 extends in the third direction Z. With this configuration, transistors can be provided at a high density on the first surface 100A of the support 100, and the channel area per unit area can be increased. This can reduce, for example, the on-resistance.

[0050] A potential higher than the potential of the second electrode 22 is applied to the first electrode 21, and a potential lower than the potential of the first electrode 21 (for example, ground potential) is applied to the second electrode 22. The first electrode 21 functions as a drain electrode, and the second electrode 22 functions as a source electrode. Note that the n-type impurity concentration of the region in contact with the first electrode 21 in the first semiconductor region 11 may be made higher than the n-type impurity concentration of the other regions. This can reduce the contact resistance between the first electrode 21 and the first semiconductor region 11.

[0051] The thickness (distance in the first direction Y) of the Schottky barrier at the first Schottky junction S1 can be controlled by the potential of the first gate electrode 31. When the Schottky barrier is thick, substantially no current flows between the second electrode 22 and the first semiconductor region 11. This provides an off state. In the off state, a depletion layer spreads from the first Schottky junction S1 into the first semiconductor region 11, making it possible to maintain a breakdown voltage.

[0052] By controlling the potential of the first gate electrode 31, the Schottky barrier becomes thinner, and for example, a tunnel current flows between the second electrode 22 and the first semiconductor region 11. The flow of the tunnel current results in an on state.

[0053] The main element 110 may further include a field plate electrode 51, a first insulating member 41, and a second insulating member .

[0054] The field plate electrode 51 is provided in a trench formed in the first semiconductor region 11, and extends in the first direction Y and the third direction Z. The field plate electrode 51 is electrically connected to, for example, the second electrode 22. The field plate electrode 51 can reduce the electric field applied to the first semiconductor region 11 in the first direction Y, and can increase the breakdown voltage. The field plate electrode 51 can be made of, for example, polycrystalline silicon.

[0055] The first insulating member 41 is provided between the first gate electrode 31 and the first semiconductor region 11, between the field plate electrode 51 and the first semiconductor region 11, between the first gate electrode 31 and the field plate electrode 51, and between the first gate electrodes 31 adjacent to each other in the second direction X, and extends in the third direction Z. The first insulating member 41 has a first gate insulating portion 41a. The first gate insulating portion 41a is provided between the first gate electrode 31 and the first semiconductor region 11, between the first gate electrode 31 and the first Schottky junction S1, and between the first gate electrode 31 and the first conductive portion 22a. The first gate electrode 31 faces the first Schottky junction S1 in the second direction X via the first gate insulating portion 41a. For example, silicon oxide can be used as the material of the first insulating member 41.

[0056] The second insulating member 42 is provided between the first gate electrode 31 and the second conductive portion 22b and between the first insulating member 41 and the second conductive portion 22b, and extends in the third direction Z. The second insulating member 42 may be made of, for example, silicon oxide.

[0057] As shown in FIG. 9(a), the substrate 101 has a second surface 101B located on the opposite side of the first surface 100A in the third direction Z. A first wiring portion D electrically connected to the first electrode 21 is provided on the second surface 101B of the substrate 101. The first electrode 21 can be electrically connected to an external circuit via the first wiring portion D. In the third direction Z, a second wiring portion S can be provided above the first semiconductor region 11, above the first gate electrode 31, and above the field plate electrode 51 via an interlayer insulating layer. The second wiring portion S is electrically connected to the second conductive portion 22b of the second electrode 22. The second electrode 22 can be electrically connected to an external circuit via the second wiring portion S. A first gate wiring G1 extending in the second direction X is provided on the multiple first gate electrodes 31 aligned in the second direction X, and the multiple first gate electrodes 31 can be electrically connected to the first gate wiring G1.

[0058] 9(b), a second wiring portion S electrically connected to the second conductive portion 22b of the second electrode 22 may be provided on the second surface 101B of the substrate 101. In the third direction Z, a first wiring portion D electrically connected to the first electrode 21 can be provided above the first semiconductor region 11, above the first gate electrode 31, and above the field plate electrode 51 via an interlayer insulating layer.

[0059] 5, a plurality of cell groups (first to fourth cell groups 71 to 74) are provided in a region in which the main element 110 of the semiconductor device is provided. In the first direction Y, a second cell group 72 is provided between the first cell group 71 and the fourth cell group 74, and a third cell group 73 is provided between the second cell group 72 and the fourth cell group 74. In each cell group, the structures shown in FIGS. 6 to 8 described above are repeatedly arranged in the second direction X.

[0060] The direction from the first electrode 21 of the first cell group 71 to the second electrode 22 of the first cell group 71 is opposite to the direction from the first electrode 21 of the second cell group 72 to the second electrode 22 of the second cell group 72. The direction from the first electrode 21 of the third cell group 73 to the second electrode 22 of the third cell group 73 is opposite to the direction from the first electrode 21 of the fourth cell group 74 to the second electrode 22 of the fourth cell group 74. The direction from the first electrode 21 of the first cell group 71 to the second electrode 22 of the first cell group 71 is the same as the direction from the first electrode 21 of the third cell group 73 to the second electrode 22 of the third cell group 73. The direction from the first electrode 21 of the second cell group 72 to the second electrode 22 of the second cell group 72 is the same as the direction from the first electrode 21 of the fourth cell group 74 to the second electrode 22 of the fourth cell group 74.

[0061] The first electrode 21 is shared between the second cell group 72 and the third cell group 73. The second electrode 22 is shared between the first cell group 71 and the second cell group 72. The second electrode 22 is shared between the third cell group 73 and the fourth cell group 74.

[0062] The main element 110 may, for example, constitute a high-side switching element and a low-side switching element in a voltage converter.

[0063] Next, the recording element 120 will be described with reference to Figures 10 and 11. In this example, the recording element 120 is provided on the same substrate 101 as the main element 110, a fourth direction in the recording element 120 coincides with the first direction Y in the main element 110, a fifth direction in the recording element 120 coincides with the second direction X in the main element 110, and a sixth direction in the recording element 120 coincides with the third direction Z in the main element 110.

[0064] The recording element 120 has a second semiconductor region 12 provided on the substrate 101 in the third direction (sixth direction) Z. The conductivity type of the second semiconductor region 12 is the first conductivity type. The material of the second semiconductor region 12 can be the same as the material of the first semiconductor region 11 of the main element 110.

[0065] The recording element 120 further has a third electrode 23 and a fourth electrode 24. The third electrode 23 and the fourth electrode 24 are located apart from each other in the first direction (fourth direction) Y. The second semiconductor region 12 is provided between the third electrode 23 and the fourth electrode 24 in the first direction (fourth direction) Y, and is electrically connected to the third electrode 23 and the fourth electrode 24. The third electrode 23, the fourth electrode 24, and the second semiconductor region 12 extend in the third direction (sixth direction) Z above the first surface 100A of the support 100.

[0066] The fourth electrode 24 has a third conductive portion 24a and a fourth conductive portion 24b. The third conductive portion 24a is in contact with the second semiconductor region 12. The second semiconductor region 12 and the third conductive portion 24a form a second Schottky junction S2. The third conductive portion 24a is located between the second semiconductor region 12 and the fourth conductive portion 24b in the first direction (fourth direction) Y. The fourth conductive portion 24b is electrically connected to the third conductive portion 24a.

[0067] The material of the third electrode 23 may be the same as the material of the first electrode 21 of the main element 110. The material of the third conductive portion 24a may be the same as the material of the first conductive portion 22a of the main element 110. The material of the fourth conductive portion 24b may be the same as the material of the second conductive portion 22b of the main element 110.

[0068] The recording element 120 further includes a second gate electrode 32. The multiple second gate electrodes 32 are aligned in a second direction (fifth direction) X. The second gate electrode 32 faces the second Schottky junction S2 in the second direction (fifth direction) X. The second gate electrode 32 extends in a third direction (sixth direction) Z. The material of the second gate electrode 32 can be the same as that of the first gate electrode 31 of the main element 110.

[0069] The thickness (distance in the first direction (fourth direction) Y) of the Schottky barrier in the second Schottky junction S2 can be controlled by the potential of the second gate electrode 32. By controlling the potential of the second gate electrode 32, the Schottky barrier becomes thinner, and for example, a tunnel current flows between the fourth electrode 24 and the second semiconductor region 12. As a result, a current flows between the third electrode 23 and the fourth electrode 24 via the second semiconductor region 12.

[0070] The recording element 120 can further include a third insulating member 43 and a fourth insulating member 44.

[0071] The third insulating member 43 is provided between the second gate electrode 32 and the second semiconductor region 12, and extends in the third direction (sixth direction) Z. As shown in FIG. 11, the third insulating member 43 has a second gate insulating portion 43a. The second gate insulating portion 43a is provided between the second gate electrode 32 and the second semiconductor region 12, between the second gate electrode 32 and the second Schottky junction S2, and between the second gate electrode 32 and the third conductive portion 24a. The second gate electrode 32 faces the second Schottky junction S2 in the second direction (fifth direction) X via the second gate insulating portion 43a. The material of the third insulating member 43 can be the same as that of the first insulating member 41 of the main element 110.

[0072] The fourth insulating member 44 is provided between the second gate electrode 32 and the fourth conductive portion 24b and between the third insulating member 43 and the fourth conductive portion 24b, and extends in the third direction (sixth direction) Z. The material of the fourth insulating member 44 can be the same as that of the second insulating member 42 of the main element 110.

[0073] The semiconductor device of the embodiment can be constructed by replacing the main element 210 shown in Figures 1A, 1B, 2, and 4 with the main element 110 shown in Figures 5 to 9(b), and replacing the recording element 220 shown in Figures 1A, 1B, 2, and 4 with the recording element 120 shown in Figures 10 and 11.

[0074] That is, the first electrode 21 of the main element 110 is electrically connected to the power supply 1000, and a voltage Vd is applied to the first electrode 21 from the power supply 1000. The second electrode 22 of the main element 110 is grounded. The first gate electrode 31 of the main element 110 is electrically connected to the gate driver 300, and a gate voltage Vg is applied to the first gate electrode 31 from the gate driver 300.

[0075] When the output dV / dt of the differentiation circuit 400, which is the input voltage to the peak hold circuit 500, is greater than the voltage charged to the capacitor 502 (the potential of the second gate electrode 32), a current flows in the forward direction through the first diode 501, charging the capacitor 502. When the input voltage to the peak hold circuit 500 (the output dV / dt of the differentiation circuit 400) becomes equal to the voltage charged to the capacitor 502, no current flows through the first diode 501. Therefore, the capacitor 502 holds the maximum value of dV / dt applied to the first electrode 21 of the main element 110 in an analog manner as an amount of charge.

[0076] When a voltage is applied between the third electrode 23 and the fourth electrode 24 of the recording element 120, the magnitude of the current (read current) flowing between the third electrode 23 and the fourth electrode 24 through the second semiconductor region 12 changes depending on the amount of charge held by the capacitor 502 (the potential of the second gate electrode 32). The amount of charge held by the capacitor 502 can be determined from the magnitude of this read current, and the maximum value of dV / dt applied to the first electrode 21 of the main element 110 can be determined from the amount of charge held by the capacitor 502. The maximum value of dV / dt makes it possible to predict the deterioration and lifespan of the main element 110 that accompanies use. For example, the main element 210 can be replaced before its performance deteriorates due to its service life or before it breaks down.

[0077] In this example, the recording element 120 also records the maximum value of dV / dt of the voltage of the first electrode 221 of the main element 210 as a continuously changing charge amount, i.e., analog data, so that a large-scale configuration is not required and costs can be reduced.

[0078] According to the main element 110 and the recording element 120 shown in FIGS. 5 to 11, the main element 110 and the recording element 120 can be formed in the same process by simply changing the mask patterns for film formation and etching for forming each component of the main element 110 and the recording element 120 between the main element 110 and the recording element 120. For example, the first semiconductor region 11 and the second semiconductor region 12 can be formed on the same substrate 101, and the main element 110 and the recording element 120 can be configured as a single chip. This allows a power semiconductor device with the recording element 120 built in to be integrated into a single chip at low cost. When the main element 110 and the recording element 120 are integrated into a single chip, it is possible to reduce the parasitic inductance of the wiring electrically connecting the main element 110 and the recording element 120.

[0079] The semiconductor device may incorporate a plurality of recording elements 120. A fifth insulating member 60 may be provided between the main element 110 and the recording element 120 on the substrate 101, as shown in Fig. 5. The fifth insulating member 60 may also be provided between the plurality of recording elements 120. The fifth insulating member 60 may be made of, for example, silicon oxide.

[0080] Alternatively, the first semiconductor region 11 and the second semiconductor region 12 may be formed on the same substrate 101, and then the chip of the main element 110 and the chip of the recording element 120 may be separated. In this case, the chip of the main element 110 and the chip of the recording element 120 may be mounted on the same wiring substrate and packaged. In this case, the wiring substrate may be included as a support for supporting the main element 110 and the recording element 120.

[0081] The third electrode 23 of the recording element 120 can be electrically connected to an external circuit via a third wiring portion provided above the second semiconductor region 12 in the third direction (sixth direction) Z. The fourth electrode 24 can be electrically connected to an external circuit via a fourth wiring portion provided above the second semiconductor region 12 in the third direction (sixth direction) Z. The second gate electrode 32 can be electrically connected to a second gate wiring G2 provided on the second gate electrode 32 and extending in the second direction (fifth direction) X.

[0082] The third electrode 23 and the fourth electrode 24 of the recording element 120 are preferably located on the first surface 100A, and not on the second surface 101B. This makes it possible to suppress leakage current between the first wiring portion D or the second wiring portion S of the main element 110 on the second surface 101B of the substrate 101 and the main electrodes (the third electrode 23 and the fourth electrode 24) of the recording element 120.

[0083] The voltage applied between the first electrode 21 and the second electrode 22 of the main element 110 is higher than the voltage applied between the third electrode 23 and the fourth electrode 24 of the recording element 120. For example, the voltage applied between the first electrode 21 and the second electrode 22 of the main element 110 is 100 V or more, and the voltage applied between the third electrode 23 and the fourth electrode 24 of the recording element 120 is about several V. Therefore, in order to increase the withstand voltage of the main element 110, it is preferable that the thickness of the first semiconductor region 11 of the main element 110 in the first direction Y is thicker than the thickness of the second semiconductor region 12 of the recording element 120 in the first direction (fourth direction) Y.

[0084] 12, for example, a resistance change memory can be used as the recording element 700. The recording element 700 has a resistance change layer 703 whose resistance changes with the charge supplied from the gate driver every time the main element is turned on.

[0085] The resistance change layer 703 is provided between the fifth electrode 701 and the sixth electrode 702 in the third direction Z. The sixth electrode 702 has a first portion 702A and a second portion 702B. The second portion 702B is provided between the first portion 702A and the resistance change layer 703. The fifth electrode 701 extends in the second direction X, and the first portion 702A of the sixth electrode 702 extends in the first direction Y. The second portion 702B and the resistance change layer 703 are provided in a columnar shape at the intersection of the fifth electrode 701 and the first portion 702A of the sixth electrode 702. The side surfaces of the sixth electrode 702, the side surfaces of the resistance change layer 703, and the top surface of the fifth electrode 701 are covered with an insulating member 704.

[0086] The fifth electrode 701 and the first portion 702A of the sixth electrode 702 may be made of, for example, titanium nitride. The second portion 702B of the sixth electrode 702 may be made of, for example, titanium. The resistance change layer 703 may be made of, for example, silicon oxide. The insulating member 704 may be made of, for example, silicon nitride.

[0087] The voltage dV / dt of the first electrode of the main element is applied to the fifth electrode 701 and the sixth electrode 702. The resistance of the variable resistance layer 703 continuously increases (or decreases) according to the dV / dt. When a dV / dt larger than the previously applied dV / dt is applied to the fifth electrode 701 and the sixth electrode 702, the resistance of the variable resistance layer 703 increases (or decreases). When a dV / dt equal to or smaller than the previously applied dV / dt is applied to the fifth electrode 701 and the sixth electrode 702, the resistance of the variable resistance layer 703 does not change. Therefore, the variable resistance layer 703 can hold the maximum value of dV / dt.

[0088] When a voltage is applied between the fifth electrode 701 and the sixth electrode 702 when reading out the resistance of the variable resistance layer 703, the magnitude of the current (read current) flowing between the fifth electrode 701 and the sixth electrode 702 changes depending on the resistance of the variable resistance layer 703. The resistance of the variable resistance layer 703 can be determined from the magnitude of this read current, and the maximum value of dV / dt applied to the first electrode of the main element can be determined from the resistance of the variable resistance layer 703.

[0089] In the recording element 700, the maximum value of the dV / dt of the voltage of the first electrode of the main element is recorded as the continuously changing resistance of the resistance change layer 703, i.e., as analog data, so that a large-scale configuration is not required and costs can be reduced.

[0090] The recording element 700 can be formed, for example, on the main element 110 shown in FIGS. 5 to 9(b) via an interlayer insulating layer, and the main element 110 and the recording element 700 can be integrated into one chip.

[0091] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0092] 11...first semiconductor region, 12...second semiconductor region, 21...first electrode, 22...second electrode, 23...third electrode, 24...fourth electrode, 31...first gate electrode, 32...second gate electrode, 100...support, 101...substrate, 110...main element, 120...recording element, 201...substrate, 210...main element, 211...first semiconductor region, 212...second semiconductor region, 220...recording element, 221...first electrode electrode, 222...second electrode, 223...third electrode, 224...fourth electrode, 231...first gate electrode, 232...second gate electrode, 300...gate driver, 400...differential circuit, 500...peak hold circuit, 502...capacitor, 700...recording element, 701...fifth electrode, 702...sixth electrode, 703...resistance change layer, S1...first Schottky junction, S2...second Schottky junction

Claims

1. a main element including a first semiconductor region, a first electrode, a second electrode, a first gate electrode, and a first insulating member located between the first gate electrode and the first semiconductor region, wherein a current flowing between the first electrode and the second electrode via the first semiconductor region is controlled by a gate voltage of the first gate electrode; a recording element electrically connected to the first electrode, the recording element configured to record a maximum value of a change amount dV / dt of a voltage of the first electrode with respect to time as analog data; A semiconductor device comprising:

2. 2. The semiconductor device according to claim 1, wherein the recording element has a capacitor that holds the maximum value of dV / dt as a charge.

3. 3. The semiconductor device according to claim 2, wherein the recording element has a second semiconductor region, a third electrode, a fourth electrode, a second gate electrode, and a second insulating member located between the second gate electrode and the second semiconductor region.

4. 4. The semiconductor device according to claim 1, wherein the recording element records a maximum value of the dV / dt when the main element is turned on.

5. 4. The semiconductor device according to claim 1, wherein the recording element records a maximum value of the dV / dt when the main element is turned off.

6. 4. The semiconductor device according to claim 1, further comprising a plurality of the recording elements, the electrical connection of which to the first electrode is switched in sequence.

7. a support having a first surface and supporting the main element and the recording element; the first electrode and the second electrode of the main element are spaced apart from each other in a first direction along the first surface, the first semiconductor region of the main element is provided between the first electrode and the second electrode in the first direction and forms a first Schottky junction with the second electrode; the first gate electrode of the main element faces the first Schottky junction in a second direction intersecting the first direction along the first surface; the third electrode and the fourth electrode of the recording element are positioned apart from each other in a fourth direction along the first surface, the second semiconductor region of the recording element is provided between the third electrode and the fourth electrode in the fourth direction and forms a second Schottky junction with the fourth electrode; 4 . The semiconductor device according to claim 3 , wherein the second gate electrode of the recording element faces the second Schottky junction in a fifth direction that intersects with the fourth direction along the first surface.

8. The support has a substrate, The semiconductor device according to claim 7 , wherein the first semiconductor region and the second semiconductor region are provided on the same substrate.

9. the substrate has a second surface located on an opposite side to the first surface in a third direction intersecting the first direction and the second direction; The semiconductor device according to claim 8 , wherein the third electrode and the fourth electrode of the recording element are located on the first surface and not on the second surface.

10. The semiconductor device according to claim 1 , wherein the recording element has a resistance change layer whose resistance changes in response to the dV / dt.

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