Electronic circuit

Abstract

To maintain an input voltage with high precision.SOLUTION: An electronic circuit includes a sample-and-hold circuit 1 which is composed of a switch circuit for holding the voltage of an input terminal Vin in synchronization with a clock signal φS, a capacitive element, and an output buffer circuit having a zero calibration function which uses the terminal of the capacitive element as an input and adjusts its own input offset voltage to zero, and a clock generation circuit 4 which outputs a clock signal CLK for zero calibration only at specific timing to cause the output buffer circuit 2a to perform the zero calibration operation.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to an electronic circuit including a sample and hold circuit. [Background technology]

[0002] When performing signal processing, it is common to use a buffer circuit consisting of an operational amplifier circuit to perform impedance conversion before A / D conversion of the output voltage of a circuit with high output impedance. Ideally, a buffer circuit should output a voltage equal to the input voltage. However, an operational amplifier circuit has an offset voltage at its input, and this offset voltage causes an error in the output voltage.

[0003] There are circuit methods in operational amplifier circuits that reduce offset voltages by performing self-calibration operations. These configurations are generally known as auto-zero amplifiers and chopper-stabilized amplifiers. These configurations are useful when you want to perform A / D conversion with high precision (see Non-Patent Document 1 and Patent Document 1).

[0004] A sample-and-hold circuit can be considered as an example of a circuit that performs impedance conversion. As shown in Figure 7, the sample-and-hold circuit 1 is composed of a switch SW1 and a capacitor C1 for holding a voltage. In the configuration shown in Figure 7, the output voltage of the output buffer circuit 2 follows the voltage of the input terminal Vin while the switch SW1 is conducting. Since a charge is held in the capacitor C1, when the switch SW1 is opened, the voltage at the moment when the switch SW1 is opened continues to be output.

[0005] When performing impedance conversion on the voltage of a terminal with high output impedance, such as a capacitive terminal inside a sample-and-hold circuit, if a self-calibrating op-amp circuit is used as an output buffer circuit, the following problems arise.

[0006] The calibration operation of an op-amp circuit, whether it is an auto-zero amplifier or a chopper-stabilized amplifier, involves switching the connection of the input terminal in the internal circuit. At this time, clock feedthrough from the switch element inside the op-amp circuit and charging and discharging of electric charge to the gate terminal of the input MOS transistor occur, causing a momentary input and output of current inside the amplifier, resulting in a voltage error at the input terminal of the op-amp circuit (the output terminal of the sample-and-hold circuit).

[0007] One example of the problem is when a self-calibrating op-amp circuit is used as the output buffer circuit 2 connected to the capacitance terminal of the sample-and-hold circuit 1 shown in Figure 7. When momentary current input / output occurs due to the calibration operation of the op-amp circuit, the charge stored in the voltage holding capacitance C1 leaks, causing an error in the held voltage. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] Special Publication No. 2009-517895 [Non-patent literature]

[0009] [Non-Patent Document 1] Reza Moghimi, “Chopper or Auto-Zero, That is the Question”, Analog Devices, Inc., 2011, <https: / / www.analog.com / jp / technical-articles / to-chop-or-auto-zero-that-is-the-question.html> Summary of the Invention [Problem to be solved by the invention]

[0010] The present invention has been made in order to solve the above-mentioned problems, and has an object to provide an electronic circuit capable of maintaining an input voltage with high precision. [Means for solving the problem]

[0011] The electronic circuit of the present invention is characterized by comprising: a sample-and-hold circuit including a switch circuit for holding the voltage of an input terminal in synchronization with a first clock signal, a capacitive element, and an output buffer circuit having a zero calibration function for adjusting its own input offset voltage to zero using the terminal of the capacitive element as an input; and a clock generation circuit configured to output a second clock signal for zero calibration only at a specific timing, thereby causing the output buffer circuit to perform a zero calibration operation. Moreover, one configuration example of the electronic circuit of the present invention is characterized in that it further includes an A / D converter configured to perform A / D conversion of an output signal of the sample-and-hold circuit, and the clock generation circuit outputs the second clock signal to the output buffer circuit only when the A / D converter performs A / D conversion. Moreover, one configuration example of the electronic circuit of the present invention is characterized in that the sample-and-hold circuit and the A / D converter are integrated in the same IC. In one configuration example of the electronic circuit of the present invention, the output buffer circuit is an auto-zero amplifier or a chopper stabilized amplifier. Effect of the Invention

[0012] According to the present invention, by providing a clock generation circuit that outputs a second clock signal for zero calibration only at a specific timing and causes the output buffer circuit to perform zero calibration operation, it is possible to minimize the charge error in the capacitance of the sample and hold circuit that occurs due to zero calibration, and it becomes possible for the sample and hold circuit to hold the input voltage with high precision. [Brief description of the drawings]

[0013] [Figure 1] FIG. 1 is a block diagram showing a configuration of an electronic circuit according to an embodiment of the present invention. [Diagram 2] FIG. 2 is a timing chart illustrating the operation of the electronic circuit according to the embodiment of the present invention. [Diagram 3] FIG. 3 is a block diagram showing a configuration example of an auto-zero amplifier. [Figure 4] Figure 4 is a timing chart illustrating the operation of the auto-zero amplifier. [Diagram 5] FIG. 5 is a block diagram showing a configuration example of a chopper stabilized amplifier. [Figure 6] FIG. 6 is a circuit diagram showing the configuration of a differential input / differential output type sample-and-hold circuit. [Figure 7] FIG. 7 is a block diagram showing the configuration of a conventional sample-and-hold circuit. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. Fig. 1 is a block diagram showing the configuration of an electronic circuit according to an embodiment of the present invention. The electronic circuit of this embodiment includes a sample-and-hold circuit 1, an output buffer circuit 2a, an A / D converter 3, and a clock generation circuit 4.

[0015] The sample-and-hold circuit 1 holds the voltage of the input terminal Vin in synchronization with the clock signal φS. As in the conventional circuit, the sample-and-hold circuit 1 is composed of a switch SW1 provided between the input terminal Vin and the output terminal Vout, and a capacitor C1 with one end connected to the output terminal Vout and the other end connected to ground.

[0016] The output buffer circuit 2a is composed of an operational amplifier circuit equipped with a zero calibration function. Although the output buffer circuit 2a is depicted as being external to the sample-and-hold circuit 1 in FIG. 1, the output buffer circuit 2a is included in the sample-and-hold circuit 1. An example of the configuration of the output buffer circuit 2a will be described later. The A / D converter 3 performs A / D conversion on the output signal of the output buffer circuit 2a. The clock generating circuit 4 supplies clock signals φS and CLK to the sample-and-hold circuit 1 and the output buffer circuit 2 a, respectively, and supplies an enable signal φC to the A / D converter 3 .

[0017] 2 is a timing chart explaining the operation of the electronic circuit of this embodiment. First, the switch SW1 of the sample-and-hold circuit 1 is turned on when the clock signal φS is at a high level (sample mode). This causes the voltage of the output terminal Vout of the sample-and-hold circuit 1 to follow the voltage of the input terminal Vin.

[0018] Next, the switch SW1 turns off when the clock signal φS is at a low level (hold mode). The sample-and-hold circuit 1 continues to output the voltage of the input terminal Vin immediately before the switch SW1 turns off from on until the switch SW1 turns on again.

[0019] The clock generation circuit 4 sets the enable signal φC to high level at the timing when the sample and hold circuit 1 enters the hold mode. This enables the operation of the A / D converter 3, and the A / D converter 3 samples the output voltage of the output buffer circuit 2a in synchronization with a clock signal (not shown) supplied from the clock generation circuit 4 and converts it into a digital signal. The clock generation circuit 4 returns the enable signal φC to low level at a predetermined timing, stopping the operation of the A / D converter 3.

[0020] Also, the clock generation circuit 4 outputs the clock signal CLK for zero calibration to the output buffer circuit 2a only when the enable signal φC is at a high level (a specific timing, during A / D conversion in this embodiment). In this way, in this embodiment, the clock signal CLK for zero calibration, which adjusts the offset voltage generated at the input of the output buffer circuit 2a to zero, is output only during A / D conversion, so that the zero calibration operation of the output buffer circuit 2a is stopped at timing other than during A / D conversion, thereby minimizing the charge error of the capacitance C1 of the sample-and-hold circuit 1 caused by the zero calibration. Since the voltage error when the sample-and-hold circuit 1 and the zero calibration operation are combined is proportional to the integrated value of the current input / output during zero calibration, the error is reduced by minimizing the number of zero calibration operations.

[0021] Next, a specific example of the output buffer circuit 2a will be described. FIG. 3 is a block diagram showing a configuration example of an auto-zero amplifier, which is an example of the output buffer circuit 2a. The auto-zero amplifier has a non-inverting input terminal connected to the positive phase input terminal Vi of the auto-zero amplifier. + The inverting input terminal is connected to the negative input terminal Vi of the auto-zero amplifier. - The main (wideband) amplifier A1 is a differential input single-phase output type amplifier with its output terminal connected to the output terminal Vo of the auto-zero amplifier, and its inverting input terminal is the negative phase input terminal Vi of the auto-zero amplifier. -a capacitor C2 having one end connected to the offset adjustment input terminal VNB of the main amplifier A1 and the other end connected to ground, a capacitor C3 having one end connected to the offset adjustment input terminal VNA of the zero adjustment amplifier A2 and the other end connected to ground, a switch SW2 provided between the non-inverting input terminal and the inverting input terminal of the zero adjustment amplifier A2, a switch SW3 provided between the non-inverting input terminal of the main amplifier A1 and the non-inverting input terminal of the zero adjustment amplifier A2, a switch SW4 provided between the output terminal of the zero adjustment amplifier A2 and the offset adjustment input terminal VNA, and a switch SW5 provided between the output terminal of the zero adjustment amplifier A2 and the offset adjustment input terminal VNB of the main amplifier A1.

[0022] The auto-zero amplifier operates in two phases (φA and φB in FIG. 4) per clock cycle. In the clock phase φA of the clock signal CLK supplied from the clock generation circuit 4, the switches SW2 and SW4 are on and the switches SW3 and SW5 are off. This causes the input terminal Vi + ,Vi - The input signal from is supplied only to the main amplifier A1. The main amplifier A1 operates in the same manner as a normal operational amplifier. The voltage stored in the capacitor C2 is applied to the offset adjustment input terminal VNB of the main amplifier A1.

[0023] When switch SW2 is on, the non-inverting input terminal and the inverting input terminal of the zero adjustment amplifier A2 are shorted, so that an output voltage according to the offset voltage of the zero adjustment amplifier A2 itself is generated at the output terminal of the zero adjustment amplifier A2, and this voltage is fed back to the zero adjustment amplifier A2 itself, canceling the offset voltage of the zero adjustment amplifier A2. This offset voltage is held in the capacitor C3 and is held even when the phase is switched.

[0024] Next, at clock phase φB of the clock signal CLK, the switches SW3 and SW5 are turned on and the switches SW2 and SW4 are turned off. At clock phase φB, the zero adjustment amplifier A2 amplifies a signal including the offset voltage of the main amplifier A1. The output voltage of the zero adjustment amplifier A2 is supplied to the offset adjustment input terminal VNB of the main amplifier A1, and the offset of the main amplifier A1 is cancelled. The output voltage of the zero adjustment amplifier A2 is held in the capacitor C2 and is held even when the phase is switched.

[0025] The main amplifier A1 and the zero adjustment amplifier A2 are both operational amplifiers with adjustable offsets. The input / output relationship of the main amplifier A1 is expressed by equation (1). Vo = α(Vi + -Vi - ) + βVNB (1)

[0026] α is the differential gain, and β is the trim gain. The input / output relationship of the zero adjustment amplifier A2 is the same as that of the main amplifier A1. In this way, by repeating the two phases, low offset and low temperature drift of the main amplifier A1 are achieved.

[0027] 5 is a block diagram showing a configuration example of a chopper stabilized amplifier, which is another example of the output buffer circuit 2a. + ,Vi - The system is equipped with a modulation circuit MOD1 that converts the input signal from the modulator 1 into an AC signal, a differential input / differential output amplifier A3 whose input is the output of the modulation circuit MOD1, a demodulation circuit DEM1 that converts the output signal of the amplifier A1 back into a DC signal, and a differential input / single-phase output low-pass filter F1 whose input is the output of the demodulation circuit DEM1.

[0028] The modulation circuit MOD1 is connected to the positive input terminal Vi of the chopper stabilized amplifier. + and the non-inverting input terminal of amplifier A3, and the negative-phase input terminal Vi of the chopper-stabilized amplifier. -and the inverting input terminal of the amplifier A3. + and the inverting input terminal of the amplifier A3. - and a switch SW9 provided between the inverting input terminal of the amplifier A3.

[0029] The demodulation circuit DEM1 is composed of a switch SW10 provided between the non-inverting output terminal of the amplifier A3 and the non-inverting input terminal of the low-pass filter F1, a switch SW11 provided between the inverting output terminal of the amplifier A3 and the inverting input terminal of the low-pass filter F1, a switch SW12 provided between the non-inverting output terminal of the amplifier A3 and the inverting input terminal of the low-pass filter F1, and a switch SW13 provided between the inverting output terminal of the amplifier A3 and the non-inverting input terminal of the low-pass filter F1.

[0030] When the clock signal CLK supplied from the clock generation circuit 4 is at a low level, the switches SW6, SW7, SW10, and SW11 are turned on, and the switches SW8, SW9, SW12, and SW13 are turned off. On the other hand, when the clock signal CLK is at a high level, the switches SW8, SW9, SW12, and SW13 are turned on, and the switches SW6, SW7, SW10, and SW11 are turned off. As a result, the modulation circuit MOD1 has a configuration in which the input terminal Vi + ,Vi - The demodulation circuit DEM1 converts the input signal from the amplifier A1 back into an AC signal.

[0031] The input offset voltage of the amplifier A3 does not pass through the modulation circuit MOD1, so it is converted to an AC signal by the demodulation circuit DEM1. Therefore, among the amplification results of the amplifier A3, only the information of the input offset voltage that has been converted to an AC signal is removed by the low-pass filter F1.

[0032] The configuration of the output buffer circuit 2a shown in FIGS. 3 and 5 is just one example, and the present invention is not limited to the configurations shown in FIGS. The sample-and-hold circuits 1, 1-1, and 1-2, the output buffer circuit 2a, and the A / D converter 3 described in this embodiment may be integrated into the same IC (Integrated Circuit). The clock generation circuit 4 may be provided inside or outside the IC. [Industrial Applicability]

[0033] The present invention can be applied to electronic circuits. [Explanation of symbols]

[0034] 1, 1-1, 1-2... sample and hold circuit, 2a... output buffer circuit, 3... A / D converter, 4... clock generation circuit, A1 to A3... amplifiers, C1, C1-1, C1-2, C2 to C3... capacitors, SW1, SW1-1, SW1-2, SW2 to SW13... switches, MOD1... modulation circuit, DEM1... demodulation circuit.

Claims

1. a sample-and-hold circuit including a switch circuit for holding a voltage of an input terminal in synchronization with a first clock signal, a capacitance element, and an output buffer circuit having a zero calibration function for adjusting its own input offset voltage to zero using a terminal of the capacitance element as an input; and a clock generating circuit configured to output a second clock signal for zero calibration only at a specific timing to cause the output buffer circuit to perform a zero calibration operation.

2. 2. The electronic circuit of claim 1, an A / D converter configured to perform A / D conversion of an output signal of the sample and hold circuit; The electronic circuit, wherein the clock generating circuit outputs the second clock signal to the output buffer circuit only when the A / D converter is performing A / D conversion.

3. 3. The electronic circuit of claim 2, 2. An electronic circuit comprising: a sample-and-hold circuit and an A / D converter integrated into a single IC;

4. 2. The electronic circuit of claim 1, 11. The electronic circuit according to claim 10, wherein the output buffer circuit is an auto-zero amplifier or a chopper stabilized amplifier.

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