Electronic apparatus

Abstract

To provide an electronic apparatus capable of maintaining communication quality required in an interface.SOLUTION: An electronic apparatus includes a first port and a second port. A first receiving circuit receives data through the first port. A first transmitting circuit transmits data via the first port. A second receiving circuit receives data through the second port. A second transmitting circuit transmits data via the second port. When the first receiving circuit and the first transmitting circuit transition from a first state conforming to a first specification to a second state conforming to a second specification, a first control circuit acquires a first adjustment value related to at least one of set values applied to a third transmitting circuit of a host connected to the first port. When the second receiving circuit and the second transmitting circuit transition from the first state to the second state, a second control circuit determines a second adjustment value, which is at least one of the set values applied to a fourth transmitting circuit of the host connected to the second port, based on the first adjustment value.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present embodiment relates to an electronic device. [Background technology]

[0002] Interfaces for connecting electronic devices, such as PCIe (Peripheral Component Interconnect-Express) (registered trademark), are known. The electronic devices are, for example, hosts and memory systems. In such interfaces, it is required to reduce the bit error rate (BER) in communication between the electronic devices and to maintain the communication quality required in the interface. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2021-197583 [Patent Document 2] U.S. Patent Registration No. 11467909 [Patent Document 3] US Patent Publication No. 2014 / 0269881 [Patent Document 4] U.S. Patent Publication No. 2019 / 0114281 Summary of the Invention [Problem to be solved by the invention]

[0004] An embodiment of the present invention provides an electronic device capable of maintaining a required communication quality in an interface. [Means for solving the problem]

[0005] The electronic device according to the present embodiment includes a first port, a second port, a first receiving circuit, a first transmitting circuit, a first control circuit, a second receiving circuit, a second transmitting circuit, and a second control circuit. The first receiving circuit receives data from an external host via the first port. The first transmitting circuit transmits data to the host via the first port. The first control circuit controls the first receiving circuit and the first transmitting circuit. The second receiving circuit receives data from the host via the second port. The second transmitting circuit transmits data to the host via the second port. The second control circuit controls the second receiving circuit and the second transmitting circuit. When the first receiving circuit and the first transmitting circuit transition from a first state in which communication with the host is performed at a first communication speed conforming to a first specification to a second state in which communication with the host is performed at a second communication speed conforming to a second specification and different from the first communication speed, the first control circuit acquires a first adjustment value for at least one of the setting values ​​applied to a third transmitting circuit of the host connected to the first port. When the second receiving circuit and the second transmitting circuit transition from the first state to the second state, the second control circuit determines a second adjustment value for at least one of the setting values ​​to be applied to the fourth transmitting circuit of the host connected to the second port based on the first adjustment value transmitted from the first control circuit. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is a diagram showing an example of the configuration of an information processing system according to an embodiment of the present invention. [Diagram 2] FIG. 2 is a diagram showing an example of the configuration of a physical layer of the electronic device according to the embodiment. [Diagram 3] 11 is a table showing examples of TxEQ values ​​according to the present embodiment. [Figure 4] 5A to 5C are diagrams showing an example of the operation of the electronic device according to the embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the specification and the drawings, the same elements are denoted by the same reference numerals.

[0008] FIG. 1 is a diagram showing an example of the configuration of an information processing system according to this embodiment.

[0009] The information processing system 100 includes a memory system 1 and a host 2. The memory system 1 and the host 2 are communicatively connected via an interface 3. The configuration and operation of the memory system 1 will be described below as an example of an electronic device according to this embodiment. The configuration and operation of the electronic device according to this embodiment can also be applied to the host 2.

[0010] The memory system 1 is, for example, a solid state drive (SSD). The memory system 1 transmits data to the outside via the interface 3. The memory system 1 also receives data from the outside via the interface 3.

[0011] The host 2 is, for example, a server or a PC (personal computer). The host 2 transmits data to the memory system 1 via the interface 3. The host 2 also receives data from the memory system 1 via the interface 3.

[0012] The interface 3 is, for example, a serial interface that complies with the PCIe specification. The interface 3 includes a link (serial link) that connects between devices. The link includes a plurality of lanes. Each lane includes a differential signal line pair (Tx+, Tx-) for transmission from the memory system 1 to the host 2 (for reception by the host 2) and a differential signal line pair (Rx+, Rx-) for transmission from the host 2 to the memory system 2 (for reception by the memory system 1).

[0013] The host 2 includes a processor 21 and a communication controller 22 .

[0014] The processor 21 is, for example, an arithmetic processing device. The processor 21 controls each component of the host 2 including the communication controller 22.

[0015] The communication controller 22 is, for example, a processing unit. The communication controller 22 is, for example, configured by a system-on-a-chip (SoC). The communication controller 22 controls communication with the memory system 1. The communication controller 22 includes a transaction layer 41, a data link layer 42, and a physical layer 43.

[0016] The physical layer 43 includes a physical (PHY) sub-block 43a and a media access control (MAC) sub-block 43b.

[0017] The memory system 1 includes a controller 11 and a nonvolatile memory 12. The controller 11 is, for example, configured as an SoC. The nonvolatile memory 12 is, for example, a NAND type flash memory.

[0018] The controller 11 receives a command from the host 2, and writes the data received from the host 2 to the nonvolatile memory 12. Alternatively, the controller 11 receives a command from the host 2, and reads the data from the nonvolatile memory 12. In other words, the controller 11 controls the nonvolatile memory 12 based on the command received from the host 2.

[0019] The controller 11 includes a communication controller 30. The communication controller 30 controls communication with the host 2 via the interface 3. The communication controller 30 includes a transaction layer 31, a data link layer 32, and a physical layer 33. The physical layer 33 also includes a physical (PHY) sub-block 33a and a media access control (MAC) sub-block 33b.

[0020] The transaction layers 31 and 41 construct and process transaction layer packets (TLPs). A TLP is a packet that is sent to or received from a peer transaction layer. The peer transaction layer of the transaction layer 31 is the transaction layer 41 of the host 2. The peer transaction layer of the transaction layer 41 is the transaction layer 31 of the memory system 1.

[0021] The Data Link Layer 32 is an intermediate layer between the Transaction Layer 31 and the Physical Layer 33. The Data Link Layer 42 is an intermediate layer between the Transaction Layer 41 and the Physical Layer 43. The Data Link Layers 32, 42 manage the links included in the interface 3 and construct and process Data Link Layer Packets (DLLPs). DLLPs are packets sent to or received from the Data Link Layer of the communication partner. The Data Link Layer of the communication partner of the Data Link Layer 32 is the Data Link Layer 42 of the host 2. The Data Link Layer of the communication partner of the Data Link Layer 42 is the Data Link Layer 32 of the memory system 1.

[0022] The physical layer 33 physically transmits and receives data via multiple lanes included in the link. The configuration of the physical layer 33 will be described in detail later.

[0023] The transaction layers 31, 41 and the data link layers 32, 42 each include an Rx circuit as a receiving circuit and a Tx circuit as a transmitting circuit. The Rx circuit receives data received by the physical layer 33 or 43. The Tx circuit transmits data to be transmitted from the physical layer 33 or 43. When the interface 3 includes multiple links, the number of Tx circuits and Rx circuits provided is equal to the number of links.

[0024] Here, the link equalization performed at a communication speed (8 Gbps) compliant with the third generation PCIe specification (Gen3) and at a communication speed (16 Gbps) compliant with the fourth generation PCIe specification (Gen4) will be described.

[0025] The optimal output waveform of data transmitted by the physical layers 33 and 43 may vary depending on the combination of three elements: the transmission path established between the communication partner, specifically, the partner device, the cable (and / or wiring pattern), and the own device. Furthermore, the optimal output waveform may differ between the output waveform of data transmitted from the partner device to the own device and the output waveform of data transmitted from the own device to the partner device. Link equalization involves adjustment of these output waveforms and adjustment of the equalizer on the receiving side. Link equalization is also called training or tuning. In Gen3 and Gen4, when the receiving characteristics are BER (Bit Error Rate) < 10 -12 must be met.

[0026] Link equalization consists of three phases: Phase 1 to Phase 3.

[0027] Phase 1: Each of the memory system 1 and the host 2 notifies the other device of its own capabilities (FS [Full Swing], LF [Low Frequency]). In Phase 1, the reception characteristics are BER<10 -4 must be met.

[0028] Phase 2: The reception characteristics of memory system 1 are BER<10 -12 The output waveform of the host 2 is adjusted so as to satisfy the above. In Phase 2, the memory system 1 takes the lead in the process.

[0029] Phase 3: Host 2's receiving characteristics are BER<10 -12 The output waveform of the memory system 1 is adjusted so as to satisfy the above. In Phase 3, the host 2 takes the lead in the process.

[0030] That is, the memory system 1 needs to control the output waveform of the host 2 in Phase 2 in order to improve the BER of the own device.

[0031] When the host 2 and the memory system 1 start communication compliant with Gen4, the host 2 and the memory system 1 work cooperatively to perform link equalization in the following order: a communication speed compliant with the first generation PCIe specification (Gen1), a communication speed compliant with Gen3, and a communication speed compliant with Gen4.

[0032] FIG. 2 is a diagram showing an example of the configuration of the physical layer 33 of the memory system 1 according to the present embodiment.

[0033] The memory system 1 includes a port P0 and a port P1. The port P0 and the port P1 each include a physical layer 33. The port P0 and the port P1 are each connected to a host 2 independently.

[0034] The physical layer 33 of the port P1 includes a PHY sub-block 33a_1 and a MAC sub-block 33b_1.

[0035] The PHY sub-block 33a_1 of the port P1 includes a receive equalization (RxEQ) circuit 51_1, an RxEQ controller 52_1, a CDR (Clock Data Recovery) circuit 53_1, and a SIPO (Serial-In / Parallel-Out) circuit 54_1.

[0036] Moreover, the MAC sub-block 33b_1 of the port P1 includes a receive data controller 55_1, an ordered set (OS) detector 56_1, a link training status state machine (LTSSM) 57_1, a host transmit equalization (HostTxEQ) controller 58_1, and an OS generator 59_1.

[0037] The RxEQ circuit 51_1 is a circuit that receives a signal from the host 2 via a differential signal line pair (Rx+, Rx-) for reception of the memory system 1. The RxEQ circuit 51_1 includes an equalizer 511_1. The equalizer 511_1 is a circuit that adjusts (optimizes) the quality of a signal (received signal) received by the RxEQ circuit 51_1.

[0038] The RxEQ controller 52_1 controls the RxEQ circuit 51_1. The RxEQ controller 52_1 also outputs an RxEQ code value to the physical layer 33 of the port P0. The RxEQ code value indicates a setting of the equalizer 511_1 for optimizing the quality of a signal received by the RxEQ circuit 51_1 in Gen3 or Gen4. The RxEQ code value is, for example, a setting value of a CTLE (Continuous Time Linear Equalizer) or a setting value of a DFE (Decision feedback Equalizer).

[0039] The CDR circuit 53_1 generates a clock from the signal received by the RxEQ circuit 51_1. The CDR circuit 53_1 detects 0 or 1 of the received signal at the cycle of the generated clock. As a result, the CDR circuit 53_1 converts the signal received by the RxEQ circuit 51_1 from an analog signal to a digital signal. The CDR circuit 53_1 transmits the converted digital signal to the SIPO circuit 54_1 as serial data.

[0040] The SIPO circuit 54_1 converts the received serial data into parallel data, and transmits the converted parallel data to the reception data controller 55_1.

[0041] The OS detector 56_1 detects an ordered set from the data received via the received data controller 55_1. When the OS detector 56_1 detects an ordered set, it outputs symbol information indicating the type of the ordered set. The ordered set is a message that can be transmitted and received between physical layers.

[0042] The LTSSM 57_1 makes a state transition based on the symbol information received from the OS detector 56_1. The LTSSM 57_1 also outputs state information of the port P1 to the reception data controller 55_1. The state information indicates, for example, a link equalization phase (Phase 1 to Phase 3) and a communication speed (Gen 1 to Gen 4).

[0043] The reception data controller 55_1 masks the data received from the SIPO circuit 54_1 when the state information of the port P1 is Recovery.RcvrLock of Gen3 or Gen4, or Recovery.Equalization.Phase0 / 1 of Gen3. That is, when the state information of the port P1 is as described above, the reception data controller 55_1 does not transmit the received data to the OS detector 56_1.

[0044] Recovery.RcvrLock is a period during which, in the Recovery state, an ordered set having a predetermined pattern is transmitted and received between the physical layer 33 of port P1 and the host 2. Recovery.Equalization.Phase0 / 1 is a period during which, in the Recovery state, the physical layer 33 of port P1 is executing Phase 0 or Phase 1 of link equalization.

[0045] When the standby time has elapsed, the reception data controller 55_1 unmasks the data received from the SIPO circuit 54_1 and transmits the received data to the OS detector 56_1.

[0046] The LTSSM57_1 stores the TxEQ value of the host 2 in a register or internal memory. The TxEQ value is a setting value related to the output waveform of data, and will be described later with reference to FIG. 3. When Phase 2 of the link equalization of Gen3 or Gen4 is completed, the LTSSM57_1 holds the TxEQ value of the host 2 optimized for Gen3 or Gen4 (hereinafter referred to as Opt_TxEQ_g3h or Opt_TxEQ_g4h). The state information of the LTSSM57_1 and the TxEQ value of the host 2 (Opt_TxEQ_g3h or Opt_TxEQ_g4h) are output to the physical layer 33 of the port P0.

[0047] The HostTxEQ controller 58_1 determines the initial value of the TxEQ value of the host 2 used in Phase 2 of Gen3 or Gen4 (hereinafter referred to as Ini_TxEQ_g3p2h or Ini_TxEQ_g4p2h). The HostTxEQ controller 58_1 receives the RxEQ code value of the port P0 from the RxEQ controller 52_0 of the port P0. The HostTxEQ controller 58_1 also receives the state information and the TxEQ value (Opt_TxEQ_g3h or Opt_TxEQ_g4h) of the port P0 from the LTSSM 57_0 of the port P0.

[0048] The HostTxEQ controller 58_1 holds a TxEQ parameter table used to obtain Ini_TxEQ_g3p2h or Ini_TxEQ_g4p2h. The HostTxEQ controller 58_1 stores this table, for example, in a register or an internal memory. The HostTxEQ controller 58_1 obtains the initial value (Ini_TxEQ_g3p2h, Ini_TxEQ_g4p2h) of the TxEQ value of the host 2 in Phase 2 of Gen3 or Gen4 of the port P1 from this table based on the TxEQ value (Opt_TxEQ_g3h, Opt_TxEQ_g4h) of the host 2 adjusted (optimized) in Gen3 or Gen4 of the port P0. The TxEQ parameter table will be described later with reference to FIG. 3.

[0049] The OS generator 59_1 generates various ordered sets. The OS generator 59_1 transmits the generated ordered sets to the host 2 via a differential signal pair (Tx+, Tx−) for transmission from the memory system 1 to the host 2.

[0050] The physical layer 33 of the port P0 includes a PHY sub-block 33a_0 and a MAC sub-block 33b_0.

[0051] The PHY sub-block 33a_0 of the port P0 includes an RxEQ circuit 51_0, an RxEQ controller 52_0, a CDR circuit 53_0, and a SIPO circuit 54_0. The configurations of the RxEQ circuit 51_0, the RxEQ controller 52_0, the CDR circuit 53_0, and the SIPO circuit 54_0 are the same as those of the RxEQ circuit 51_1, the RxEQ controller 52_1, the CDR circuit 53_1, and the SIPO circuit 54_1, respectively.

[0052] Moreover, the MAC sub-block 33b_0 of the port P0 includes a receive data controller 55_0, an OS detector 56_0, an LTSSM 57_0, a HostTxEQ controller 58_0, and an OS generator 59_0. The receive data controller 55_0, the OS detector 56_0, the LTSSM 57_0, the HostTxEQ controller 58_0, and the OS generator 59_0 have the same configurations as the receive data controller 55_1, the OS detector 56_1, the LTSSM 57_1, the HostTxEQ controller 58_1, and the OS generator 59_1, respectively.

[0053] FIG. 3 is a table showing an example of the TxEQ value of the host 2 in Phase 2 of Gen3 or Gen4 according to this embodiment. In the table of FIG. 3, each setting (TxEQ value) of the TxEQ of the host 2 includes three parameters, namely, De-emphasis (DE), Pre-Shoot1 (PS1), and BOOST. DE, PS1, and BOOST are parameters related to the voltage ratio of the TxEQ of the host 2. 42 TxEQ values ​​are displayed in FIG. 3. The output waveform of the host 2 is changed by setting the parameters DE, PS1, and BOOST. In this embodiment, the TxEQ values ​​are divided into three groups GP1 to GP3 depending on the characteristics of the output waveform. TxEQ values ​​having similar characteristics of the output waveform are classified into the same group. For example, the BOOST of the TxEQ values ​​belonging to group GP1 is 2.5 dB or less. The BOOST of the TxEQ values ​​belonging to group GP2 is greater than 2.5 dB and less than 6.0 dB. The BOOST of the TxEQ values ​​belonging to group GP3 is greater than 6.0 dB. The TxEQ values ​​may be classified into groups based on DE or PS1. The number of groups into which the TxEQ values ​​are divided is not limited to three. The TxEQ values ​​may be classified so that one TxEQ value belongs to multiple groups. The HostTxEQ controller 58_1 may hold multiple TxEQ parameter tables with different groupings.

[0054] The memory system 1 requests the host 2 to apply the TxEQ value selected from the TxEQ parameter table in Phase 2 of Gen3 or Gen4. The memory system 1 causes the host 2 to change the TxEQ value so that the reception characteristics of the memory system 1 become BER<10 -12 The optimal TxEQ value (Opt_TxEQ_g3h or Opt_TxEQ_g4h) for host 2 that satisfies the above is obtained.

[0055] Next, the operation of the memory system 1 according to this embodiment will be described.

[0056] FIG. 4 is a diagram showing an example of the operation of the memory system 1 according to the present embodiment.

[0057] (Gen1) The host 2 transmits the ordered set EQ_TS2 to the port P0 and the port P1 of the memory system 1 at a communication speed conforming to Gen1 (a10, a11). The ordered set EQ_TS2 is an ordered set that specifies the initial value Ini_TxEQ_g3d of the TxEQ value of the memory system 1 in Gen3.

[0058] The physical layer 33 of the port P0 and the port P1 receives the ordered set EQ_TS2. The physical layer 33 of the port P0 and the port P1 sets the initial value of the TxEQ value of the memory system 1 in Gen3 to Ini_TxEQ_g3d.

[0059] (Gen3:Phase0) The physical layer 33 of the port P0 and the port P1 adjusts the characteristics of the equalizer on the receiving side so as to satisfy the receiving characteristics required in Phase 1 according to the receiving state of the ordered set EQ_TS2 while the TxEQ value of the host 2 is unknown (a220, a221). The period for optimizing the characteristics of the equalizer on the receiving side is also called the RxEQ period.

[0060] (Gen3:Phase1) In preparation for receiving data transmitted from the memory system 1 based on the specified initial value Ini_TxEQ_g3d of the TxEQ value, the host 2 adjusts the characteristics of the equalizer on the receiving side to satisfy the reception characteristics required in Phase 1 (a210, a211).

[0061] In Phase 1, the physical layer 33 of the host 2 and the port P0 of the memory system 1 notify each other of their own capabilities to the other device (a20). In Phase 1, the physical layer 33 of the host 2 and the port P1 of the memory system 1 also notify each other of their own capabilities to the other device (a21). After notifying the other device of its own capabilities, the physical layer 33 of the port P1 waits until the wait time STB1 has elapsed.

[0062] (Gen3:Phase2) When Phase 1 is completed, Phase 2 is executed at port P0 under the initiative of the memory system 1. The memory system 1 (more specifically, the physical layer 33 of port P0) selects, for example, one of the settings S0 to S9 of the TxEQ value described with reference to Fig. 3 as an initial value Ini_TxEQ_g3p2h. The memory system 1 requests the host 2 to apply the selected TxEQ value to communication with port P0 (a30).

[0063] The host 2 applies the TxEQ value requested by the memory system 1 to communication with port P0. The host 2 transmits an ordered set to notify port P0 of the memory system 1 of the applied TxEQ value (a40). The memory system 1 can confirm that the requested TxEQ value for port P0 has been applied by the host 2 based on the received ordered set.

[0064] The memory system 1 adjusts the characteristics of the equalizer 511_0 of the port P0 (a230).

[0065] The memory system 1 repeats a30, a40, and a230 for multiple TxEQ values. The upper limit of the period during which the TxEQ value of the host 2 can be adjusted in Phase 2 is determined. Therefore, the number of times a30, a40, and a230 are executed for various TxEQ values ​​of the host 2 is limited. Therefore, the number of settings of the TxEQ value applied to the host 2 is limited. For example, the settings of the TxEQ value applied to the host 2 are limited to the settings S0 to S9 belonging to multiple groups GP1 to GP3 shown in FIG. 3. Hereinafter, the application of a certain TxEQ value by the memory system 1 to the host 2 and adjustment of the characteristics of the equalizers 511_0 and 511_1 of the port P0 or P1 is also referred to as "sweeping".

[0066] The memory system 1 determines the TxEQ value that obtains the highest signal quality (e.g., the smallest BER) among the multiple TxEQ values ​​for the port P0 as the optimum value Opt_TxEQ_g3h0. The memory system 1 requests the host 2 to apply the optimum value Opt_TxEQ_g3h0 as the TxEQ value for the port P0 (a50). For example, it is assumed that the highest signal quality is obtained in the setting S8 among the TxEQ value settings S0 to S9 in FIG. 3. In this case, the memory system 1 determines the setting S8 as the optimum value Opt_TxEQ_g3h0. Then, the memory system 1 requests the host 2 to apply the setting S8 to the port P0.

[0067] The host 2 applies the optimum value Opt_TxEQ_g3h0 requested by the memory system 1 to the TxEQ value for the port P0. The host 2 transmits an ordered set for notifying the applied optimum value Opt_TxEQ_g3h0 to the port P0 of the memory system 1 (a60).

[0068] The physical layer 33 of the port P0 receives the ordered set for notifying the optimum value Opt_TxEQ_g3h0. The physical layer 33 of the port P0 holds the received ordered set. This ordered set indicates the optimum value Opt_TxEQ_g3h0 of the TxEQ value of the host 2.

[0069] When the physical layer 33 (more specifically, LTSSM 57_0) of port P0 sets the TxEQ value of host 2 to the optimum value Opt_TxEQ_g3h0, it transmits state information STp0 indicating that Phase 2 of Gen3 has been completed (i.e., indicating that the optimum value Opt_TxEQ_g3h0 has been acquired) to the physical layer 33 of port P1 (a65). In addition, the physical layer 33 of port P0 transmits the optimum value Opt_TxEQ_g3h0 of the TxEQ value of host 2 and the RxEQ code value of the RxEQ circuit 51_0 at this time to port P1.

[0070] When the standby time STB1 has elapsed, the physical layer 33 of the port P1 transitions from Phase 1 (standby state) to Phase 2. Phase 2 in the port P1 is also executed under the initiative of the memory system 1.

[0071] When the physical layer 33 of the port P1 has received the state information STp0, it selects an initial value (Ini_TxEQ_g3p2h) of the TxEQ value of the host 2 in Phase 2 of the port P1 based on the optimum value Opt_TxEQ_g3h0 of the TxEQ value of the host 2 determined in the port P0. The physical layer 33 of the port P1 selects an initial value of the TxEQ value in Phase 2 of the port P1 from the group to which the optimum value Opt_TxEQ_g3h0 in the port P0 belongs, for example, among the groups GP1 to GP3 shown in FIG. 3. For example, when the optimum value Opt_TxEQ_g3h0 is S8, the physical layer 33 of the port P1 selects an initial value of the TxEQ value in Phase 2 of the port P1 from the group GP2. The physical layer 33 of the port P1 requests the host 2 to apply the selected initial value to the communication with the port P1 (a31). If the physical layer 33 of the port P1 does not receive the state information STp0 from the port P0 by the waiting time STB1, the physical layer 33 of the port P1 selects a predetermined value as the initial value of the TxEQ value in Phase 2 of the port P1. In this case, the physical layer 33 of the port P1 may sweep the TxEQ parameter table without identifying the groups GP1 to GP3.

[0072] The physical layer 33 of the port P1 may select an initial value of the TxEQ value in Phase 2 of the port P1 further depending on the RxEQ code value received from the port P0. For example, the physical layer 33 of the port P1 may determine which of a plurality of TxEQ parameter tables held by the HostTxEQ controller 58_1 to use depending on the RxEQ code value. Alternatively, the physical layer 33 of the port P1 may select an initial value of the TxEQ value in Phase 2 from a group different from the group to which the optimal value Opt_TxEQ_g3h0 belongs depending on the RxEQ code value. For example, when the set value of CTLE or DFE is the maximum value or the minimum value in the settable range, the initial value of the TxEQ value in Phase 2 may be selected from a group different from the group to which the optimal value Opt_TxEQ_g3h0 belongs.

[0073] The host 2 applies the TxEQ value requested by the memory system 1 to communication with port P1. The host 2 transmits an ordered set to notify port P1 of the memory system 1 of the applied TxEQ value (a41). The memory system 1 can confirm that the requested TxEQ value for port P1 has been applied by the host 2 based on the received ordered set.

[0074] The memory system 1 adjusts the characteristics of the equalizer 511_1 of the port P1 (a231).

[0075] The memory system 1 repeats a31, a41, and a231 for multiple TxEQ values ​​in the group to which the optimal value Opt_TxEQ_g3h0 for port P0 belongs among groups GP1 to GP3. For example, if the optimal value Opt_TxEQ_g3h0 belongs to group GP2, the memory system 1 executes a31, a41, and a231 for multiple TxEQ values ​​in group GP2. That is, the memory system 1 repeats the sweep for multiple TxEQ values ​​in group GP2.

[0076] As described above, the upper limit of the period during which the TxEQ value of the host 2 can be adjusted in Phase 2 is determined. However, the TxEQ value applied to the host 2 for port P1 is limited to the TxEQ value of group GP2. Therefore, the memory system 1 can repeatedly perform a sweep on port P1 for multiple TxEQ values ​​similar to the optimal value Opt_TxEQ_g3h0 of the TxEQ value for port P0. As a result, it is highly likely that a TxEQ value that can obtain high signal quality even for port P1 can be found within the limited adjustment period.

[0077] The memory system 1 determines the TxEQ value that provides the highest signal quality among the multiple TxEQ values ​​in the group GP2 for the port P1 as the optimum value Opt_TxEQ_g3h1. The memory system 1 requests the host 2 to apply the optimum value Opt_TxEQ_g3h1 as the TxEQ value for the port P1 (a51).

[0078] The host 2 applies the optimum value Opt_TxEQ_g3h1 requested by the memory system 1 to the TxEQ value for the port P1. The host 2 transmits an ordered set for notifying the applied optimum value Opt_TxEQ_g3h1 to the port P1 of the memory system 1 (a61).

[0079] The physical layer 33 of the port P1 receives the ordered set for notifying the optimum value Opt_TxEQ_g3h1. The physical layer 33 of the port P1 holds the received ordered set. This ordered set indicates the optimum value Opt_TxEQ_g3h1 of the TxEQ value of the host 2.

[0080] The memory system 1 completes Phase 2 on the port P1.

[0081] (Gen3:Phase3) When Phase 2 is completed in port P0, Phase 3 in port P0 is executed under the initiative of the host 2. The host 2 selects one of the TxEQ value settings in the memory system 1. The host 2 requests port P0 of the memory system 1 to apply the selected TxEQ value (a70).

[0082] The memory system 1 applies to the port P0 the TxEQ value requested by the host 2. The memory system 1 transmits an ordered set to notify the host 2 of the applied TxEQ value (a80).

[0083] The host 2 adjusts the characteristics of the equalizer on the receiving side of the physical layer 43 connected to the port P0 of the memory system 1 (a240).

[0084] Host 2 repeats a70, a80 and a240 for multiple TxEQ values.

[0085] The host 2 determines the TxEQ value that provides the highest signal quality among the multiple TxEQ values ​​for the port P0 as the optimum value Opt_TxEQ_g3d0. The host 2 requests the memory system 1 to apply the optimum value Opt_TxEQ_g3d0 as the TxEQ value for the port P0 (a90).

[0086] The memory system 1 applies the optimum value Opt_TxEQ_g3d0 requested by the host 2 to the TxEQ value of the port P0. The memory system 1 transmits an ordered set for notifying the host 2 of the applied optimum value Opt_TxEQ_g3d0 (a100).

[0087] This completes link equalization for port P0 at a communication speed compliant with Gen3.

[0088] Furthermore, when Phase 2 is completed in port P1, Phase 3 in port P1 is executed under the initiative of host 2. Host 2 selects one of the settings of the TxEQ value in memory system 1. Host 2 requests port P1 of memory system 1 to apply the selected TxEQ value (a71).

[0089] The memory system 1 applies to the port P1 the TxEQ value requested by the host 2. The memory system 1 transmits an ordered set to notify the host 2 of the applied TxEQ value (a81).

[0090] The host 2 adjusts the characteristics of the equalizer on the receiving side of the physical layer 43 connected to the port P1 of the memory system 1 (a241).

[0091] Host 2 repeats a71, a81 and a241 for multiple TxEQ values.

[0092] The host 2 determines the TxEQ value that provides the highest signal quality among the multiple TxEQ values ​​for the port P1 as the optimum value Opt_TxEQ_g3d1. The host 2 requests the memory system 1 to apply the optimum value Opt_TxEQ_g3d1 as the TxEQ value for the port P1 (a91).

[0093] The memory system 1 applies the optimum value Opt_TxEQ_g3d1 requested by the host 2 to the TxEQ value of the port P1. The memory system 1 transmits an ordered set for notifying the host 2 of the applied optimum value Opt_TxEQ_g3d1 (a101).

[0094] This completes link equalization at a communication speed compliant with Gen3 for port P1 as well.

[0095] When the Gen3 link equalization is completed, the host 2 and the memory system 1 perform link equalization at a communication speed conforming to Gen4.

[0096] The host 2 transmits the ordered set EQ_TS2 to the port P0 and the port P1 of the memory system 1 at a communication speed conforming to Gen3 (a110, a111). The ordered set EQ_TS2 is an ordered set that specifies an initial value Ini_TxEQ_g4d of the TxEQ value of the memory system 1 in Gen4. Note that, around the timing of a110 or a111, the physical layer 33 of the port P0 and the port P1 may transmit the ordered set EQ_TS2 that specifies an initial value Ini_TxEQ_g4p1h of the TxEQ value of the host 2 in Phase 1 of Gen4. If an optimum value (Opt_TxEQ_g4h0) described later has already been obtained in the port P0, the physical layer 33 of the port P1 may select the initial value Ini_TxEQ_g4p1h based on the optimum value Opt_TxEQ_g4h0.

[0097] (Gen4:Phase0) The physical layer 33 of the port P0 and the port P1 adjusts the characteristics of the equalizer on the receiving side according to the reception state of the ordered set EQ_TS2 so as to satisfy the reception characteristics required in Phase 1 (a260, a261).

[0098] (Gen4:Phase1) In preparation for receiving data transmitted from the memory system 1 based on the specified initial value Ini_TxEQ_g4d of TxEQ, the host 2 adjusts the characteristics of the equalizer on the receiving side to satisfy the receiving characteristics required in Phase 1 (a250, a251).

[0099] In Phase 1, the physical layers 33 of the host 2 and the port P0 of the memory system 1 notify each other of their own capabilities to the other device (a120). In Phase 1, the physical layers 33 of the host 2 and the port P1 of the memory system 1 also notify each other of their own capabilities to the other device (a121). After notifying the other device of its own capabilities, the port P1 waits until the wait time STB2 has elapsed.

[0100] (Gen4:Phase2) When Phase 1 is completed, Phase 2 is executed at port P0 under the initiative of the memory system 1. The memory system 1 (more specifically, the physical layer 33 of port P0) selects an initial value of the TxEQ value in Phase 2 of Gen4, similar to Phase 2 of Gen3. The memory system 1 requests the host 2 to apply the selected TxEQ value to communication with port P0 (a130).

[0101] The host 2 applies the TxEQ value requested by the memory system 1 to communication with the port P0. The host 2 transmits an ordered set for notifying the port P0 of the memory system 1 of the applied TxEQ value (a140).

[0102] The memory system 1 adjusts the characteristics of the equalizer 511_0 of the port P0 (a270).

[0103] The memory system 1 repeats a130, a140, and a270 for multiple TxEQ values. That is, the memory system 1 repeats the sweep for multiple TxEQ values. The upper limit of the period for obtaining the TxEQ value of the host 2 is also determined in Phase 2 of Gen4. Therefore, the number of sweeps is limited. For example, the setting of the TxEQ value applied to the host 2 is limited to the settings S0 to S9 shown in FIG. 3.

[0104] The memory system 1 determines the TxEQ value that provides the highest signal quality among the multiple TxEQ values ​​for the port P0 as the optimum value Opt_TxEQ_g4h0. The memory system 1 requests the host 2 to apply the optimum value Opt_TxEQ_g4h0 as the TxEQ value for the port P0 (a150).

[0105] The host 2 applies the optimum value Opt_TxEQ_g4h0 requested by the memory system 1 to the TxEQ value for the port P0. The host 2 transmits an ordered set for notifying the applied optimum value Opt_TxEQ_g4h0 to the port P0 of the memory system 1 (a160).

[0106] The physical layer 33 of the port P0 receives the ordered set for notifying the optimum value Opt_TxEQ_g4h0. The physical layer 33 of the port P0 holds the received ordered set. This ordered set indicates the optimum value Opt_TxEQ_g4h0 of the TxEQ value of the host 2.

[0107] When the physical layer 33 (more specifically, LTSSM 57_0) of port P0 sets the TxEQ value of host 2 to the optimum value Opt_TxEQ_g4h0, it transmits state information STp0 indicating that Phase 2 of Gen4 has been completed (i.e., indicating that the optimum value Opt_TxEQ_g4h0 has been acquired) to the physical layer 33 of port P1 (a165). In addition, the physical layer 33 of port P0 transmits the optimum value Opt_TxEQ_g4h0 of the TxEQ value of host 2 and the RxEQ code value of the RxEQ circuit 51_0 to port P1.

[0108] When the wait time STB2 has elapsed, the physical layer 33 of the port P1 transitions from Phase 1 (waiting state) to Phase 2. Phase 2 in the port P1 is also executed under the initiative of the memory system 1. The wait times STB1 and STB2 are determined according to predetermined time limits from the start to the completion of Gen3 and Gen4, respectively.

[0109] When the physical layer 33 of the port P1 has received the state information STp0, it selects an initial value (Ini_TxEQ_g4p2h) of the TxEQ value of the host 2 in Phase 2 of the port P1 based on the optimal value Opt_TxEQ_g4h0 of the TxEQ value of the host 2 determined in the port P0. The physical layer 33 of the port P1 selects an initial value of the TxEQ value in Phase 2 of the port P1 from, for example, the group to which the optimal value Opt_TxEQ_g4h0 in the port P0 belongs, among the groups GP1 to GP3 shown in FIG. 3. For example, when the optimal value Opt_TxEQ_g4h0 is S7, the physical layer 33 of the port P1 selects an initial value of the TxEQ value in Phase 2 of the port P1 from the group GP3. The physical layer 33 of the port P1 requests the host 2 to apply the selected TxEQ value to the communication with the port P1 (a131). If the physical layer 33 of the port P1 does not receive the state information STp0 from the port P0 within the waiting time STB2, the physical layer 33 of the port P1 selects a predetermined value as the initial value of the TxEQ value in Phase 2 of the port P1.

[0110] As in Gen3, the physical layer 33 of port P1 may select the initial value of the TxEQ value in Phase2 of port P1 further depending on the RxEQ code value received from port P0.

[0111] The host 2 applies the TxEQ value requested by the memory system 1 to communication with the port P1. The host 2 transmits an ordered set for notifying the port P1 of the memory system 1 of the applied TxEQ value (a141).

[0112] The memory system 1 adjusts the characteristics of the equalizer 511_1 of the port P1 (a271).

[0113] The memory system 1 repeats a131, a141, and a271 for multiple TxEQ values ​​in the group to which the optimal value Opt_TxEQ_g4h0 for port P0 belongs among groups GP1 to GP3. For example, if the optimal value Opt_TxEQ_g4h0 belongs to group GP3, the memory system 1 executes a131, a141, and a271 for multiple TxEQ values ​​in group GP3. That is, the memory system 1 repeats the sweep for multiple TxEQ values ​​in group GP3.

[0114] As with Phase 2 of Gen3, the TxEQ value applied to host 2 for port P1 is limited to the TxEQ of group GP3, so that during the limited adjustment period, it is highly likely that a TxEQ value that can obtain high signal quality will also be required for port P1.

[0115] The memory system 1 determines the TxEQ value that provides the highest signal quality among the multiple TxEQ values ​​in the group GP3 for the port P1 as the optimum value Opt_TxEQ_g4h1. The memory system 1 requests the host 2 to apply the optimum value Opt_TxEQ_g4h1 as the TxEQ value for the port P1 (a151).

[0116] The host 2 applies the optimum value Opt_TxEQ_g4h1 requested by the memory system 1 to the TxEQ value for the port P1. The host 2 transmits an ordered set for notifying the applied optimum value Opt_TxEQ_g4h1 to the port P1 of the memory system 1 (a161).

[0117] The physical layer 33 of the port P1 receives the ordered set for notifying the optimum value Opt_TxEQ_g4h1. The physical layer 33 of the port P1 holds the received ordered set. This ordered set indicates the optimum value Opt_TxEQ_g4h1 of the TxEQ of the host 2.

[0118] The memory system 1 completes Phase 2 on the port P1.

[0119] (Gen4:Phase3) When Phase 2 is completed on port P0, Phase 3 on port P0 is executed under the initiative of host 2. a170, a180, a190, a200, and a280 in Phase 3 of Gen4 on port P0 are the same as a70, a80, a90, a100, and a240 in Phase 3 of Gen3, respectively. a171, a181, a191, a201, and a281 in Phase 3 of Gen4 on port P1 are the same as a71, a81, a91, a101, and a241 in Phase 3 of Gen3, respectively.

[0120] This completes link equalization for ports P0 and P1 at communication speeds compliant with Gen4.

[0121] When link equalization for Gen5 or later is required, the host 2 and the memory system 1 perform link equalization for Gen5 or later in the same manner as for Gen3 or Gen4.

[0122] In this embodiment, the memory system 1 determines the initial value and the optimum value of the TxEQ value of the host 2 in Phase 2 of Gen3 (or Gen4) of port P1 based on the optimum value Opt_TxEQ_g3h0 (or Opt_TxEQ_g4h0) of the TxEQ value of the host 2 in Phase 2 of Gen3 (or Gen4) of port P0. However, the memory system 1 may determine the initial value and the optimum value of the TxEQ value of the host 2 in Phase 2 of Gen3 (or Gen4) of port P0 based on the optimum value Opt_TxEQ_g3h1 (or Opt_TxEQ_g4h1) of the TxEQ value of the host 2 in Phase 2 of Gen3 (or Gen4) of port P1.

[0123] The memory system 1 according to this embodiment determines the initial value and optimal value of the TxEQ value of the host 2 in Phase 2 of Gen3 of port P1 based on the optimal value Opt_TxEQ_g3h0 of the TxEQ value of the host 2 in Phase 2 of Gen3 of port P0. Also, the memory system 1 determines the initial value and optimal value of the TxEQ value of the host 2 in Phase 2 of Gen4 of port P1 based on the optimal value Opt_TxEQ_g4h0 of the TxEQ value of the host 2 in Phase 2 of Gen4 of port P0. This makes it possible to improve the accuracy of optimization of the TxEQ value of the host 2 in port P1. Therefore, the BER required in Gen3 and Gen4 in port P1 (for example, BER<10 -12 ) is more likely to be satisfied. That is, the memory system 1 can improve the communication quality required in the interface.

[0124] Furthermore, according to this embodiment, in Phase 2 of Gen3 and Gen4 of port P1, the memory system 1 limits the sweep range based on the TxEQ value (Opt_TxEQ_g3h0, Opt_TxEQ_g4h0) of the host 2 optimized in port P0. Therefore, in Phase 2 of Gen3 or Gen4 of port P1, the TxEQ value of the host 2 is swept in a narrower range than the sweep range of port P0. Therefore, the number of sweeps in Phase 2 of Gen3 and Gen4 of port P1 can be reduced. This allows the RxEQ period of the memory system 1 to be shortened.

[0125] (Modification) The host 2 can omit Phase 2 and Phase 3 in the link equalization of Gen4. Even if Phase 2 and Phase 3 of Gen4 are omitted, the memory system 1 can meet the reception characteristics required for Gen4 (BER<10 -12 ) must be satisfied.

[0126] In the memory system 1 of this modification, an initial value (Ini_TxEQ_g4p2h) of the TxEQ value of the host 2 in Phase 2 of Gen4 of port P1 is determined based on the optimal value (Opt_TxEQ_g3h0) of the TxEQ value of the host 2 obtained in Phase 2 of Gen3 of port P0. Since the initial value (Ini_TxEQ_g4p2h) of the TxEQ value is the optimal TxEQ value of the host 2 in Gen3, it is possible to increase the possibility of satisfying the reception characteristics required in Gen4 even if Phases 2 and 3 of Gen4 are omitted.

[0127] The above embodiment is applicable to communication speeds that comply with the next-generation PCIe specification succeeding the fourth generation. The above embodiment is also applicable to interface specifications other than the PCIe specification.

[0128] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0129] 100 Information Processing Systems 1. Memory System 2 Host 3. Interface 33 Physical Layer P0 Port P1 Port 33a_0,33a_1 PHY sub-block 33b_0,33b_1 MAC subblock 51_0,51_1 RxEQ circuit 52_0,52_1 RxEQ controller 53_0,53_1 CDR circuit 54_0,54_1 SIPO circuit 55_0,55_1 Receive data controller 56_0,56_1 OS detector 57_0,57_1 LTSSM 58_0,58_1 HostTxEQ controller 59_0,59_1 OS generator

Claims

1. A first port; A second port; a first receiving circuit for receiving data from an external host via the first port; a first transmitting circuit for transmitting data to the host via the first port; a first control circuit that controls the first receiving circuit and the first transmitting circuit; a second receiving circuit for receiving data from the host via the second port; a second transmitting circuit for transmitting data to the host via the second port; a second control circuit that controls the second receiving circuit and the second transmitting circuit; The first control circuit is obtain a first adjustment value for at least one of setting values ​​to be applied to a third transmission circuit of the host connected to the first port when the first reception circuit and the first transmission circuit transition from a first state in which communication with the host is performed at a first communication speed conforming to a first specification to a second state in which communication with the host is performed at a second communication speed conforming to a second specification and different from the first communication speed; Sending the first adjustment value to the second control circuit; when the second receiving circuit and the second transmitting circuit transition from the first state to the second state, the second control circuit determines a second adjustment value, which is at least one of setting values ​​to be applied to a fourth transmitting circuit of the host connected to the second port, based on the first adjustment value transmitted from the first control circuit; electronic equipment.

2. The first control circuit is In the second state, measuring a reception characteristic of the first reception circuit every time a plurality of setting values ​​are applied to the third transmission circuit, and acquiring, as the first adjustment value, a setting value that provides the best reception characteristic of the first reception circuit among the plurality of setting values ​​applied to the third transmission circuit; The second control circuit is in the second state, when measuring the reception characteristics of the second reception circuit every time a plurality of setting values ​​are applied to the fourth transmission circuit, a first setting value to be initially applied to the fourth transmission circuit is determined from among the plurality of setting values ​​to be applied to the fourth transmission circuit based on the first adjustment value.

2. The electronic device according to claim 1.

3. the reception characteristic of the first reception circuit is a bit error rate (BER) of data received by the first reception circuit; the first control circuit acquires, as the first adjustment value, a setting value that provides the smallest BER of the first receiving circuit among the plurality of setting values ​​to be applied to the third transmitting circuit; 3. The electronic device according to claim 2.

4. the plurality of setting values ​​applied to the third transmission circuit or the fourth transmission circuit are classified into a plurality of groups including at least a first group, the first adjustment value is included in the first group, and each of the plurality of setting values ​​included in the first group is equal to or greater than a first value and less than a second value; The second control circuit determines the first setting value from a plurality of setting values ​​included in the first group.

4. The electronic device according to claim 2 or 3.

5. the second control circuit determines the second adjustment value from the plurality of setting values ​​included in the first group by applying the plurality of setting values ​​included in the first group to the fourth transmission circuit, respectively; 5. The electronic device according to claim 4.

6. the first control circuit transmits state information indicating that the first adjustment value has been acquired to the second control circuit; When the second receiving circuit and the second transmitting circuit transition from the first state to the second state, the second control circuit waiting to determine the second adjustment value until the state information is received; In response to receiving the state information, a process of determining the second adjustment value based on the first adjustment value is started.

2. The electronic device according to claim 1.

7. The first control circuit is obtain a third adjustment value for at least one of the setting values ​​to be applied to the third transmission circuit when the first reception circuit and the first transmission circuit transition from the second state to a third state in which the first reception circuit and the first transmission circuit communicate with the host at a third communication speed that is compliant with a third specification and different from the second communication speed; Sending the third adjustment value to the second control circuit; the second control circuit determines a fourth adjustment value, which is at least one of setting values ​​to be applied to the fourth transmission circuit, based on the third adjustment value transmitted from the first control circuit when the second reception circuit and the second transmission circuit transition from the second state to the third state; 2. The electronic device according to claim 1.

8. The first control circuit is obtaining a fifth adjustment value for at least one of the settings applied to the first receiving circuit; Sending the fifth adjustment value to the second control circuit; The second control circuit determines the second adjustment value based on the first adjustment value and the fifth adjustment value transmitted from the first control circuit.

2. The electronic device according to claim 1.

9. the first control circuit acquires, as the fifth adjustment value, a setting value that provides the best reception characteristic of the first reception circuit, from among the plurality of setting values ​​that are applied to the first reception circuit; 9. The electronic device according to claim 8.

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