Manufacturing method of semiconductor device and semiconductor device

Abstract

To provide a manufacturing method of a semiconductor device capable of narrowing a dicing line width and improving the variation in the dicing line width.SOLUTION: A manufacturing method for a semiconductor device according to an embodiment is a manufacturing method for a semiconductor device arranged in a region surrounded by a first dicing line extending in a first direction on a semiconductor wafer and a second dicing line perpendicular to the first direction, the semiconductor device includes a cell region in which a semiconductor element is provided in a semiconductor substrate, and a termination region in which metal wiring electrically connected to the semiconductor element is provided on the semiconductor substrate. In this manufacturing method, a stopper film is formed around the metal wiring in the termination region, a protective film is formed that covers the metal wiring and terminates on a side of the stopper film, and the semiconductor wafer is diced along the first dicing line and the second dicing line.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] An embodiment of the present invention relates to a method for manufacturing a semiconductor device, and a semiconductor device. [Background technology]

[0002] As an example of a semiconductor device, a vertically structured semiconductor device having a cell region and a termination region is known, in which a power semiconductor element such as an IGBT (Insulated Gate Bipolar Transistor) or a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is provided.

[0003] On the other hand, in the termination region, metal wiring electrically connected to the power semiconductor element is provided. This metal wiring is covered with a protective film. In a development process, which is one of the manufacturing processes of this protective film, the end of the protective film may be formed in a tapered shape on the dicing line. In this case, in order to ensure the coverage of the metal wiring, it is necessary to design the dicing line width with a margin. In addition, since it is difficult to ensure the uniformity of the end shape of the protective film within the wafer, the dicing line width is likely to vary. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2020-98826 A Summary of the Invention [Problem to be solved by the invention]

[0005] The problem to be solved by the present invention is to provide a semiconductor device and a manufacturing method thereof that can ensure the coverage of metal wiring, narrow the dicing line width, and improve the variation in the dicing line width. [Means for solving the problem]

[0006] A method for manufacturing a semiconductor device according to one embodiment is a method for manufacturing a semiconductor device that is arranged in a region surrounded by a first dicing line extending in a first direction on a semiconductor wafer and a second dicing line perpendicular to the first direction, the semiconductor device including a cell region in which a semiconductor element is provided in a semiconductor substrate, and a termination region in which metal wiring electrically connected to the semiconductor element is provided on the semiconductor substrate. In this manufacturing method, a stopper film is formed around the metal wiring in the termination region, a protective film is formed that covers the metal wiring and terminates on a side of the stopper film, and the semiconductor wafer is diced along the first dicing line and the second dicing line. [Brief description of the drawings]

[0007] [Figure 1] 1 is a plan view of a semiconductor device according to a first embodiment. [Diagram 2] 2 is a cross-sectional view taken along the line AA shown in FIG. [Diagram 3] 2 is a cross-sectional view taken along the line BB shown in FIG. 1. [Figure 4] 4A to 4C are cross-sectional views showing a process of forming an oxide film. [Diagram 5] 4A to 4C are cross-sectional views showing a lithography process. [Figure 6] 10A to 10C are cross-sectional views showing an etching step. [Figure 7] 11A to 11C are cross-sectional views showing a photoresist removing step. [Figure 8] 4A to 4C are cross-sectional views showing a process of forming a protective film. [Figure 9] 11 is a cross-sectional view of a termination region of a semiconductor device according to a comparative example. [Figure 10] 11 is a cross-sectional view of a termination region of a semiconductor device according to a comparative example. [Figure 11] FIG. 11 is a plan view of a semiconductor device according to a second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Hereinafter, an embodiment of the present invention will be described with reference to the drawings, but the present invention is not limited to the embodiment.

[0009] (First embodiment) FIG. 1 is a plan view of a semiconductor device 1 according to a first embodiment. The semiconductor device 1 shown in FIG. 1 is in a state before being diced from a semiconductor wafer 10. In the following description, the arrangement and configuration of each part of the semiconductor device may be described using the X-axis, Y-axis, and Z-axis shown in each figure. The X-axis, Y-axis, and Z-axis are mutually orthogonal and represent the X-direction, Y-direction, and Z-direction, respectively. In addition, the Z-direction may be described as upward and the opposite direction as downward. In this embodiment, the X-direction and the Y-direction correspond to the first direction and the second direction, respectively, and represent in-plane directions parallel to the front surface (or rear surface) of the semiconductor device 1. The Z-direction corresponds to the third direction and represents an out-of-plane direction perpendicular to the front surface (or rear surface) of the semiconductor device 1.

[0010] Also, p, p + The notation means that the p-type impurity concentration increases in this order. - , n, n + The notation indicates that the n-type impurity concentration increases in this order.

[0011] The impurity concentration can be measured by, for example, SIMS (Secondary Ion Mass Spectrometry). The relative level of the impurity concentration can also be determined from the level of the carrier concentration obtained by, for example, SCM (Scanning Capacitance Microscopy). The distance, such as the depth of the semiconductor region, can also be obtained by, for example, SIMS.

[0012] As shown in FIG. 1, a semiconductor wafer 10 has a plurality of semiconductor devices 1 arranged in a matrix along the X and Y directions. A first dicing line L1 extending in the X direction is provided between the semiconductor devices 1 facing each other in the Y direction. A second dicing line L2 extending in the Y direction is provided between the semiconductor devices 1 facing each other in the X direction. That is, on the semiconductor wafer 10, the semiconductor device 1 is arranged in a region surrounded by the first dicing line L1 and the second dicing line L2. In this embodiment, the widths of the first dicing line L1 and the second dicing line L2 are the same, but may be different.

[0013] Each semiconductor device 1 has a cell region 1a and a termination region 1b provided around the cell region 1a. The structure of the cell region 1a will now be described with reference to FIG.

[0014] Fig. 2 is a cross-sectional view taken along the cutting line AA shown in Fig. 1. As shown in Fig. 2, the cell region 1a has a first electrode 11, a second electrode 12, and a semiconductor substrate 13. Here, a case will be described in which the semiconductor element provided in the cell region 1a is an IGBT. However, the structure of the cell region 1a is not limited to the structure shown in Fig. 2. For example, the semiconductor element provided in the cell region 1a may be a MOSFET.

[0015] The first electrode 11 is provided on the back surface of the semiconductor substrate 13. The first electrode 11 can be formed using a metal such as aluminum. The first electrode 11 functions as a collector electrode.

[0016] The second electrode 12 faces the first electrode 11 in the Z direction across the semiconductor substrate 13. The second electrode 12 can be formed using a metal such as aluminum. The second electrode 12 functions as an emitter electrode.

[0017] The semiconductor substrate 13 is p + Collector layer 131, n + Buffer layer 132, n - Base layer 133, p base layer 134, n+ It has an emitter region 135 , a gate electrode 136 , and a gate insulating film 137 .

[0018] p + The collector layer 131 is provided on the first electrode 11. + The buffer layer 132 is p + It is provided on the collector layer 131. + On the buffer layer 132, - A base layer 133 is provided.

[0019] n - A p-base layer 134 is provided on the base layer 133. The p-base layer 134 includes n + The emitter region 135 is in contact with + The emitter region 135 is in contact with the second electrode 12. When the voltage between the gate electrode 136 and the second electrode 12 (emitter electrode) becomes equal to or higher than the threshold voltage, an n-channel is formed in the p-base layer 134. As a result, in the cell region 1a, + From the collector layer 131 through the n-channel + A current path is created to the emitter region 135 .

[0020] The gate electrode 136 is connected to the p-base layer 134 and the n-type base layer 135 via a gate insulating film 137. + It faces emitter region 135. Gate electrode 136 can be formed using, for example, polysilicon. Gate insulating film 137 is, for example, a silicon oxide (SiO2) film. Next, the structure of termination region 1b will be described with reference to FIG.

[0021] Fig. 3 is a cross-sectional view taken along line BB shown in Fig. 1. As shown in Fig. 3, termination region 1b has semiconductor substrate 13, metal wiring 14, protective film 15, and stopper film 16.

[0022] The structure of the semiconductor substrate 13 is the same as that of the cell region 1a, and therefore a detailed description thereof will be omitted. +The emitter region 135, the gate electrode 136, and the gate insulating film 137 are not provided.

[0023] The metal wiring 14 is provided on the upper surface of the semiconductor substrate 13. The metal wiring 14 is electrically connected to, for example, the second electrode 12 of the cell region 1a. The material of the metal wiring 14 is, for example, aluminum (Al), an alloy of aluminum and copper (AlCu), or an alloy of aluminum and silicon (AlSi).

[0024] The protective film 15 covers the metal wiring 14. The protective film 15 is a resin film such as a polyimide film. When the protective film 15 is formed, if the protective film 15 spreads from the termination region 1b to the dicing line of the semiconductor wafer 10, the dicing line width W varies. Therefore, in this embodiment, in order to prevent the protective film 15 from spreading, a stopper film 16 is provided on the outermost periphery of the termination region 1b. As a result, the distance between the stopper films 16 facing each other in the X direction and the Y direction becomes the dicing line width W.

[0025] The stopper film 16 may be a conductive film made of aluminum, copper, etc., or may be an insulating film made of silicon oxide (SiO2), silicon nitride (SiN), etc. In order to more reliably prevent the protection film 15 from spreading, it is desirable that the height h of the stopper film 16 is greater than the thickness t of the metal wiring 14.

[0026] 4 to 8, a method for manufacturing the semiconductor device 1 according to this embodiment will be described. Here, a method for manufacturing the termination region 1b in the semiconductor device 1 will be described. Note that the cell region 1a can be formed by a commonly used manufacturing method before the formation of the termination region 1b, and therefore a detailed description thereof will be omitted.

[0027] 4, an oxide film 160 is formed so as to cover the upper surface of the semiconductor substrate 13 and the surfaces of the metal wirings 14. The oxide film 160 is formed by, for example, CVD (Chemical Vapor Deposition). Note that a nitride film or a conductive film may be formed instead of the oxide film 160.

[0028] 5, a pattern of photoresist 170 is formed by lithography on the oxide film 160. In this embodiment, the photoresist 170 is applied to the portion of the oxide film 160 that is to be left as the stopper film 16.

[0029] 6, the oxide film 160 is etched using the photoresist 170 as a mask. The oxide film 160 is etched by, for example, RIE (Reactive Ion Etching).

[0030] 7, the photoresist 170 is removed. As a result, the stopper film 16 is formed around the metal wiring 14. The stopper film 16 can also be formed by stacking the oxide film 160 by performing the steps shown in FIGS. 4 to 7 multiple times.

[0031] Finally, as shown in FIG. 8, a protective film 15 is formed so as to cover the metal wiring 14 and terminate on the side of the stopper film 16 facing the metal wiring 14. The protective film 15 can be formed by commonly used manufacturing processes such as an exposure process and a development process. This completes the termination region 1b. After that, the semiconductor wafer 10 is diced into a lattice shape along the first dicing line L1 and the second dicing line L2 using a blade. This separates the semiconductor wafer 10 into a plurality of semiconductor devices 1 (semiconductor chips).

[0032] Now, a comparative example to be compared with this embodiment will be described with reference to FIGS.

[0033] 9 and 10 are cross-sectional views of termination region 1b of a semiconductor device according to a comparative example. In Fig. 9 and Fig. 10, the same components as those in semiconductor device 1 described above are denoted by the same reference numerals, and duplicated explanations will be omitted.

[0034] As shown in Figures 9 and 10, the termination region 1b of the semiconductor device according to this comparative example does not have a stopper film 16. Therefore, the end of the protective film 15 has a tapered shape. For example, in Figure 9, the taper angle of the end of the protective film 15 is small, so that the protective film 15 tends to spread from the termination region 1b to the second dicing line L2. Therefore, in order to ensure the coverage of the metal wiring 14, it is necessary to design the dicing line width W1 to be wider.

[0035] Furthermore, the tapered shape of the end of protective film 15 shown in Fig. 10 is different from the tapered shape of the end of protective film 15 shown in Fig. 9. As a result, dicing line width W2 shown in Fig. 10 is longer than dicing line width W1 shown in Fig. 9. When the uniformity of the end shape of protective film 15 is lost in this way, the dicing line width is likely to vary.

[0036] In contrast, in this embodiment, the stopper film 16 is formed before the protective film 15 as described above. Therefore, the end of the protective film 15 contacts the side surface of the stopper film 16 and is prevented from moving toward the second dicing line L2. This makes it possible to fix the dicing line width W to the distance between the stopper films 16. That is, the size of the dicing line width W can be controlled by the distance between the stopper films 16. Therefore, it is possible to narrow the dicing line width W and improve the variation in the dicing line width.

[0037] Second embodiment Fig. 11 is a plan view of a semiconductor device according to a second embodiment. The semiconductor device 2 shown in Fig. 11 is in a state before being diced from a semiconductor wafer 20. In Fig. 11, the same components as those in the semiconductor device 1 according to the first embodiment described above are denoted by the same reference numerals.

[0038] The semiconductor device 2 according to this embodiment has a cell region 2a and a termination region 2b. The structure of the cell region 2a is similar to the structure of the cell region 1a according to the first embodiment, and therefore a description thereof will be omitted.

[0039] Furthermore, termination region 2b has a structure similar to that of termination region 1b according to the first embodiment. Furthermore, termination region 2b can be formed by the same process as the manufacturing method of termination region 1b described in the first embodiment. However, in this embodiment, the planar shape of stopper film 16 formed on semiconductor wafer 20 is different from that of semiconductor device 1 according to the first embodiment.

[0040] 1, in the semiconductor device 1 according to the first embodiment, the stopper film 16 extends not only to the outer periphery of the termination region 1b but also to the intersection region R between the first dicing line L1 and the second dicing line L2. As a result, in the intersection region R, the portion where the stopper film 16 is provided becomes a convex portion, and the portion where the stopper film 16 is not provided becomes a concave portion. Therefore, when the blade dices the semiconductor wafer 10 along the first dicing line L1 and the second dicing line L2, dicing of the concave and convex portions occurs.

[0041] 11, in the semiconductor device 2 according to this embodiment, the stopper film 16 terminates in the termination region 1b and does not extend into the intersection region R. That is, the stopper film 16 is not provided in the intersection region R. Therefore, there are no convex or concave portions in the intersection region R. As a result, when the blade dices the semiconductor wafer 20 along the first dicing line L1 and the second dicing line L2, the intersection region R is diced in a flat portion.

[0042] According to the present embodiment described above, as in the first embodiment, stopper film 16 is formed in front of protective film 15 in termination region 2b. Therefore, the end of protective film 15 contacts the side surface of stopper film 16 and is prevented from moving toward second dicing line L2. This makes it possible to fix dicing line width W to the distance between stopper films 16. Therefore, it is possible to narrow dicing line width W and improve the variation in dicing line width.

[0043] In addition, in this embodiment, the dicing of the intersection region R is flat dicing. Therefore, it is possible to dice the semiconductor wafer 20 more smoothly than in the first embodiment.

[0044] In the first and second embodiments, the stopper film 16 remains as one of the components of the semiconductor devices 1 and 2, but may be removed before or after the dicing process because removing the stopper film 16 does not affect the electrical characteristics of the semiconductor devices 1 and 2.

[0045] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope of the invention and its equivalents described in the claims, as well as in the scope and spirit of the invention. [Explanation of symbols]

[0046] 1, 2: Semiconductor device 1a, 2a: Cell area 1b, 2b: Termination area 10, 20: Semiconductor wafer 13: Semiconductor substrate 14: Metal wiring 15:Protective film 16: Stopper film L1: First dicing line L2: Second dicing line

Claims

1. A method for manufacturing a semiconductor device, the semiconductor device being disposed in a region surrounded by a first dicing line extending in a first direction on a semiconductor wafer and a second dicing line perpendicular to the first direction, the semiconductor device comprising: a cell region in which a semiconductor element is provided in a semiconductor substrate; and a termination region in which metal wiring electrically connected to the semiconductor element is provided on the semiconductor substrate, forming a stopper film around the metal wiring in the termination region; forming a protective film that covers the metal wiring and terminates on a side surface of the stopper film; A method for manufacturing a semiconductor device, comprising: dicing the semiconductor wafer along the first dicing lines and the second dicing lines.

2. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the stopper film is an oxide film, a nitride film or a conductive film.

3. 3. The method for manufacturing a semiconductor device according to claim 1, wherein the height of said stopper film is greater than the thickness of said metal wiring.

4. covering the metal wiring and an upper surface of the semiconductor substrate with the oxide film, the nitride film, or the conductive film; applying a photoresist to a portion of the oxide film, the nitride film, or the conductive film that is to be left as the stopper film; Etching the oxide film, the nitride film, or the conductive film using the photoresist as a mask; The method for manufacturing a semiconductor device according to claim 2 , further comprising removing the photoresist.

5. 3. The method for manufacturing a semiconductor device according to claim 1, wherein the stopper film extends to an intersection region between the first dicing line and the second dicing line.

6. 3. The method for manufacturing a semiconductor device according to claim 1, wherein said stopper film terminates in said termination region and does not extend into an intersection region R between said first dicing line and said second dicing line.

7. 3. The method for manufacturing a semiconductor device according to claim 1, wherein the protective film is a polyimide film.

8. 3. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor element is an insulated gate bipolar transistor (IGBT) or a metal oxide semiconductor field effect transistor (MOSFET).

9. a cell region in which a semiconductor element is provided; a termination region surrounding the cell region; The termination region is Metal wiring electrically connected to the semiconductor element; A protective film covering the metal wiring; a stopper film having a side surface in contact with an end portion of the protective film.

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