Covering for plasma treatment and structure for plasma treatment

Abstract

To provide a structure for a plasma treatment.SOLUTION: A structure for a plasma treatment includes a dicing jig 10 including an annular frame 11 and an adhesive tape 12 that is attached to the frame 11 to cover an opening 11A of the frame 11, a wafer 20 attached to the center of the adhesive tape 12, and a cover ring 30 for a plasma treatment that is attached to the adhesive tape 12 exposed between the frame 11 and the wafer 20. The cover ring 30 for a plasma treatment has a first surface 301 attached to the adhesive tape and a second surface 302 formed on the opposite side of the first surface 301. A chip 200 divided by a groove 21 has a first surface 201 attached to the adhesive tape 12 and a second surface 202 formed on the opposite side of the first surface 201, and the step Δh between the second surface 302 of the cover ring 30 for a plasma treatment and the second surface 202 of the chip 200 is 1.000 mm or less.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to a covering for plasma processing, which is used when performing plasma processing on a wafer in a state where the wafer is attached to an adhesive tape of a dicing jig, and a structure for plasma processing. [Background technology]

[0002] As RFID (Radio Frequency Identification) and discrete semiconductor chips become smaller, there is an increasing demand for thinner wafers (100 μm or less, or even 50 μm or less) during dicing, down from the current thickness (150 μm to 200 μm). If damage caused by backgrinding when thinning the wafer or damage caused by dicing occurs on the front or side surface of a chip, the chip will crack or chip, resulting in a decrease in yield.

[0003] Conventionally, the improvement method involves removing the damaged layer by polishing (precision polishing) or dry etching after backgrinding. Patent Document 1 discloses that cracks in each chip obtained by dividing a wafer are removed by plasma etching. Moreover, Patent Document 2 discloses that dicing is performed by plasma etching. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2019-102592 A, paragraph 0081 [Patent Document 2] JP 2022-89007 A, paragraph 0028 Summary of the Invention [Problem to be solved by the invention]

[0005] In Patent Document 2, as shown in FIG. 12, the wafer 500 is attached to the center of a synthetic resin adhesive tape 620 attached to a frame 610 of a transport carrier 600, and the transport carrier 600 holding the wafer 500 is placed between electrodes in a chamber of a plasma etching device, and the wafer 500 is subjected to plasma processing. If an abnormal discharge occurs during the plasma processing while the wafer 500 is held by the transport carrier 600, the wafer 500 cannot be suitably etched. For this reason, it is desirable to reduce particle generation during plasma processing. It is desirable to reduce particle generation not only in the plasma method in which the transport carrier is placed between electrodes, but also in the case of performing plasma processing of a wafer by placing the transport carrier on a processing stage.

[0006] SUMMARY OF THE PRESENT DISCLOSURE In view of the above, an object of the present invention is to provide a covering for plasma processing that prevents generation of particles, and a structure for plasma processing that includes the covering. [Means for solving the problem]

[0007] The plasma processing structure of the present invention comprises a dicing jig having an annular frame and an adhesive tape attached to the frame and covering an opening of the frame, a wafer attached to the center of the adhesive tape, and a plasma processing covering attached to the adhesive tape and exposed between the frame and the wafer.

[0008] By attaching a covering for plasma processing to the areas of the adhesive tape that are not covered by the wafer, scattering of the adhesive tape during plasma processing is prevented.

[0009] The wafer may have grooves for dividing the wafer into chips, or may not have grooves. The grooves are formed by cutting the wafer in the thickness direction from the front surface opposite the back surface where the wafer has been back-ground, and may be full cuts for separating the wafer into chips, or half cuts for dividing the wafer into regions for forming individual chips. The back surface of the wafer where the back-ground has been applied is attached to the adhesive tape of the jig. The plasma processing structure is not limited to a plasma type in which it is disposed between electrodes, but may be disposed on a processing stage and used for plasma processing of a wafer.

[0010] The plasma processing cover has a first surface attached to the adhesive tape and a second surface formed on the opposite side of the first surface, the wafer has a first surface attached to the adhesive tape and a second surface formed on the opposite side of the first surface, and the step between the second surface of the plasma processing cover and the second surface of the wafer is 1.000 mm or less. The step can be measured by a CNC (Computerized Numerical Control) image measuring device. The temperature is controlled at 23°C, and the thickness of the plasma processing cover placed on a surface plate and the wafer placed within the inner circumference can be measured. The significant figures of the CNC image measuring device are three decimal places, which is a number obtained by rounding off the fourth digit, and the unit is mm. The step can also be measured by a probe using three-dimensional contact measurement for an object (plasma processing cover and the wafer placed within the inner circumference) placed on a surface plate in a similar indoor environment. In this case, the significant figures are five decimal places, which is the number obtained by rounding off the sixth digit, and the unit is mm. Alternatively, a laser microscope can also be used.

[0011] Here, the second surface of the wafer refers to the area inside the peripheral portion, excluding the peripheral portion that is not formed as a chip. When a groove is formed in the wafer, the chip or the chip forming portion has a first surface attached to the adhesive tape and a second surface formed on the opposite side of the first surface, and the second surface of the chip or the chip forming portion is a step between the second surface of the plasma processing cover ring.

[0012] By making the step 1.000 mm or less, the etching amount of the wafer (each chip and chip formation part) can be uniformly performed in the plasma processing of the wafer. On the other hand, if the step between the second surface of the plasma processing cover ring and the second surface of the wafer (chip and chip formation part) exceeds 1.000 mm, the etching amount may vary on the wafer surface. This is because, when the inner peripheral surface of the plasma processing cover ring is exposed to the plasma and the corner portion formed by the inner peripheral surface and the second surface protrudes into the plasma, the plasma is concentrated at this corner portion due to the charging of both the inner peripheral surface and the second surface, and a plasma with a higher density than the surroundings is formed, that is, the edge effect is caused, and etching on the plasma processing cover ring side proceeds faster, and the etching amount at the portion near the periphery of the wafer is smaller than that at the portion near the center. In order to minimize this edge effect, it is desirable to make the plasma processing cover ring and the wafer the same thickness to minimize the influence, but the larger the step, the more repeatedly the plasma processing cover ring can be used, and the step affects the life (number of uses) of the plasma processing cover ring. However, in the pressure range of several to several tens of pascals used in etching, if there is a step of approximately 3,000 mm or more, arc discharge, commonly known as abnormal discharge, may occur, and burning or melting due to high temperatures may occur. For these reasons, the safe step that will not cause abnormal discharge is set at 1,000 mm or less.

[0013] The present invention relates to a plasma processing cover ring that is attached to an adhesive tape around a wafer of a dicing jig, the plasma processing cover ring having a circular opening and formed in a plate shape, and made of any of Si, SiO2, and SiC.

[0014] A plasma processing covering can be attached to the areas of the adhesive tape that are not covered by the wafer, thereby preventing the adhesive tape from scattering or becoming contaminated by plasma.

[0015] The plasma treatment covering of the present invention preferably has a flatness tolerance of 0.050 mm or less on the first surface to be attached to the adhesive tape according to JIS B0021:1998 18.2. This improves adhesion to the adhesive tape 12. On the other hand, if the flatness tolerance is greater than 0.050 mm, adhesion to the adhesive tape decreases, and there is a risk of air entering the gap between the adhesive tape and the plasma treatment covering when it is attached to the adhesive tape. The adhesive tape has, for example, a base layer thickness of about 0.100 mm or more and 0.200 mm or less, and an adhesive layer thickness of 0.050 mm or less. The base layer has a certain degree of conformity to macroscopic undulations on the surface of the plasma treatment covering, but does not have a conformity to microscopic roughness on the surface of the plasma treatment covering, resulting in gaps. Therefore, in order to ensure adhesion by attaching the plasma treatment covering to the adhesive tape without gaps, the first surface of the plasma treatment covering needs to have a roughness that ensures conformity to microscopic parts by the adhesive layer. The flatness tolerance can be measured by a CNC image measuring machine.

[0016] The covering for plasma processing of the present invention preferably has a resistivity of 100 Ω·cm or less, which allows the covering for plasma processing to have an antistatic function and to prevent charged particles from adhering to the covering and re-scattering. Effect of the Invention

[0017] According to the present invention, by attaching the plasma processing cover ring to the adhesive tape around the wafer, it is possible to suppress the generation of particles originating from the adhesive tape. Also, it is possible to prevent abnormal discharge and perform plasma processing well. [Brief description of the drawings]

[0018] [Figure 1] 1 is a plan view showing a structure for plasma processing according to a first embodiment of the present invention. [Diagram 2] 2 is a cross-sectional view of the plasma processing structure taken along line S1-S1 in FIG. [Diagram 3] FIG. 3 is an enlarged view of the area surrounded by the dashed line in FIG. 2. [Figure 4] 1A to 1C are diagrams illustrating a method for manufacturing a covering for plasma processing. [Diagram 5] 1A to 1C are diagrams illustrating a plasma processing method. [Figure 6] FIG. 4 is a plan view showing a structure for plasma processing according to a second embodiment of the present invention. [Figure 7] 7 is a cross-sectional view of the plasma processing structure taken along line S2-S2 in FIG. 6. [Figure 8] FIG. 8 is an enlarged view of the area surrounded by the dashed line in FIG. [Figure 9] 8 is an enlarged view of a plasma processing cover ring surrounded by a dashed line in FIG. 7. [Figure 10] 7 is a cross-sectional view of a first modified example of the cover ring for plasma processing according to the second embodiment of FIG. 6. [Figure 11] 7 is a cross-sectional view of a second modified example of the cover ring for plasma processing according to the second embodiment of FIG. 6. [Figure 12] 1A and 1B are diagrams illustrating a conventional plasma processing of a wafer. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0019] Hereinafter, a first embodiment of the present invention will be described with reference to the drawings.

[0020] [First embodiment] As shown in FIGS. 1 and 2, a structure 1 for plasma processing according to a first embodiment includes a dicing jig 10, a wafer 20, and a covering for plasma processing (hereinafter referred to as covering) 30.

[0021] The jig 10 includes an annular frame 11 made of a metal such as stainless steel or a synthetic resin with a circular opening 11A, and an adhesive tape 12 attached to the frame 11 to cover the opening 11A. The frame 11 has a large ratio (100×φ1 / W10) of the inner diameter φ1 of the opening 11A to the dimension W10, and the inner diameter φ1 of the opening 11A of the frame 11 is 349.5 mm or more and less than 350.5 mm when it is to be used for a wafer with a diameter of 300 mm. In the illustrated example, the dimension W10 is the width, but the same applies to the vertical dimension in a plan view. The adhesive tape 12 has a surface 121 that is joined to the wafer 20 and is made of an adhesive layer, and is preferably a UV tape having a base layer made of a synthetic resin and an adhesive layer made of a UV-curable resin. The adhesive tape is UV tape, and the UV tape has a base layer thickness of 0.200 mm and an adhesive layer thickness of 0.050 mm, for example. An opening 11A passes through the frame 11, and an adhesive side surface 121 of the adhesive tape 12 is exposed in a circular shape through the opening 11A of the frame 11.

[0022] The wafer 20 has a back surface that has been subjected to back grinding, and a front surface formed of a protective layer such as SiO2 that covers the wiring pattern on the opposite side to the back surface, and may or may not have grooves for dividing into chips. In the following explanation, it is assumed that the wafer 20 has grooves 21 for dividing into chips.

[0023] The wafer 20 is held by the jig 10 with its back surface attached to the surface 121 of the adhesive tape 12 on the opening 11A side, and with its front surface and the grooves 21 for dividing the wafer into chips cut in the thickness direction from the front surface exposed. The grooves 21 may be half-cut or full-cut. In the illustrated example, the grooves 21 are full-cut and divided into the chips 200. The periphery of the wafer 20 has a cut-out orientation flat or notch, and is formed by a circle of a certain diameter from the center except for this portion. The thickness of the wafer 20 is not particularly limited, but is, for example, 0.775 mm or less, preferably 0.100 mm or less, more preferably 0.050 mm or less, and desirably 0.001 mm or more.

[0024] Although the drawing does not show the cross-sectional structure of the wiring pattern of the chip 200, the groove 21 reaches from the surface on the protective layer side covering the wiring pattern of the wafer 20 to the Si layer made of silicon constituting the back surface.

[0025] Each chip 200 has a first surface 201 attached to adhesive tape 12 and a second surface that is exposed and located on the opposite side to first surface 201. When half-cut grooves 21 are formed in wafer 20, the area that is separated by grooves 21 and that will be used as a chip when divided by additional processing is referred to as a chip forming portion. Like chip 200, the chip forming portion also has a first surface that is attached to adhesive tape 12 and a second surface that is formed on the opposite side to the first surface.

[0026] The covering ring 30 has a circular opening 31 and is formed in a plate shape. Specifically, as shown in Fig. 3, the covering ring 30 has an annular first surface 301 attached to the adhesive tape 12, an annular second surface 302 disposed on the opposite side of the first surface 301 and formed parallel to the first surface 301, a cylindrical inner peripheral surface 303 disposed between the inner peripheral edge of the first surface 301 and the inner peripheral edge of the second surface 302, and an outer peripheral surface 304 disposed between the outer peripheral edge of the first surface 301 and the outer peripheral edge of the second surface 302, and each portion around the central axis C of the covering ring 30 has a cross-sectional shape cut by a virtual plane passing through the central axis C formed into a rectangle by the first surface 301, the second surface 302, the inner peripheral surface 303, and the outer peripheral surface 304. The first surface 301 and the second surface 302 are formed on flat surfaces. The inner peripheral surface 303 is formed into a cylindrical surface having an inner diameter φ31, and the outer peripheral surface 304 is formed into a cylindrical surface having an outer diameter φ32.

[0027] When the covering ring 30 is viewed in plan as in FIG. 1, the outer peripheral surface 304 presents a circle concentric with the inner peripheral surface 303. In addition, as shown in FIG. 2, the ratio of the inner diameter φ31 to the outer diameter φ32 of the covering ring 30 (100×φ31 / φ32) is set large, for example, to 86.14% or more. For example, the inner diameter φ31 of the covering ring 30 is 300.2 mm or more and 300.5 mm or less, and the outer diameter φ32 is 347.5 mm or more and 348.5 mm or less. In addition, the thickness t1 of the covering ring 30 is set smaller than the difference (φ32-φ31) between the outer diameter φ32 and the inner diameter φ31, for example, 0.050 mm or more and 1.775 mm or less, preferably 1.000 mm or less, and more preferably 0.500 mm or less. If the thickness t1 is 0.775 mm or more, the number of repeated uses can be increased. If the thickness t1 is less than 0.050 mm, the plate will be easily deformed, causing cracks and chipping, making it difficult to attach the plate to the jig 10, etc.

[0028] Moreover, the inner peripheral surface 303 constitutes the opening 31, which penetrates in the thickness direction from the first surface 301 to the second surface 302, and the inner diameter φ31 of the inner peripheral surface 303 is set to be larger than the outer diameter φ20 of the wafer 20 (φ20<φ31). The outer diameter φ32 of the cover ring 30 is set to be smaller than the inner diameter φ1 of the opening 11A of the frame 11 (φ32<φ20).

[0029] The cover ring 30 is made of silicon, SiO2, or SiC, and is preferably made of silicon, which has good peelability against UV curable resin. As for silicon, since polycrystals have grain boundaries, it is preferable to use single crystal silicon.

[0030] Furthermore, the resistivity of the covering 30 is set to, for example, 100 Ω·cm or less, so that the covering 30 has an antistatic function and can prevent charged particles from adhering to the covering 30 and re-scattering the particles. In addition, when the cover ring 30 is made of single crystal silicon, the metal contamination of the silicon on the second surface 302 of the cover ring 30 is 1.0×10 11 atom / cm 2 The following is the result.

[0031] The first surface 301 of the covering 30 has a flatness tolerance (JIS B0021:1998, "18.2 Flatness Tolerance") of, for example, 0.050 mm or less in order to allow the covering 30 to adhere to the adhesive tape 12. In the following, an example will be described in which the flatness tolerance of the first surface 301 is 0.050 mm.

[0032] If the flatness tolerance is greater than 0.050 mm, the adhesion to the adhesive tape 12 decreases, and there is a risk that air may get into the gap between the adhesive tape 12 and the covering 30 when the structure 1 is attached to the adhesive tape 12. In this case, the structure 1 is placed in the chamber of a plasma etching device, and the chamber is depressurized to a vacuum state (for example, the vacuum degree of the chamber is set to 5×10 -3The vacuum is evacuated to 100 Pa. When the pressure is increased to 100 psi, the air in the gap expands adiabatically and pushes the adhesive tape 12 out like a balloon. If the adhesive tape 12 expands in this way, it can cause abnormal discharge and lead to variations in the amount of etching. In addition, since the covering 30 is thin, there is a risk that the covering will crack due to the expansion of the air in the gap. Furthermore, if air remains in the gap when the covering 30 is peeled off from the adhesive tape 12, it can inhibit the curing of the UV curable resin and prevent the covering 30 from being peeled off.

[0033] Therefore, in order to attach the covering 30 to the adhesive tape 12 without any gaps and ensure adhesion, the first surface 301 of the covering 30 needs to have a roughness that ensures the conformability of the adhesive layer to microscopic parts. Specifically, the flatness tolerance is set to be equal to or less than the thickness of the adhesive layer.

[0034] In this way, by making the flatness tolerance of the first surface 301 equal to or less than the thickness of the adhesive layer, the adhesion and followability with the adhesive tape 12 can be improved. The arithmetic mean roughness Ra of the first surface 301 is not limited, but is, for example, 0.050 mm or less, and preferably 0.001 mm or less. The arithmetic mean roughness Ra of the second surface 302 is also not limited, but is preferably, for example, 0.01 μm so as to form a mirror surface. By making the second surface 302 mirror-finished, there is an advantage that minute protrusions on the surface are eliminated, sputtering and excessive etching when exposed to plasma can be suppressed, and the number of particles in the vacuum chamber is not increased.

[0035] As shown in Fig. 3, in a state where the cover ring 30 and the wafer 20 are attached to the adhesive tape 12 of the jig 10, the step Δh between the second surface 302 of the cover ring 30 and the second surface 202 of the chip 200 is set to 1.000 mm or less. If the step Δh exceeds 1.000 mm, the amount of etching for the chip 200 arranged closer to the peripheral portion 22 of the wafer 20 becomes smaller than the amount of etching for the chip 200 arranged closer to the center, so that the amount of etching may vary on the wafer surface. The variation in the amount of etching is linked to the difference in the amount of removal of the damaged layer on the side surface of the chip formed as the groove 21 for division, so that there is a risk that the strength improvement of the chip taken from the region closer to the peripheral portion 22 may be reduced.

[0036] The cause of this variation is that, in the process of inserting the structure 1 into the chamber of a plasma etching device and performing plasma processing on the wafer 20, if the inner peripheral surface 303 of the cover ring 30 is exposed to plasma and a corner 35 formed by the inner peripheral surface 303 and the second surface 302 of the cover ring 30 protrudes into the plasma, plasma is concentrated at this corner 35 due to charging of both the inner peripheral surface 303 and the second surface 302, forming a plasma with a higher density than the surroundings, that is, due to the edge effect, and etching on the cover ring 30 side progresses faster, and the amount of etching at the portion near the periphery of the wafer 20 is smaller than that at the portion near the center. In order to minimize this edge effect, it is desirable to make the cover ring 30 and the wafer 20 the same thickness to minimize the effect, but the larger the step difference Δh, the more repeatedly the cover ring 30 can be used, and the step difference Δ affects the life (number of uses) of the cover ring 30. However, in the pressure range of several to several tens of pascals used in etching, if there is a step of approximately 3,000 mm or more, arc discharge, commonly called abnormal discharge, may occur, and burning or melting due to high temperatures may occur. For these reasons, the safe step Δh, which does not cause abnormal discharge, is set to 1,000 mm or less.

[0037] The thickness of the covering 30 is not limited to being thicker than the wafer 20, but may be the same thickness as the wafer 20 or thinner than the wafer 20. In the following, an example in which the covering 30 is thicker than the wafer 20 will be described.

[0038] The step height Δh can be measured using CNC image measurement on a surface plate in a temperature-controlled room (for example, 23°C). It can also be measured using a probe-type three-dimensional contact measuring device, a laser microscope, or a laser displacement measuring device.

[0039] Furthermore, in the cover ring 30, the parallelism tolerance (JIS B0021:1998 "18.9.4 Parallelism tolerance of surfaces related to datum planes") of the first surface 301 relative to the second surface 302 is set to, for example, 0.050 mm or less. Specifically, the parallelism tolerance is set to the thickness of the adhesive layer or less. In order to obtain in-plane uniformity of the amount of etching on the wafer 20, it is desirable to set the thickness of the inner peripheral surface 303 side of the cover ring 30, which is in the vicinity of the wafer, to 1.000 mm or less. Hereinafter, an example will be explained in which the parallelism tolerance of the first surface 301 with respect to the second surface 302 is 0.050 mm.

[0040] 1, in the structure 1, a covering 30 is disposed around the wafer 20. Also, as shown in Fig. 2 and Fig. 3, the covering 30 is attached to the adhesive tape 12 of the jig 10, and among the surface 121 of the adhesive tape 12 exposed through the opening 11A of the frame 11, the covering 30 covers a non-wafer-attached area 121A around the wafer 20 that is not covered by the wafer 20.

[0041] With the cover ring 30 attached to the wafer non-attached portion 121A, a first gap 41 is formed between the wafer 20 and the cover ring 30. The interval w1 between the outer peripheral surface 23 of the wafer 20 and the inner peripheral surface 303 of the cover ring 30 is, for example, 0.25 mm or more and 1.00 mm or less. If the interval w1 is larger than 1.00 mm, the exposed area of ​​the adhesive tape 12 from the first gap 41 becomes large, and there is a risk that the organic components scattered by the plasma will increase, and if it is less than 0.25 mm, it becomes difficult to place the cover ring 30 on the wafer non-attached portion 121A without touching the wafer 20. Note that the outer peripheral surface 23 of the wafer 20 with respect to the interval w1 is an outer peripheral surface formed at a constant diameter from the center, and excludes the groove 21, notch, or orientation flat.

[0042] With the cover ring 30 attached to the wafer non-attached portion 121A, a second gap 42 is formed between the cover ring 30 and the frame 11. The gap w2 between the outer peripheral surface 304 of the cover ring 30 and the inner peripheral surface 113 of the frame 11 is, for example, 0.25 mm or more and 1.00 mm or less, and is preferably about 0.50 mm. If the gap w2 is larger than 1.00 mm, the exposed area of ​​the adhesive tape 12 from the second gap 42 becomes large, and there is a risk that the organic components scattered by the plasma will increase, and if it is less than 0.25 mm, it becomes difficult to place the cover ring 30 on the wafer non-attached portion 121A without touching the frame 11.

[0043] (Method of manufacturing the covering 30) As shown in FIG. 4, the manufacturing method for the cover ring 30 includes a sheet material forming process for forming a sheet material with a circular opening, a lapping process for removing unevenness and warping from the surface of the sheet material, a chemical etching process for etching the lapped surface of the sheet material, a polishing process for polishing the etched surface after the etching process, and a cleaning process for cleaning the polished surface.

[0044] In the plate forming process, an ingot is sliced ​​to produce a disk, and then an opening is made in this disk to produce a plate for the cover ring 30.

[0045] The lapping process involves roughly polishing the plate material. In this process, the plate material is held by a carrier, and lapping slurry is placed between the rotating high-precision lapping plate and the surface to be polished, and polishing is performed. This transfers the flatness of the lapping plate to the plate material, improving the parallelism of both sides of the plate material. This results in the surface to be polished having an arithmetic mean roughness Ra of 0.300 mm or less.

[0046] The lapping slurry is composed of lapping abrasive grains and lapping liquid. The lapping abrasive grains are made of SiC or Al2O3. The lapping liquid can be, for example, pure water, tap water, processing oil, etc.

[0047] The chemical etching process is performed using an acidic etching solution. As the etching solution, a mixed solution of hydrofluoric acid (HF), nitric acid (HNO3), and acetic acid (CH3COOH) is used. Preferably, the mixture contains 5% to 40% hydrofluoric acid, 25% nitric acid, and 12.5% ​​acetic acid, with the remainder being pure water. The etching solution removes cracks and dents on the first annular processed surface of the plate material and the second annular processed surface located on the opposite side. As a result, after etching, the arithmetic mean roughness Ra of each of the first and second processed surfaces of the plate material is, for example, 0.050 mm or less. Also, instead of immersing the plate material in the etching solution bath, CMP (chemical mechanical polishing) may be performed. Through the chemical etching process, the first processed surface is formed as the first surface 301. Also, the first surface 301 is formed to have a flatness tolerance of 0.050 mm or less.

[0048] In the polishing process, the second processed surface that has been subjected to the chemical etching process is mechanically polished (polishing that does not include chemical reactions such as CMP) to further reduce the roughness of the etched surface, forming the second processed surface into a mirror surface. After this polishing process, the second processed surface becomes a mirror surface with an arithmetic mean roughness Ra of, for example, 0.01 μm, which constitutes the second surface 302. Based on the second surface 302 thus formed, the first surface 301 is formed to have a parallelism tolerance of 0.050 mm or less.

[0049] In the polishing process, the plate is held by a carrier in a polishing device, and a finishing slurry is placed between the rotating pad and the surface to be polished to perform polishing. The finishing slurry is composed of finishing abrasive grains and finishing liquid. The finishing abrasive grains are made of SiO2, and the finishing liquid is, for example, pure water or city water, and preferably pure water is used.

[0050] In the cleaning process, the plate is placed in pure water and ultrasonic waves are applied to remove any residue remaining on the surface. After the cleaning process, the covering 30 is completed.

[0051] Next, a plasma processing method for the wafer 20 using the jig 10 and the cover ring 30 will be described. As shown in FIG. 5, the plasma processing method includes a wafer attachment process in which a wafer without grooves for chip division (not shown) is attached to the center of surface 121 on the opening 11A side of adhesive tape 12 of jig 10; a dicing process in which the wafer is held by jig 10 and divided into chips by a rotating blade of a dicing device to form wafer 20 having grooves 21; a ring attachment process in which a cover ring 30 is attached to non-wafer attachment areas 121A around wafer 20 that are not covered by adhesive tape 12 of jig 10 to form structure 1; a plasma etching process in which structure 1 is placed in the chamber of a plasma etching device and damaged layers on the chip side surfaces that form grooves 21 and on second surface 202 of the chip are removed by plasma; a UV irradiation process in which ultraviolet rays are irradiated onto an adhesive material made of a UV-curable resin of adhesive tape 12; and a peeling process in which cover ring 30 is peeled off from jig 10.

[0052] In this manner, before the cover ring 30 is placed over the non-wafer-attached portion 121A of the jig 10, the wafer 20 held by the jig 10 is processed to form grooves 21 for dividing into chips by making cuts in the surface with a rotary blade while held by the jig 10. After the grooves 21 for division are formed, the cover ring 30 is attached to the non-wafer-attached portion 121A as shown in Figs. 2 and 3, thereby forming the structure 1.

[0053] In the plasma etching process, the structure 1 is transported to a chamber of a plasma etching device and placed between electrodes. Then, a processing gas is supplied from a shower head into the depressurized chamber, and a plasma is generated by a voltage applied between the electrodes. This causes the wafer 20 placed in the center of the structure 1 to be plasma-processed. For example, damaged layers such as cracks on the side of the chip that constitutes the groove 21 of the wafer 20 are etched and removed. The second surface 202 of the chip is also etched to remove cracks and the like. During this plasma processing, the adhesive tape 12 around the wafer 20 is closely covered with the cover ring 30, so that the plasma is prevented from contacting the adhesive tape 12.

[0054] After the plasma etching process, the UV curable resin constituting the adhesive material is cured in the UV irradiation process, so that the cover ring 30 can be easily peeled off from the jig 10. In addition, since the adhesive force fixing each chip 200 is also reduced by the UV irradiation process, each chip 200 can also be easily separated from the jig 10.

[0055] According to this embodiment, by attaching the covering 30 to the adhesive tape 12 exposed between the frame 11 and the wafer 20, it is possible to prevent the organic components constituting the adhesive tape 12 from scattering due to the plasma. This makes it possible to reduce the number of particles generated from the adhesive tape 12. Note that the covering 30 is exposed to the plasma and scraped down to a thinner thickness in the same manner as the wafer 20 during the plasma processing of the wafer 20, but if the thickness before use is 0.775 mm or more, the number of times it can be repeatedly used increases, and it can be used for, for example, 10 plasma processing operations, although this depends on the processing conditions.

[0056] [Second embodiment] As shown in FIGS. 6 and 7, the plasma processing structure 2 of the second embodiment includes a jig 10, a wafer 20, and a cover ring 30A.

[0057] The structure 2 of the second embodiment is different from the structure 1 of the first embodiment in the covering 30A. The covering 30A of the second embodiment is the same as the covering 30 of the first embodiment in that it covers the non-wafer-attached portion 121A of the surface 121 of the adhesive tape 12 exposed through the opening 11A of the frame 11 that is not covered by the wafer 20, but it differs from the covering 30 of the first embodiment in that it covers the frame 11 of the jig 10. Note that the same or equivalent configurations as those of the first embodiment are denoted by the same reference numerals, and their description will be omitted.

[0058] 8 and 9, the covering ring 30A is formed in a plate shape and has a circular opening 31. Specifically, the covering ring 30A includes an annular first surface 301A to be attached to the adhesive tape 12, an annular second surface 302A disposed on the opposite side of the first surface 301A and formed parallel to the first surface 301A, a first inner peripheral surface 303A extending from the edge of the inner peripheral side of the first surface 301A toward the second surface 302A, and a second inner peripheral surface 304A extending from the edge of the inner peripheral side of the second surface 302A toward the first surface 301A. 03B, an annular third surface 303C arranged between first inner circumferential surface 303A and second inner circumferential surface 303B, a first outer circumferential surface 304A extending from the outer circumferential edge of first surface 301A toward second surface 302A, a second outer circumferential surface 304B extending from the outer circumferential edge of second surface 302A toward first surface 301A, and an annular fourth surface 304C arranged between first outer circumferential surface 304A and second outer circumferential surface 304B.

[0059] The second surface 302A has a dimension W32 in a direction perpendicular to the central axis C that is set larger than the dimension W31 of the first surface 301A in a direction perpendicular to the central axis C, and the second surface 302A extends in a radially outer direction D1 and a radially inner direction D2 from the first surface 301A. The radially outer direction D1 is a direction perpendicular to the central axis C of the jig 10 that moves away from the central axis C, and the direction opposite to the radially outer direction D1 and toward the central axis C is referred to as the radially inner direction D2.

[0060] The third surface 303C and the fourth surface 304C are formed parallel to the first surface 301A.

[0061] The second inner circumferential surface 303B is formed into a cylindrical surface having an inner diameter φ31A, and the first inner circumferential surface 303A is formed into a cylindrical surface having an inner diameter φ33, and the inner diameter φ31A of the second inner circumferential surface 303B is set smaller than the inner diameter φ33 of the first inner circumferential surface 303A (φ31A<φ33).

[0062] The first outer peripheral surface 304A is formed as a cylindrical surface with an outer diameter φ34, and the second outer peripheral surface 304B is formed as a cylindrical surface with an outer diameter φ32A, and the outer diameter φ32A of the second outer peripheral surface 304B is set to be larger than the outer diameter φ34 of the first outer peripheral surface 304A (φ34<φ32A).

[0063] As a result, first inner circumferential surface 303A, second inner circumferential surface 303B, first outer circumferential surface 304A, and second outer circumferential surface 304B form concentric circles as shown in Fig. 6. Note that in Fig. 6, first inner circumferential surface 303A, first outer circumferential surface 304A, and inner circumferential surface 113 of frame 11 are indicated by dashed lines.

[0064] Similarly to the cover ring 30 of the first embodiment, the cover ring 30A also has a large ratio of the inner diameter φ31A to the outer diameter φ32A of the second outer circumferential surface 304B (100×φ31A / φ32A).

[0065] The inner diameter φ33 of the first inner circumferential surface 303A is 313.7 mm or more and 314.7 mm or less, and the outer diameter φ34 of the first outer circumferential surface 304A is 359.5 mm or more and 360.5 mm or less. The first inner circumferential surface 303A and the first outer circumferential surface 304A may be formed in a tapered shape. The thickness t1 of the cover ring 30A is set to be smaller than the difference (φ32A-φ31A) between φ32A and the inner diameter φ31A.

[0066] In the cover ring 30A, the first outer peripheral surface 304A and the fourth surface 304C form the outer peripheral step 32. In the outer peripheral step 32, the thickness t2 from the second surface 302A to the fourth surface 304C is set smaller than the dimension in the thickness direction from the first surface 301A to the fourth surface 304C (step Δt2) (t2<Δt2).

[0067] Furthermore, the first inner peripheral surface 303A and the third surface 303C constitute an inner peripheral stepped portion 33. In the inner peripheral stepped portion 33, the thickness t3 from the second surface 302A to the third surface 303C is set larger than the dimension in the thickness direction (step Δt3) from the first surface 301A to the third surface 303C (Δt3 < t3). Also, the outer peripheral step Δt2 is set larger than the inner peripheral step Δt3 (Δt3 < Δt2).

[0068] By providing these outer peripheral stepped portion 32 and inner peripheral stepped portion 33 adjacent to the first surface 301A, the portion from the third surface 303C through the first surface 301A to the fourth surface 304C is formed in a concavo-convex shape.

[0069] Also, the opening 31 is constituted by the first inner peripheral surface 303A, the third surface 303C, and the second inner peripheral surface 303B. The inner diameter φ33 of the first inner peripheral surface 303A is set larger than the outer diameter φ20 of the wafer 20 (φ20 < φ33), and the inner diameter φ31A of the second inner peripheral surface 303B is set smaller than the outer diameter φ20 of the wafer 20 (φ31A < φ20). The outer diameter φ34 of the first outer peripheral surface 304A is set smaller than the inner diameter φ1 of the opening 11A of the frame 11 (outer diameter φ34 < φ1). Also, the outer diameter φ32A of the second outer peripheral surface 304B is set larger than the inner diameter φ1 of the opening 11A of the frame 11 and the dimension W10 (φ1 < φ32A).

[0070] In the cover ring 30A formed in this way, the region of the first surface 301A (hereinafter referred to as the first surface region) is formed thicker than the region of the third surface 303C (hereinafter referred to as the third surface region) and the region of the fourth surface 304C (hereinafter referred to as the fourth surface region), and is pasted to the adhesive tape 12 to constitute a tape adhered portion 310 that covers the non-wafer adhered portion 121A. The fourth surface region projects radially outward D1 from the tape adhered portion 310 to constitute a frame covering portion 320 that covers the frame 11. The third surface region projects radially inward D2 from the tape adhered portion 310 to constitute a wafer covering portion 330 that covers the peripheral edge portion 22 of the wafer 20.

[0071] The frame covering portion 320 is configured to cover at least a portion of the second surface 112 of the frame 11 opposite the first surface 111 that supports the adhesive tape, and preferably to cover the entire second surface 112 .

[0072] 8, with the first surface 301A of the tape adhering portion 310 of the covering 30A attached to the adhesive tape 12, the frame 11 is placed in the outer circumferential step portion 32, and the fourth surface 304C faces the second surface 112 of the frame 11. In addition, the first outer circumferential surface 304A faces the inner circumferential surface 113 of the frame 11, and a second gap 42 is formed therebetween.

[0073] In this manner, frame covering portion 320 extends from tape covering portion 310 in radially outward direction D1 to cover second surface 112 of frame 11, thereby blocking frame 11 from contacting plasma and preventing metal contamination of chip 200 (wafer 20). Furthermore, frame covering portion 320 covers second gap 42, thereby blocking portion 121B of adhesive tape 12 between tape covering portion 310 and frame 11 from plasma. This further prevents adhesive tape 12 from scattering.

[0074] With the first surface 301A of the tape attachment portion 310 of the cover ring 30A attached to the adhesive tape 12, the peripheral edge portion 22 of the wafer 20 is placed on the inner peripheral step portion 33, and the third surface 303C of the cover ring 30A faces the surface of the wafer 20. Moreover, the first inner peripheral surface 303A of the cover ring 30A faces the outer peripheral surface 23 of the wafer 20, and a first gap 41 is formed therebetween.

[0075] In addition, peripheral portion 22 of wafer 20 is a region that is not formed as a chip on wafer 20, and wafer covering portion 330 is configured not to cover chips 200 or chip forming portions divided by grooves 21. For example, when dimension L1 of wafer covering portion 330 projecting in radial inward direction D2 is 1.00 mm or less and dimension L1 is equal to or less than interval w1 of first gap 41, covering ring includes a gap covering portion that does not cover peripheral portion 22 of wafer 20 and covers first gap 41, instead of wafer covering portion 330.

[0076] In this way, the wafer covering portion 330 extends from the tape covering portion 310 in the radially inward direction D2 to cover the first gap 41, and thus the portion 121C of the adhesive tape 12 that is not covered by the tape covering portion 310 and is located between the tape covering portion 310 and the wafer 20 among the wafer non-attached portion 121A can be shielded from the plasma. This further prevents the adhesive tape 12 from scattering.

[0077] The cover ring 30A of this embodiment is preferably designed so that the portion located at a position higher than the wafer 20 does not protrude toward the central axis C.

[0078] The covering 30B shown in FIG. 10 omits the wafer covering portion 330 and consists of a tape covering portion 310 and a frame covering portion 320, and the cylindrical inner peripheral surface 303 is disposed between the inner peripheral edge of the first surface 301A and the inner peripheral edge of the second surface 302A.

[0079] The covering 30C shown in FIG. 11 is composed of a tape covering portion 310A and a frame covering portion 320, omitting the wafer covering portion 330. The tape covering portion 310 is formed with the same thickness t1 from the edge of the inner circumference side of the first surface 301A to the edge of the outer circumference side of the first surface 301A as shown in FIG. 9, but the tape covering portion 310A is formed so that the outer circumference side is thicker than the inner circumference side. Specifically, the tape covering portion 310A includes a wafer proximate portion 311 arranged adjacent to the wafer 20 via a first gap 41, and an outer portion 312 formed thicker than the wafer proximate portion 311 and provided outside the wafer proximate portion 311. The wafer proximate portion 311 and the outer portion 312 form an annular first surface 301A to be attached to the adhesive tape 12. The outer portion 312 and the frame covering portion 320 form an annular second surface 302A formed parallel to the first surface 301A. The wafer proximity portion 311 has a first inner peripheral surface 303D extending from the edge of the inner peripheral side of the first surface 301A, and an annular third surface 303E. The outer portion 312 has a second inner peripheral surface 303F extending from the edge of the inner peripheral side of the first surface 301A. The inner diameter of the second inner peripheral surface 303F is set to be larger than the inner diameter of the first inner peripheral surface 303D. The inner peripheral edge of the third surface 303E is connected to the first inner peripheral surface 303D, and the outer peripheral edge of the third surface 303E is connected to the second inner peripheral surface 303F. The third surface 303E is disposed on the opposite side to the first surface 301A, and is exposed in a state where the cover ring 10C is attached to the adhesive tape 12.

[0080] Furthermore, the third surface 303E and the second inner peripheral surface 303F constitute the inner peripheral step 33A, and for example, in the inner peripheral step 33A, the thickness t4 of the wafer proximity portion 311 from the first surface 301A to the third surface 303E is set to be smaller than the step ΔT4 between the third surface 303E and the second surface 302A (t4<Δt4). The thickness t4 of the wafer proximity portion 311 is not limited to being thicker than the wafer 20, and may be the same thickness as the wafer 20 or thinner than the wafer 20. A dimension L2 by which the wafer proximity portion 311 protrudes from the second inner peripheral surface 303F toward the central axis C is preferably 0.10 mm or less.

[0081] In this manner, the second inner circumferential surface 303F is positioned at a position shifted in the radially outward direction D1 from the first inner circumferential surface 303D of the wafer proximity portion 311, thereby making it possible to reduce the edge effect caused by the corner portion 35A formed by the second inner circumferential surface 303F and the second surface 302A. This allows the etching process of the wafer 20 to be performed uniformly.

[0082] Also in the coverings 30A, 30B, 30C, the first surfaces 301A of the tape covering portions 310, 310A are formed so that the flatness tolerance is 0.050 mm or less, similar to the first surface 301 in the first embodiment. Furthermore, the first surface 301A is also formed so that the parallelism tolerance based on the second surface 302A is 0.050 mm or less, similar to the first surface 301 in the first embodiment.

[0083] Flatness tolerance, parallelism tolerance and surface roughness can be measured by measuring the surface roughness by contacting a probe on a surface plate in a temperature-controlled room (for example, 23°C), or a laser microscope can be used. Also, second surface 302A on the opposite side to first surface 301A, in the illustrated example, is formed so that the surfaces of tape covering portion 310, frame covering portion 320, and wafer covering portion 330 are flush with each other, and further, second surface 302A is preferably a mirror surface having an arithmetic mean roughness Ra of 0.010 mm or less. The step Δh between the second surface 202 of the chip 200 of the wafer 20 and the second surface 302A of the cover ring 30A is preferably set to 1.000 mm or less, similarly to the first embodiment.

[0084] The average thickness t1 of the tape attachment portion 310 constituting the first surface 301A is, for example, not less than 1.700 mm and not more than 1.800 mm.

[0085] Here, the average value of the thickness t1 of the tape covering portion 310 is the average value of the measured values ​​at a plurality of points arranged at intervals of an angle θ of 45 degrees, where θ is the angle around the central axis C shown by ● in FIG. 6. As shown by ▲ in FIG. 6 and FIG. 9, at each angle, the measurement point P1 near the inner circumferential surface of the tape covering portion 310, the measurement point P2 near the outer circumferential surface, and the measurement point P3 between them are measured. Furthermore, the measurement point P1 at each angle is a point at which the distance (r1) from the central axis is constant, and the first surface side and the second surface side are measured, respectively, and the average value of the measured values ​​on the first surface and the second surface is taken as the measured value at each angle. Furthermore, the measurement point P2 at each angle is also a point at which the distance (r2) from the central axis is constant, and the measurement point P3 at each angle is also a point at which the distance (r3) from the central axis is constant, and the measurement points P2 and P3 are also measured on the first surface side and the second surface side, respectively, and the average value of the measured values ​​on the first surface and the second surface is taken as the measured value at each angle. The thickness of the tape-attached portion 310 of the covering 30 can be measured using a CNC image measuring device, a probe contact type three-dimensional contact measuring device, a laser microscope, or the like.

[0086] The inner diameter (φ31A) is 302.0 mm, the outer diameter (φ32A) is 380.0 mm, the inner diameter φ33 of the tape-attaching portion 310 is 314.2 mm, and the outer diameter φ34 of the tape-attaching portion 310 is 360.0 mm. The measured values ​​of the thickness at each angle (0 degrees, 45 degrees, 90 degrees, 135 degrees, 180 degrees, 225 degrees, 270 degrees, 315 degrees) and each measurement point (P1, P2, P3), and the average thickness AVE1 for each measurement point (P1, P2, P3) are shown in Table 1. In addition, the flatness tolerance of this covering 30A is 0.050 mm for the first surface 301A, and the parallelism tolerance of the first surface 301A based on the second surface 302A is 0.050 mm.

[0087] [Table 1]

[0088] Furthermore, the overall average value AVE2 was calculated from the sum of the average value AVE1 of the measurement point P1, the average value AVE1 of the measurement point P2, and the average value AVE1 of the measurement point P3, and rounded off to the fourth decimal place to obtain 1.766 mm. The absolute values ​​of the differences between the measurement values ​​of the measurement points of each angle and the average value AVE2 (P1-AVE2, P1-AVE2, P1-AVE3) are as shown in Table 1. The thickness of the adhesive layer is 0.050 mm, which is set to a dimension equivalent to the flatness tolerance and parallelism tolerance of the first surface 301A, and furthermore, the thickness of the adhesive layer is set to be larger than the absolute values ​​of the differences (P1-AVE2, P1-AVE2, P1-AVE3).

[0089] In this way, by the difference from the average thickness AVE2 being in the range of less than the thickness (=0.050 mm) of the adhesive layer of the adhesive tape, the adhesive layer of the adhesive tape conforms to the shape of the micro-roughness of the first surface 301A, eliminating gaps and providing good adhesion.

[0090] In the second embodiment of the plasma processing structure 2, the non-wafer-attached area 121A is covered with a covering 30A to prevent the adhesive tape 12 from scattering, and further, the frame 11 is covered with a frame covering portion 320 to prevent contamination of the metal constituting the frame 11, thereby making it possible to perform plasma processing of the wafer 20 more efficiently.

[0091] The present invention can be practiced without being limited to the above-described description and illustrated examples.

[0092] For example, as another modification of the covering 30A of the second embodiment, the covering can be configured by omitting the frame covering portion 320 that covers the frame 11.

[0093] When the cover ring provides a wafer covering portion, it can cover the peripheral edge of the wafer, thereby isolating the portion of the adhesive tape between the wafer and the tape covering portion from the plasma.

[0094] By providing the wafer covering portion and the frame covering portion on the cover ring, scattering of the adhesive tape is reliably prevented even if the first gap or the second gap is large. In other words, it is possible to increase the first gap or the second gap, and it is also easy to attach the cover ring to the jig.

[0095] 5, the plasma treatment is performed on a wafer in which full-cut grooves 21 are formed by a dicing process, but the plasma treatment may also be performed on a wafer in which half-cut grooves 21 are formed by a dicing process. The dimensions and number of chips shown in the drawings are examples and are not limited to these.

[0096] In the structure for plasma processing of the present invention, the wafer may not be diced. In this case, the wafer has a first surface attached to the adhesive tape and a second surface formed on the opposite side of the first surface, and the step between the second surface and the second surface of the cover ring may be 1.000 mm or less. The first surface of the wafer is the back surface that has been back-ground, and the second surface is the surface on the wiring pattern side. The second surface excludes the peripheral portion that is not formed as a chip.

[0097] The shape of the outer periphery of the cover ring in the first embodiment and the shape of the first outer peripheral surface of the cover ring in the second embodiment are shown as being circular to correspond to the shape of the opening of the jig frame, but if the opening of the frame is polygonal or other shaped, it is preferable that the first outer peripheral surface is formed to correspond to the shape of the opening of the frame to reduce the gap with the frame. The shape of the edge on the outer periphery of the frame and the shape of the cross section of the frame are not limited to the illustrated examples. The plasma processing of the wafer is not limited to the plasma processing in which the structure is placed between electrodes, but may be performed by placing the structure on a processing stage. [Explanation of symbols]

[0098] 1,2 Structure for plasma processing 10 Jig 11 Frame 11A aperture 12 Adhesive Tape 20 wafers 200 chips 201 Front page 202 Second page 30, 30A, 30B, 30C Plasma treatment cover ring 301,301A Front page 302,302A Second side 41 First Gap 42 Second Gap Δh Step

Claims

1. a dicing jig including an annular frame and an adhesive tape attached to the frame to cover an opening of the frame; A wafer attached to the center of the adhesive tape; a covering for plasma processing attached to the adhesive tape exposed between the frame and the wafer.

2. the plasma treatment covering has a first surface attached to the adhesive tape and a second surface formed on the opposite side to the first surface, the wafer has a first surface attached to the adhesive tape and a second surface formed on an opposite side to the first surface; 2. The structure for plasma processing according to claim 1, wherein a step between the second surface of the cover ring for plasma processing and the second surface of the wafer is 1.000 mm or less.

3. A plasma processing cover ring that is attached to an adhesive tape around a wafer of a dicing jig, comprising: It has a circular opening and is formed in a plate shape, Si, SiO ２ 2. A covering for plasma processing, comprising either silicon carbide or silicon carbide.

4. 4. The covering for plasma processing according to claim 3, wherein the flatness tolerance of the first surface to be attached to the adhesive tape is 0.050 mm or less as defined in 18.2 of JIS B0021:1998.

5. 4. The covering for use in plasma processing according to claim 3, which has a resistivity of 100 Ω·cm or less.

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