Semiconductor device and manufacturing method thereof

Abstract

To provide a semiconductor device and a manufacturing method thereof that can suppress variation in characteristics between individual semiconductor devices.SOLUTION: A semiconductor device according to an embodiment of the present invention includes a first electrode, a first semiconductor region of a first conductivity type, a gate electrode, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, and a second electrode. The gate electrode is provided on the first semiconductor region via a gate insulating layer. The second semiconductor region faces the gate electrode in a second direction via the gate insulating layer. The second semiconductor region includes a first portion, a second portion provided on the first portion and having a higher impurity concentration of the second conductivity type than the first portion, and a third portion located between the second portion and the gate electrode in the second direction and having a higher concentration of a first element than the second portion. The first element is one or more selected from the group consisting of carbon, germanium, antimony, and indium.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same. [Background technology]

[0002] Semiconductor devices such as Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) and Insulated Gate Bipolar Transistors (IGBTs) are used for applications such as power conversion, etc. It is desirable for the variation in characteristics between individual semiconductor devices to be small. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2021-44518 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the embodiments of the present invention is to provide a semiconductor device and a manufacturing method thereof that can suppress variations in characteristics between semiconductor devices. [Means for solving the problem]

[0005] According to the embodiment, the semiconductor device according to the embodiment of the present invention includes a first electrode, a first semiconductor region of a first conductivity type, a gate electrode, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, and a second electrode. The first semiconductor region is provided on the first electrode and is electrically connected to the first electrode. The gate electrode is provided on the first semiconductor region via a gate insulating layer. The second semiconductor region faces the gate electrode via the gate insulating layer in a second direction perpendicular to a first direction from the first electrode to the first semiconductor region. The second semiconductor region includes a first portion, a second portion provided on the first portion and having a higher impurity concentration of the second conductivity type than the first portion, and a third portion located between the second portion and the gate electrode in the second direction and having a higher concentration of a first element than the second portion. The first element is one or more selected from the group consisting of carbon, germanium, antimony, and indium. The third semiconductor region is provided on the second semiconductor region. The second electrode includes a contact portion provided on the second portion and aligned with the third semiconductor region in the second direction, and is electrically connected to the second semiconductor region and the third semiconductor region. According to an embodiment of the present invention [Brief description of the drawings]

[0006] [Figure 1] 1 is a perspective cross-sectional view showing a portion of a semiconductor device according to an embodiment. [Diagram 2] FIG. 2 is an enlarged cross-sectional view of a portion of FIG. [Diagram 3] 1 is a graph illustrating characteristics of a semiconductor device according to an embodiment. [Figure 4] 1 is a graph illustrating characteristics of a semiconductor device according to an embodiment. [Diagram 5] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 6] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 7] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 8] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 9] FIG. 11 is a perspective cross-sectional view showing a portion of another semiconductor device according to an embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, each embodiment of the present invention will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as the actual ones. Even when the same part is shown, the dimensions and ratios of each part may be shown differently depending on the drawing. In this specification and each drawing, elements similar to those already explained are given the same reference numerals, and detailed explanations are omitted as appropriate. In the following description, n + , n, n - and p + The notation p indicates the relative impurity concentration in each conductivity type. + has a relatively higher n-type impurity concentration than n, - indicates that the n-type impurity concentration is relatively lower than that of n. + indicates that the p-type impurity concentration is relatively higher than that of p. Each embodiment described below may be implemented by inverting the p-type and n-type of each semiconductor region.

[0008] FIG. 1 is a perspective cross-sectional view showing a part of a semiconductor device according to an embodiment. The semiconductor device 100 according to the embodiment shown in FIG. - p-type (first conductivity type) drift region 1 (first semiconductor region), p-type (second conductivity type) base region 2 (second semiconductor region), n + Source region 3 (third semiconductor region), n + The semiconductor device includes a drain region 4, a gate electrode 10, a gate insulating layer 11, an insulating layer 12, a lower electrode 21 (first electrode), and an upper electrode 22 (second electrode). In FIG. 1, the upper electrode 22 is indicated by a dashed line.

[0009] In the description of the embodiment, an XYZ orthogonal coordinate system is used. - The direction toward the drift region 1 is defined as the Z direction (first direction). Two directions that are perpendicular to the Z direction and perpendicular to each other are defined as the X direction (second direction) and the Y direction (third direction). - The direction toward the n-type drift region 1 is called "up" and the opposite direction is called "down." These directions are - The shape is based on the relative position to the drift region 1 and is independent of the direction of gravity.

[0010] A lower electrode 21 is provided on the lower surface of the semiconductor device 100. + The drain region 4 is provided on the lower electrode 21 and is electrically connected to the lower electrode 21. - The drift region 1 is n + The n-type drain region 4 is provided on the n-type drain region 4. - The drift region 1 is n + The n-type drain region 4 is electrically connected to the lower electrode 21. - The n-type impurity concentration of the n-type drift region 1 is + The n-type impurity concentration of the n-type drain region 4 is lower than that of the n-type drain region 4.

[0011] The gate electrode 10 is connected to the n-type - The p-type drift region 1 is provided on the p-type base region 2. - The n-type drift region 1 is provided on the n-type drift region 1. + The p-type source region 3 is provided on the p-type base region 2. - A part of the p-type drift region 1, the p-type base region 2, and the n + At least a portion of the source region 3 faces the gate electrode 10 in the X direction with the gate insulating layer 11 interposed therebetween.

[0012] The upper electrode 22 is connected to the p-type base region 2 and the n +The upper electrode 22 is provided on the p-type source region 3 and is located on the upper surface of the semiconductor device 100. The upper electrode 22 includes a contact portion 22a. The contact portion 22a extends downward and contacts a part of the p-type base region 2 and the n-type + The gate electrode 10 is aligned with the source region 3. An insulating layer 12 is provided between the gate electrode 10 and the upper electrode 22, and the gate electrode 10 and the upper electrode 22 are electrically isolated from each other.

[0013] p-type base region 2, n + A plurality of p-type source regions 3, gate electrodes 10, and contact portions 22a are provided in the X direction. The p-type base region 2 is located between adjacent gate electrodes 10 in the X direction. + The source region 3, the gate electrodes 10, and the contact portions 22a extend in the Y direction.

[0014] FIG. 2 is an enlarged cross-sectional view of a portion of FIG. 2, the p-type base region 2 includes a first portion 2a, a second portion 2b, and a third portion 2c. The second portion 2b and the third portion 2c are provided on the first portion 2a. The second portion 2b and the third portion 2c are aligned with each other in the X direction. The contact portion 22a is located on the second portion 2b. The third portion 2c is located between the second portion 2b and the gate electrode 10 in the X direction.

[0015] The p-type impurity concentration in the second portion 2b and the p-type impurity concentration in the third portion 2c are higher than the p-type impurity concentration in the first portion 2a. Also, the concentration of the first element in the third portion 2c is higher than the concentration of the first element in the second portion 2b and the concentration of the first element in the first portion 2a. The first element is one or more selected from the group consisting of carbon, germanium, antimony, and indium.

[0016] As shown in FIG. 2, the p-type base region 2 may further include a fourth portion 2d. The fourth portion 2d is located above the second portion 2b and the third portion 2c, and is aligned with the contact portion 22a in the X direction. The concentration of the first element in the fourth portion 2d is higher than the concentration of the first element in the second portion 2b and the concentration of the first element in the first portion 2a. The concentration of the first element in the fourth portion 2d may be the same as or different from the concentration of the first element in the third portion 2c. In addition, the p-type impurity concentration in the fourth portion 2d is lower than the p-type impurity concentration in the second portion 2b.

[0017] In the illustrated example, the p-type base region 2 includes a pair of third portions 2c spaced apart from each other and a pair of fourth portions 2d spaced apart from each other. The second portion 2b is located between the pair of third portions 2c in the X direction. The contact portion 22a is located between the pair of fourth portions 2d in the X direction. The second portion 2b and the pair of fourth portions 2d are in contact with the contact portion 22a.

[0018] 3 and 4 are graphs illustrating the characteristics of the semiconductor device according to the embodiment. 3 shows the distribution of p-type impurity concentration along the line A1-A2 in FIG. 2. FIG. 4 shows the distribution of p-type impurity concentration along the line B1-B2 in FIG. 2. In FIG. 3, the horizontal axis represents the position P X The vertical axis represents the p-type impurity concentration C [atoms / cm 3 In FIG. 4, the horizontal axis represents the position P Z The vertical axis represents the p-type impurity concentration C [atoms / cm 3 3 shows the results of measuring the p-type impurity concentration in the second portion 2b and the third portion 2c along the X direction. Fig. 4 shows the results of measuring the p-type impurity concentration along the Z direction from the interface between the second portion 2b and the contact portion 22a toward the first portion 2a.

[0019] In each of the concentration distributions shown in FIG. 3 and FIG. 4, the maximum impurity concentration is "1". In the concentration distribution shown in FIG. 3, the region where the impurity concentration is in the range of 0.1 to 0.001 times the maximum value is defined as the first region r1. In the concentration distribution shown in FIG. 4, the region where the impurity concentration is in the range of 0.1 to 0.001 times the maximum value is defined as the second region r2. In this case, the length L1 of the first region r1 is less than 0.5 times the length L2 of the second region r2. That is, the spread of the p-type impurity from the second portion 2b along the X direction is smaller than the spread of the p-type impurity from the second portion 2b along the Z direction. For example, the length L1 is smaller than 0.5 times the length L2 and larger than 0.1 times the length L2. The concentration of the first element in the first region r1 is higher than the concentration of the first element in the second region r2.

[0020] The p-type impurity concentration and the concentration of the first element in each portion of the p-type base region 2 can be obtained by secondary ion mass spectrometry (SIMS) or an atom probe. Alternatively, the carrier density in each portion of the p-type base region 2 may be measured by a scanning capacitance microscope (SCM). The carrier density can be considered to be substantially equal to the impurity concentration in each portion. Therefore, the distribution of the carrier density in the p-type base region 2 can be used as the distribution of the p-type impurity concentration in the p-type base region 2.

[0021] The operation of the semiconductor device 100 will now be described. With a positive voltage applied to the lower electrode 21 relative to the upper electrode 22, a voltage equal to or greater than the threshold is applied to the gate electrode 10. As a result, a channel (inversion layer) is formed in the p-type base region 2, and the semiconductor device 100 is turned on. Electrons flow through the channel from the upper electrode 22 to the lower electrode 21. When the voltage applied to the gate electrode 10 becomes lower than the threshold, the channel in the p-type base region 2 disappears, and the semiconductor device 100 is turned off.

[0022] An example of the material of each component will be described. n - p-type drift region 1, p-type base region 2, n + shaped source region 3, and n+ The gate electrode 10 includes a conductive material such as polysilicon. The gate insulating layer 11 and the insulating layer 12 include an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. The lower electrode 21 and the upper electrode 22 include a metal such as aluminum, titanium, or copper. The gate electrode 10 includes a conductive material such as polysilicon. The gate insulating layer 11 and the insulating layer 12 include an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. The lower electrode 21 and the upper electrode 22 include a metal such as aluminum, titanium, or copper.

[0023] 5(a), 5(b), 6(a), 6(b), 7(a), 7(b), 8(a), and 8(b) are cross-sectional views showing a manufacturing method of a semiconductor device according to an embodiment. First, n - Semiconductor regions 1x and n + A semiconductor substrate is provided that includes a semiconductor region 4x. - The semiconductor region 1x is n + Located on top of the semiconductor region 4x. - The n-type impurity concentration in the n-type semiconductor region 1x is + The n-type impurity concentration in the n-type semiconductor region 4x is lower than that in the n-type semiconductor region 4x. - A p-type impurity is ion-implanted into the upper surface of the n-type semiconductor region 1x to form a p-type semiconductor region 2x. A part of the p-type semiconductor region 2x and the n-type semiconductor region 2x are ion-implanted by reactive ion etching (RIE). - A part of the shaped semiconductor region 1x is removed, thereby forming an opening OP0 extending in the Y direction, as shown in FIG.

[0024] Thermal oxidation causes n -An insulating layer 11x is formed along the surface of the p-type semiconductor region 1x and the surface of the p-type semiconductor region 2x. A conductive layer 10x is formed on the insulating layer 11x by chemical vapor deposition (CVD). The opening OP0 is filled with the conductive layer 10x. The upper surface of the conductive layer 10x is recessed by chemical mechanical polishing (CMP) and wet etching. As a result, a plurality of conductive layers 10x separated from each other are formed inside the plurality of openings OP0, as shown in FIG. 5(b).

[0025] An n-type impurity is ion-implanted into the upper surface of the p-type semiconductor region 2x, + A shaped semiconductor region 3x is formed. An insulating layer 12x is formed on the conductive layer 10x and the insulating layer 11x by CVD. A part of the insulating layer 12x and a part of the insulating layer 11x are removed by RIE. As a result, an opening OP1 is formed. + A portion of the semiconductor region 3x is exposed through the opening OP1.

[0026] Through the above steps, as shown in FIG. 6(a), - type semiconductor region 1x, p type semiconductor region 2x, n + A structure is produced that includes a semiconductor region 3x, a conductive layer 10x, an insulating layer 11x, and an insulating layer 12x. - The direction from the p-type semiconductor region 1x to the conductive layer 10x is parallel to the Z direction. The p-type semiconductor region 2x faces the conductive layer 10x in the X direction via the insulating layer 11x.

[0027] Through the opening OP1, n + A part of the p-type semiconductor region 3x and a part of the p-type semiconductor region 2x are removed. As a result, an opening OP2 is formed as shown in Fig. 6(b). The opening OP2 is located between the conductive layers 10x adjacent to each other in the X direction.

[0028] As shown in Fig. 7(a), an element is ion-implanted into the p-type semiconductor region 2x through the opening OP2 at a first angle with respect to the Z direction. The element to be implanted is one or more selected from the group consisting of carbon, germanium, antimony, indium, argon, and silicon. As a result, the element is implanted into the side surface of the opening OP2 and the region 2y located at the corner of the bottom of the opening OP2.

[0029] As shown in FIG. 7(b), p-type impurities are ion-implanted into the p-type semiconductor region 2x through the opening OP2 at a second angle with respect to the Z direction. The second angle is smaller than the first angle. As a result, the p-type impurities are implanted into the region 2z located at the bottom of the opening OP2. The n-type impurities and p-type impurities implanted thus far are activated by a heat treatment.

[0030] 7(a) and 7(b), as an example, the aspect ratio of the opening OP2 is 2 or more and 3 or less. The aspect ratio is the ratio of the dimension of the opening OP2 in the Z direction to the dimension of the opening OP2 in the X direction. In this case, the first angle with respect to the Z direction in the XZ plane is set to 9 degrees or more and 22 degrees or less. The second angle with respect to the Z direction in the XZ plane is set to 0 degrees or more and 7 degrees or less.

[0031] As shown in Fig. 8(a), metal layers 22x to 22z are formed in sequence by sputtering. Metal layer 22y is formed on metal layer 22x. Metal layer 22z is formed on metal layer 22y. Metal layer 22x contains titanium nitride. Metal layer 22y contains titanium. Metal layer 22z contains aluminum.

[0032] n + Until the semiconductor region 4x reaches a predetermined thickness, n + The bottom surface of the semiconductor region 4x is ground. + A metal layer 21x is formed on the lower surface of the semiconductor region 4x. The metal layer 21x contains aluminum. Through the above steps, the semiconductor device 100 is manufactured as shown in FIG.

[0033] Advantages of the embodiment will be described. As shown in FIG. 2, the p-type base region 2 preferably includes a second portion 2b. By providing the second portion 2b having a higher p-type impurity concentration, the electrical resistance between the p-type base region 2 and the contact portion 22a can be reduced. As shown in FIG. 7(b), the second portion 2b is formed by ion-implanting p-type impurities and performing a heat treatment. When the heat treatment is performed, the p-type impurities diffuse. When the p-type impurity concentration in the vicinity of the gate insulating layer 11 increases due to this diffusion, the voltage threshold of the gate electrode 10 changes.

[0034] In particular, for the semiconductor device 100, it is desirable to form more gate electrodes 10 per unit area. By increasing the number of gate electrodes 10 per unit area, the number of channels per unit area can be increased, and the on-resistance of the semiconductor device 100 can be reduced. On the other hand, as the number of gate electrodes 10 increases, the distance between the gate electrodes 10 becomes narrower. The distance in the X direction between the gate electrode 10 and the contact portion 22a also becomes shorter. As a result, the influence of the diffusion of p-type impurities on the threshold voltage of the gate electrode 10 becomes greater. For example, the variation in the threshold voltage for turning on the semiconductor device increases for each semiconductor device.

[0035] Regarding this problem, in this embodiment, the third portion 2c is provided in the p-type base region 2. The concentration of the first element in the third portion 2c is higher than the concentration of the first element in the second portion 2b. In the region where the first element is injected, the crystal of the semiconductor material is destroyed, and at least a part of the region becomes amorphous. When the p-type impurity diffuses, the p-type impurity is more likely to remain in the amorphous region than in the crystalline region. By providing the third portion 2c between the second portion 2b and the gate insulating layer 11, the p-type impurity diffusing toward the gate insulating layer 11 is more likely to remain in the third portion 2c. This makes it possible to suppress the diffusion of the p-type impurity toward the gate insulating layer 11 and suppress the fluctuation of the threshold value of the gate electrode 10.

[0036] Moreover, the first element is one or more selected from the group consisting of carbon, germanium, antimony, and indium. These elements are easy to implant ions into and have a sufficient atomic radius to destroy the crystal lattice of silicon. The effect on the operation of the semiconductor device 100 is small. Furthermore, according to the semiconductor device 100, the diffusion of p-type impurities in the Z direction is not suppressed. Therefore, the thickness of the second portion 2b in the Z direction can be formed to be sufficiently large. The electrical resistance between the p-type base region 2 and the contact portion 22a can be sufficiently reduced.

[0037] According to the embodiment, it is possible to suppress a decrease in the thickness of the second portion 2b in the Z direction and to suppress a change in the threshold voltage of the gate electrode 10.

[0038] By providing the third portion 2c, in the p-type base region 2, a difference occurs between the concentration distribution of the p-type impurity in the X direction from the second portion 2b toward the gate insulating layer 11 and the concentration distribution of the p-type impurity in the Z direction from the second portion 2b toward the first portion 2a. In general, the distance of diffusion of the p-type impurity in a semiconductor region is constant regardless of the direction. In contrast, in the semiconductor device 100, since the third portion 2c is provided, the distance of diffusion of the p-type impurity in the X direction is shorter than the distance of diffusion of the p-type impurity in the Z direction. As a result, as shown in FIG. 3 and FIG. 4, the length L1 of the first region r1 is less than 0.5 times the length L2 of the second region r2.

[0039] Preferably, the concentration of the first element in the third portion 2c is 3.0×10 17 atoms / cm 3 The concentration of the first element is 3.0×10 17 atoms / cm 3 By making the concentration of the first element in the third portion 2c higher than 5.0×10, the diffusion of the p-type impurity can be effectively suppressed in the third portion 2c. On the other hand, if the concentration of the first element in the third portion 2c is excessively high, the operation of the semiconductor device 100 may become unstable. For this reason, the concentration of the first element in the third portion 2c is set to 5.0×10 20 atoms / cm 3 It is preferable that the temperature is lower than 100°C.

[0040] The first element is preferably at least one selected from the group consisting of carbon and germanium. Carbon and germanium are group 4 elements and are electrically neutral. Even if carbon and germanium are contained in the p-type base region 2, these elements do not substantially affect the operation of the semiconductor device 100.

[0041] In the manufacturing method according to the present embodiment, when the step shown in FIG. 7(a) is performed, argon or silicon may be ion-implanted into the p-type semiconductor region 2x in addition to carbon, germanium, antimony, and indium. By ion-implanting argon or silicon into the p-type semiconductor region 2x, the crystallinity of the region into which these elements are implanted is destroyed, and at least a part of the region becomes amorphous. In the subsequent heat treatment step, the diffusion of the p-type impurity is suppressed by the region.

[0042] FIG. 9 is a perspective cross-sectional view showing a part of another semiconductor device according to the embodiment. The semiconductor device 110 shown in Fig. 9 is an IGBT. Compared with the semiconductor device 100, the semiconductor device 110 has n + Instead of the drain region 4, + The n-type collector region 5 and the n-type buffer region 6 are also included. + The source region 3 is n + It functions as an emitter region 3e. + The n-type collector region 5 is provided on the lower electrode 21 and is electrically connected to the lower electrode 21. The n-type buffer region 6 is + Collector region 5 and n - The n-type buffer region 6 is provided between the n-type drift region 1 and the n-type impurity concentration is - The n-type impurity concentration in the n-type drift region 1 is higher than that in the n-type drift region 2.

[0043] When a voltage equal to or higher than the threshold is applied to the gate electrode 10 while a positive voltage is applied to the lower electrode 21 with respect to the upper electrode 22, the semiconductor device 110 is turned on. At this time, a channel (inversion layer) is formed in the p-type base region 2 near the gate insulating layer 11. Electrons pass through this channel to + Shape emitter area 3e to n - The holes are injected into the n-type drift region 1. - The n-type drift region 1 is injected with - Conductivity modulation occurs in the n-type drift region 1, - The electrical resistance of the p-type drift region 1 decreases. When the voltage applied to the gate electrode 10 thereafter becomes lower than the threshold voltage, the channel in the p-type base region 2 disappears, and the semiconductor device 110 enters an off state.

[0044] In the semiconductor device 110, the third portion 2c is provided in the p-type base region 2, thereby making it possible to suppress the diffusion of the p-type impurity from the second portion 2b toward the gate insulating layer 11. This makes it possible to suppress the variation in the threshold voltage of the gate electrode 10 while suppressing the reduction in the thickness of the second portion 2b in the Z direction.

[0045] Embodiments of the invention include the following features. (Feature 1) A first electrode; a first semiconductor region of a first conductivity type provided on the first electrode and electrically connected to the first electrode; a gate electrode provided on the first semiconductor region via a gate insulating layer; a second semiconductor region of a second conductivity type facing the gate electrode via the gate insulating layer in a second direction perpendicular to a first direction from the first electrode toward the first semiconductor region, A first part; a second portion provided on the first portion and having a higher impurity concentration of a second conductivity type than the first portion; a third portion located between the second portion and the gate electrode in the second direction and having a higher concentration of the first element than the second portion; the first element being one or more selected from the group consisting of carbon, germanium, antimony, and indium; a third semiconductor region of the first conductivity type provided on the second semiconductor region; a second electrode including a contact portion provided on the second portion and aligned with the third semiconductor region in the second direction, the second electrode being electrically connected to the second semiconductor region and the third semiconductor region; A semiconductor device comprising: (Feature 2) The concentration of the first element in the third portion is 3.0×10 17 atoms / cm 3 Higher than 5.0×10 20 atoms / cm 3 2. The semiconductor device according to claim 1, (Feature 3) the second semiconductor region further includes a fourth portion aligned with the contact portion in the second direction, 3. The semiconductor device according to feature 1 or 2, wherein a concentration of the first element in the fourth portion is higher than a concentration of the first element in the second portion. (Feature 4) the second semiconductor region is provided between a pair of the gate electrodes adjacent to each other in the second direction, the second semiconductor region includes a pair of the third portions, 4. The semiconductor device according to any one of features 1 to 3, wherein the second portion is located between the pair of third portions in the second direction. (Feature 5) 5. The semiconductor device according to any one of Features 1 to 4, wherein the first element is carbon or germanium. (Feature 6) A first electrode; a first semiconductor region of a first conductivity type provided on the first electrode and electrically connected to the first electrode; a gate electrode provided on the first semiconductor region via a gate insulating layer; a second semiconductor region of a second conductivity type facing the gate electrode via the gate insulating layer in a second direction perpendicular to a first direction from the first electrode toward the first semiconductor region, A first part; a second portion provided on the first portion and having a higher impurity concentration of a second conductivity type than the first portion; the second semiconductor region, a third semiconductor region of the first conductivity type provided on the second semiconductor region; a second electrode including a contact portion provided on the second semiconductor region and aligned with the third semiconductor region in the second direction, the second electrode being electrically connected to the second semiconductor region and the third semiconductor region; a length of a first region in which the impurity concentration is within a range of 0.1 to 0.001 times the maximum value when a concentration distribution of an impurity of a second conductivity type is measured along the second direction from the second portion toward the gate insulating layer, the length of the first region being within a range of 0.1 to 0.001 times the maximum value when a concentration distribution of the impurity is measured along the first direction from an interface between the second portion and the contact portion toward the first portion, is less than 0.5 times a length of a second region being within a range of 0.1 to 0.001 times the maximum value when a concentration distribution of the impurity is measured along the first direction from an interface between the second portion and the contact portion toward the first portion. (Feature 7) a concentration of the first element in the first region is higher than a concentration of the first element in the second region; 7. The semiconductor device according to feature 6, wherein the first element is one or more selected from the group consisting of carbon, germanium, antimony, and indium. (Feature 8) a first semiconductor region of a first conductivity type; a conductive layer provided on the first semiconductor region via an insulating layer; a second semiconductor region of a second conductivity type facing the conductive layer via the insulating layer in a second direction perpendicular to a first direction from the first semiconductor region toward the conductive layer; a third semiconductor region of the first conductivity type provided on the second semiconductor region; removing a portion of the second semiconductor region and a portion of the third semiconductor region to form an opening in a structure including the above-mentioned; ion-implanting one or more of the group consisting of carbon, germanium, antimony, indium, argon, and silicon into the second semiconductor region through the opening at a first angle relative to the first direction; and ion-implanting an impurity of a second conductivity type into the second semiconductor region through the opening at a second angle with respect to the first direction that is smaller than the first angle.

[0046] Although some embodiments of the present invention have been illustrated above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, modifications, etc. can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are included in the scope of the invention and its equivalents described in the claims. In addition, the above-mentioned embodiments can be implemented in combination with each other. [Explanation of symbols]

[0047] 1:n - Shape drift region, 1x:n - type semiconductor region, 2: p-type base region, 2a: first part, 2b: second part, 2c: third part, 2d: fourth part, 2x: p-type semiconductor region, 3: n + Shape source area, 3e:n + Shape emitter area, 3x:n + Semiconductor area, 4:n + Shaped drain region, 4x:n + Semiconductor area, 5:p + 1: n-type collector region, 6: n-type buffer region, 10: gate electrode, 10x: conductive layer, 11: gate insulating layer, 11x, 12, 12x: insulating layer, 21: lower electrode, 21x: metal layer, 22: upper electrode, 22a: contact portion, 22x to 22z: metal layer, 100, 110: semiconductor device, OP0 to OP2: openings, r1: first region, r2: second region

Claims

1. A first electrode; a first semiconductor region of a first conductivity type provided on the first electrode and electrically connected to the first electrode; a gate electrode provided on the first semiconductor region via a gate insulating layer; a second semiconductor region of a second conductivity type facing the gate electrode via the gate insulating layer in a second direction perpendicular to a first direction from the first electrode toward the first semiconductor region, A first portion; and a second portion provided on the first portion and having a higher impurity concentration of a second conductivity type than the first portion; a third portion located between the second portion and the gate electrode in the second direction and having a higher concentration of the first element than the second portion; the first element being at least one selected from the group consisting of carbon, germanium, antimony, and indium; a third semiconductor region of the first conductivity type provided on the second semiconductor region; a second electrode including a contact portion provided on the second portion and aligned with the third semiconductor region in the second direction, the second electrode being electrically connected to the second semiconductor region and the third semiconductor region; A semiconductor device comprising:

2. The concentration of the first element in the third portion is 3.0×10 １７ atoms / cm ３ Higher than 5.0 x 10 ２０ atoms / cm ３ The semiconductor device according to claim 1 , wherein

3. the second semiconductor region further includes a fourth portion aligned with the contact portion in the second direction, The semiconductor device according to claim 1 , wherein a concentration of the first element in the fourth portion is higher than a concentration of the first element in the second portion.

4. the second semiconductor region is provided between a pair of the gate electrodes adjacent to each other in the second direction, the second semiconductor region includes a pair of the third portions, The semiconductor device according to claim 1 , wherein the second portion is located between the pair of third portions in the second direction.

5. 3. The semiconductor device according to claim 1, wherein the first element is carbon or germanium.

6. A first electrode; a first semiconductor region of a first conductivity type provided on the first electrode and electrically connected to the first electrode; a gate electrode provided on the first semiconductor region via a gate insulating layer; a second semiconductor region of a second conductivity type facing the gate electrode via the gate insulating layer in a second direction perpendicular to a first direction from the first electrode toward the first semiconductor region, A first portion; and a second portion provided on the first portion and having a higher impurity concentration of a second conductivity type than the first portion; the second semiconductor region including a third semiconductor region of the first conductivity type provided on the second semiconductor region; a second electrode including a contact portion provided on the second semiconductor region and aligned with the third semiconductor region in the second direction, the second electrode being electrically connected to the second semiconductor region and the third semiconductor region; a length of a first region in which the impurity concentration is within a range of 0.1 to 0.001 times the maximum value when a concentration distribution of an impurity of a second conductivity type is measured along the second direction from the second portion toward the gate insulating layer, the length of the first region being within a range of 0.1 to 0.001 times the maximum value when a concentration distribution of the impurity is measured along the first direction from an interface between the second portion and the contact portion toward the first portion, is less than 0.5 times a length of a second region in which the impurity concentration is within a range of 0.1 to 0.001 times the maximum value when a concentration distribution of the impurity is measured along the first direction from an interface between the second portion and the contact portion toward the first portion.

7. a concentration of the first element in the first region is higher than a concentration of the first element in the second region; 7. The semiconductor device according to claim 6, wherein the first element is at least one selected from the group consisting of carbon, germanium, antimony, and indium.

8. a first semiconductor region of a first conductivity type; a conductive layer provided on the first semiconductor region via an insulating layer; a second semiconductor region of a second conductivity type facing the conductive layer via the insulating layer in a second direction perpendicular to a first direction from the first semiconductor region toward the conductive layer; a third semiconductor region of the first conductivity type provided on the second semiconductor region; removing a portion of the second semiconductor region and a portion of the third semiconductor region to form an opening in a structure including the ion-implanting one or more selected from the group consisting of carbon, germanium, antimony, indium, argon, and silicon into the second semiconductor region through the opening at a first angle relative to the first direction; and ion-implanting an impurity of a second conductivity type into the second semiconductor region through the opening at a second angle with respect to the first direction that is smaller than the first angle.

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