Radiation-hardened semiconductor power device

Abstract

To provide a radiation-hardened semiconductor device which balances the need to block high voltages while minimizing and / or reducing additional on-state resistance losses.SOLUTION: A radiation-hardened semiconductor device is provided which includes: a heavily doped substrate of a semiconductor device; and a drift layer having a substantially uniform doping concentration and a thickness. The doping concentration and the thickness of the drift layer are such that, when the semiconductor device is operating at the maximum voltage rating, an electrical field profile in the drift layer extends less than 80% of the thickness of the drift layer, realizing the radiation-hardened nature of the device.SELECTED DRAWING: Figure 5A

Description

[Technical field]

[0001] This invention was made with Government support contract no. 80NSSC21K0766 awarded by the National Aeronautics and Space Administration (NASA). The Government has certain rights in this invention.

[0002] These teachings relate generally to semiconductor power devices, and more particularly to radiation hardened semiconductor power devices. [Background technology]

[0003] Semiconductor devices can be used in a variety of applications. These semiconductor devices, such as silicon carbide (SiC) power MOSFETs (metal oxide semiconductor field effect transistors), offer commercial advantages such as high power applications. Due to the large band gap of SiC-based power electronic devices, these devices are believed to be more resistant to the effects of radiation in these applications. However, SiC semiconductor power devices are susceptible to at least one event effects, particularly one event burnout, and may be susceptible to failure at high blocking voltages due to their intolerance to radiation. Summary of the Invention [Means for solving the problem]

[0004] Various needs will be met, at least in part, through the provision of a radiation hardened semiconductor power device as described in the following detailed description, particularly when considered in conjunction with the drawings. A full and enabling disclosure of the presently described aspects, including the best mode thereof, directed to one of ordinary skill in the art, is set forth herein with reference to the accompanying drawings, in which: [Brief description of the drawings]

[0005] [Figure 1A] FIG. 1 illustrates a conventional semiconductor device known in the art. [Figure 1B] 1 is a graph of a conventional semiconductor device operating at a breakdown voltage as known in the art. [Figure 2A] 1 is a graph of drift layer resistance as a function of drift doping for a known semiconductor device. [Figure 2B] 1 is a graph of drift layer thickness as a function of drift doping for a known semiconductor device. [Figure 3A] FIG. 1 illustrates a first prior art semiconductor device. [Figure 3B] 1 is a graph of a first prior art semiconductor device operating at a breakdown voltage. [Figure 3C] FIG. 1 illustrates a second prior art semiconductor device. [Figure 3D] 1 is a graph of a second prior art semiconductor device operating at a breakdown voltage. [Figure 4] FIG. 1 illustrates a third prior art semiconductor device. [Figure 5A] FIG. 1 illustrates a radiation hardened semiconductor power device according to an embodiment. [Figure 5B] 5B is a graph illustrating the radiation-hardened semiconductor power device of FIG. 5A operating at a breakdown voltage. [Figure 6A] 5B is a graph depicting drift layer resistance as a function of drift doping for known semiconductor devices as compared to the radiation hardened semiconductor power device of FIG. 5A. [Figure 6B] 5B is a graph depicting drift layer thickness as a function of drift doping for known semiconductor devices as compared to the radiation hardened semiconductor power device of FIG. 5A. [Figure 7] 1 depicts a method of forming a radiation hardened semiconductor power device according to one embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0006] Elements in the figures are illustrated for simplicity and clarity and are not necessarily drawn to scale. For example, the dimensions and / or relative positions of some of the elements in the figures may be exaggerated relative to other elements to help improve understanding of various embodiments of the present teachings. Also, common but well-understood elements that are useful or necessary in commercially available embodiments are often not depicted to facilitate a less cluttered view of these various embodiments of the present teachings. While certain acts and / or steps may be described or depicted in a particular chronological order, those skilled in the art will understand that no particularity with respect to such order is actually required.

[0007] Unless a different specific meaning is specifically stated herein, the terms and expressions used herein have their ordinary technical meaning as dictated by such terms and expressions by those skilled in the art as described above. The word "or" as used herein should be construed as having a disjunctive rather than a conjunctive construction unless otherwise indicated. The terms "coupled," "fixed," "attached to," and the like refer to both direct coupling, fastening, or attachment and indirect coupling, fastening, or attachment through one or more intermediate components or features unless otherwise indicated herein.

[0008] The singular forms "a," "an," and "the" include plural references unless the context dictates otherwise.

[0009] As used herein throughout the specification and claims, approximating terms are applied to modify any quantitative expression that can vary permissibly without resulting in a change in the basic function to which it pertains. Thus, values ​​modified by terms such as "about," "approximately," and "substantially" are not limited to the exact value specified. In at least some cases, approximating terms can correspond to the precision of an instrument for measuring a numerical value or the precision of a method or machine for constructing or manufacturing a component and / or system. For example, approximating terms may state that a value is within a margin of 10 percent.

[0010] A conventional semiconductor device 10 as shown in FIG. 1A typically includes a p-type layer 12, an epitaxial layer 14 that functions as a drift or depletion layer, and a substrate 16. The conventional semiconductor device 10 also includes a junction 18 between the epitaxial layer 14 and the substrate 16, and a junction 19 between the epitaxial layer 14 and the p-type layer 12. The conventional semiconductor device 10 may additionally include a source region 17 and a drain region 15. In addition, the conventional semiconductor device 10 may include a gate dielectric layer 13 and a gate electrode 11. The conventional semiconductor device 10 may provide a high blocking voltage and thus be useful in high power applications as discussed above. However, the conventional semiconductor device 10 may be prone to failure at high blocking voltages due to intolerance to radiation and may fail to survive a radiation event. As known in the art, an exemplary radiation event may occur when a semiconductor device is struck by a heavy ion, beta radiation, gamma radiation, or neutrons while operating near its maximum voltage rating. The high energies associated with these ions are difficult to shield semiconductor devices from, leaving behind many electron-hole pairs. These radiation events can be characterized as single event effects and / or single event burnouts. Ultimately, these radiation events can result in device failure in some cases. Current technology provides solutions to this, but in doing so, additional challenges and difficulties arise, as discussed below.

[0011] FIG. 1B illustrates a one-dimensional cross-sectional graph 22 of a conventional semiconductor device 10 operating at a breakdown voltage, as known in the art, with the x-axis being linear distance and the y-axis being electric field magnitude. Graph 22 illustrates the depletion of the epitaxial layer of the conventional semiconductor device 10 along with the magnitude of the electric field profile across the epitaxial layer 14 toward the junction 18 with the substrate 16. FIG. 1B illustrates a semiconductor device having a 9 um epitaxial layer operating at a maximum voltage rating of 1600V. FIG. 1B illustrates the conventional semiconductor device 10 immediately prior to breakdown. When the semiconductor device breaks down at the junction 19, the resulting electric field profile is a trapezoidal electric field across the epitaxial layer and substrate of the conventional semiconductor device 10, as shown in graph 22. The trapezoidal electric field profile indicates that the epitaxial layer is completely depleted. If breakdown continues to occur or if operation of the conventional semiconductor device 10 is carried out at higher operating voltages, the conventional semiconductor device 10 may become damaged over time.

[0012] 2A and 2B, graphs 26 and 28 illustrate exemplary design curves for known semiconductor power devices. Specifically, graph 26 illustrates a design curve for a unipolar SiC device blocking region showing blocking layer resistance as a function of blocking layer doping for a particular design blocking voltage. Graph 28 illustrates a design curve for a unipolar SiC device blocking region showing blocking layer thickness as a function of blocking layer doping for a particular design blocking voltage. Triangular electric field breakdown limits are illustrated by diagonal lines in both graphs 26 and 28. The design curves to the left of the triangular breakdown voltage limit range illustrate known devices from the 1.2 kV to 7.5 kV device class. The design curves illustrate devices that result in a trapezoidal electric field profile, i.e., devices that include a drift layer that is fully depleted at the highest voltage rating. Furthermore, as shown in graphs 26 and 28, the design curves run substantially vertically at the triangular field breakdown limit for each device class design curve, which means that adding drift thickness cannot increase the breakdown voltage, assuming a constant drift layer doping.

[0013] In use, graphs 26 and 28 can be used in the design process of conventional semiconductor devices of different ratings, such as conventional semiconductor device 10 and particularly epitaxial or drift layers such as epitaxial layer 14. Typically, the design process begins with selecting a target breakdown voltage for the application in which conventional semiconductor device 10 will be used. Once selected, a doping concentration for the target breakdown voltage is selected. The doping concentration is typically selected near the minimum of the curve of the design of graph 26 using the particular device class intended. The minimum of the curve of the design tends to be near the triangular breakdown limit of the curve for the device class. The minimum of the curve of the design indicates the minimum drift layer resistance. Graphs 28 and 26 provide the required thickness and resulting resistance, respectively. As noted above, these conventional device designs have a combination of doping concentration and thickness selected to be within the threshold of the triangular electric field breakdown limit for the intended device class. For devices designed with a triangular field breakdown limit, as the applied voltage is increased toward the limit, the drift layer will be completely depleted just as the device reaches breakdown. For devices below the triangular field breakdown limit, the drift layer will be depleted before the device reaches breakdown. The resulting field profile is trapezoidal and extends partially into the substrate. Graphs 26 and 28 are provided only as an illustration of the design process, and in reality, epitaxial doping / thickness specifications may include tolerances. As a result, the specifications will result in a rectangular shape on a thickness vs. doping plot and a more complex shape on a resistance vs. doping plot.

[0014] 3A, 3C, and 4 illustrate several different approaches to achieving radiation hardened semiconductor power devices. Traditional approaches to achieving radiation hardening include the inclusion of load reduction and buffer layers. Device load reduction involves taking a semiconductor device design with a higher voltage rating and setting a lower maximum operating voltage than the device was originally designed to handle. Devices that are loaded reduced to operate at a maximum operating voltage typically have a less doped and thicker drift layer compared to an unloaded semiconductor device originally designed to operate at the same maximum operating voltage. As such, loaded reduced devices have significantly higher on-state losses compared to an unloaded semiconductor device designed to operate at the same maximum operating voltage. FIGS. 3A and 3C illustrate devices that can be used as loaded reduced devices.

[0015] As shown in Figure 3A, a first prior art device 30 is shown including a p-type layer 32, a large lightly doped epitaxial layer 34, a heavily doped substrate 36, and a junction 38 where the large lightly doped epitaxial layer 34 and the heavily doped substrate 36 meet. As used herein, a heavily doped substrate is defined as a layer having a dopant concentration of 1x10^18 cm -3 and 4×10^19 cm -3The doping concentration may include between 1000 and 10000 volts. For illustrative purposes only, the heavily doped substrate 36 is only partially shown. Graph 40 illustrates the depletion of the first prior art device 30 by how deep the electric field profile extends into the large lightly doped epitaxial layer 34 toward the junction 38 and the heavily doped substrate 36, as shown in FIG. 3B. Specifically, graph 40 illustrates a one-dimensional cross-sectional graph of the first prior art device 30 operating at a breakdown voltage, with the x-axis being linear distance and the y-axis being electric field magnitude. The first prior art device 30 is a 4.5 kV class device operated at a 5 kV breakdown voltage. Similar to the conventional semiconductor device 10 and graph 22, the first prior art device 30 operating at a breakdown voltage has a trapezoidal electric field across the drift layer of the first prior art device 30.

[0016] A second prior art solution using the device is provided in FIG. 3C, which shows a second prior art device 50 including a p-type layer 52, a large lightly doped epitaxial layer 54, a heavily doped substrate 56, and a junction 58 where the large lightly doped epitaxial layer 54 and the heavily doped substrate 56 meet. For illustrative purposes only, the heavily doped substrate 56 is shown smaller than the large lightly doped epitaxial layer 54. A graph 60 illustrates the depletion of the second prior art device 50 according to how deep the electric field profile extends into the large lightly doped epitaxial layer 34, as shown in FIG. 3D. Specifically, the graph 60 illustrates a one-dimensional cross-sectional graph of the second prior art device 50 operating at a breakdown voltage, with the x-axis being linear distance and the y-axis being electric field magnitude. The second prior art device 50 is a 4.5 kV class device operated at a 5.5 kV breakdown voltage. In contrast to the first prior art device 30, the second prior art device 50 is able to avoid complete depletion of the large lightly doped epitaxial layer 54 when operated at the highest operating voltage. In this case, the second prior art device 50 breaks down before the large lightly doped epitaxial layer 54 is fully depleted to achieve high voltage blocking.

[0017] Due to the size of the large lightly doped epitaxial layer 54 of the second prior art device 50, the device breaks down substantially completely depleted compared to the size of the large lightly doped epitaxial layer 34 of the first prior art device 30. Because the second prior art device 50, and in particular the large lightly doped epitaxial layer 54, breaks down substantially completely depleted rather than after complete depletion as shown in graph 40 of the first prior art device 30, the second prior art device 50 can be more useful in blocking high voltages. While the large lightly doped epitaxial layer 54 was not completely depleted, as shown in graph 60, the large lightly doped epitaxial layer 54 had substantially 100% depletion. Comparing the first prior art device 30 and the second prior art device 50, specifically the large lightly doped epitaxial layer 34 and the large lightly doped epitaxial layer 54, adding about 40% additional thickness to the epitaxial layer results in about a 10% increase in breakdown voltage.

[0018] The devices shown in Figures 3A and 3C can be operated as derated devices. As discussed above, a derated device is one that operates at a much lower voltage, such as the first prior art device 30 and the second prior art device 50 operating at 1.2 kV. In doing so, the device is more likely to survive a radiation event, resulting in a radiation hardened device. However, due to the lower doping concentration, the on-state resistance loss of such a device is much higher than the device originally designed for 1.2 kV based on the design curves in graphs 26 and 28. Specifically, as shown in Figure 2A and Figures 6A and 6B discussed below, the drift layer resistance of the first prior art device 30 and the second prior art device 50 is much higher than the conventional semiconductor device 10, which is a 1.2 kV class device. Additionally, the first prior art device 30 and the second prior art device 50 may be more costly due to the need for consistent and uniform epitaxial layer doping at lower doping levels due to the low doping of the epitaxial layers.

[0019] 4, a semiconductor device 80 having a buffer layer is shown. Semiconductor device 80 includes a p-type layer 82, a drift layer 84, a buffer layer 83, and a substrate 86. Semiconductor device 80 includes a drift to buffer junction 85 and a buffer to substrate junction 87.

[0020] During a radiation event, the buffer layer 83 disperses at least a portion of the resulting electric field created in the drift layer 84 through the buffer layer 83 before it reaches the substrate 86. The dispersion can additionally spread the electric field across the buffer layer 83 and delay depletion of the drift layer 84. In so doing, the semiconductor device 80 can withstand a radiation event, such as a single event impact and / or a single event burnout when the semiconductor device is struck by a heavy ion, beta radiation, gamma radiation, or neutron while operating near its maximum voltage rating. While the semiconductor device 80 can be considered radiation hardened, similar to the first prior art device 30 and the second prior art device 50 operating as a depleted device, the drift layer 84 can be fully and / or substantially depleted to the extent of 90% or more depletion. Additionally, due to the added buffer layer 83, the semiconductor device 80 is more complicated to construct than the conventional semiconductor device 10, the first prior art device 30, and the second prior art device 50. Complex constructions are more time consuming and expensive due to the need for more complex epitaxial layer growth.

[0021] Generally speaking, various aspects of the present disclosure provide radiation hardened semiconductor devices that balance the need to block high voltages while minimizing and / or reducing additional on-state resistance losses. This can be achieved through the use of a thick drift layer that is highly doped compared to the epitaxial layers of the devices discussed above. In doing so, the amount of depletion in the present disclosure is significantly less than the other devices described. While one skilled in the art may consider this to be wasteful and / or to add additional resistance due to the doping or length of the thick drift layer, in doing so, the devices of the present disclosure can block high voltages and survive radiation events while maintaining a smaller amount of on-state resistance losses. Additionally, the devices of the present disclosure may be more cost effective to produce because the buffer layer 83 of the semiconductor device 80 is a complex structure to manufacture and the lightly doped nature of the large lightly doped epitaxial layers 34 and 54 of the first prior art device 30 and the second prior art device 50, respectively, results in a more costly epitaxial layer having a higher resistivity.

[0022] 5A, a radiation hardened semiconductor device 100 is shown. The radiation hardened semiconductor device 100 includes a p-type layer 102, a drift layer 104 (e.g., a large highly doped epitaxial layer, etc.), a substrate 106, and a junction 108. The drift layer 104 is designed to enable the radiation hardened semiconductor device 100 to block high voltages and survive radiation events while maintaining relatively low on-state resistance losses compared to a depleted device. In some embodiments, the drift layer 104 has a 1×10 15 cm -3 and 1.5×10 16 cm -3and a thickness between 15 μm and 200 μm. In some embodiments, for use with a maximum voltage rating of about 1200 V, the drift layer 104 includes a thickness between 15 μm and 50 μm, and for use with a maximum voltage rating of about 4500 V, the drift layer 104 includes a thickness between 50 μm and 200 μm. As used herein, the drift layer 104 is highly doped compared to the large lightly doped epitaxial layers 34 and 54 described above. The drift layer 104 has less doping compared to the substrate 106.

[0023] The electric field resulting from operating the radiation hardened semiconductor device 100 at its highest voltage rating is shown in FIG. 5B. Specifically, FIG. 5B illustrates a one-dimensional cross-sectional graph of the radiation hardened semiconductor device 100 operating at the breakdown voltage, with the x-axis being linear distance and the y-axis being electric field magnitude. The radiation hardened semiconductor device 100 is a 1.2 kV class device. As illustrated by graph 110, the resulting electric field profile is a substantially triangular electric field. This is due to the radiation hardened semiconductor device 100 being depleted at about 80% or less, or in other words, the electric field penetrating only 80% of the drift layer 104. In this case, the electric field profile penetrates about 40% of the large drift layer 104. As shown in graph 110, the depletion of the radiation hardened semiconductor device 100 is illustrated by how deep the electric field profile extends into the drift layer 104 toward the junction 108 and substrate 106.

[0024] Compared to the devices described above, the additional thickness and doping of the drift layer 104 results in a device in which no more than 80% of the drift layer 104 is depleted when breakdown occurs while operating at the highest voltage rating. Because the drift layer 104, and in turn the radiation-hardened semiconductor device 100, is not fully depleted, the radiation-hardened semiconductor device 100 is able to withstand radiation events while minimizing and / or optimizing on-state resistance losses.

[0025] In some embodiments, the drift layer 104 may be less than 60% depleted, so that the electric field extends less than 60% into the drift layer 104 when operating at a given maximum operating voltage. In another embodiment, the drift layer 104 may be less than 50% to 20% depleted. The radiation-hardened semiconductor device 100 may be a unipolar radiation-hardened semiconductor device. By way of example, the radiation-hardened semiconductor device 100 may be a silicon carbide diode or a metal-oxide-semiconductor field-effect transistor (MOSFET). Additionally, the radiation-hardened semiconductor device 100 may be a junction barrier Schottky (JBS) diode.

[0026] Compared to the conventional semiconductor device 10, the radiation hardened semiconductor device 100 maintains a similar doping level of the drift layer 104 compared to the epitaxial layer 14 of a non-hardened device design at the same voltage rating. In contrast, the radiation hardened semiconductor device 100 includes a significantly thicker drift layer 104 compared to the epitaxial layer 14. The thickness of the drift layer 104 has been found to achieve the advantages described herein as it relates to blocking high voltages, surviving radiation events, avoiding full depletion, and optimizing on-state resistance losses. By increasing the thickness of the drift layer 104 and maintaining a similar doping relative to the conventional semiconductor device 10, radiation hardening is achieved in the radiation hardened semiconductor device 100.

[0027] In some embodiments, by including a more highly doped and thicker drift layer, radiation-hardened semiconductor device 100 is substantially less susceptible to single event effects and / or single event burn-out, which may occur when a semiconductor device is struck by heavy ions, beta radiation, gamma radiation, or neutrons while operating near its maximum voltage rating, which is a known failure point for conventional semiconductor devices 10.

[0028] 6A and 6B, graphs 120 and 122 illustrate curves of example designs for known semiconductor power devices, including the radiation-hardened semiconductor device 100 of FIG. 5. Similar to graph 26, graph 120 illustrates drift layer resistance as a function of drift doping. Similar to graph 28, graph 122 illustrates drift layer thickness as a function of drift doping. Triangular field breakdown limits are illustrated by diagonal lines in both graphs 120 and 122. The drift layer resistance, drift doping, and drift layer thickness of radiation-hardened semiconductor device 100 are provided as point 101 in both graphs 120 and 122.

[0029] As shown in graph 120, radiation hardened semiconductor device 100 includes drift doping and drift layer resistance, as shown at point 31 in relation to first prior art device 30 and at point 51 in relation to second prior art device 50, which is greater than the conventional 1.2 kV class design device described above, but less than the 4.5 kV class design device described above. Similarly, as shown in graph 122, radiation hardened semiconductor device 100 includes drift doping comparable to the conventional 1.2 kV class design device and greater than the 4.5 kV class design device described above. Finally, radiation hardened semiconductor device 100 has a drift layer thickness greater than the conventional 1.2 kV class design device, but comparable to the 4.5 kV class design device described above. As discussed above, because radiation hardened semiconductor device 100 includes a thicker drift layer that is more heavily doped, the device is able to withstand radiation events unlike conventional semiconductor devices. This is due to the drift layer not being fully depleted at the breakdown voltage, by at least a 20% margin, contrary to the conventional design curves shown in graphs 120 and 122. The design process for radiation hardened semiconductor device 100 allows for devices having combinations of doping concentrations and thicknesses that are outside of designs resulting from conventional design processes.

[0030] As shown in Figure 7, in designing and forming a radiation hardened semiconductor device 100, a substrate 106 is prepared. In step 710, an epitaxial growth chamber is used to grow and / or form a drift layer 104 on the substrate 106. In step 720, source, gate, and drain structures are formed over the drift layer 104. In step 730, a drift layer doping concentration and a drift layer thickness (n) are selected as discussed above. Finally, in step 740, a drift layer 104 is formed having a drift layer doping concentration and a drift layer thickness at least 20% greater than n.

[0031] As discussed above, the device of the present disclosure can block high voltages and survive radiation events while maintaining and enabling a smaller amount of on-state resistance loss. This results in the device being optimized and more cost-effective to manufacture than the known devices mentioned above. In comparison to the buffer layer 83 of the semiconductor device 80 making the structure complicated to manufacture, and the lightly doped nature of the large lightly doped epitaxial layers 34 and 54 of the first prior art device 30 and the second prior art device 50, respectively, making the epitaxial layers more expensive with higher on-state resistance loss, this approach provides an additional advantage while making the device more cost-effective.

[0032] Further aspects of the present disclosure are provided by the subject matter of the following sections.

[0033] A semiconductor device comprising a highly doped substrate and a drift layer disposed on the highly doped substrate, the drift layer having a doping concentration and a thickness such that an electric field profile in the drift layer extends less than 80% of the thickness of the drift layer when the semiconductor device is operated at a predetermined target operating voltage.

[0034] The semiconductor device of any preceding clause, wherein the electric field profile is substantially triangular.

[0035] The semiconductor device of any preceding clause, wherein the electric field profile in the drift layer extends through less than 60% of the thickness of the drift layer when the semiconductor device is operated at the predetermined target operating voltage.

[0036] The semiconductor device of any preceding clause, wherein the electric field profile in the drift layer extends through less than 50% of the thickness of the drift layer when the semiconductor device is operated at the predetermined target operating voltage.

[0037] The semiconductor device of any preceding clause, wherein when the semiconductor device is operated at a predetermined target operating voltage, the electric field profile in the drift layer extends through less than 30% of the thickness of the drift layer.

[0038] The semiconductor device of any preceding clause, wherein the electric field profile in the drift layer extends through less than 20% of the thickness of the drift layer when the semiconductor device is operated at the predetermined target operating voltage.

[0039] The semiconductor device of any preceding clause, wherein the electric field profile in the drift layer extends through less than 45% of the thickness of the drift layer when the semiconductor device is operated at the predetermined target operating voltage.

[0040] The semiconductor device of any preceding clause, wherein the semiconductor device is a unipolar radiation hardened semiconductor device.

[0041] The semiconductor device of any preceding clause, wherein the semiconductor device is a silicon carbide diode or a metal oxide semiconductor field effect transistor (MOSFET).

[0042] The semiconductor device of any preceding clause, wherein the predetermined target operating voltage is 1.2 kV.

[0043] The semiconductor device of any preceding clause, wherein the electric field profile in the drift layer extends 17 μm into the drift layer at the predetermined target operating voltage.

[0044] When a semiconductor device operates at a given target operating voltage, the doping concentration of the drift layer is 6×10^15 cm -3 and 1.5×10^16cm -3 and the thickness of the drift layer is between 15 μm and 50 μm.

[0045] The semiconductor device of any preceding clause, wherein the predetermined target operating voltage is 4.5 kV.

[0046] The semiconductor device of any preceding clause, wherein the electric field profile in the drift layer extends 54 μm into the drift layer at the predetermined target operating voltage.

[0047] When a semiconductor device operates at a given target operating voltage of 4500V, the doping concentration of the drift layer is 1×10^15 cm -3 and 2×10^15cm -3 and the thickness of the drift layer is between 50 μm and 200 μm.

[0048] A method of forming a semiconductor of any preceding clause, comprising forming a drift layer on a substrate through epitaxy; and forming source, gate, and drain structures over the drift layer.

[0049] The method of forming a semiconductor of any preceding clause, comprising selecting a drift layer doping concentration and a drift layer thickness (n) based on reducing the on-state resistance of the drift layer at a given operating voltage, and forming a drift layer having a drift layer doping concentration and a drift layer thickness that is at least 20% greater than n.

[0050] 1. A semiconductor device comprising: a highly doped substrate; and a drift layer on the highly doped substrate, the drift layer having a doping concentration and a thickness, the doping concentration selected based on reducing a drift layer resistance of the drift layer operating at a predetermined target operating voltage, wherein an electric field profile in the drift layer extends n μm into the drift layer at the predetermined target operating voltage, and the thickness of the drift layer is at least 20% greater than n μm.

[0051] The semiconductor device of any preceding clause, wherein the drift layer has a thickness at least 40% greater than n μm when the semiconductor device operates at a predetermined target operating voltage.

[0052] The semiconductor device of any preceding clause, wherein the drift layer has a thickness at least 50% greater than n μm when the semiconductor device operates at a predetermined target operating voltage.

[0053] This description uses examples to disclose the disclosure, including the best mode, and further to enable those skilled in the art to practice the disclosure, including making and using any device or system, and performing any incorporated methods. The patentable scope of the disclosure is defined by the claims, and may include other examples that occur to those skilled in the art. Such other examples are intended to be within the scope of the claims if they include structural elements that do not differ from the literal words of the claims, or if they include equivalent structural elements that have insignificant differences from the literal words of the claims.

[0054] Further aspects of the invention are provided by the subject matter of the following sections. [Section 1] A highly doped substrate; a drift layer disposed on the highly doped substrate, the drift layer having a doping concentration and a thickness; a semiconductor device, wherein the doping concentration and the thickness of the drift layer are such that an electric field profile in the drift layer extends through less than 80% of the thickness of the drift layer when the semiconductor device operates at a predetermined target operating voltage. [Section 2] 13. The semiconductor device of any preceding claim, wherein the electric field profile is substantially triangular. [Section 3] 13. The semiconductor device of any preceding claim, wherein the electric field profile in the drift layer extends through less than 60% of the thickness of the drift layer when the semiconductor device is operated at the predetermined target operating voltage. [Section 4] 13. The semiconductor device of any preceding claim, wherein the electric field profile in the drift layer extends through less than 50% of the thickness of the drift layer when the semiconductor device is operated at the predetermined target operating voltage. [Section 5] 13. The semiconductor device of any preceding claim, wherein the electric field profile in the drift layer extends through less than 30% of the thickness of the drift layer when the semiconductor device is operated at the predetermined target operating voltage. [Section 6] 13. The semiconductor device of any preceding claim, wherein the electric field profile in the drift layer extends through less than 20% of the thickness of the drift layer when the semiconductor device is operated at the predetermined target operating voltage. [Section 7] 13. The semiconductor device of any preceding claim, wherein the electric field profile in the drift layer extends through less than 45% of the thickness of the drift layer when the semiconductor device is operated at the predetermined target operating voltage. [Section 8] 13. The semiconductor device of any preceding claim, wherein the semiconductor device is a unipolar radiation hardened semiconductor device. [Section 9] 13. The semiconductor device of any preceding claim, wherein the semiconductor device is a silicon carbide diode or a metal oxide semiconductor field effect transistor (MOSFET). [Section 10] 13. The semiconductor device of any preceding claim, wherein the predetermined target operating voltage is 1.2 kV. [Section 11] 13. The semiconductor device of any preceding claim, wherein the electric field profile in the drift layer extends 17 μm into the drift layer at the predetermined target operating voltage. [Section 12] When the semiconductor device is operated at the predetermined target operating voltage, the doping concentration of the drift layer is 6×10 15 cm -3 and 1.5×10 16 cm -3 and the thickness of the drift layer is between 15 μm and 50 μm. [Section 13] 13. The semiconductor device of any preceding claim, wherein the predetermined target operating voltage is 4.5 kV. [Section 14] 13. The semiconductor device of any preceding claim, wherein the electric field profile in the drift layer extends 54 μm into the drift layer at the predetermined target operating voltage. [Section 15] When the semiconductor device is operated at the predetermined target operating voltage of 4500 V, the doping concentration of the drift layer is 1×10 15 cm -3 and 2×10 15 cm -3 and the thickness of the drift layer is between 50 μm and 200 μm. [Section 16] forming the drift layer on the substrate via epitaxy; and forming source, gate and drain structures over the drift layer. [Section 17] selecting a drift layer doping concentration and a drift layer thickness (n) based on reducing an on-state resistance of the drift layer at a given operating voltage; and forming said drift layer having said drift layer doping concentration and said drift layer thickness at least 20% greater than n. [Section 18] A highly doped substrate; a drift layer on the highly doped substrate, the drift layer having a doping concentration and a thickness; the doping concentration is selected based on reducing a drift layer resistance of the drift layer operating at a predetermined target operating voltage; an electric field profile in the drift layer extends n μm into the drift layer at the given target operating voltage; A semiconductor device, wherein the thickness of the drift layer is at least 20% greater than n μm. [Section 19] 13. The semiconductor device of any preceding claim, wherein the thickness of the drift layer is at least 40% greater than n μm when the semiconductor device is operated at the predetermined target operating voltage. [Section 20] 13. The semiconductor device of any preceding claim, wherein the thickness of the drift layer is at least 50% greater than n μm when the semiconductor device is operated at the predetermined target operating voltage. [Explanation of symbols]

[0055] 10 Conventional Semiconductor Devices 11 Gate electrode 12 p-type layer 13 Gate dielectric layer 14 Drift layer, depletion layer, epitaxial layer 15 Drain region 16 Base material 17 Source Area 18 Junction 19 Junction 22 One-dimensional cross-sectional graph 26 Graphs 28 Graphs 30 First Prior Art Device 31 points 32 p-type layer 34 Large lightly doped epitaxial layers 36 Highly doped substrate 38 Junction 40 Graphs 50 Second Prior Art Device 51 points 52 p-type layer 54 Large lightly doped epitaxial layers 56 Highly doped substrate 58 Junction 60 Graphs 80 Semiconductor Devices 82 p-type layer 83 Buffer Layer 84 Drift Layer 85 Buffer Junction 86 Base material 87 Base material bonding 100 Radiation-hardened semiconductor devices 101 points 102 p-type layer 104 Drift Layer 106 Base material 108 Junction 110 Graph 120 Graphs 122 Graphs

Claims

1. A highly doped substrate; a drift layer disposed on the highly doped substrate, the drift layer having a doping concentration and a thickness; a semiconductor device, wherein the doping concentration and the thickness of the drift layer are such that an electric field profile in the drift layer extends through less than 80% of the thickness of the drift layer when the semiconductor device is operated at a predetermined target operating voltage.

2. The semiconductor device of claim 1 , wherein the electric field profile is substantially triangular.

3. 2. The semiconductor device of claim 1, wherein the electric field profile in the drift layer extends through less than 60% of the thickness of the drift layer when the semiconductor device is operated at the predetermined target operating voltage.

4. 2. The semiconductor device of claim 1, wherein the electric field profile in the drift layer extends through less than 50% of the thickness of the drift layer when the semiconductor device is operated at the predetermined target operating voltage.

5. 2. The semiconductor device of claim 1, wherein the electric field profile in the drift layer extends through less than 30% of the thickness of the drift layer when the semiconductor device is operated at the predetermined target operating voltage.

6. 2. The semiconductor device of claim 1, wherein the electric field profile in the drift layer extends through less than 20% of the thickness of the drift layer when the semiconductor device is operated at the predetermined target operating voltage.

7. 2. The semiconductor device of claim 1, wherein the electric field profile in the drift layer extends through less than 45% of the thickness of the drift layer when the semiconductor device is operated at the predetermined target operating voltage.

8. The semiconductor device of claim 1 , wherein the semiconductor device is a unipolar radiation hardened semiconductor device.

9. The semiconductor device of claim 1 , wherein the semiconductor device is a silicon carbide diode or a metal oxide semiconductor field effect transistor (MOSFET).

10. 2. The semiconductor device of claim 1, wherein the predetermined target operating voltage is 1.2 kV.

11. 11. The semiconductor device of claim 10, wherein the electric field profile in the drift layer extends 17 μm into the drift layer at the predetermined target operating voltage.

12. When the semiconductor device is operated at the predetermined target operating voltage, the doping concentration of the drift layer is 6×10 １５ cm －３ and 1.5 x 10 １６ cm －３ 11. The semiconductor device of claim 10, wherein the thickness of the drift layer is between 15 μm and 50 μm.

13. 2. The semiconductor device of claim 1, wherein the predetermined target operating voltage is 4.5 kV.

14. 14. The semiconductor device of claim 13, wherein the electric field profile in the drift layer extends 54 μm into the drift layer at the predetermined target operating voltage.

15. When the semiconductor device is operated at the predetermined target operating voltage of 4500 V, the doping concentration of the drift layer is 1×10 １５ cm －３ and 2 x 10 １５ cm －３ 14. The semiconductor device of claim 13, wherein the thickness of the drift layer is between 50 μm and 200 μm.

16. forming the drift layer on the substrate via epitaxy; 2. The method of forming a semiconductor device of claim 1, further comprising forming source, gate and drain structures over the drift layer.

17. selecting a drift layer doping concentration and a drift layer thickness (n) based on reducing the on-state resistance of the drift layer at a given operating voltage; forming the drift layer having the drift layer doping concentration and the drift layer thickness at least 20% greater than n.

18. A highly doped substrate; a drift layer on the highly doped substrate, the drift layer having a doping concentration and a thickness; the doping concentration is selected based on reducing a drift layer resistance of the drift layer operating at a predetermined target operating voltage; an electric field profile in the drift layer extends n μm into the drift layer at the given target operating voltage; A semiconductor device, wherein the thickness of the drift layer is at least 20% greater than n μm.

19. 20. The semiconductor device of claim 18, wherein the thickness of the drift layer is at least 40% greater than n μm when the semiconductor device is operated at the predetermined target operating voltage.

20. 20. The semiconductor device of claim 18, wherein the thickness of the drift layer is at least 50% greater than n μm when the semiconductor device is operated at the predetermined target operating voltage.

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