Power semiconductor device and power conversion device including the same
By optimizing the doping concentration and depth of conductivity type wells in a power semiconductor device, the electric field concentration at trench corners is dispersed, preventing gate oxide breakdown and reducing cell pitch issues, thereby enhancing the device's performance.
Patent Information
- Application Number
- JP2024144164
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2023-09-19
- Filing Date
- 2024-08-26
- Publication Date
- 2025-04-01
AI Technical Summary
The challenge in power semiconductor devices, particularly in SiC Trench MOSFETs, is to prevent gate oxide breakdown due to electric field concentration at the trench corners and to avoid reducing cell pitch caused by ion implantation side straggling.
The solution involves forming a power semiconductor device with a substrate and multiple epi layers of specific conductivity types, including first and second wells of different conductivity types. The device includes a trench gate structure with a gate insulating layer and a trench gate electrode, where the doping concentration and depth of the wells are optimized to disperse electric fields and prevent breakdown.
This approach effectively prevents gate oxide breakdown and reduces the risk of cell pitch reduction due to side straggling, while also increasing breakdown voltage and improving current density.
Smart Images
Figure 2025044140000001_ABST
Abstract
Description
[Technical field]
[0001] The embodiments relate to a power semiconductor element, a power semiconductor module, a power conversion device, and a manufacturing method thereof. [Background technology]
[0002] Power semiconductors are one of the key elements that determine the efficiency, speed, durability and reliability of power electronic systems.
[0003] Recently, with the development of the power electronics industry, the silicon ((Silicon)Si) power semiconductors that have been used until now have reached their physical limits, and research into WBG (Wide Bandgap) power semiconductors such as silicon carbide ((Silicon Carbide)SiC) and gallium nitride ((Galium Nitride)GaN) as replacements is being actively conducted.
[0004] WBG power semiconductor elements have a band gap energy approximately three times that of Si power semiconductor elements, which gives them the following characteristics: low intrinsic carrier concentration, high dielectric breakdown field (approximately 4 to 20 times), high thermal conductivity (approximately 3 to 13 times), and large electron saturation velocity (approximately 2 to 2.5 times).
[0005] These characteristics allow them to operate in high-temperature, high-voltage environments, and they have high switching speeds and low switching losses. Among these, gallium nitride (GaN) power semiconductor elements can be used in low-voltage systems, while silicon carbide (SiC) power semiconductor elements are suitable for high-voltage systems.
[0006] Conventional SiC MOSFET power semiconductors are generally referred to as VDMOSFETs, which stand for vertical diffused structure, and can also be simply referred to as DMOSFETs, which have a double-diffused structure. SiC MOSFETs can also be classified into planar MOSFETs and trench MOSFETs depending on the channel direction.
[0007] Among them, the trench MOSFET has a structure in which a channel is formed on the sidewall of a trench. For this purpose, a gate insulating film is formed on the sidewall of the trench, and a gate electrode is formed in the trench.
[0008] SiC MOSFET has high on-resistance due to low channel mobility and large channel resistance, so trench MOSFET has been proposed to reduce this. Trench MOSFET has the advantage of increasing channel density by forming a channel on the trench sidewall.
[0009] However, trench MOSFETs have a problem in that the trench gate oxide, which has a shorter drift distance than the P-base (P-well), has a larger electric field, and the electric field is concentrated especially at the trench edge, which causes the gate oxide to break down early and reduces the BV (breakdown voltage).
[0010] For example, in the case of SiC Trench MOSFET, the breakdown electric field strength is 10 times that of silicon (Si), so SiC semiconductor devices are used under conditions where a voltage nearly 10 times that of Si devices is applied. As a result, the gate insulating film formed in the trench is also subjected to an electric field 10 times stronger than that of silicon devices, which creates the problem that the gate insulating film can easily break down at the corners of the trench.
[0011] In order to prevent electric field concentration at the corners of the trench, internal technology is researching a process to form a p-type well (P-base) deeper than the gate trench, but forming such a deep p-type well requires ion implantation energy that exceeds the level of a typical process.In addition, high-energy ion implantation causes severe ion implantation outside the target area, which leads to a problem of reduced cell pitch due to difficulty in controlling lateral straggling. Summary of the Invention [Problem to be solved by the invention]
[0012] One of the technical objectives of the power semiconductor device and the power conversion device and the method for manufacturing the power semiconductor device according to the embodiments is to prevent the problem of a reduction in cell pitch due to lateral straggling while preventing electric field concentration at the corners of the trench.
[0013] The technical problems of the embodiments are not limited to those described in this section, but include those that can be understood from the description of the invention. [Means for solving the problem]
[0014] The power semiconductor device according to the embodiment includes a substrate 111, a first epitaxial layer 112a of a first conductivity type disposed on the substrate 111, a second epitaxial layer 112b of a first conductivity type disposed on the first epitaxial layer 112a of the first conductivity type, a first well 121a of a second conductivity type partially formed in the first epitaxial layer 112a of the first conductivity type, a second well 121b of a second conductivity type formed in the second epitaxial layer 112b of the first conductivity type, and an ion implantation layer of a second conductivity type disposed in the second well 121b of the second conductivity type. The semiconductor device may include an implantation region 122 and a source region 115, a source electrode 142 disposed on the source region 115, a gate insulating layer 131 formed in a trench region T in which the second conductive type ion implantation region 122 and a portion of the first conductive type second epitaxial layer 112b have been removed, a trench gate 132 disposed on the gate insulating layer 131, an interlayer insulating layer 150 disposed on the trench gate 132, and a gate electrode electrically connected to the trench gate 132.
[0015] In an embodiment, a side surface of the first well 121a of the second conductivity type and a side surface of the second well 121b of the second conductivity type may be aligned upward on the substrate.
[0016] A doping concentration of a first well of a second conductivity type formed in the first epilayer of the first conductivity type may be different from a doping concentration of a second well of a second conductivity type formed in the second epilayer of the first conductivity type.
[0017] The doping concentration of the first well 121a of the second conductivity type formed in the first epitaxial layer 112a of the first conductivity type may be higher than the doping concentration of the second well 121b of the second conductivity type formed in the second epitaxial layer 112b of the first conductivity type.
[0018] The doping concentration of a first well of a second conductivity type formed under the trench gate may have a concentration gradient that changes abruptly from the doping concentration of a second well of a second conductivity type formed adjacent to the trench gate.
[0019] The doping concentration of the first well of the second conductivity type is 2×10 17 ~2×10 19 / cm 3 and the doping concentration of the second well of the second conductivity type is 1×10 16 ~1×10 17 / cm 3 may be also.
[0020] An interface is formed between the first well of the second conductivity type formed in the first epitaxial layer 112a of the first conductivity type and the second well 121b of the second conductivity type.
[0021] The interface between the first well of the second conductivity type and the second well of the second conductivity type is located at substantially the same position as a lower surface of the trench gate.
[0022] A first distance between the first wells of a second conductivity type formed in the first epilayer of the first conductivity type and a second distance between the second wells of a second conductivity type formed in the second epilayer of the first conductivity type may be different.
[0023] A first distance D1 between first wells of a second conductivity type formed in the first epitaxial layer 112a of the first conductivity type may be longer than a second distance D2 between second wells 121b of a second conductivity type formed in the second epitaxial layer 112b of the first conductivity type.
[0024] A part of a lower corner of the second well of the second conductivity type does not have to overlap vertically with the first well of the second conductivity type.
[0025] The first well of the second conductivity type is disposed below the trench gate, and the second well of the second conductivity type is disposed horizontally of the trench gate.
[0026] The depth of the second well of the second conductivity type may be different from the depth of the first well of the second conductivity type. The depth of the second well of the second conductivity type may be lower than the depth of the first well of the second conductivity type.
[0027] Also, a power conversion device according to the embodiment may include any one of the power semiconductor devices.
[0028] Also, a method for manufacturing a power semiconductor device according to the embodiment includes the steps of growing a first epitaxial layer 112a of a first conductivity type on a substrate 111, implanting ions into the first epitaxial layer 112a of the first conductivity type to partially form a first well 121a of a second conductivity type, growing a second epitaxial layer 112b of the first conductivity type on the first epitaxial layer 112a of the first conductivity type, implanting ions into the second epitaxial layer 112b of the first conductivity type to partially form a second well 121b of a second conductivity type, and growing the second well 121a of the second conductivity type on the first epitaxial layer 112a of the first conductivity type. The method may include forming a second conductive type ion implantation region 122 and a source region 115 in the first conductive type second epitaxial layer 121b, forming a trench region T by removing a portion of the second conductive type ion implantation region 122 and the first conductive type second epitaxial layer 112b, forming a gate insulating layer 131 and a trench gate 132 in the trench region, forming an interlayer insulating layer 150 on the trench gate 132, and forming a gate electrode electrically connected to the trench gate 132.
[0029] A side surface of the first well 121a of the second conductivity type and a side surface of the second well 121b of the second conductivity type may be aligned upward on the substrate.
[0030] The doping concentration of the first well 121a of the second conductivity type formed in the first epitaxial layer 112a of the first conductivity type may be higher than the doping concentration of the second well 121b of the second conductivity type formed in the second epitaxial layer 112b of the first conductivity type.
[0031] A first distance D1 between first wells of a second conductivity type formed in the first epitaxial layer 112a of the first conductivity type may be longer than a second distance D2 between second wells 121b of a second conductivity type formed in the second epitaxial layer 112b of the first conductivity type. Effect of the Invention
[0032] According to the power semiconductor device and the power conversion device including the same and the method for manufacturing the power semiconductor device according to the embodiments, there is a technical effect of preventing the problem of pitch reduction due to lateral straggling while preventing electric field concentration at the corners of the trench.
[0033] For example, in the power semiconductor device 100 according to the embodiment, the second conductivity type well 121 is formed without using high energy ion implantation, thereby preventing the problem of pitch reduction due to lateral straggling of dopants, and the second conductivity type second well 121b is formed in a region deeper than the trench, thereby making it possible to disperse the electric field concentrated at the gate trench bottom corner, thereby preventing destruction of the gate insulating layer.
[0034] In addition, according to the embodiment, the doping concentration of the first well 121a of the second conductivity type formed under the trench gate 132 is higher than the doping concentration of the second well 121b of the second conductivity type, which has the effect of expanding a depletion layer toward the substrate 111, thereby providing a technical effect of increasing the breakdown voltage. In addition, according to the embodiment, the doping concentration of the second well 121b of the second conductivity type formed around the trench gate 132 is lower than the doping concentration of the first well 121a of the second conductivity type, which provides a composite technical effect of decreasing the threshold voltage and increasing the current density.
[0035] Furthermore, according to the second embodiment, the first distance D1 between the third wells 121c of the second conductivity type formed in the first epitaxial layer 112a of the first conductivity type may be longer than the second distance D2 between the second wells 121b of the second conductivity type formed in the second epitaxial layer 112b of the first conductivity type.
[0036] According to the second embodiment, the first distance D1 between the third wells 121c of the second conductivity type formed under the trench gates 132 is controlled to be longer than the second distance D2 between the second wells 121b of the second conductivity type formed around the trench gates 132, thereby increasing the movement width of electrons, thereby producing a special technical effect of reducing Ron.
[0037] The technical effects of the embodiments are not limited to those described in this section, but include those that can be understood from the description of the invention. [Brief description of the drawings]
[0038] [Figure 1] FIG. 1 is a diagram illustrating a configuration example of a power conversion device 1000 according to an embodiment. [Diagram 2] FIG. 2 is a cross-sectional view of a power semiconductor device 100 according to an embodiment. [Diagram 3] FIG. 3 is a cross-sectional view of a power semiconductor device 100 according to an embodiment. [Figure 4] FIG. 4 is a cross-sectional view of a power semiconductor element 102 according to the second embodiment. [Diagram 5] FIG. 5 is a cross-sectional view illustrating a manufacturing process of the power semiconductor element 100 according to the embodiment. [Figure 6] FIG. 6 is a cross-sectional view illustrating a manufacturing process of the power semiconductor element 100 according to the embodiment. [Figure 7] FIG. 7 is a cross-sectional view illustrating a manufacturing process of the power semiconductor element 100 according to the embodiment. [Figure 8] FIG. 8 is a cross-sectional view illustrating a manufacturing process of the power semiconductor element 100 according to the embodiment. [Figure 9] FIG. 9 is a cross-sectional view illustrating a manufacturing process of the power semiconductor element 100 according to the embodiment. [Figure 10] FIG. 10 is a cross-sectional view illustrating a manufacturing process of the power semiconductor element 100 according to the embodiment. [Figure 11] FIG. 11 is a cross-sectional view illustrating a manufacturing process of the power semiconductor element 100 according to the embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0039] Hereinafter, the invention according to the embodiment for solving the above problems will be described in more detail with reference to the drawings.
[0040] The suffixes "module" and "section" for components used in the following description are merely given to facilitate the writing of the specification and do not impart any particular significance or role to the components themselves. Therefore, the terms "module" and "section" can be used interchangeably.
[0041] Terms including ordinal numbers such as first, second, etc. may be used to describe various components, but the components are not limited by the terms. The terms are used only to distinguish one component from another.
[0042] A singular expression includes a plural expression unless the context clearly indicates otherwise.
[0043] In this application, the terms "including," "having," or "comprising" are intended to specify the presence of any feature, number, step, operation, component, part, or combination thereof set forth in the specification, but are not to be understood as precluding the presence or additional possibility of one or more other features, number, steps, operations, components, parts, or combinations thereof.
[0044] (Example) FIG. 1 is a diagram illustrating a configuration example of a power conversion device 1000 according to an embodiment.
[0045] The power conversion device 1000 according to the embodiment can receive DC power from a battery or a fuel cell, convert it into AC power, and supply the AC power to a predetermined load. For example, the power conversion device 1000 according to the embodiment can include an inverter, receive DC power from a battery, convert it into three-phase AC power, and supply it to a motor M, and the motor M can provide power to an electric vehicle, a fuel cell vehicle, etc.
[0046] The power conversion device 1000 according to the embodiment may include a power semiconductor device 100. The power semiconductor device 100 may be, but is not limited to, a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), and may include an Insulated Gate Bipolar Transistor (IGBT).
[0047] For example, the power conversion device 1000 may include a plurality of power semiconductor devices 100a, 100b, 100c, 100d, 100e, and 100f, and may include a plurality of diodes (not shown). Each of the plurality of diodes may be included in the power semiconductor devices 100a, 100b, 100c, 100d, 100e, and 100f in the form of an internal diode, but is not limited thereto, and may be disposed separately.
[0048] The embodiment can convert DC power into AC power by controlling the on / off of the multiple power semiconductor elements 100a to 100f. For example, the power conversion device 1000 according to the embodiment can supply positive polarity power to the motor M by turning on the first power semiconductor element 100a and turning off the second power semiconductor element 100b in a first time interval of one cycle, and supply negative polarity power to the motor M by turning off the first power semiconductor element 100a and turning on the second power semiconductor element 100b in a second time interval of one cycle.
[0049] In the embodiment, a group of power semiconductor elements arranged in series on the high voltage line and the low voltage line on the input side may be called an arm. For example, the first power semiconductor element 100a and the second power semiconductor element 100b may form a first arm, the third power semiconductor element 100c and the fourth power semiconductor element 100d may form a second arm, and the fifth power semiconductor element 100e and the sixth power semiconductor element 100f may form a third arm.
[0050] The upper and lower power semiconductor devices in each arm are controlled not to be turned on at the same time. For example, the first and second power semiconductor devices 100a and 100b in the first arm are not turned on at the same time but can be turned on and off alternately.
[0051] A high voltage is applied to each of the power semiconductor elements 100a-100f when the elements are turned off. For example, when the first power semiconductor element 100a is turned on and the second power semiconductor element 100b is turned off, the input voltage is applied to the second power semiconductor element 100b as is. The voltage input to the second power semiconductor element 100b is a relatively high voltage, and the withstand voltage of each of the power semiconductor elements 100a-100f is designed to be at a high level so that the elements can withstand such a high voltage.
[0052] Each of the power semiconductor elements 100a to 100f can conduct a high current when it is turned on. The motor M is driven by a relatively high current, and this high current is supplied to the motor M through the power semiconductors that are turned on.
[0053] A high voltage applied to each of the power semiconductor elements 100a-100f may induce high switching loss. A high current passing through the power semiconductor elements 100a-100f may induce high conduction loss. In order to dissipate heat generated by such losses, the power semiconductor elements 100a-100f may be packaged in a power semiconductor module including a heat dissipation means.
[0054] The power semiconductor device 100 of the embodiment may be a silicon carbide (SiC) power semiconductor device, which is capable of operating in a high temperature and high voltage environment and has a high switching speed and low switching loss.
[0055] Meanwhile, the power conversion device 1000 according to the embodiment may include a plurality of power semiconductor modules.
[0056] For example, the multiple power semiconductor elements 100a to 100f shown in FIG. 1 may be packaged in one power semiconductor module, or the power semiconductor elements constituting each arm may be packaged in one power semiconductor module.
[0057] For example, the first power semiconductor device 100a, the second power semiconductor device 100b, the third power semiconductor device 100c, the fourth power semiconductor device 100d, the fifth power semiconductor device 100e, and the sixth power semiconductor device 100f shown in FIG. 1 may be packaged into one power semiconductor module.
[0058] In order to increase the current capacity, additional power semiconductor elements may be arranged in parallel with each of the power semiconductor elements 100a to 100f. In this case, the number of power semiconductor elements included in the power semiconductor module may be more than six.
[0059] The power converter 1000 according to the embodiment may include a diode-type power semiconductor element in addition to the transistor-type power semiconductor elements 100a to 100f. For example, a first diode (not shown) may be arranged in parallel with the first power semiconductor element 100a, and a second diode (not shown) may be arranged in parallel with the second power semiconductor element 100b. Such diodes may also be packaged together in one power semiconductor module. The diodes may also be arranged in the form of internal diodes in each power semiconductor element.
[0060] Next, the power semiconductor elements constituting each arm may be packaged into one power semiconductor module.
[0061] For example, the first power semiconductor element 100a and the second power semiconductor element 100b constituting the first arm may be packaged in a first power semiconductor module, the third power semiconductor element 100c and the fourth power semiconductor element 100d constituting the second arm may be packaged in a second power semiconductor module, and the fifth power semiconductor element 100e and the sixth power semiconductor element 100f constituting the third arm may be packaged in a third power semiconductor module.
[0062] In addition, there may be additional power semiconductor elements arranged in parallel with each of the power semiconductor elements 100a-100f to increase the current capacity, and in this case, the number of power semiconductor elements included in each power semiconductor module may be more than two. Each arm may also include a diode-type power semiconductor element (not shown) in addition to the transistor-type power semiconductor elements 100a-100f, and such a diode may also be packaged together in one power semiconductor module. The diode may also be arranged in the form of an internal diode in each power semiconductor element.
[0063] FIG. 2 is a cross-sectional view of one of the power semiconductor devices 100 according to the embodiment.
[0064] The power semiconductor device 100 according to the embodiment may include a source electrode 130 and a gate electrode 175 disposed on a given semiconductor epitaxial layer 120 , and a drain electrode 105 disposed on a lower side of the semiconductor epitaxial layer 120 .
[0065] In the form of a MOSFET, the source electrode 130 or the gate electrode 175 may include an Al-based metal, and the drain electrode 105 may include, but is not limited to, Ti / Ni / Ag metal including a Ti layer, a Ni layer, and an Ag layer, NiV / Ag, V(vanadium) / Ni / Ag, etc.
[0066] One of the technical problems in the embodiment is to prevent the problem of a reduction in cell pitch due to lateral straggling while preventing electric field concentration at the corners of the trench.
[0067] Hereinafter, a power semiconductor device 100 according to an embodiment for solving the above technical problem will be described.
[0068] FIG. 3 is a cross-sectional view of a power semiconductor device 100 according to an embodiment.
[0069] First, referring to FIG. 3, the power semiconductor device 100 of the embodiment may include at least one of a drain electrode 105, a substrate 111, a first conductive type epitaxial layer 112, a second conductive type well 121, a second conductive type ion implantation region 122, a first conductive type source region 115, a source contact region 141, a second conductive type contact region 123, a source electrode 142, a gate insulating layer 131, a gate 132, and an interlayer insulating layer 150.
[0070] The first conductive type epitaxial layer 112 may include a first conductive type first epitaxial layer 112a and a second conductive type second epitaxial layer 112b.
[0071] In addition, the second conductive type well 121 may include a first conductive type well 121a and a second conductive type well 121b.
[0072] The first conductivity type may be N-type and the second conductivity type may be P-type, but is not limited thereto. The substrate 111 and the first conductivity type epitaxial layer 112 may include, but are not limited to, SiC (Silicon Carbide).
[0073] Specifically, the power semiconductor device 100 of the embodiment may include a substrate 111, a first epitaxial layer 112a of a first conductivity type disposed on the substrate 111, and a second epitaxial layer 112b of a first conductivity type disposed on the first epitaxial layer 112a of the first conductivity type.
[0074] The embodiment may also include a first well 121a of a second conductivity type partially formed in the first epitaxial layer 112a of the first conductivity type, and a second well 121b of a second conductivity type formed in the second epitaxial layer 112b of the first conductivity type.
[0075] The embodiment may also include a second conductivity type ion implantation region 122 partially disposed in the second conductivity type second well 121b, a source region 115 disposed on the second conductivity type ion implantation region 122, and a second conductivity type contact region 123.
[0076] The embodiment may also include a source electrode 142 disposed on the source region 115 and the second conductive type contact region 123, a gate insulating layer 131 formed on a bottom surface and sidewalls of a trench region T (see FIG. 11) in which a portion of the second conductive type ion implantation region 122 and the first conductive type second epitaxial layer 112b have been removed, a gate 132 disposed on the gate insulating layer 131, an interlayer insulating layer 150 disposed on the trench gate 132, and a gate electrode (not shown) electrically connected to the trench gate 132.
[0077] According to the power semiconductor device and the power conversion device including the same and the method for manufacturing the power semiconductor device according to the embodiments, there is a technical effect of preventing the problem of pitch reduction due to lateral straggling while preventing electric field concentration at the corners of the trench.
[0078] Lateral straggling refers to an unintended increase in ion implantation in the lateral direction, and when lateral straggling occurs, the electron movement width becomes narrower, resulting in an increase in Ron.
[0079] In order to solve such problems, the power semiconductor device 100 of the embodiment includes a first epitaxial layer 112a of a first conductivity type and a second epitaxial layer 112b of the first conductivity type arranged sequentially on a substrate 111, and includes a first well 121a of a second conductivity type formed in the first epitaxial layer 112a of the first conductivity type and a second well 121b of a second conductivity type formed in the second epitaxial layer 112b of the first conductivity type.
[0080] In the power semiconductor device 100 according to the embodiment, a first epitaxial layer 112a of a first conductivity type is grown on a substrate 111, and then a first well 121a of a second conductivity type is formed in the first epitaxial layer 112a of the first conductivity type by ion implantation. Thereafter, a second epitaxial layer 112b of a first conductivity type is grown on the first epitaxial layer 112a of the first conductivity type, and a second well 121b of a second conductivity type is formed in the second epitaxial layer 112b of the first conductivity type by ion implantation.
[0081] A side surface of the first well 121a of the second conductivity type and a side surface of the second well 121b of the second conductivity type may be aligned upward on the substrate.
[0082] As a result, according to the embodiment, the second conductivity type well 121 is formed without using high energy ion implantation, thereby preventing the problem of pitch reduction due to lateral straggling of dopants, and the second conductivity type second well 121b is formed in a region deeper than the trench, thereby making it possible to disperse the electric field concentrated at the gate trench bottom corner, thereby preventing destruction of the gate insulating layer.
[0083] In addition, the doping concentration of the first well 121a of the second conductivity type formed in the first epitaxial layer 112a of the first conductivity type in the embodiment may be higher than the doping concentration of the second well 121b of the second conductivity type formed in the second epitaxial layer 112b of the first conductivity type.
[0084] For example, according to the embodiment, there is a technical effect of implementing a concentration gradient in which the doping concentration of the first well 121a of the second conductivity type formed under the trench gate 132 changes abruptly from the doping concentration of the second well 121b of the second conductivity type formed adjacent to the trench gate 132.
[0085] For example, the doping concentration of the first well 121a of the second conductivity type is 2×10 17 ~2×10 19 / cm 3 The doping concentration of the second well 121b of the second conductivity type may be 1×10 16 ~1×10 17 / cm 3 It may be, but is not limited to this.
[0086] According to the embodiment, the doping concentration of the first well 121a of the second conductivity type formed under the trench gate 132 is higher than the doping concentration of the second well 121b of the second conductivity type, which has the effect of expanding a depletion layer toward the substrate 111, thereby providing a technical effect of increasing the breakdown voltage. Also, according to the embodiment, the doping concentration of the second well 121b of the second conductivity type formed around the trench gate 132 is lower than the doping concentration of the first well 121a of the second conductivity type, which provides a composite technical effect of decreasing the threshold voltage and increasing the current density.
[0087] Next, FIG. 4 is a cross-sectional view of a power semiconductor device 102 according to a second embodiment.
[0088] The second embodiment can employ the technical features of the embodiments described above, and the following description will focus on the features of the second embodiment.
[0089] Referring to FIG. 4, in the power semiconductor device 102 according to the second embodiment, the first well 121 of the second conductivity type may include a third well 121c of the second conductivity type formed in the first epitaxial layer 112a of the first conductivity type, and a second well 121b of the second conductivity type formed in the second epitaxial layer 112b of the first conductivity type.
[0090] According to the second embodiment, a third well 121c of a second conductivity type can be formed in a first epitaxial layer 112a of a first conductivity type by ion implantation. Then, a second well 121b of a second conductivity type can be formed in a second epitaxial layer 112b of a first conductivity type grown on the first epitaxial layer 112a of a first conductivity type by ion implantation.
[0091] In this case, the first distance D1 between the third wells 121c of the second conductivity type formed in the first epitaxial layer 112a of the first conductivity type may be longer than the second distance D2 between the second wells 121b of the second conductivity type formed in the second epitaxial layer 112b of the first conductivity type.
[0092] According to the second embodiment, the first distance D1 between the third wells 121c of the second conductivity type formed under the trench gates 132 is controlled to be longer than the second distance D2 between the second wells 121b of the second conductivity type formed around the trench gates 132, thereby increasing the movement width of electrons, thereby producing a special technical effect of reducing Ron.
[0093] Next, a manufacturing process of the power semiconductor device 100 according to the embodiment shown in FIG. 3 will be described with reference to FIGS.
[0094] First, referring to FIG. 5, a first epitaxial layer 112a of a first conductivity type may be grown on a substrate 111.
[0095] The first conductivity type first epitaxial layer 112a may include a first conductivity type buffer layer (not shown) and a first conductivity type drift layer (not shown).
[0096] The substrate 111 and the first conductive type first epitaxial layer 112a may include, but are not limited to, a 4H-SiC material, for example, the substrate 111 and the first conductive type first epitaxial layer 112a may include 3C-SiC or 6H-SiC.
[0097] Next, a first well 121a of a second conductivity type can be formed in the first epitaxial layer 112a of the first conductivity type by ion implantation.
[0098] 6, a second epitaxial layer 112b of a first conductive type may be grown on the first epitaxial layer 112a of the first conductive type, and then a second well 121b of a second conductive type may be formed in the second epitaxial layer 112b of the first conductive type by ion implantation.
[0099] For example, the first well 121a of the second conductive type and the second well 121b of the second conductive type may be formed by forming a hard mask pattern (not shown) and implanting ions using the hard mask pattern as a mask. The first well 121a of the second conductive type and the second well 121b of the second conductive type may be, but are not limited to, a P-type body.
[0100] The hard mask pattern may include, but is not limited to, a polysilicon pattern and an oxide pattern.
[0101] The first well 121a of the second conductivity type and the second well 121b of the second conductivity type are ion-implanted with a P-type dopant, for example, Al, boron, or the like, but are not limited thereto.
[0102] According to the embodiment, the second conductive type well 121 is formed without using high energy ion implantation, thereby preventing the problem of pitch reduction due to lateral straggling of dopants, and the second conductive type second well 121b is formed in a region deeper than the trench gate 132 to be formed later, thereby making it possible to disperse the electric field concentrated at the gate trench bottom corner, thereby preventing the destruction of the gate insulating layer.
[0103] In addition, the doping concentration of the first well 121a of the second conductivity type formed in the first epitaxial layer 112a of the first conductivity type in the embodiment may be higher than the doping concentration of the second well 121b of the second conductivity type formed in the second epitaxial layer 112b of the first conductivity type.
[0104] For example, according to the embodiment, there is a technical effect of implementing a concentration gradient in which the doping concentration of the first well 121a of the second conductivity type formed under the trench gate 132 changes abruptly from the doping concentration of the second well 121b of the second conductivity type formed adjacent to the trench gate 132.
[0105] For example, the doping concentration of the first well 121a of the second conductivity type is 2×10 17 ~2×10 19 / cm 3 The doping concentration of the second well 121b of the second conductivity type may be 1×10 16 ~1×10 17 / cm 3 It may be, but is not limited to this.
[0106] According to the embodiment, the doping concentration of the first well 121a of the second conductivity type formed under the trench gate 132 is higher than the doping concentration of the second well 121b of the second conductivity type, which has the effect of expanding a depletion layer toward the substrate 111, thereby providing a technical effect of increasing the breakdown voltage. Also, according to the embodiment, the doping concentration of the second well 121b of the second conductivity type formed around the trench gate 132 is lower than the doping concentration of the first well 121a of the second conductivity type, which provides a composite technical effect of decreasing the threshold voltage and increasing the current density.
[0107] Referring next to FIG. 7, a second conductivity type ion implantation region 122 can be formed by ion implanting Al, boron, or the like into the second epitaxial layer 112b of the first conductivity type and the second well 121b of the second conductivity type.
[0108] 8, the second conductivity type ion implantation region 122 may be implanted with ions using a second hard mask pattern (not shown) as an ion implantation mask to form the first conductivity type source region 115. For example, an N-type dopant such as nitrogen or phosphorus may be implanted at about 1×10 18 cm -3 ~Approx. 7×10 19 cm -3 The first conductive type source region 115 can be formed by implanting ions at a concentration of 100 .mu.m or more in a self-aligned manner.
[0109] Also, the second conductive type contact region 123 may be formed using a third hard mask pattern (not shown) as an ion implantation mask. The second conductive type contact region 123 may function to maintain the zero potential of the second conductive type ion implantation region 122 and may function as a body diode.
[0110] Next, referring to FIG. 9, a trench region T can be formed by partially removing the first conductive type source region 115, the second conductive type ion implantation region 122, and the first conductive type second epitaxial layer 112b using a predetermined hard mask pattern (not shown) as a mask.
[0111] 10, a gate insulating layer 131 may be formed in the trench region T, and a trench gate 132 may be formed on the gate insulating layer 131.
[0112] The gate insulating layer 131 may be, but is not limited to, a thermal oxide film or a deposited oxide film using LPCVD, etc. The trench gate 132 may be, but is not limited to, polysilicon.
[0113] Thereafter, the source contact 141 can be formed. For example, the source contact 141 can be formed using Ti or Ni, but is not limited thereto.
[0114] Furthermore, the drain electrode 105 can be formed on the substrate 111 using Ti / Al.
[0115] 11, an interlayer insulating layer 150 may be formed on the trench gate 132 and the gate insulating layer 131, and a source electrode 142 may be formed on the interlayer insulating layer 150 and the source contact 141.
[0116] The interlayer insulating layer 150 may be formed of an oxide layer or a nitride layer, but is not limited thereto.
[0117] The source electrode 142 may be made of, but is not limited to, Al, etc. Also, the source electrode 142 may further include a barrier metal layer.
[0118] According to the power semiconductor device and the power conversion device including the same and the method for manufacturing the power semiconductor device according to the embodiments, there is a technical effect of preventing the problem of pitch reduction due to lateral straggling while preventing electric field concentration at the corners of the trench.
[0119] For example, in the power semiconductor device 100 according to the embodiment, the second conductivity type well 121 is formed without using high energy ion implantation, thereby preventing the problem of pitch reduction due to lateral straggling of dopants, and the second conductivity type second well 121b is formed in a region deeper than the trench, thereby making it possible to disperse the electric field concentrated at the gate trench bottom corner, thereby preventing destruction of the gate insulating layer.
[0120] In addition, according to the embodiment, the doping concentration of the first well 121a of the second conductivity type formed under the trench gate 132 is higher than the doping concentration of the second well 121b of the second conductivity type, which has the effect of expanding a depletion layer toward the substrate 111, thereby providing a technical effect of increasing the breakdown voltage. In addition, according to the embodiment, the doping concentration of the second well 121b of the second conductivity type formed around the trench gate 132 is lower than the doping concentration of the first well 121a of the second conductivity type, which provides a composite technical effect of decreasing the threshold voltage and increasing the current density.
[0121] Furthermore, according to the second embodiment, the first distance D1 between the third wells 121c of the second conductivity type formed in the first epitaxial layer 112a of the first conductivity type may be longer than the second distance D2 between the second wells 121b of the second conductivity type formed in the second epitaxial layer 112b of the first conductivity type.
[0122] According to the second embodiment, the first distance D1 between the third wells 121c of the second conductivity type formed under the trench gates 132 is controlled to be longer than the second distance D2 between the second wells 121b of the second conductivity type formed around the trench gates 132, thereby increasing the movement width of electrons, thereby producing a special technical effect of reducing Ron.
[0123] Although the present invention has been described above with reference to an embodiment thereof, it should be readily apparent to a person skilled in the art that the present invention can be modified and changed in various ways without departing from the spirit and scope of the present invention as set forth in the claims below.
Claims
1. A substrate; a first epitaxial layer of a first conductivity type disposed on the substrate; a second epitaxial layer of a first conductivity type disposed on the first epitaxial layer of the first conductivity type; a first well of a second conductivity type partially formed in the first epitaxial layer of the first conductivity type; a second well of a second conductivity type formed in the second epitaxial layer of the first conductivity type; an ion implantation region and a source region of a second conductivity type disposed in a second well of the second conductivity type; a source electrode disposed on the source region; a gate insulating layer formed in the second conductive type ion implantation region and a trench region in which a portion of the first conductive type second epitaxial layer is removed; a trench gate disposed on the gate insulating layer; an interlayer insulating layer disposed on the trench gate; a gate electrode electrically connected to the trench gate.
2. The power semiconductor device of claim 1 , wherein a side surface of the first well of the second conductivity type and a side surface of the second well of the second conductivity type are aligned in an upward direction on the substrate.
3. 2. The power semiconductor device according to claim 1, wherein a doping concentration of the first well of the second conductivity type formed in the first epitaxial layer of the first conductivity type is higher than a doping concentration of the second well of the second conductivity type formed in the second epitaxial layer of the first conductivity type.
4. 2. The power semiconductor device according to claim 1, wherein an interface is formed between the first well of the second conductivity type and the second well of the second conductivity type formed in the first epitaxial layer of the first conductivity type.
5. 5. The power semiconductor device according to claim 4, wherein a first distance between the first wells of the second conductivity type formed in the first epitaxial layer of the first conductivity type is different from a second distance between the second wells of the second conductivity type formed in the second epitaxial layer of the first conductivity type.
6. 6. The power semiconductor device according to claim 5, wherein a first distance between the first wells of the second conductivity type formed in the first epilayer of the first conductivity type is longer than a second distance between the second wells of the second conductivity type formed in the second epilayer of the first conductivity type.
7. The power semiconductor device according to claim 6 , wherein a part of a lower corner of the second well of the second conductivity type does not vertically overlap with the first well of the second conductivity type.
8. the first well of the second conductivity type is disposed below the trench gate; The power semiconductor device according to claim 1 , wherein the second well of the second conductivity type is disposed at a horizontal position of the trench gate.
9. The power semiconductor device according to claim 8 , wherein a depth of the second well of the second conductivity type is less than a depth of the first well of the second conductivity type.
10. A power conversion device comprising the power semiconductor element according to any one of claims 1 to 9.