Manufacturing apparatus and memory device

Abstract

To improve the efficiency of memory device manufacturing.SOLUTION: A manufacturing apparatus according to an embodiment includes a wafer holding unit 90 that holds a wafer 100, an ion source 91 that outputs an ion beam, a shutter holding unit 95A that holds a shutter 93 and positions the shutter 93 between the wafer holding unit 90 and the ion source 91 when preventing the wafer 100 from being irradiated with the ion beam, and a target holding unit 95B that holds a target 97 that holds a through hole 970 and positions the target 97 between the wafer holding unit 90 and the ion source 91 when a first layer including a component of the target 97 is formed on the wafer.SELECTED DRAWING: Figure 7

Description

[Technical field]

[0001] The embodiments relate to a manufacturing apparatus and a memory device. [Background technology]

[0002] 2. Description of the Related Art Magnetic memories using magnetoresistance effect elements as memory elements are known. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Patent No. 6,153,067 [Patent Document 2] U.S. Pat. No. 5,024,747 [Patent Document 3] US Patent Application Publication No. 2009 / 0178917 Summary of the Invention [Problem to be solved by the invention]

[0004] Aim to improve the efficiency of memory device manufacturing. [Means for solving the problem]

[0005] A manufacturing apparatus according to an embodiment includes a wafer holding unit that holds a wafer, an ion source that outputs an ion beam, a shutter holding unit that holds a shutter and positions the shutter between the wafer holding unit and the ion source when preventing the wafer from being irradiated with the ion beam, and a target holding unit that holds a target that holds a through hole and positions the target between the wafer holding unit and the ion source when a first layer including the target is formed on the wafer. [Brief description of the drawings]

[0006] [Figure 1] FIG. 2 is a block diagram for explaining the configuration of a memory device according to the first embodiment. [Diagram 2] 1 is a circuit diagram for explaining the configuration of a memory cell array of a memory device according to a first embodiment. [Diagram 3] FIG. 2 is a plan view for explaining the configuration of a memory cell array of the memory device according to the first embodiment. [Figure 4] 4 is a cross-sectional view taken along line IV-IV in FIG. 3, showing an example of a cross-sectional structure of the memory cell array of the memory device according to the first embodiment. [Diagram 5] FIG. 2 is a cross-sectional view illustrating the configuration of a memory element of the memory device according to the first embodiment. [Figure 6] FIG. 1 is a block diagram showing a system including a manufacturing apparatus according to a first embodiment. [Figure 7] FIG. 2 is a schematic diagram for explaining the configuration of a manufacturing apparatus according to the first embodiment. [Figure 8] FIG. 2 is a plan view showing the configuration of members used in the manufacturing apparatus according to the first embodiment. [Figure 9] 5A to 5C are cross-sectional process views showing a process in a manufacturing method of the memory device according to the first embodiment. [Figure 10] 3A to 3C are schematic diagrams showing the state of the manufacturing apparatus of the first embodiment in the manufacturing process of the memory device. [Figure 11] 3A to 3C are schematic diagrams showing the state of the manufacturing apparatus of the first embodiment in the manufacturing process of the memory device. [Figure 12] 5A to 5C are cross-sectional process views showing a process in a manufacturing method of the memory device according to the first embodiment. [Figure 13] 3A to 3C are schematic diagrams showing the state of the manufacturing apparatus of the first embodiment in the manufacturing process of the memory device. [Figure 14] 5A to 5C are cross-sectional process views showing a process in a manufacturing method of the memory device according to the first embodiment. [Figure 15] FIG. 5 is a schematic diagram for explaining the configuration of a manufacturing apparatus according to a second embodiment. [Figure 16] 5A and 5B are schematic diagrams showing the state of a manufacturing apparatus according to a second embodiment in a memory device manufacturing process. [Figure 17] 5A and 5B are schematic diagrams showing the state of a manufacturing apparatus according to a second embodiment in a memory device manufacturing process. [Figure 18] FIG. 13 is a diagram showing a modification of the memory device according to the embodiment. [Figure 19] FIG. 13 is a diagram showing a modified example of the manufacturing apparatus according to the embodiment. [Figure 20] 10A to 10C are diagrams showing a modified example of the method for manufacturing a memory device according to the embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] A manufacturing apparatus according to an embodiment, a memory device according to an embodiment, and a manufacturing method for a memory device according to an embodiment will be described with reference to FIGS. 1 to 20. In the following description, elements having the same function and configuration are given the same reference numerals. In addition, in each of the following embodiments, when components (e.g., circuits, wiring, various voltages and signals, etc.) are given reference numerals with a distinguishing numeral / letter at the end, and do not need to be distinguished from each other, a description (reference numeral) with the numeral / letter at the end omitted is used. In each of the following embodiments, when "a / b layer" is indicated, it indicates a laminated structure of a layer containing element a and a layer containing element b. In this case, the layer containing element a is laminated on the layer containing element b.

[0008] <Embodiment> 1. First embodiment A memory device according to a first embodiment, a manufacturing apparatus according to the first embodiment, and a manufacturing method for the memory device according to the first embodiment will be described with reference to FIGS.

[0009] The memory device of the embodiment includes, for example, a magnetic memory using an element having a magnetoresistance effect due to a magnetic tunnel junction as a resistance change element. Hereinafter, the element having the magnetoresistance effect due to a magnetic tunnel junction (magnetoresistance effect element) is also called an MTJ element.

[0010] 1.1 Configuration The configuration of a memory device according to a first embodiment will be described with reference to FIGS.

[0011] 1.1.1 Memory Device Configuration 1 is a block diagram showing the configuration of a magnetic memory as a memory device 1 of this embodiment. As shown in Fig. 1, the magnetic memory 1 includes a memory cell array 10, a row selection circuit 11, a column selection circuit 12, a decode circuit 13, a write circuit 14, a read circuit 15, a voltage generation circuit 16, an input / output circuit 17, and a control circuit 18.

[0012] The memory cell array 10 includes a plurality of memory cells MC, each of which is associated with a row and a column. Memory cells MC in the same row are connected to the same word line WL. Memory cells MC in the same column are connected to the same bit line BL.

[0013] The row selection circuit 11 is connected to the memory cell array 10 via the word lines WL. The row selection circuit 11 is supplied with a decoded result (row address) of the address ADD from the decode circuit 13. The row selection circuit 11 sets a word line WL corresponding to a row based on the decoded result of the address ADD to a selected state. In the following, the word line WL set to a selected state is called a selected word line WL. The word lines WL other than the selected word line WL are called unselected word lines WL.

[0014] The column selection circuit 12 is connected to the memory cell array 10 via bit lines BL. The column selection circuit 12 is supplied with a decoded result (column address) of the address ADD from the decode circuit 13. The column selection circuit 12 sets a bit line BL corresponding to a column based on the decoded result of the address ADD to a selected state. In the following, the bit line BL set to the selected state is called a selected bit line BL. The bit lines BL other than the selected bit line BL are called unselected bit lines BL.

[0015] The decode circuit 13 decodes an address ADD from the input / output circuit 17. The decode circuit 13 supplies the decoded result of the address ADD to the row selection circuit 11 and the column selection circuit 12. The address ADD includes a column address and a row address to be selected.

[0016] The write circuit 14 writes data to the memory cells MC. The write circuit 14 includes, for example, a write driver (not shown).

[0017] The read circuit 15 reads data from the memory cells MC. The read circuit 15 includes, for example, a sense amplifier (not shown).

[0018] The voltage generation circuit 16 uses the power supply voltage to generate voltages for various operations of the memory cell array 10. The power supply voltage is provided from a device (not shown) external to the magnetic memory 1. For example, the voltage generation circuit 16 generates various voltages used in a write operation and outputs them to the write circuit 14. For example, the voltage generation circuit 16 generates various voltages used in a read operation and outputs them to the read circuit 15.

[0019] The input / output circuit 17 is responsible for communication with devices external to the magnetic memory 1. The input / output circuit 17 transfers an address ADD from outside the magnetic memory 1 to the decode circuit 13. The input / output circuit 17 transfers a command CMD from outside the magnetic memory 1 to the control circuit 18. The input / output circuit 17 transmits and receives various control signals CNT between the outside of the magnetic memory 1 and the control circuit 18. The input / output circuit 17 transfers data DAT from outside the magnetic memory 1 to the write circuit 14. The input / output circuit 17 outputs the data DAT transferred from the read circuit 15 to the outside of the magnetic memory 1.

[0020] The control circuit 18 controls the operations of the row selection circuit 11, column selection circuit 12, decode circuit 13, write circuit 14, read circuit 15, voltage generation circuit 16, and input / output circuit 17 in the magnetic memory 1 based on the control signal CNT and command CMD.

[0021] 1.1.2 Memory cell array configuration The configuration of the memory cell array of the magnetic memory 1 of this embodiment will be described with reference to Fig. 2. Fig. 2 is a circuit diagram showing the configuration of the memory cell array of the magnetic memory of the embodiment. In Fig. 2, the word lines WL are classified and shown by subscripts including the index "<>".

[0022] In this embodiment, the magnetic memory 1 is, for example, a magnetoresistive random access memory (MRAM).

[0023] 2, a plurality of memory cells MC are arranged in a matrix in the memory cell array 10. Each memory cell MC is connected to a plurality of bit lines BL (BL <0> , B.L. <1> , … , BL <n>) and multiple word lines WL (WL <0> , W.L. <1> , …, W.L. <m>) and a pair of M and N. Note that M and N are natural numbers.<i,j> (0≦i≦M, 0≦j≦N) is the word line WL and bit line BL <j>is connected between the

[0024] Memory cell MC<i,j> is a switching element SEL connected in series.<i,j> and magnetoresistance effect element MTJ<i,j> For example, one end of the switching element SEL is connected to a word line WL. The other end of the switching element SEL is connected to one end of the magnetoresistive element MTJ. The other end of the magnetoresistive element MTJ is connected to a bit line BL.

[0025] The switching element SEL is a two-terminal switching element. A two-terminal switching element differs from a three-terminal switching element such as a transistor in that it does not include a third terminal. When the voltage applied between the two terminals is less than a threshold voltage Vth (voltage applied between the two terminals<threshold voltage Vth), the switching element SEL is in a high resistance state. The high resistance state is, for example, an "off" state in which the switching element SEL is electrically non-conductive. When the voltage applied between the two terminals is equal to or greater than the threshold voltage Vth (voltage applied between the two terminals≧threshold voltage Vth), the switching element SEL changes to a low resistance state. The low resistance state is, for example, an "on" state in which the switching element SEL is electrically conductive.

[0026] For example, when the voltage applied to the corresponding memory cell MC is less than the threshold voltage Vth (voltage applied to the corresponding memory cell MC<threshold voltage Vth), the switching element SEL acts as an insulator with a high resistance value and blocks the current. That is, the switching element SEL is turned off.

[0027] When the voltage applied to the corresponding memory cell MC is equal to or higher than the threshold voltage Vth (voltage applied to the corresponding memory cell MC≧threshold voltage Vth), the switching element SEL acts as a conductor with a low resistance and passes a current, i.e., the switching element SEL is turned on.

[0028] The switching element SEL switches between passing and blocking a current according to the magnitude of the voltage applied to the corresponding memory cell MC, regardless of the polarity of the voltage applied between the two terminals (regardless of the direction of the flowing current).

[0029] The magnetoresistive element MTJ can switch its resistance state to a low resistance state or a high resistance state by a current controlled by the switching element SEL. The magnetoresistive element MTJ functions as a memory element. Data can be written to the magnetoresistive element MTJ by changing the resistance state of the magnetoresistive element MTJ. The magnetoresistive element MTJ holds the written data in a non-volatile manner. Data can be read from the magnetoresistive element MTJ.

[0030] The shape of the memory cells MC in the memory cell array 10 and the arrangement of the memory cells MC relative to the bit lines BL and word lines WL will be described with reference to Fig. 3. Fig. 3 shows an example of a plan view for explaining an example of the configuration of the memory cell array 10 of the magnetic memory 1 of the present embodiment. In Fig. 3, three word lines WL <m-1>、WL <m>, and W.L.<m+1> and three bit lines BL <n-1>、BL <n>, and B.L.<n+1> A plurality of memory cells MC provided between the first and second memory cells MC are shown (1≦m≦M-1, 1≦n≦N-1). For ease of explanation, an interlayer insulating film is omitted in FIG.

[0031] 3, the memory cell array 10 is provided above a substrate 20. In the following description, a plane parallel to the surface of the substrate 20 is referred to as the XY plane. A direction perpendicular to the XY plane is referred to as the Z direction. Two directions parallel to the XY plane are referred to as the X direction and the Y direction. The X direction and the Y direction are perpendicular to each other.

[0032] A plurality of memory cells MC are provided between word lines WL and bit lines BL. In the example of Fig. 3, the word lines WL are provided below the memory cells MC, and the bit lines BL are provided above the memory cells MC. However, the up-down relationship between the word lines WL and the bit lines BL may be reversed.

[0033] Each of the plurality of memory cells MC has, for example, a circular planar shape along the XY cross section.

[0034] The word lines WL are aligned along the Y direction. Each of the word lines WL extends along the X direction. The bit lines BL are aligned along the X direction. Each of the bit lines BL extends along the Y direction. The distance (spacing) between two word lines WL can be set to be substantially equal to the distance between two bit lines BL, for example. One memory cell MC is provided at a portion where one bit line BL and one word line WL intersect.

[0035] The cross-sectional structure of the memory cell array 10 will be described with reference to Fig. 4. Fig. 4 is a cross-sectional view showing an example of the cross-sectional structure of the memory cell array of the magnetic memory of the embodiment. The cross section of Fig. 4 is taken along line IV-IV of Fig. 3.

[0036] The memory cell array 10 is provided above a semiconductor substrate 20 .

[0037] The memory cell array 10 includes a plurality of conductors 21, a plurality of electrodes 22, a plurality of elements (variable resistance layers) 23, a plurality of electrodes 24, a plurality of elements 25, a plurality of electrodes 26, and a plurality of conductors 27.

[0038] For example, a plurality of conductors 21 are provided on the upper surface of the substrate 20. The plurality of conductors 21 are arranged along the Y direction. Each of the plurality of conductors 21 extends along the X direction in a region not shown. Each of the plurality of conductors 21 functions as a word line WL. An insulator 41 is provided in a portion between two adjacent conductors 21. This insulates each of the plurality of conductors 21 from one another.

[0039] 4, a case has been described in which the plurality of conductors 21 are provided on the substrate 20, but this is not limiting. For example, the plurality of conductors 21 may be provided away from the substrate 20 without contacting the substrate 20. For example, when the substrate 20 is a semiconductor substrate, an insulating layer (interlayer insulating film) is provided between the substrate 20 and the conductors 21. In this case, an element such as a field effect transistor is provided on the upper surface of the semiconductor substrate 20 so as to be covered with the insulating layer. The field effect transistor is an element that constitutes a CMOS circuit such as a row selection circuit.

[0040] A plurality of electrodes 22 are provided on the upper surface of each of the plurality of conductors 21. The plurality of electrodes 22 provided on the upper surface of the same conductor 21 are aligned in the X direction in a region not shown. Note that, of the plurality of electrodes 22, two electrodes 22 provided on two conductors 21, respectively, are shown in Fig. 4. Each of the plurality of electrodes 22 is used as a lower electrode BE of a memory cell MC.

[0041] One of the plurality of elements 23 is provided on the upper surface of each of the plurality of electrodes 22. Each of the plurality of elements 23 is used as a switching element SEL. The element 23 includes at least one layer (a variable resistance layer).

[0042] Of the plurality of electrodes 24, one corresponding electrode 24 is provided on the upper surface of each element 23. Each of the plurality of electrodes 24 functions as an intermediate electrode ME of the memory cell MC. The configuration of the electrode 24 will be described in detail later.

[0043] Of the plurality of elements 25, one corresponding element 25 is provided on the upper surface of each of the plurality of electrodes 24. Each of the plurality of elements 25 functions as a memory element. The element 25 is, for example, a magnetoresistance effect element MTJ. The configuration of the element 25 will be described in detail later.

[0044] One of the multiple electrodes 26 is provided on the upper surface of each of the multiple elements 25. Each of the multiple electrodes 26 is used as a top electrode TE of the memory cell MC.

[0045] One conductor 27 extending in the Y direction is provided so as to contact the upper surface of each of the multiple electrodes 26 aligned in the Y direction. The multiple conductors 27 are aligned in the X direction in an area not shown. Each of the multiple conductors 27 extends along the Y direction. Each of the multiple conductors 27 functions as a bit line BL.

[0046] 1.1.3 Switching elements The configuration of the switching element SEL (23) of the magnetic memory 1 of this embodiment will be described with reference to FIG.

[0047] The element 23 used as the switching element SEL includes a variable resistance layer (also called a selector layer). The resistance state of the variable resistance layer element 23 becomes a high resistance state (non-conductive state) or a low resistance state (conductive state) depending on the voltage applied to the switching element SEL (memory cell MC).

[0048] The element (variable resistance layer) 23 contains at least one element selected from the group consisting of boron (B), aluminum (Al), gallium (Ga), indium (In), carbon (C), silicon (Si), germanium (Ge), tin (Sn), arsenic (As), phosphorus (P), and antimony (Sb).

[0049] The element 23 may be, for example, an insulator containing a dopant (impurity). The dopant added to the insulator used in the element 23 is an impurity that contributes to electrical conduction in the insulator. An example of the insulator used in the element 23 is silicon oxide. When the material of the element 23 is silicon oxide, for example, phosphorus or arsenic is used as the dopant added to the silicon oxide. However, the type of dopant added to the silicon oxide of the element 23 is not limited to the above examples.

[0050] The element 23 may be made from a material that has snap-back properties.

[0051] 1.1.4 Intermediate electrode The configuration of the intermediate electrode ME of the magnetic memory 1 of this embodiment will be described with reference to FIG.

[0052] Each of the multiple electrodes 24 includes three conductors (conductive layers) 240, 241, and 242.

[0053] The conductor 240 is provided on the upper surface of each of the multiple elements 23. The conductor 240 is, for example, a layer composed of at least one member selected from carbon (C) and carbon nitride (CN). The conductor 240 preferably has an amorphous structure. The height (thickness) HA from the lower surface to the upper surface of the conductor 240 in the Z direction is, for example, 2 nanometers (nm) or more and 20 nanometers (nm) or less. If the height HA is within this range, the conductor 240 is prevented from peeling off from the upper surface of the element 23.

[0054] In this embodiment, a portion composed of one or more elements may contain unintended impurities different from the elements. The unintended impurities include, for example, elements contained in a gas used in the manufacturing process of the magnetic memory 1 and elements mixed into the portion from a member surrounding the portion.

[0055] The conductor 241 is provided on the upper surface of the conductor 240. The conductor 241 is, for example, a layer containing a high-melting point metal element (high-melting point metal-containing member). The conductor 241 is made of, for example, at least one member selected from a simple substance of a high-melting point metal element and a compound of a high-melting point metal element. In this embodiment, the high-melting point metal is, for example, a material having a melting point higher than iron (Fe) and cobalt (Co).

[0056] The simple substance of the high melting point metal element and the compound of the high melting point metal element used in the conductor 241 are, for example, titanium (Ti), tantalum (Ta), tungsten (W), titanium nitride (TiN), tantalum nitride (TaN), and tungsten nitride (WN). The conductor 241 has, for example, a crystal structure. The height (thickness) HB from the lower surface to the upper surface of the conductor 241 in the Z direction is preferably, for example, 0.1 nanometers (nm) or more and 3 nanometers (nm) or less.

[0057] The conductor 241 is formed by injecting or depositing a material containing a high melting point metal element using a manufacturing apparatus described below.

[0058] The conductor 242 is provided on the upper surface of the conductor 241. Like the conductor 240, the conductor 242 is a layer made of at least one member selected from, for example, carbon (C) and carbon nitride (CN). The conductor 242 preferably has an amorphous structure. The height (thickness) HC from the lower surface to the upper surface of the conductor 242 in the Z direction is preferably, for example, 0.1 nanometers (nm) or more and 3 nanometers (nm) or less. Regarding the surface roughness (roughness, flatness) of the upper surface of the conductor 241, for example, a parameter Ra indicating the surface roughness is 0.6 nm or less.

[0059] 1.1.5 Magnetoresistance effect element The configuration of the magnetoresistive element MTJ of the magnetic memory 1 of this embodiment will be described with reference to Fig. 5. Fig. 5 is a cross-sectional view showing the configuration of the magnetoresistive element MTJ of the magnetic memory 1 of this embodiment.

[0060] The element 25 used as the magnetoresistive element MTJ includes a ferromagnetic body 31, a non-magnetic body 32, a ferromagnetic body 33, a non-magnetic body , a ferromagnetic body 35, and a non-magnetic body .

[0061] The ferromagnetic body 31 is a conductive layer (conductive film) having ferromagnetism. The ferromagnetic body 31 has an easy axis direction perpendicular to the film surface (Z direction). The magnetization direction of the ferromagnetic body 31 is changed by applying a torque of a magnitude capable of reversing the magnetization direction of the ferromagnetic body 31 (torque equal to or greater than the magnetization reversal threshold of the ferromagnetic body 31) to the magnetoresistance effect element MTJ.

[0062] The ferromagnetic body 31 may include at least one element of iron (Fe), cobalt (Co), and nickel (Ni). The ferromagnetic body 31 may further include boron (B). More specifically, the ferromagnetic body 31 includes, for example, cobalt iron boron (CoFeB), iron boride (FeB), or cobalt boride (CoB). The ferromagnetic body 31 is used as a memory layer SL of the MTJ element.

[0063] The non-magnetic body 32 is provided under the lower surface of the ferromagnetic body 31. The non-magnetic body 32 is an insulating layer (insulating film) having non-magnetic properties. The non-magnetic body 32 is used as a tunnel barrier layer TB of the MTJ element.

[0064] The non-magnetic material 32 is provided between the ferromagnetic material 31 and the ferromagnetic material 33 and forms a magnetic tunnel junction together with the ferromagnetic material 31 and the ferromagnetic material 33 .

[0065] When an initial amorphous layer such as cobalt iron boron (CoFeB) is used as the interface layer of the ferromagnetic material 31, the nonmagnetic material 32 functions as a seed material that becomes a nucleus for growing a crystalline film from the interface with the ferromagnetic material 31 in the crystallization process of the ferromagnetic material 31. Similarly, when cobalt iron boron (CoFeB) is used as the interface layer of the ferromagnetic material 33, the nonmagnetic material 32 also functions as a seed material for the ferromagnetic material 33. Here, the initial amorphous layer is a layer that is in an amorphous state immediately after deposition and crystallizes after annealing. For example, the nonmagnetic material 32 has a tetragonal or cubic structure with the film surface oriented to the (001) plane.

[0066] An example of an insulator used for the non-magnetic body 32 is magnesium oxide (MgO). Magnesium oxide (MgO) has a NaCl structure. When magnesium oxide (MgO) is used for the non-magnetic body 32, the (001) interface of magnesium oxide (MgO) and the (001) interface of cobalt iron boron (CoFeB) match each other. Therefore, the cobalt iron boron (CoFeB) undergoes crystal growth by annealing treatment and becomes a body-centered cubic structure oriented in (001).

[0067] The ferromagnetic body 33 is provided under the lower surface of the non-magnetic body 32. The ferromagnetic body 33 is a conductive layer having ferromagnetism. The ferromagnetic body 33 is used as a reference layer RL of the MTJ element. The ferromagnetic body 33 has an easy axis direction perpendicular to the film surface (Z direction). The magnetization direction of the ferromagnetic body 33 is fixed. In the example of FIG. 5, the magnetization direction of the ferromagnetic body 33 is a direction from the ferromagnetic body 33 to the ferromagnetic body 31. Note that "the magnetization direction is fixed" means that the magnetization direction of the ferromagnetic body 33 does not change when a torque large enough to reverse the magnetization direction of the ferromagnetic body 31 is applied to the magnetoresistance effect element MTJ.

[0068] For example, an interface layer is used for the ferromagnetic material 33. As the interface layer for the ferromagnetic material 33, an initial amorphous layer such as Cobalt Iron Boron (CoFeB) is used.

[0069] An auxiliary ferromagnetic layer is provided in the ferromagnetic body 33 so as to contact the surface of the cobalt iron boron (CoFeB) layer as an interface layer opposite to the surface contacting the magnesium oxide (MgO) layer. The auxiliary ferromagnetic layer includes at least one alloy film selected from, for example, cobalt platinum (CoPt), cobalt nickel (CoNi), and cobalt palladium (CoPd). The auxiliary ferromagnetic layer is a laminate such as a laminate film including Co / Pt or a laminate film including Co / Pd. The cobalt iron boron (CoFeB) layer as the initial amorphous layer is used by being laminated with the above-mentioned laminate film including CoPt, CoPd, Co / Pt, or a laminate film including Co / Pd. In this case, the interface layer of the ferromagnetic body 33, for example, the CoFeB layer, is formed closer to the non-magnetic body 32 including MgO oriented in (001) than other layers.

[0070] A non-magnetic body 34 is provided under the lower surface of the ferromagnetic body 33. The non-magnetic body 34 is a conductive layer having non-magnetic properties. The non-magnetic body 34 is used as a spacer layer SP of the MTJ element. The non-magnetic body 34 is made of a material containing one or more selected from, for example, ruthenium (Ru), osmium (Os), rhodium (Rh), iridium (Ir), vanadium (V), and chromium (Cr). For example, the film thickness of the non-magnetic body 34 is 2 nanometers (nm) or less.

[0071] The ferromagnetic body 35 is provided under the lower surface of the non-magnetic body 34. The ferromagnetic body 35 is a conductive layer having ferromagnetism. The ferromagnetic body 35 is used as a shift cancellation layer SCL of the MTJ element. The ferromagnetic body 35 has an easy axis direction perpendicular to the film surface (Z direction). The magnetization direction of the ferromagnetic body 35 is fixed. In the example of FIG. 5, the magnetization direction of the ferromagnetic body 35 is a direction from the ferromagnetic body 33 to the ferromagnetic body 35. The ferromagnetic body 35 includes at least one member selected from, for example, cobalt platinum (CoPt), cobalt nickel (CoNi), and cobalt palladium (CoPd). The ferromagnetic body 35 may be a laminate such as a laminate film including Co / Pt or a laminate film including Co / Pd.

[0072] The ferromagnetic body 33 and the ferromagnetic body 35 are antiferromagnetically coupled by the nonmagnetic body 34. That is, the ferromagnetic body 33 and the ferromagnetic body 35 are coupled so as to have antiparallel magnetization directions. Such a coupled structure of the ferromagnetic body 33, the nonmagnetic body 34, and the ferromagnetic body 35 is called an SAF (Synthetic Anti-Ferromagnetic) structure. Due to the SAF structure, the ferromagnetic body 35 can offset the effect of the leakage magnetic field of the ferromagnetic body 33 on the change in the magnetization direction of the ferromagnetic body 31. As a result, the ferromagnetic body 35 can substantially reduce the leakage magnetic field of the ferromagnetic body 33.

[0073] A non-magnetic body 36 is provided under the lower surface of the ferromagnetic body 35. The non-magnetic body 36 is a conductive layer having non-magnetic properties. The non-magnetic body 36 is used as an underlayer UL of the MTJ element. The non-magnetic body 38 includes at least one member selected from, for example, zirconium (Zr), hafnium (Hf), tungsten (W), chromium (Cr), molybdenum (Mo), niobium (Nb), titanium (Ti), tantalum (Ta), vanadium (V), ruthenium (Ru), and platinum (Pt).

[0074] The magnetoresistive element MTJ can take either a low resistance state or a high resistance state depending on whether the relative relationship (magnetization arrangement state) of the magnetization directions of the memory layer SL and the reference layer RL is parallel or antiparallel. In this embodiment, the magnetization direction of the memory layer SL relative to the magnetization direction of the reference layer RL is controlled by passing a write current through the magnetoresistive element MTJ. Specifically, a write method is adopted that utilizes spin transfer torque (STT) generated by passing a current through the magnetoresistive element MTJ.

[0075] When a write current Ic0 of a certain magnitude flows through the magnetoresistive element MTJ in a direction from the memory layer SL to the reference layer RL, i.e., in the direction of the arrow A1 in FIG. 5, the relative relationship between the magnetization directions of the memory layer SL and the reference layer RL becomes parallel. When the relative relationship between the magnetization directions is parallel, the resistance value of the magnetoresistive element MTJ becomes the lowest, and the magnetoresistive element MTJ is set to a low resistance state. This low resistance state is called a "P (Parallel) state." The P state of the magnetoresistive element MTJ is defined as, for example, a data "0" state.

[0076] When a write current Ic1 flows through the magnetoresistive element MTJ in a direction from the reference layer RL to the memory layer SL, i.e., in the direction of the arrow A2 in FIG. 5, the relative relationship between the magnetization directions of the memory layer SL and the reference layer RL becomes anti-parallel. When the relative relationship between the magnetization directions is anti-parallel, the resistance value of the magnetoresistive element MTJ becomes the highest, and the magnetoresistive element MTJ is set to a high resistance state. This high resistance state is called an "AP (Anti-Parallel) state." The AP state of the magnetoresistive element MTJ is defined as, for example, a state of data "1." For example, the write current Ic1 is greater than the write current Ic0.

[0077] The method of defining data "1" and data "0" is not limited to the above example. For example, the P state may be defined as data "1" and the AP state may be defined as data "0".

[0078] The write and read operations of the magnetic memory 1 of this embodiment are performed using well-known techniques.

[0079] In this embodiment, an intermediate electrode 24 including a conductor 241 containing a refractory metal element is provided between the switching element SEL and the magnetoresistive element MTJ.

[0080] The conductor 241 in the intermediate electrode 24 can prevent the surface roughness of the upper surface of the intermediate electrode 24 from worsening even if the upper surface of the member (layer) 23 that constitutes the switching element SEL is rough.

[0081] Moreover, according to the embodiment, a conductor 242 having an amorphous structure is included between the magnetoresistive element MTJ and the conductor 241. This prevents the crystal structure of the conductor 241 from affecting the structure and / or properties of the layers constituting the magnetoresistive element MTJ. For example, the intermediate electrode 24 is prevented from affecting the structure and / or properties of the non-magnetic material 36 that functions as the underlayer UL in the magnetoresistive element MTJ.

[0082] As a result, in the magnetic memory 1 of the present embodiment, the characteristics of the magnetoresistive element MTJ can be improved.

[0083] 1.2 Manufacturing equipment The configuration of a manufacturing apparatus used to manufacture the magnetic memory 1 of the first embodiment will be described with reference to FIGS.

[0084] FIG. 6 is a block diagram illustrating a manufacturing system for manufacturing the magnetic memory of this embodiment.

[0085] The manufacturing system 900 includes a film forming apparatus 7, a transfer mechanism 8, and an etching apparatus 9.

[0086] The film forming apparatus 7 is an apparatus for forming a plurality of components (layers, films) such as the above-mentioned ferromagnetic material, non-magnetic material, conductive material (e.g., electrode), and insulator. For example, the film forming apparatus 7 forms various components on a wafer by various film formation techniques such as a vacuum deposition method, a sputtering method, an ALD (Atomic layer deposition) method, or a CVD (Chemical vapor deposition) method.

[0087] The film forming apparatus 7 is connected to an etching apparatus 9 via a transfer mechanism 8 .

[0088] The transfer mechanism 8 transfers the wafer from the film forming apparatus 7 to the etching apparatus 9 or from the etching apparatus 9 to the film forming apparatus 7 while maintaining the vacuum.

[0089] The etching apparatus 9 etches various members formed on the wafer based on a certain pattern. In this embodiment, the etching apparatus 9 is an ion beam etching apparatus (IBE apparatus).

[0090] Other semiconductor manufacturing tools (not shown), such as a reactive ion etching tool, a chemical mechanical polishing (CMP) tool, and an exposure tool, may be further connected to the transfer mechanism 8 .

[0091] FIG. 7 is a schematic diagram showing an example of the configuration of an ion beam etching apparatus 9 in this embodiment.

[0092] As shown in FIG. 7, the ion beam etching apparatus 9 of this embodiment includes a wafer holder 90, an ion source 91, a position control mechanism 92, a shutter 93, a shutter holder 95A, a target holder 95B, a vacuum chamber 98, and a vacuum pump 99.

[0093] In use of the apparatus, the wafer 100 and the target 97 are placed in the ion beam etching apparatus 9 .

[0094] The vacuum chamber 98 is a housing capable of maintaining high airtightness (vacuum state). The vacuum pump 99 is connected to the vacuum chamber 98. The vacuum pump 99 evacuates the air inside the vacuum chamber 98, and sets the inside of the vacuum chamber 98 to an ultra-high vacuum state.

[0095] The wafer holder 90 , the ion source 91 , the position control mechanism 92 , the shutter 93 , the shutter holder 95 A, and the target holder 95 B are provided in a vacuum chamber 98 .

[0096] The wafer holding part 90 holds a wafer 100 on which components of the magnetic memory 1 are formed. The wafer holding part 90 includes a wafer clamp part 94A. The wafer 100 is fixed to the wafer holding part 90 by the wafer clamp part 94A. The wafer holding part 90 is connected to a position control mechanism 92. The position of the wafer holding part 90 is controlled by the position control mechanism 92. This allows the position (e.g., angle) of the wafer 100 relative to the ion source 91 to be controlled.

[0097] The ion source 91 is disposed in the vacuum chamber 98 so as to face the wafer holder 90. The ion source 91 outputs an ion beam IB of argon (Ar) toward the wafer holder 90. The ion beam IB is irradiated onto the wafer 100 on the wafer holder 90. The ion beam IB etches a member on the wafer 100. The ion source 91 can control the acceleration energy, the exit angle, and the exit range of the ion beam IB. The exit angle of the ion beam IB is an angle with respect to a direction perpendicular to the upper surface of the wafer 100. The exit angle of the ion beam IB can be controlled within a range from 0 degrees to 90 degrees. The exit angle of the ion beam IB can also be controlled by controlling the angle of the wafer holder 90.

[0098] The position control mechanism 92 drives the wafer holder 90, the shutter holder 95A, and the target holder 95B based on instructions input to an input mechanism (not shown) of the ion beam etching apparatus 9. This controls the position of the wafer 100, the position of the shutter 93, and the position of the target 97.

[0099] The shutter 93 is connected to a shutter holder 95A. The shutter holder 95A holds the shutter 93. The shutter holder 95A is driven under the control of the position control mechanism 92. This controls the position of the shutter 93 in the vacuum chamber 98. When the ion source 91 is driven, in order to block the ion beam IB from being irradiated onto the wafer 100, the shutter 93 is positioned on the path of the ion beam IB between the wafer holder 90 and the ion source 91 by the shutter holder 95A and the position control mechanism 92. When the ion beam IB is irradiated onto the wafer 100, the shutter 93 is positioned on a position not on the path of the ion beam IB between the wafer holder 90 and the ion source 91 by the shutter holder 95A and the position control mechanism 92.

[0100] The target holder 95B holds a target 97. The target holder 95B is driven under the control of the position control mechanism 92. This controls the position of the target 97 in the vacuum chamber 98. The target holder 95B can be controlled by the position control mechanism 92 independently of the shutter holder 95A.

[0101] The target 97 is provided in a vacuum chamber 98 in order to form components of the magnetic memory 1 in the ion beam etching apparatus 9. When the components of the magnetic memory 1 are formed on the wafer 100 using the target 97, the target 97 is placed on the path of the ion beam IB between the wafer holder 90 and the ion source 91 by the target holder 95B and the position control mechanism 92.

[0102] FIG. 8 is a plan view showing an example of the structure of a target 97, as viewed from the traveling direction of an ion beam, in a manufacturing apparatus (ion beam etching apparatus) 9 of this embodiment.

[0103] 8 includes a material for forming the conductor (member containing a high-melting point metal element) 241 of the intermediate electrode 24. For example, the target 97 is an object (plate) made of at least one of titanium (Ti), tantalum (Ta), tungsten (W), titanium nitride (TiN), tantalum nitride (TaN), and tungsten nitride (WN).

[0104] A plurality of through-holes 970 are provided in the target 97. The through-holes 970 extend along the traveling direction of the ion beam.

[0105] With the target 97 disposed between the wafer holder 90 and the ion source 91, the ion beam IB passes through the through-hole 970. Collisions between the ion beam IB and the target 97 in the through-hole 970 during the passage of the ion beam IB cause the target material (target atoms or target molecules) SRa on the inner wall of the through-hole 970 to be sputtered. The sputtered target material SRa reaches the wafer 100. The sputtered target material SRa is deposited on a material (layer) on the wafer 100, or is implanted into a material on the wafer 100.

[0106] As a result, a member (layer) formed from the target 97 is formed on the wafer 100 .

[0107] For example, the position of the conductor 241 in the intermediate electrode 24 can be controlled by controlling the acceleration energy (intensity) of the ion beam IB irradiated to the through hole 970. As a more specific example, when the acceleration energy of the ion beam IB is high, the member SRa sputtered from the target 97 penetrates into a deep position in the other member (for example, a member made of carbon). In this case, the conductor 241 is formed in a position close to the switching element SEL (element 23) in the other member. As a more specific example, when the acceleration energy of the ion beam IB irradiated to the through hole 970 is low, the member SRa sputtered from the target 97 penetrates into a shallow position in the other member (for example, a member made of carbon) or is deposited on the surface of the other member. In this case, the conductor 241 is formed in a position close to the magnetoresistance effect element MTJ (element 25) in the other member.

[0108] When a layer containing a high melting point metal element is formed on a component on the wafer 100, the target 97 is disposed between the wafer 100 and the ion source 91 so as to overlap the wafer 100. This allows the sputtered target component SRa to be deposited on the component on the wafer 100 or implanted into the component relatively uniformly.

[0109] For example, by controlling the emission angle of the ion beam IB, when the target 97 is disposed between the wafer 100 and the ion source 91, it is possible to control the ion beam IB so that it does not reach the wafer 100 through the through-hole 970.

[0110] The ion beam etching apparatus 9 of the present embodiment can perform etching of the components of the magnetic memory 1 by the ion beam IB and formation of the components of the magnetic memory 1 on the wafer 100 within a single apparatus.

[0111] As a result, the ion beam etching apparatus 9 of this embodiment can reduce the number of times the wafer 100 is transferred between the film forming apparatus 7 and the ion beam etching apparatus 9.

[0112] As a result, the ion beam etching apparatus 9 of the present embodiment can improve the efficiency of manufacturing memory devices (for example, magnetic memories).

[0113] 1.3 Manufacturing method A method for manufacturing the magnetic memory 1 of this embodiment using the ion beam etching apparatus 9 of this embodiment will be described with reference to FIGS.

[0114] 9, 12, and 14 are cross-sectional views showing each step of the method for manufacturing the magnetic memory of this embodiment. FIG. 10, 11, and 13 are schematic views showing the state of the ion beam etching apparatus 9 in each step of the method for manufacturing the magnetic memory 1 of this embodiment.

[0115] 9, a plurality of conductors 21 that will become wiring (e.g., word lines WL) are formed on a substrate 20 of a wafer 100 by various semiconductor manufacturing equipment. An insulator 41 is embedded in the spaces between the plurality of conductors 21 by various semiconductor manufacturing equipment.

[0116] A conductive layer (electrode layer) 22Z that becomes the lower electrode BE is formed on the conductor 21 and the insulator 41 by the film forming apparatus .

[0117] A member (variable resistance layer) 23Z for forming the switching element SEL is formed on the conductive layer 22Z by the film forming apparatus .

[0118] A conductive layer (member) 24Z for forming the intermediate electrode ME is formed on the variable resistance layer 23Z by a film forming apparatus 7. The conductive layer 24Z is made of at least one member selected from, for example, carbon (C) and carbon nitride (CN).

[0119] After the formation of the conductive layer 24Z, the wafer 100 is transferred from the film formation apparatus 7 to an ion beam etching apparatus 9 via a transfer mechanism 8 for etching back the top surface of the conductive layer 24Z.

[0120] As shown in FIG. 10, in an ion beam etching apparatus 9, a wafer 100 on which components of the magnetic memory 1 are formed is placed on a wafer holder 90.

[0121] During the period from when the ion source 91 is started to when it is driven under desired conditions, the shutter 93 is disposed between the wafer holder 90 and the ion source 91 by the shutter holder 95A and the position control mechanism 92. The shutter 93 prevents the ion beam IB in an unstable energy state from being irradiated onto the wafer 100. This prevents members on the wafer 100 from being etched in an unintended state.

[0122] For example, in the etch-back process for planarizing the surface (upper part) of the intermediate electrode 24, the target 97 is not disposed between the wafer holder 90 and the ion source 91.

[0123] 11, after the output (acceleration energy) of the ion beam IB of the ion source 91 reaches a predetermined condition, the shutter 93 is moved from the position between the wafer holder 90 and the ion source 91 to another position by the shutter holder 95A and the position control mechanism 92. As a result, the ion beam IB output from the ion source 91 is irradiated onto the wafer 100.

[0124] 12, the upper portion 249X of the conductive layer 24X is removed by etching back the conductor with the ion beam IB. This controls the surface roughness of the upper surface of the conductive layer 24X. This etchback also controls the dimension of the conductive layer 24X (intermediate electrode ME) in the Z direction.

[0125] As shown in FIG. 13, after etching back the conductive layer 24X, a target 97 is positioned between the wafer holder 90 and the ion source 91 by the target holder 95B and the position control mechanism 92 to form a layer made of a material containing a high-melting point metal element.

[0126] An ion beam IB is output toward the target 97. The emission angle of the ion beam IB is controlled so that the ion beam IB collides with an inner wall in the through-hole 970. The ion beam IB passes through the through-hole 970 and can be irradiated (collided) with a member on the wafer 100.

[0127] When the ion beam IB is irradiated onto the through-hole 970, a portion of the inner wall of the target 97 is sputtered by the ion beam IB colliding with the inner wall. This causes the sputtered target member SRa to be released from the target 97. The target member SRa sputtered from the target 97 flies towards the wafer 100. Depending on the acceleration energy of the ion beam IB, the sputtered target member SRa is implanted into the conductive layer 24X.

[0128] As a result, as shown in FIG. 12, a layer 241X containing a high-melting point metal element is formed between the layer 240X and the layer 242X in the conductive layer 24X.

[0129] Depending on the magnitude of the acceleration energy of the ion beam IB, a layer 241X containing a high melting point metal element may be deposited on the upper surface of the member for forming the intermediate electrode. In this case, the layer 242X is formed on the layer 241X by the film forming apparatus 7.

[0130] After the formation of the layer 241X containing a refractory metal element, an etch-back process may be performed on the conductive layer 24Z (24X).

[0131] As shown in FIG. 14, after the wafer 100 including the etched-back conductive layer 24X is transferred from the ion beam etching apparatus 9 to the film forming apparatus 7 via the transfer mechanism 8, a member 25Z for forming the magnetoresistive effect element MTJ is formed on the conductive layer 24X by the film forming apparatus 7.

[0132] A conductive layer (electrode layer) 26Z serving as an upper electrode is formed on the member 25Z by a film forming apparatus 7. The conductive layer 26Z can also be used as, for example, a hard mask. For example, a mask (not shown) is formed on the conductive layer 26Z by various manufacturing devices.

[0133] The wafer 100 on which the member 25Z and the conductive layer 26Z are formed is transferred from the film forming apparatus 7 to the ion beam etching apparatus 9 via the transfer mechanism 8 for etching by the ion beam IB. The wafer 100 is mounted on a wafer holder 90 in the ion beam etching apparatus 9.

[0134] As shown in FIG. 10, a shutter 93 is placed between a wafer holder 90 and an ion source 91 by a shutter holder 95A and a position control mechanism 92 during the period until the energy state of the ion beam IB is stabilized.

[0135] 11, after the ion beam IB has stabilized, the shutter 93 is moved from the position between the wafer holder 90 and the ion source 91 to another position by the shutter holder 95A and the position control mechanism 92. This causes the ion beam IB to be irradiated onto the wafer 100.

[0136] During etching of the wafer 100 on which the member 25Z and the conductive layer 26Z are formed, the target 97 is positioned by the target holder 95B and the position control mechanism 92 at a position not between the wafer holder 90 and the ion source 91.

[0137] By irradiation with the ion beam IB, the components on the wafer 100 are etched according to the mask pattern.

[0138] 4, the upper electrode TE having a predetermined shape, the magnetoresistive element MTJ having a predetermined shape, the intermediate electrode ME having a predetermined shape, the switching element SEL having a predetermined shape, and the lower electrode BE having a predetermined shape are formed. In this manner, the memory cell MC including the magnetoresistive element MTJ and the switching element SEL is formed on the conductor 21.

[0139] An insulator (not shown) is formed in the spaces between the memory cells MC by a film deposition apparatus 7.

[0140] Conductors 27 that will become wiring (eg, bit lines BL) are formed on the memory cells MC and on the insulators by various types of semiconductor manufacturing equipment.

[0141] Through the above steps, the memory cell array 10 of the magnetic memory 1 of this embodiment is completed.

[0142] 1.4 Summary The memory device (for example, a magnetic memory) 1 of this embodiment includes an intermediate electrode 24 between the switching element SEL and the memory element (magnetoresistive element) MTJ. The intermediate electrode 24 includes a conductor 241 containing a high-melting point metal element between two conductors 240 and 242.

[0143] When the surface roughness of the intermediate electrode that contacts the memory element is deteriorated, the structure and / or properties of the components constituting the memory element are deteriorated, which may result in deterioration of the characteristics of the memory element. In addition, due to the deterioration of the surface roughness of the intermediate electrode, the components constituting the intermediate electrode are more likely to be mixed into the memory element.

[0144] In the memory device 1 of this embodiment, the conductor 241 containing a high melting point metal element can suppress deterioration of the surface roughness of the surface of the intermediate electrode 24 in contact with the memory element MTJ. This can suppress deterioration of the properties of the components of the memory element MTJ in the memory device 1 of this embodiment. Also, in the memory device 1 of this embodiment, it can suppress the components of the intermediate electrode 24 from being mixed into the memory element MTJ.

[0145] As a result, the memory device 1 of this embodiment can suppress deterioration of the characteristics of the memory elements.

[0146] The ion beam etching apparatus 9 of this embodiment has a target holder 95B that holds a target 97 containing a high-melting point metal element. The target 97 includes a plurality of through holes 970 through which the ion beam IB can pass.

[0147] When the ion beam IB enters the through-hole 970, a portion of the inner wall of the through-hole 970 is sputtered by the ion beam IB. As a result, in the ion beam etching apparatus 9 of this embodiment, the sputtered target member SRa flies toward the wafer 100.

[0148] As a result, the ion beam etching apparatus 9 of this embodiment can perform, within a single apparatus, etching of components of the memory device 1 using an ion beam as well as formation of components of the memory device 1, such as the component 241 containing a high-melting point metal element of the intermediate electrode 24 in the memory cell MC.

[0149] As a result, the ion beam etching apparatus 9 of the present embodiment can improve the efficiency of memory device manufacturing.

[0150] 2. Second embodiment The manufacturing apparatus of the second embodiment will be described with reference to FIGS.

[0151] FIG. 15 is a schematic diagram showing a configuration example of a manufacturing apparatus (ion beam etching apparatus) 9 used for manufacturing the magnetic memory 1 of this embodiment.

[0152] 15, in the ion beam etching apparatus 9 of the present embodiment, the wafer clamp unit 94B is formed of a material containing a high melting point metal element. The wafer clamp unit 94B includes one or more selected from titanium (Ti), tantalum (Ta), tungsten (W), titanium nitride (TiN), tantalum nitride (TaN), and tungsten nitride (WN).

[0153] The wafer clamp unit 94B is used as a supply source (target) for forming the conductor (layer) 241 of the intermediate electrode 24 that contains a high melting point metal element.

[0154] The side surface of the wafer clamp portion 94B is preferably inclined at a certain angle φ with respect to the upper surface of the wafer 100. The angle φ is greater than 0 degrees and less than 90 degrees.

[0155] The wafer clamp part 94B serving as a target can be disposed in the vicinity of the wafer 100. Therefore, even if the acceleration energy of the ion beam IB is relatively low, the sputtered member SRb can be implanted into a member on the wafer 100. For example, when the acceleration energy of the ion beam IB is about 100 eV, the sputtered member SRb is implanted inside the member (e.g., a carbon layer) on the wafer 100.

[0156] 16 and 17 are schematic diagrams showing the state of the ion beam etching apparatus 9 of this embodiment in the manufacturing process of the magnetic memory 1 of this embodiment.

[0157] As shown in FIG. 16, during normal etching by ion beam irradiation, the emission angle and / or emission range of the ion beam IB1 from the ion source 91 is controlled so that the ion beam IB1 is not irradiated onto the wafer clamp portion 94B.

[0158] As a result, the ion beam IB1 is irradiated only onto the wafer 100 without being irradiated onto the wafer clamp portion 94B.

[0159] Therefore, the components of the wafer clamping portion 94B do not get mixed with the components on the wafer 100 during normal etching using the ion beam IB.

[0160] 17, when forming the layer 241 containing a high-melting-point metal element by ion beam irradiation, the emission angle and / or emission range of the ion beam IB2 from the ion source 91 is controlled so that the ion beam IB2 is irradiated onto the wafer clamp unit 94B. For example, the emission angle θ of the ion beam IB2 when forming the layer 241 is made larger than the emission angle of the ion beam IB1 when performing normal etching so that the ion beam IB2 collides with the wafer clamp unit 94B. Alternatively, the emission range of the ion beam IB2 when forming the layer 241 is made larger than the emission range of the ion beam IB1 when performing normal etching.

[0161] The member SRb of the wafer clamp unit 94B sputtered by the ion beam IB2 is implanted into the conductive layer (member) 24Z on the wafer 100 at a position according to the magnitude of the acceleration energy of the ion beam IB2. Depending on the magnitude of the acceleration energy of the ion beam IB2, the member SRb of the wafer clamp unit 94B may be deposited on the conductive layer 24Z.

[0162] As a result, in the ion beam etching apparatus 9, a layer 241 made of the material (member SRb) of the wafer clamp portion 94B is formed on the wafer 100. The layer 241 contains a high-melting point metal element.

[0163] For example, the ion beam IB2 irradiated onto the wafer 100 may etch back the upper portion of a member (eg, the conductive layer 24Z) on the wafer 100.

[0164] When the wafer clamp unit 94B is used as a supply source for forming a member containing a high melting point metal element as in this embodiment, the configuration of the ion beam etching apparatus 9 can be simplified.

[0165] The ion beam etching apparatus 9 of this embodiment can obtain the same effects as those of the above-described embodiments.

[0166] 3. Variations Modifications of the memory device and manufacturing apparatus of the embodiment will be described with reference to FIGS.

[0167] FIG. 18 is a cross-sectional view showing a modified example of the magnetic memory 1 of the embodiment.

[0168] 18, the intermediate electrode 24Q includes two conductors 240 and 241. The intermediate electrode 24Q does not include any other conductor between the magnetoresistive element MTJ and the conductor 241.

[0169] The conductor 241 containing a high melting point metal element is in direct contact with the magnetoresistive element MTJ.

[0170] Thus, in this modification, the intermediate electrode 24Q is a laminate having a two-layer structure including the two conductors 240 and 241.

[0171] Even when the intermediate electrode 24Q has the structure shown in FIG. 18, the magnetic memory 1 of the modified example can obtain the effects of the above-described embodiment.

[0172] FIG. 19 is a cross-sectional view showing a modified example of the ion beam etching apparatus 9 of the embodiment.

[0173] As shown in FIG. 19, the ion beam etching apparatus 9 may include a target holder 95B that holds a target 97 having a through hole 970, and a wafer clamp 94B made of the same material as the target 97.

[0174] By irradiating the target 97 and the wafer clamp portion 94B with an ion beam, a component containing a high-melting point metal element from the target 97 and a component containing a high-melting point metal element from the wafer clamp portion 94B are implanted into the conductive layer 24Z made of carbon (or carbon nitride) or deposited on the conductive layer 24Z.

[0175] Even when the ion beam etching apparatus 9 has the configuration shown in FIG. 19, the ion beam etching apparatus 9 of the modified example can obtain the effects of the above-described embodiment.

[0176] FIG. 20 is a diagram showing a modified example of the method for manufacturing the magnetic memory 1 according to the embodiment.

[0177] As shown in FIG. 20, the etching back of the components on the wafer 100 and the formation of the layer containing a refractory metal element may be performed substantially simultaneously.

[0178] In this case, a target 97 having a through hole 970 is placed between the wafer holder 90 and the ion source 91 when the conductive layer 24Z is etched back.

[0179] Some of the ion beam IB passes through the through-holes 970 of the target 97 and reaches the wafer 100. As a result, the upper portion 249X of the conductive layer 24X on the wafer 100 is etched back, as shown in FIG.

[0180] Also, another ion beam IB collides with the target 97 in the through hole 970. This causes the sputtered target member SRa to fly to the wafer 100. As a result, a layer (conductor) 241X containing a high-melting-point metal element is formed in or on the conductive layer 24X being etched back.

[0181] The modified manufacturing method of the magnetic memory 1 according to the embodiment can improve the efficiency of the manufacturing process of the magnetic memory 1.

[0182] 4. Other In the above-mentioned embodiment, the memory device (magnetic memory) 1 in which the magnetoresistance effect element is used in the memory element MTJ is illustrated. However, the type of the memory element MTJ is not limited as long as the intermediate electrode 24 between the memory element MTJ and the switching element SEL has a structure including a layer 241 including a high melting point metal element.

[0183] For example, the memory device 1 of the embodiment may be a memory device using a transition metal oxide element having variable resistance characteristics as a memory element (e.g., a resistance change memory such as ReRAM (Resistive Random Access Memory)), a memory device using a phase change element as a memory element (e.g., a phase change memory such as PCRAM (Phase Change Random Access Memory)), or a memory device using a ferroelectric element as a memory element (e.g., a ferroelectric memory such as FeRAM (Ferroelectric Random Access Memory)).

[0184] The manufacturing apparatus (ion beam etching apparatus) 9 of the above-described embodiment may be used for purposes other than the manufacture of memory devices. For example, the manufacturing apparatus 9 of the embodiment may be used for the manufacture of semiconductor devices such as processors, image sensors, or power devices.

[0185] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0186] 1: memory device, SEL: switching element, MTJ: memory element, 24: electrode, 240, 241, 242: conductor, 9: manufacturing equipment, 90: wafer holder, 91: ion source, 92: position control mechanism, 93: shutter, 94A, 94B: wafer clamp, 95A: shutter holder, 95B: target holder, 97: target, 98: vacuum chamber, 99: vacuum pump, 970: through hole.< / n> < / m> < / j> < / m> < / n>

Claims

1. a wafer holder for holding a wafer; an ion source that outputs an ion beam; a shutter holder that holds a shutter and disposes the shutter between the wafer holder and the ion source when preventing the wafer from being irradiated with the ion beam; a target holder that holds a target that holds a through hole and disposes the target between the wafer holder and the ion source when a first layer including a component of the target is formed on the wafer; A manufacturing apparatus comprising:

2. a control mechanism connected to the shutter holder and the target holder, for moving the shutter holder and the target holder to control the position of the shutter and the position of the target; The manufacturing apparatus according to claim 1 , further comprising:

3. The target contains a high melting point metal element. The manufacturing apparatus according to claim 1 .

4. The target includes at least one of titanium (Ti), tantalum (Ta), tungsten (W), titanium nitride (TiN), tantalum nitride (TaN), and tungsten nitride (WN); The manufacturing apparatus according to claim 1 .

5. a feature of the wafer is etched by the ion beam; The manufacturing apparatus according to claim 1 .

6. forming the first layer on the wafer by sputtering the target with the ion beam irradiated into the through hole; The manufacturing apparatus according to claim 1 .

7. Etching a second layer on the wafer with the ion beam passing through the through hole. The manufacturing apparatus according to claim 6.

8. the first layer includes at least one of titanium (Ti), tantalum (Ta), tungsten (W), titanium nitride (TiN), tantalum nitride (TaN), and tungsten nitride (WN); The second layer includes at least one of carbon (C) and carbon nitride (CN); The manufacturing apparatus according to claim 7.

9. the wafer including a first member of a first element and a second member formed on the first member is placed on the wafer holder; the second member is etched by a first ion beam; The target is disposed between the wafer and the ion source; a second ion beam is applied to the target, and a first layer including a material of the target is formed in or on the second material; the wafer, on which a third member of a second element is formed above the second member after the first layer is formed, is placed on the wafer holder; the first member, the second member, the first layer, and the third member are etched by a third ion beam to form a memory cell including the first element and the second element. The manufacturing apparatus according to claim 1 .

10. the second component includes one of carbon and carbon nitride; The first layer contains a high melting point metal element. The manufacturing apparatus according to claim 9.

11. the first layer includes at least one of titanium (Ti), tantalum (Ta), tungsten (W), titanium nitride (TiN), tantalum nitride (TaN), and tungsten nitride (WN); The manufacturing apparatus according to claim 10.

12. a wafer holder for holding a wafer; a wafer clamp portion that fixes the wafer on the wafer holder and includes a high melting point metal element; an ion source that outputs an ion beam; Equipped with When etching a component on the wafer, the ion beam is irradiated onto the wafer; When forming the first layer containing the high melting point metal element on the wafer, the ion beam is irradiated onto the wafer clamp unit. Manufacturing equipment.

13. a shutter holder that holds a shutter and disposes the shutter between the wafer holder and the ion source when preventing the wafer from being irradiated with the ion beam; a control mechanism connected to the shutter holder and configured to move the shutter holder and control the position of the shutter; The manufacturing apparatus of claim 12 further comprising:

14. The wafer clamping portion includes at least one of titanium (Ti), tantalum (Ta), tungsten (W), titanium nitride (TiN), tantalum nitride (TaN), and tungsten nitride (WN); The manufacturing apparatus according to claim 12.

15. placing the wafer, the wafer including a first member of a first element and a second member formed on the first member, on the wafer holder; the ion beam is irradiated onto the wafer clamp portion, and the first layer is formed in or on the second member by sputtering a member of the wafer clamp portion; the wafer, on which a third member of a second element is formed on the second member after the formation of the first layer, is placed on the wafer holder; the first member, the second member, the first layer, and the third member are etched by the ion beam to form a memory cell including the first element and the second element; The manufacturing apparatus according to claim 12.

16. the second component includes one of carbon and carbon nitride; the first layer includes at least one of titanium (Ti), tantalum (Ta), tungsten (W), titanium nitride (TiN), tantalum nitride (TaN), and tungsten nitride (WN); The manufacturing apparatus according to claim 15.

17. A memory element; A switching element; an electrode between the memory element and the switching element; Equipped with The electrode is a first conductor including one of carbon (C) and carbon nitride (CN); a second conductor including a high melting point metal element; Including, the second conductor directly contacts the memory element; Memory device.

18. The second conductor includes at least one of titanium (Ti), tantalum (Ta), tungsten (W), titanium nitride (TiN), tantalum nitride (TaN), and tungsten nitride (WN); 20. The memory device of claim 17.

19. The memory element is a magnetoresistance effect element.

20. The memory device of claim 17.

Images