Information processing device and method

Abstract

To provide an information processing device that enables chips having initial failures to be estimated with high accuracy.SOLUTION: A first data set is a set of inspection results for each chip obtained by a first inspection for a plurality of chips formed on or cut from the wafer. A second data set is a set of data indicating the presence or absence of early failures obtained by a second inspection for the plurality of chips, for each chip. A processor identifies a cluster of chips that do not satisfy a first criterion on the basis of the first data set. The processor then calculates a third data set, which is a set of feature amounts for each chip related to a distance to the cluster. The processor then generates a trained machine learning model by training using the first data set and the third data set as input data and using the second data set as truth data.SELECTED DRAWING: Figure 7

Description

[Technical field]

[0001] The present embodiment relates to an information processing apparatus and method. [Background technology]

[0002] One type of defect in semiconductor integrated circuits is known as early failure. Early failure is one of the failures that occur after a product is shipped, and occurs after a significantly smaller number of uses than the product's useful life.

[0003] When manufacturing chips for semiconductor integrated circuits, it is desirable to accurately estimate whether or not each of a plurality of chips formed on a wafer or a plurality of chips cut from a wafer has an initial failure. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2008-300599 A Summary of the Invention [Problem to be solved by the invention]

[0005] An object of one embodiment is to provide an information processing apparatus and method that enable accurate estimation of chips that have initial failures. [Means for solving the problem]

[0006] According to one embodiment, an information processing device includes a processor. The processor acquires a first data set and a second data set. The first data set is a set of inspection results for each chip obtained by a first inspection for a plurality of chips formed on a wafer or cut out from the wafer. The second data set is a set of data indicating the presence or absence of an initial failure for each chip obtained by a second inspection for the plurality of chips. The processor identifies a cluster of chips that does not satisfy a first criterion based on the first data set. Then, the processor calculates a third data set that is a set of feature amounts for each chip related to a distance to the cluster. Then, the processor executes learning for a machine learning model using the first data set and the third data set as input data and the second data set as correct answer data. Then, the processor outputs the learned machine learning model. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram showing an example of a configuration of an information processing apparatus according to an embodiment. [Diagram 2] 6 is a diagram showing an example of a calculation operation of a surrounding feature set executed by the information processing apparatus according to the embodiment; [Diagram 3] 11 is another diagram showing an example of the operation of calculating a surrounding feature set executed by the information processing device according to the embodiment. FIG. [Figure 4] 11 is a diagram showing an example of an operation of identifying a bad cluster, which is executed by the information processing apparatus according to the embodiment; [Diagram 5] FIG. 4 is a diagram showing an example of data used for learning an incipient fault estimation model according to the embodiment. [Figure 6] FIG. 13 is a diagram showing a method of using the trained incipient fault estimation model according to the embodiment. [Figure 7] 4 is a flowchart showing an example of an operation for generating an initial fault estimation model according to the embodiment. [Figure 8] 11 is a flowchart showing an example of a score calculation operation according to an embodiment. [Figure 9]FIG. 11 is a diagram for explaining a specific example of a method for determining a second item according to the embodiment. [Figure 10] 11 is a flowchart showing an example of an operation of estimating a chip CP having an initial failure according to an embodiment. [Figure 11] 13A and 13B are diagrams for explaining an averaging operation on a test data set according to a modified example. [Figure 12] 13A and 13B are diagrams showing an example of processing a peripheral feature amount set according to a modified example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] The information processing device according to the embodiment has two main functions: a function to generate an early failure estimation model, and a function to estimate a chip having an early failure using the early failure estimation model. The early failure estimation model is a trained machine learning model that outputs numerical information indicating the probability of whether or not a chip has an early failure.

[0009] The information processing device according to the embodiment may be configured as a computer of an inspection device that inspects wafers or chips, or may be configured as a device (e.g., a server) separate from the inspection device. The function of generating an early failure estimation model and the function of estimating chips having early failures using the early failure estimation model may be implemented in different computers. For example, the function of generating an early failure estimation model may be implemented in a server, and the function of estimating chips having early failures using the early failure estimation model may be implemented in a computer of the inspection device.

[0010] In this way, the two functions of the information processing device according to the embodiment can be implemented in various computers. Here, as an example, the following description will be given assuming that the two functions are implemented in one computer.

[0011] Hereinafter, an information processing apparatus and method according to an embodiment will be described in detail with reference to the accompanying drawings. Note that the present invention is not limited to the embodiment.

[0012] (Embodiment) FIG. 1 is a diagram illustrating an example of a configuration of an information processing device according to an embodiment.

[0013] The information processing device 1 includes a CPU (Central Processing Unit) 10, a storage device 11, a RAM (Random Access Memory) 12, a ROM (Read Only Memory) 13, an IO (Input / Output) device 14, and a bus 15. The CPU 10, the storage device 11, the RAM 12, the ROM 13, and the IO device 14 are electrically connected to the bus 15.

[0014] In addition to these, the information processing device 1 may also include an HMI (Human Machine Interface) for an operator to operate the information processing device 1, and the like.

[0015] The CPU 10 is a processor that executes computer programs.

[0016] The IO device 14 is an interface for the information processing device 1 to transfer data between the information processing device 1 and an external device. The IO device 14 may be an interface device capable of wireless data transfer, or may be an interface device capable of data transfer via a wired communication path.

[0017] The RAM 12 is a volatile memory that operates faster than the ROM 13 or the storage device 11. The RAM 12 provides the CPU 10 with an area as a cache or a buffer.

[0018] The ROM 13 and the storage device 11 are memories capable of storing information, such as data or computer programs, in a non-volatile manner. The storage device 11 can store more information than the ROM 13. The storage device 11 can be configured, for example, by a hard disk drive (HDD), a solid state drive (SSD), or a combination of these.

[0019] The storage device 11 may be provided outside the information processing device 1, and the information processing device 1 and the storage device 11 may be connected via a network or the like. The storage device 11 may be a removable device such as a Universal Serial Bus (USB) memory, a Secure Digital (SD) card, or an external HDD.

[0020] The storage device 11 stores a model generation program 20 and an early failure estimation program 21. The model generation program 20 is a computer program for realizing a function of generating an early failure estimation model. The early failure estimation program 21 is a computer program for realizing a function of estimating a chip having an early failure using the early failure estimation model. The CPU 10 loads these computer programs from the storage device 11 to the RAM 12. The CPU 10 executes these computer programs loaded into the RAM 12 to realize each function.

[0021] When generating an initial fault estimation model, the information processing device 1 uses one or more test data sets and an initial fault label set.

[0022] Each inspection data set is a set of inspection results (referred to as inspection data) for each chip obtained by the first inspection. Each inspection data set includes inspection data for multiple chips included in one wafer.

[0023] The first inspection is performed before shipment of the wafer or chips. The first inspection may be performed on a plurality of chips formed on the wafer, or may be performed on a plurality of chips cut out from the wafer. Each piece of inspection data is associated with position information on the wafer of the chip from which the data was obtained.

[0024] The first test may include tests of multiple items. When each chip is a memory chip, the tests of multiple items included in the first test may include, for example, a test of a neutral threshold, a test of a leakage current after applying stress between electrodes, a test of the number of memory blocks whose characteristic values ​​do not satisfy a standard, etc. The neutral threshold is the value of the threshold voltage of a memory cell transistor in a state where no write or read has been performed yet.

[0025] The early failure label set is a set of inspection data for each chip obtained by the second inspection, and includes the inspection data for all chips included in one wafer.

[0026] The second inspection is an inspection for the presence or absence of an early failure. The inspection data from the second inspection is binary data indicating whether or not there is an early failure. The inspection data from the second inspection is referred to as an early failure label.

[0027] If each chip is a memory chip, the second test is, for example, to execute a cycle of programming data and erasing data multiple times, and then, for example, to execute a test to see whether the data can be read normally. A chip that cannot read data normally is determined to have an early failure. A chip that can read data normally is determined to not have an early failure.

[0028] The performance of the wafer or chip on which the second inspection has been performed is degraded compared to the chip in the state immediately before the second inspection. Therefore, the wafer or chip on which the second inspection has been performed is not suitable for shipment. If the second inspection is performed on all chips, the presence or absence of initial failures for all chips will be determined. However, the chip on which the second inspection has been performed cannot be shipped. Therefore, it is desired to accurately estimate the presence or absence of initial failures without performing the second inspection.

[0029] The early failure estimation model is a model for calculating the probability of occurrence of an early failure without needing the results of the second inspection. In order to make such a judgment possible, the early failure label obtained by the second inspection is used as the ground truth data during learning.

[0030] When defective chips are densely packed on a wafer, there is a tendency that early failures are more likely to occur in chips adjacent to the group of densely packed defective chips. Therefore, the information processing device 1 calculates a peripheral feature amount, which is a feature amount related to the distance to the group of defective chips, for each chip. Then, a peripheral feature amount set including the peripheral feature amounts for all chips included in one wafer is used to determine early failures.

[0031] In this specification, a defective chip refers to a chip whose inspection data for a certain inspection item is worse than the standard for a non-defective chip. The standard for a non-defective chip is determined autonomously by the information processing device 1, as will be described in detail later. Therefore, a defective chip does not have to be synonymous with a chip that does not satisfy the inspection standard for whether or not it can be shipped.

[0032] The group of defective chips is identified by clustering. Hence, hereinafter, the group of defective chips is referred to as a defective cluster. The method of identifying the defective cluster by clustering will also be described in detail later.

[0033] 2 and 3 are diagrams illustrating an example of the operation of calculating a surrounding feature set executed by the information processing device 1 according to the embodiment.

[0034] Part (A) of FIG. 2 depicts a plurality of chips CP formed on a wafer WF. Each chip CP is hatched based on the inspection data obtained by a first inspection of a certain item. For simplicity of explanation, as an example, the inspection data can be 0, 5, or 10. The blackened chip CPs are chip CPs with inspection data of 10. The dot-hatched chip CPs are chip CPs with inspection data of 5. The whitened chip CPs are chip CPs with inspection data of 0.

[0035] The information processing device 1 classifies these chips CP into a group of defective chips and a group of first non-defective chips by binarization using a binarization threshold value Th (S1).

[0036] In step S1, the information processing device 1 identifies a chip CP whose inspection data does not meet the standard for a good chip as a defective chip. The first good chip is a chip whose inspection data meets the standard for a good chip. The binarization threshold Th is a threshold that defines the standard for a good chip.

[0037] Whether a chip CP whose inspection data is greater than the binarization threshold value Th or a chip CP whose inspection data is smaller than the binarization threshold value Th is regarded as a defective chip depends on the type of inspection data.

[0038] In the case of inspection data of a type in which the larger the value, the worse the condition, the information processing device 1 classifies chips CP whose inspection data is greater than the binarization threshold value Th as defective chips, and classifies chips CP whose inspection data is smaller than the binarization threshold value Th as first good chips. In the case of inspection data of a type in which the smaller the value, the worse the condition, the information processing device 1 classifies chips CP whose inspection data is greater than the binarization threshold value Th as first good chips, and classifies chips CP whose inspection data is smaller than the binarization threshold value Th as defective chips.

[0039] For a chip CP whose inspection data is equal to the binarization threshold value Th, the information processing device 1 may classify it as a first good chip or as a defective chip.

[0040] Part (B) of FIG. 2 shows the results of classification using the binarization threshold value Th. The blackened chips CP are chips CP classified as defective chips. The whitened chips CP are chips CP classified as first-quality chips. Note that the inspection data here is of a type in which the larger the value, the worse the condition. Therefore, chips CP with inspection data larger than the binarization threshold value Th are classified as defective chips, and chips CP with inspection data smaller than the binarization threshold value Th are classified as first-quality chips.

[0041] Next, the information processing device 1 identifies bad clusters by clustering (S2).

[0042] In part (C) of FIG. 2, the black chips CP are chips that form defective clusters. The diagonally hatched chips CP are defective chips that do not form defective clusters. A defective chip that does not form a defective cluster is referred to as an isolated defective chip.

[0043] Let us now turn to Figure 3 for explanation. After identifying the defective cluster, the information processing device 1 identifies a chip CP adjacent to the defective cluster from among the first non-defective chips (S3).

[0044] Part (D) of FIG. 3 shows the result of identifying chip CPs adjacent to the defective cluster. The black chip CPs are chip CPs that constitute the defective cluster. The dot-hatched chip CPs are chip CPs adjacent to the defective cluster.

[0045] In the example shown in part (D), being adjacent to a defective cluster means being in contact with any of the chip CPs constituting the defective cluster at a side or a corner. The definition of being adjacent to a defective cluster is not limited to this. For example, a first good chip that is in contact with any of the chip CPs constituting the defective cluster at a side or a corner via a predetermined number of chip CPs or less may be identified as a chip CP adjacent to the defective cluster. In other words, a chip CP that is considered to be close to the defective cluster is identified as a chip CP adjacent to the defective cluster.

[0046] In the example shown in part (D), not only the chip CP adjacent to the defective cluster but also the chip CP adjacent to the isolated defective chip are identified. This is because the second adjacent chip is considered to have a higher probability of early failure occurrence than the second good chip, although not as high as the first adjacent chip. The chip CP with vertical line hatching is the chip CP adjacent to the isolated defective chip.

[0047] Hereinafter, the chip CP adjacent to the defective cluster is referred to as the first adjacent chip. The chip CP adjacent to the isolated defective chip is referred to as the second adjacent chip. The chip CP that is not a defective chip, the first adjacent chip, or the second adjacent chip is referred to as the second good chip.

[0048] Next, the information processing device 1 acquires the peripheral feature of each chip CP, as shown in part (E). The information processing device 1 assigns a peripheral feature of "5" to the chip CP that constitutes the defective cluster. The information processing device 1 assigns a peripheral feature of "4" to the isolated defective chip. The information processing device 1 assigns a peripheral feature of "3" to the first adjacent chip. The information processing device 1 assigns a peripheral feature of "2" to the second adjacent chip. The information processing device 1 assigns a peripheral feature of "1" to the second non-defective chip.

[0049] It is optional to specify the second adjacent chip. It is optional to make the values ​​of the peripheral feature quantities different between the second good chip and the second adjacent chip. It is optional to make the values ​​of the peripheral feature quantities different between the isolated defective chip and the chips CP constituting the defective cluster. As long as different values ​​are given to each chip CP as the peripheral feature quantities according to the distance to the defective cluster, the way in which the peripheral feature quantities are given can be modified in various ways.

[0050] Hereinafter, a chip CP that is neither a defective chip nor the first adjacent chip will be referred to as a third good chip. In the example shown in FIG. 3, the third good chip is the second adjacent chip or the second good chip.

[0051] FIG. 4 is a diagram illustrating an example of an operation of identifying a bad cluster, which is executed by the information processing device 1 according to the embodiment.

[0052] As described above, the bad clusters are identified by clustering. As the clustering algorithm, an algorithm capable of adjusting the cluster identification result by a parameter is used. As an example of the algorithm capable of adjusting the bad cluster identification result by a parameter, the information processing device 1 identifies the bad clusters based on an algorithm called DBSCAN (Density-Based Spatial Clustering of Applications with Noise).

[0053] DBSCAN uses two parameters. These two parameters are called parameters P N , P R It is written as follows.

[0054] The information processing device 1 selects one defective chip and calculates a radius P R Then, the information processing device 1 counts the number of defective chips included in the set circle. When the number of defective chips included in the set circle is P NIf the number of defective chips included in the set circle is less than P, the information processing device 1 does not regard the selected defective chip as a component of the defective cluster. N If the number is greater than the number of defective chips, the information processing device 1 regards the selected defective chip as a component of a defective cluster.

[0055] In the example shown in FIG. 4, the number of defective chips included in a circle Ca centered on a certain defective chip CPa is one. For example, N If the number of defective chips in the circle Ca is "3", the number of defective chips in the circle Ca is P N Since the number of defective chips CPa is smaller than the number of defective chips already determined to be a component of a certain defective cluster, the defective chip CPa is determined not to be a component of the defective cluster. R All defective chips in a circle are in the same circle even if the number of defective chips in the circle is P N At least one of the defective clusters is considered to belong to the defective cluster.

[0056] The number of defective chips in the circle Cb centered on another defective chip CPb is 5. The number of defective chips in the circle Cb is P N Since the number is greater than 1, the defective chip CPa is determined to be a component of the defective cluster.

[0057] The information processing device 1 selects the defective chips, sets the circles, and performs a judgment based on the number of defective chips included in the circles for each defective chip in one wafer WF. This identifies a defective cluster. A defective chip that is not a component of a defective cluster is identified as an isolated defective chip.

[0058] According to DBSCAN, for example, P N If the value of is "1", it can be identified as a cluster even if the number of elements is "1". Also, if the radius P R P in the circle NAs long as more than one defective chip is included, the group of defective chips can be identified as a single cluster even if the group of defective chips is composed of two or more groups that are spaced apart from each other. That is, in an embodiment, a defective cluster may be composed of one defective chip. Also, a defective cluster may be composed of two or more groups that are spaced apart from each other.

[0059] It should be noted that the clustering algorithm that can be used to identify defective clusters is not limited to DBSCAN. Any algorithm can be used as long as it can identify groups of closely packed defective chips. Even an algorithm that does not use parameters can be used. However, when an algorithm that does not use parameters is used, the parameter optimization described later is not performed for that algorithm.

[0060] The information processing device 1 executes learning of an incipient fault estimation model by using the test data set and a peripheral feature set calculated from the test data set.

[0061] FIG. 5 is a diagram illustrating an example of data used for learning the initial fault estimation model according to the embodiment.

[0062] 5, two test data sets DS1 and DS2 and two peripheral feature sets FS1 and FS2 are used as explanatory variables, and an initial fault label set is used as a response variable. That is, for an initial fault estimation model, learning is performed using two test data sets DS1 and DS2 and two peripheral feature sets FS1 and FS2 as input data, and the initial fault label set as ground truth data.

[0063] The inspection dataset DS1 is an inspection dataset obtained by the first inspection of item I1. The inspection dataset DS2 is an inspection dataset obtained by the first inspection of item I2. The surrounding feature set FS1 is a surrounding feature set calculated from the inspection dataset obtained by the first inspection of item I3. The surrounding feature set FS2 is a surrounding feature set calculated from the inspection dataset obtained by the first inspection of item I4. The inspection datasets DS1, DS2 and the surrounding feature sets FS1, FS2 are obtained from a common wafer WF.

[0064] Note that the inspection data set used to calculate the surrounding feature set may be an inspection data set used as an explanatory variable, or may not be an inspection data set used as an explanatory variable.

[0065] Furthermore, the number of inspection data sets used as explanatory variables is arbitrary as long as it is equal to or greater than 1. Similarly, the number of peripheral feature sets used as explanatory variables is arbitrary as long as it is equal to or greater than 1.

[0066] Hereinafter, an inspection item for obtaining an inspection data set used as an explanatory variable is referred to as a first item. An inspection item for obtaining an inspection data set used for calculating a peripheral feature set used as an explanatory variable is referred to as a second item. In the example shown in FIG. 5, items I1 and I2 each correspond to the first item. Items I3 and I4 each correspond to the second item.

[0067] By using the trained early failure estimation model 100 configured in this manner, it becomes possible to accurately estimate the chip CP having an early failure.

[0068] 6 is a diagram showing a method of using the trained incipient fault estimation model according to the embodiment, which corresponds to the example shown in FIG.

[0069] The initial fault estimation model 100 receives the test data sets DS3 and DS4 and the peripheral feature sets FS3 and FS4.

[0070] The inspection data set DS3 is an inspection data set obtained by inspecting item I1 on multiple chips CP (referred to as multiple chips CP to be judged) of a certain wafer WF. The inspection data set DS4 is an inspection data set obtained by inspecting item I2 on the multiple chips CP to be judged. The surrounding feature set FS3 is a surrounding feature set calculated from the inspection data set obtained by inspecting item I3 on ​​the multiple chips CP to be judged. The surrounding feature set FS4 is a surrounding feature set calculated from the inspection data set obtained by inspecting item I4 on the multiple chips CP to be judged.

[0071] The initial failure estimation model 100 outputs an initial failure probability for each of a plurality of chips CP to be judged based on input data. The initial failure probability is the probability that the chip CP has an initial failure.

[0072] The early failure probability is numerical information corresponding to the possibility that the chip CP has an early failure. As the numerical information output by the early failure estimation model 100, any numerical information expressed other than probability may be adopted as long as it corresponds to the possibility that the chip CP has an early failure.

[0073] As mentioned many times, a set of peripheral features, which are features related to the distance to a defective cluster, is used as one of the input data of the early failure estimation model 100. Therefore, the method of identifying a defective cluster or a defective chip may affect the accuracy of estimating a chip CP having an early failure.

[0074] Therefore, the information processing device 1 determines the value of the binarization threshold Th for identifying the defective chip and the parameter P N , P RThe optimization is configured to optimize the binarization threshold Th and the parameter P so that the accuracy of the estimation of the chip CP having the initial failure is as high as possible. N , P R The aim of the present invention is to set the respective values ​​of

[0075] In addition, in the manufacturing process of a wafer or chip, a number of first inspections are performed. The selection of the inspection data set used to calculate the peripheral feature set can also affect the accuracy of the estimation of the chip CP having early failures.

[0076] Therefore, the information processing device 1 is configured to select, from among a plurality of test data sets, an test data set that enables the most accurate estimation of chips CP having initial defects as the test data set for calculating the peripheral feature set.

[0077] Threshold value Th and parameter P N , P R Details of how to optimize the values ​​of each of and how to select a test data set for computing the marginal feature set will be made clear in the description of the operation.

[0078] In the following, the binarization threshold Th and the parameter P N , P R These are collectively called parameters Th and P N , P R In addition, the accuracy of the estimation of the chip CP having an initial fault is simply denoted as the estimation accuracy.

[0079] Next, the operation of the information processing device 1 will be described.

[0080] 7 is a flowchart showing an example of an operation for generating the initial fault estimation model 100 according to the embodiment. Each process shown in this flowchart is realized by the CPU 10 executing the model generation program 20.

[0081] First, the CPU 10 acquires a plurality of inspection data sets obtained by a first inspection on a plurality of chips CP of a certain wafer WF, and an initial failure label set obtained by a second inspection on the plurality of chips CP of the wafer WF (S101).

[0082] The plurality of test data sets and the initial fault label set are stored, for example, in the storage device 11. The CPU 10 may acquire these sets from the storage device 11. Alternatively, the CPU 10 may acquire these sets from an external device (for example, a test device or a server) via the IO device 14.

[0083] Next, the CPU 10 selects one of the multiple test data sets (S102).

[0084] After the process of S102, (i) the parameters Th, P N , P R and (ii) optimizing the values ​​of the parameters Th, P N , P R and evaluating the estimation accuracy when the value of (i) is used. The process of S102 is a process of selecting one test dataset to be the target of the operations (i) and (ii). The test dataset selected as the target of the operations (i) and (ii) is referred to as the first target dataset. Also, the evaluation value of the estimation accuracy is referred to as the score.

[0085] Here, the score is numerical information that assumes a larger value as the estimation accuracy increases. In other words, a larger score value means better estimation accuracy, and a smaller score value means worse estimation accuracy. Note that the relationship between the score value and the estimation accuracy is not limited to this.

[0086] Parameters Th, P N , P R In the optimization operation of the value of , the score calculation operation calculates the score by using the parameters Th, P N , P RThe score calculation is performed multiple times with some or all of the parameters Th and P N , P R In order to make some or all of the parameters Th, P N , P R There are multiple candidate value sets (referred to as candidate value sets) for Th, P. N , P R Each candidate value in each candidate value set is determined so that some or all of the candidate values ​​are different from any of the other candidate value sets.

[0087] The CPU 10 selects one of the multiple candidate value sets and uses the selected candidate value set as the parameters Th, P N , P R (S103). Next, the CPU 10 executes a score calculation operation (S104).

[0088] FIG. 8 is a flowchart illustrating an example of a score calculation operation according to the embodiment.

[0089] First, the CPU 10 identifies defective chips based on a comparison between the inspection data of each chip included in the first target data set and the binarization threshold value Th (S201). The CPU 10 executes the same process as S1 using the candidate value of the binarization threshold value Th set by the process of S103.

[0090] CPU10 sets the parameter P N , P R The CPU 10 identifies bad clusters by clustering using the parameter P set in the process of S103 (S202). N , P R Using the candidate values, perform the same process as S2.

[0091] Based on the defective cluster, the CPU 10 identifies a group of the first adjacent chips and a group of the third good chips (S203). The CPU 10 identifies a group of the first adjacent chips and a group of the third good chips by a process similar to the process of S3. The group of the third good chips is a group including the second adjacent chip and the second good chip. In other words, the third good chip is not a defective chip but is a chip not included in the first adjacent chips.

[0092] The CPU 10 calculates a score (referred to as score SC) using the following formula (1) (S204): In this specification, "*" denotes a multiplication operator. SC = (R1 - R2) * R3 (1)

[0093] R1 is the incidence rate of early failure chips in the group of first adjacent chips. In other words, R1 is the ratio of the number of chips CP with early failures in the group of first adjacent chips to the number of chips CP in the group of first adjacent chips.

[0094] R2 is the incidence rate of early failure chips in the group of third good chips. In other words, R2 is the ratio of the number of chips CP having early failures included in the group of third good chips to the number of chips CP included in the group of third good chips.

[0095] R3 is the ratio of the number of chips CP with early failures included in the group of first neighboring chips to the total number of early failure chips.

[0096] The CPU 10 identifies early-failure chips included in the group of first adjacent chips based on the early failure label set, and calculates R1 by dividing the number of identified early-failure chips by the number of chips CP included in the group of first adjacent chips.

[0097] Furthermore, the CPU 10 identifies early failure chips included in the third group of good chips based on the early failure label set, and calculates R2 by dividing the number of identified early failure chips by the number of chips CP included in the third group of good chips.

[0098] Then, the CPU 10 calculates the score SC based on R1, R2, and R3 and equation (1).

[0099] If a group of chips determined to have early failures contains many chips that do not actually have early failures, the yield rate will decrease. Also, if a group of chips estimated not to have early failures contains chips that actually have early failures, chips with early failures will be shipped, which may cause a loss of customer trust. Therefore, the calculation method of the score SC is designed to take into account both the yield rate and the screening performance.

[0100] The (R1-R2) part on the right side of equation (1) corresponds to the yield rate. A larger value of (R1-R2) means a higher yield rate. The R3 part on the right side of equation (2), which is multiplied by (R1-R2), corresponds to the screening performance. A larger value of R3 means higher screening performance.

[0101] Equation (1) is configured so that the score SC is calculated by multiplying (R1-R2) by R3. The score SC is higher when the yield rate is higher and when the screening performance is higher. Therefore, the binarization threshold Th and the parameter P are calculated using equation (1). N , P R By optimizing the settings of the binarization threshold Th and parameter P, a high yield rate and high screening performance can be achieved at the same time. N , P R It is possible to determine the set value of

[0102] The calculation method of the score SC is not limited to this. As long as the score SC is calculated based on the number of early failure chips included in the first group of adjacent chips and the number of early failure chips included in the first group of good chips, the calculation method of the score SC may be modified arbitrarily. For example, the score SC may be obtained by adding (R1-R2) and R3.

[0103] Following the process of S204, the CPU 10 determines whether or not the ratio of the number of the third conforming chips to the number of the first adjacent chips is less than a predetermined threshold value Th1 (S205).

[0104] If the ratio of the number of third good chips to the number of first adjacent chips exceeds a predetermined threshold value Th1 (S205: No), CPU 10 determines whether the ratio of the number of initial failed chips included in the group of first adjacent chips to the total number of initial failed chips is less than a predetermined threshold value Th2 (S206).

[0105] The total number of early failure chips used in the process of S206 is the total number of early failure chips in all wafers. When the series of operations shown in FIG. 8 is executed for each of one or more wafers, the CPU 10 calculates the total number of early failure chips in the one or more wafers. Then, the CPU 10 uses the total number obtained by the calculation in the determination process of S206.

[0106] The process of S205 is a judgment process executed to prevent the yield rate from becoming extremely low, and therefore, a threshold value Th1 is set based on the allowable lower limit of the yield rate.

[0107] The process of S206 is a judgment process executed to prevent the screening performance from becoming extremely low, and therefore, a threshold value Th2 is set based on the allowable lower limit of the screening performance.

[0108] If the ratio of the number of third good chips to the number of first adjacent chips does not meet threshold value Th1 (S205: Yes), or if the ratio of the number of initial faulty chips included in the group of first adjacent chips to the total number of initial faulty chips does not meet threshold value Th2 (S206: Yes), CPU 10 reduces the value of score SC (S207) and the score calculation operation ends.

[0109] In the process of S207, the CPU 10 sets the value of the score SC to, for example, 0 or a negative value. By significantly lowering the value of the score SC corresponding to the combination of the first target data set and the used candidate value set, this combination becomes less likely to be adopted.

[0110] If the ratio of the number of initial faulty chips included in the group of first adjacent chips to the total number of initial faulty chips exceeds the threshold value Th2 (S206: Yes), the CPU 10 skips the process of S207 and ends the score calculation operation.

[0111] As described above, the score SC is numerical information that takes a larger value as the estimation accuracy is higher. Therefore, decreasing the value of the score SC in S205 and S207 is to deem the estimation accuracy to be poor for the sake of convenience. That is, the CPU 10 changes the score SC to a poor value in S205 and S207. Therefore, for example, if the score SC is numerical information that takes a smaller value as the estimation accuracy is higher, the CPU 10 increases the value of the score SC in S205 and S207.

[0112] Returning to FIG. After the score calculation operation, the CPU 10 stores the score SC in association with the first target data set and the candidate value set used in the score calculation operation. The CPU 10 stores this information in the RAM 12, for example.

[0113] The CPU 10 judges whether or not an unselected candidate value set remains (S105). If an unselected candidate value set remains (S105: Yes), the CPU 10 selects one of the unselected candidate value sets and sets the selected candidate value set as the parameters Th, P N , P R (S106). Then, the control proceeds to S104.

[0114] If there are no unselected candidate value sets remaining (S105: No), CPU 10 associates the best score among the multiple scores obtained by the score calculation operations performed multiple times for the current first target data set, and the candidate value set at the time the best score was obtained, with the first target data set (S107).

[0115] 8, the score is designed to be larger as the estimation accuracy is higher. Therefore, in the process of S107, the CPU 10 stores the highest score and the candidate value set when the highest score was obtained.

[0116] In the embodiment, the CPU 10 executes the score calculation operation for all candidate value sets by the loop process of S103 to S106 in order to identify the best score and the candidate value set that can obtain the best score. The CPU 10 may use a method such as Bayesian optimization to identify the candidate value set that can obtain the best score and the best score from a part of the candidate value sets.

[0117] The CPU 10 resets the selection history of the candidate value sets (S108), and then determines whether or not any unselected test data sets remain (S109).

[0118] If there are unselected test data sets remaining (S109: Yes), the CPU 10 selects one of the unselected test data sets as a new first target data set (S110), and then the control proceeds to S103.

[0119] If there are no unselected inspection data sets remaining (S109: No), the CPU 10 selects the second item and parameters Th, P based on the best score (the highest score in this example) of each inspection data set. N , P R The final setting value is determined (S111).

[0120] In the process of S111, the CPU 10 identifies the test data set with the highest score SC. Then, the CPU 10 determines the item of the first test from which the identified test data set was obtained as the second item. The CPU 10 also determines the candidate value set associated with the identified test data set as the second item, using the parameters Th, P N , P R This is determined as the final setting value.

[0121] As described above, the number of test data sets for the second item is not limited to 1. In the process of S111, a predetermined number of items are determined as the second items based on a predetermined number of test data sets having the highest score SC.

[0122] 9 is a diagram for explaining a specific example of a method for determining a second item according to an embodiment. In the example shown in this figure, the highest score of the test data set for item Ia is 20 points, which is the highest, the highest score of the test data set for item Ik is 15 points, which is the second highest, the highest score of the test data set for item Id is 13 points, which is the third highest, and the highest score of the test data set for item Iw is 9 points, which is the fourth highest.

[0123] When the number of second items is set to two, the CPU 10 selects the item Ia and the item Ik as the two items having the highest maximum scores, and determines each of the item Ia and the item Ik as the second item.

[0124] Then, the CPU 10 calculates the candidate value set when the highest score is obtained for the test data set of the item Ia by using the parameters Th and P N , P RThe set of candidate values ​​that obtains the highest score for the test data set of item Ik is determined as the final set of parameters Th, P N , P R This is determined as the final setting value.

[0125] Returning to FIG. Following the process of S111, the CPU 10 calculates a set of surrounding feature amounts from the second item of the inspection data set (S112). N , P R The final set value is used to execute the processes in S1 to S4, thereby acquiring a peripheral feature set.

[0126] Next, the CPU 10 generates the incipient fault estimation model 100 by learning using the first item of the test data set and the peripheral feature set as input data and the incipient fault label set as correct answer data (S113).

[0127] The CPU 10 outputs the generated initial failure estimation model 100 to the RAM 12, the storage device 11, an external device, or the like (S114), and the operation of generating the initial failure estimation model 100 according to the model generation program 20 is completed.

[0128] 10 is a flowchart showing an example of an operation of estimating a chip CP having an initial fault according to an embodiment of the present invention. Each process shown in this flowchart is realized by the CPU 10 executing the initial fault estimation program 21.

[0129] The CPU 10 acquires an inspection data set of a first item for the wafer WF to be judged and an inspection data set of a second item for the wafer WF to be judged (S301).

[0130] The CPU 10 also calculates parameters Th and P associated with the second item. N , P R The set value (that is, the final set value determined in the process of S111) is obtained (S302).

[0131] The CPU 10 calculates a set of surrounding features from the second test data set (S303). N , P R The process of S1 to S4 is executed using the set values ​​to obtain a surrounding feature set.

[0132] The CPU 10 inputs the first item of the test data set and the peripheral feature set to the early failure estimation model 100 to calculate the early failure probability for each chip CP (S304).

[0133] Then, the CPU 10 estimates the chip CP having an initial failure based on the initial failure probability of each chip CP (S305). The CPU 10 estimates the chip CP having an initial failure by, for example, comparing the initial failure probability with a predetermined threshold value. More specifically, the CPU 10 estimates that a chip CP having an initial failure probability higher than a predetermined threshold value Th3 is a chip CP having an initial failure. The CPU 10 estimates that a chip CP having an initial failure probability lower than the threshold value Th3 is a chip CP not having an initial failure. Note that the method of estimation based on the initial failure probability is not limited to this. After the process of S305, the operation of identifying the chip CP having an initial failure is completed.

[0134] As described above, according to the embodiment, the CPU 10 acquires an inspection data set and an initial fault label set (see, for example, S101 in FIG. 7). Then, the CPU 10 identifies a defective cluster, that is, a cluster of chips that do not meet the criteria for a non-defective product, based on the inspection data set (see, for example, S112 in FIG. 7 and S1 to S2 in FIG. 2). Then, the CPU 10 calculates a peripheral feature set, which is a set of features for each chip CP related to the distance to the defective cluster (see, for example, S112 in FIG. 7 and S3 to S4 in FIG. 3). Then, the CPU 10 executes learning for the machine learning model using the inspection data set and the peripheral feature set as input data and the initial fault label set as ground truth data (see, for example, S113 in FIG. 7). Then, the CPU 10 outputs the initial fault estimation model 100, which is a trained machine learning model.

[0135] Therefore, it is possible to accurately estimate the chip CP having an initial failure.

[0136] According to the embodiment, the chip CP does not meet the standard for a non-defective product when the inspection data is worse than the binarization threshold Th (see, for example, S1 in FIG. 2). N , P R The score calculation operation is executed multiple times by changing the value of the binarization threshold Th (see, for example, S103 to S106 in FIG. 7). In the score calculation operation, the CPU 10 identifies a group of defective chips (referred to as a first group) based on a candidate value of the binarization threshold Th (see, for example, S201 in FIG. 8), and then compares the first group with the parameter P N , P Rand candidate values ​​of initial faults (see, for example, S202 in FIG. 8). In the score calculation operation, the CPU 10 further identifies a first group of adjacent chips (referred to as the second group) and a third group of non-defective chips (referred to as the third group). In the score calculation operation, the CPU 10 further calculates a score SC based on the number of chips having initial faults included in the second group and the number of chips having initial faults CP included in the third group. Based on the results of multiple score calculation operations, the CPU 10 selects the binarization threshold Th and parameter P that will give the best score. N , P R The value of is determined (for example, see S107 in FIG. 7), and the determined value is converted into a binary value by a threshold value Th and a parameter P N , P R Then, the CPU 10 sets the binarization threshold value Th and the parameter P N , P R Using the set value, chips CP that do not meet the criteria for non-defective products are identified (see, for example, S112 in FIG. 7 and S1 to S2 in FIG. 2).

[0137] Therefore, the binarization threshold Th and the parameter P are set so that the estimation accuracy is as high as possible. N , P R The aim of the present invention is to set the respective values ​​of

[0138] Furthermore, in the embodiment, in the score calculation operation, the CPU 10 calculates a score SC based on the difference between the ratios R1 and R2 and the ratio R3 (see, for example, S204 in FIG. 8). The ratio R1 is the ratio of the number of chips having early failures included in the second group to the number of chips CP included in the second group. The ratio R2 is the ratio of the number of chips having early failures included in the third group to the number of chips CP included in the third group. The ratio R3 is the ratio of the number of chips having early failures included in the second group to the total number of chips CP having early failures.

[0139] Therefore, the binarization threshold Th and the parameter P N , PR It is possible to determine the set value of

[0140] In the embodiment, the CPU 10 executes a score calculation operation multiple times for each of a plurality of test data sets (see, for example, S102 to S110 in FIG. 7). Each of the plurality of test data sets is a test data set obtained by testing a different item. The CPU 10 selects at least one item having the best score among the plurality of items based on the best score calculated for each test data set as a second item (see, for example, S111 in FIG. 7 and FIG. 9). The CPU 10 executes identifying a defective cluster and calculating a peripheral feature set based on the test data set related to the second item (see, for example, S112 in FIG. 7, S1 to S2 in FIG. 2, and S3 to S4 in FIG. 3).

[0141] Therefore, it is possible to select, from among a plurality of test data sets, a test data set that can improve the estimation accuracy as the test data set for calculating the surrounding feature set.

[0142] Also, according to an embodiment, in a score calculation operation, if the ratio of the number of third good chips to the number of first adjacent chips does not meet threshold value Th1, the CPU 10 sets the value of the score SC to a value worse than the value calculated by equation (1) (see, for example, S205 and S207 in Figure 8).

[0143] Therefore, in cases where the yield rate is expected to be extremely low, it is possible to set the evaluation value to a low value.

[0144] Furthermore, according to the embodiment, in the score calculation operation, if the ratio of the number of chips having initial faults included in the group of first adjacent chips to the number of chips having initial faults CP does not meet the threshold value Th2, the CPU 10 sets the value of the score SC to a value worse than the value calculated by equation (1) (see, for example, S206 and S207 in FIG. 8).

[0145] Therefore, in cases where the screening performance is expected to be extremely low, it is possible to set the evaluation value to a low value.

[0146] According to the embodiment, the CPU 10 identifies a failure cluster based on the test data set (see, for example, S301 to S303 in FIG. 10 and S1 to S2 in FIG. 2). Then, the CPU 10 calculates a peripheral feature set based on the failure cluster (see, for example, S303 in FIG. 10 and S3 to S4 in FIG. 3). Then, the CPU 10 inputs the test data set and the peripheral feature set to a trained early failure estimation model 100 configured to output numerical information corresponding to the possibility that the chip CP has an early failure, thereby acquiring the numerical information (see, for example, S304 in FIG. 10). Then, the CPU 10 estimates a chip CP having an early failure based on the numerical information (see, for example, S305 in FIG. 10).

[0147] Therefore, it is possible to accurately estimate the chip CP having an initial failure.

[0148] (Modification) The CPU 10 may perform various data processing operations on the surrounding feature sets used for learning and estimation. As a modification of the embodiment, an example of processing operations that may be performed on the surrounding feature sets will be described.

[0149] First, the CPU 10 calculates a set of surrounding feature amounts by performing the processes of S1 to S4 on the inspection data set obtained in the first inspection of the second item. The CPU 10 executes data processing on the set of surrounding feature amounts.

[0150] In a modified example, the CPU 10 performs averaging on the inspection data set obtained in the first inspection of the second item, and multiplies the inspection data set after the averaging by the surrounding feature set.

[0151] FIG. 11 is a diagram for explaining the averaging operation on the test data set according to the modified example.

[0152] Part (A) of Fig. 11 shows an example of an inspection data set 200 obtained in the first inspection of the second item. Inspection data is shown in a rectangle representing each chip CP. Also, each chip CP determined to be a defective chip by the binarization threshold value Th is hatched with oblique lines.

[0153] The CPU 10 performs averaging on the inspection data set 200 (S11). The CPU 10 calculates the average value of the inspection data of all chips CP included in a predetermined range centered on one chip CP, and sets the average value as the averaged inspection data of the one chip CP.

[0154] Here, as an example, a range of 3x3 chips is used for averaging. For example, when focusing on chip CPc, the average value of the inspection data of nine chips CP included in the range AR1 of 3x3 chips centered on chip CPc is used as the inspection data after averaging of chip CPc. CPU 10 executes such processing for the inspection data of all chips CP.

[0155] The averaging process results in an averaged inspection data set 201 shown in part (B) of FIG.

[0156] 12 is a diagram showing an example of processing of a surrounding feature set according to a modified example. As shown in this figure, the CPU 10 multiplies a surrounding feature set 202 before data processing by an averaged inspection data set 201 to obtain a surrounding feature set after data processing.

[0157] In this manner, according to the modified example, the peripheral feature set after data processing is used for generating the incipient failure estimation model 100 and for estimation using the incipient failure estimation model 100.

[0158] In the modified example, data processing is performed by multiplying the averaged inspection data set 201 by the surrounding feature set 202. However, the example of data processing is not limited to this. For example, the CPU 10 may multiply the non-averaged inspection data set 200 by the surrounding feature set 202.

[0159] (Variation 2) The method of calculating the score in the score calculation operation can be modified in various ways.

[0160] For example, the CPU 10 constructs a machine learning model using a decision tree algorithm in addition to the incipient failure estimation model 100. Then, the CPU 10 can use the importance of the explanatory variables as the score SC.

[0161] In another example, the CPU 10 constructs a machine learning model in addition to the incipient fault estimation model 100. Then, the CPU 10 can use a SHAP (SHapley Additive exPlanation) value of the machine learning model as the score SC.

[0162] In yet another example, the CPU 10 may use, as the score SC, a receiver operating characteristic area under curve (ROCAUC) when predicting a defect using one set of peripheral features.

[0163] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0164] 1 Information processing device, 10 CPU, 11 Storage device, 12 RAM, 13 ROM, 14 IO device, 15 Bus, 20 Model generation program, 21 Early failure estimation program, 100 Early failure estimation model, 200, 201 Inspection data set, 202 Peripheral feature set, AR1 range, CP, CPc chip, CPa, CPb defective chip, Ca, Cb circle.

Claims

1. Obtaining a first data set which is a set of inspection results for each chip obtained by a first inspection on a plurality of chips formed on a wafer or cut from the wafer, and a second data set which indicates the presence or absence of an initial failure for each chip obtained by a second inspection on the plurality of chips; identifying clusters of chips that do not meet a first criterion based on the first data set; Computing a third data set, the third data set being a set of features for each chip related to distance to the cluster; Executing learning on a machine learning model using the first data set and the third data set as input data and the second data set as correct answer data; Outputting the trained machine learning model; and a processor executing An information processing device comprising:

2. Failure to meet the first criterion is a test result value worse than a first threshold value; The processor, identifying a first group which is a group of chips having test results worse than a second threshold value, identifying a cluster of chips having test result values ​​worse than the second threshold value based on the first group and a parameter value for clustering, identifying a second group which is a group of chips adjacent to the cluster among the plurality of chips, and a third group which is a group of chips among the plurality of chips having test result values ​​better than the second threshold value and not included in the second group, and performing a score calculation operation multiple times while varying the second threshold value and the parameter value to calculate a score based on the number of chips having initial failures included in the second group and the number of chips having initial failures included in the third group; identifying the second threshold value and the parameter value that yields the best score based on the results of the multiple score calculation operations; and setting the identified second threshold value as the first threshold value; identifying clusters of chips that do not meet the first criterion using the identified parameter values; and further configured to perform The information processing device according to claim 1 .

3. The processor, in the score calculation operation, a difference between a first ratio, which is a ratio of the number of chips having early failures in the second group to the number of chips in the second group, and a second ratio, which is a ratio of the number of chips having early failures in the third group to the number of chips in the third group; a ratio of the number of chips having early failures in the second group to the total number of chips having early failures; and Calculate a score based on It was configured as follows: The information processing device according to claim 2 .

4. The first test includes a test of multiple items, the first data set includes a plurality of fourth data sets, each of which is obtained by testing a different item among the plurality of items; each of the plurality of fourth data sets is a set of test results for each chip obtained by testing one of the plurality of items; The processor, performing said plurality of score calculation operations for each fourth data set to calculate a best score for each fourth data set; selecting at least one item from among said plurality of items, the best score calculated for each fourth data set being best among said plurality of fourth data sets; identifying clusters of chips that do not meet the first criterion based on a fourth data set of the at least one selected item and calculating the third data set; and further configured to perform The information processing device according to claim 2 .

5. and if, in the score calculation operation, a ratio of the number of chips included in the third group to the number of chips included in the second group is less than a third threshold, the processor sets the value of the score to a value worse than a calculated value. It was configured as follows: The information processing device according to claim 3 .

6. setting the score to a value worse than the calculated value if a ratio of the number of chips having early failures in the second group to the number of chips having early failures among the plurality of chips is less than a fourth threshold. It was configured as follows: The information processing device according to claim 3 .

7. Identifying a cluster of chips that does not satisfy a first criterion based on a first data set, which is a set of inspection results for each chip obtained by a first inspection on a plurality of chips formed on or cut from the wafer; Computing a second data set, the second data set being a set of features for each chip related to distance to the cluster; obtaining numerical information by inputting the first data set and the second data set into a trained machine learning model configured to output numerical information corresponding to a likelihood that a chip has an early failure; estimating chips having early failures based on the numerical information; and a processor configured to execute An information processing device comprising:

8. Obtaining a first data set which is a set of inspection results for each chip obtained by a first inspection on a plurality of chips formed on a wafer or cut from the wafer, and a second data set which indicates the presence or absence of an initial failure for each chip obtained by a second inspection on the plurality of chips; identifying clusters of chips that do not meet a first criterion based on the first data set; Computing a third data set, the third data set being a set of features for each chip related to distance to the cluster; generating a machine learning model by training using the first data set and the third data set as input data and the second data set as ground truth data; The method includes:

9. Identifying a cluster of chips that does not satisfy a first criterion based on a first data set, which is a set of inspection results for each chip obtained by a first inspection on a plurality of chips formed on or cut from the wafer; Computing a second data set, the second data set being a set of features for each chip related to distance to the cluster; obtaining numerical information by inputting the first data set and the second data set into a trained machine learning model configured to output numerical information corresponding to a likelihood that a chip has an early failure; estimating chips having early failures based on the numerical information; and The method includes:

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