Semiconductor storage device

Abstract

To provide a semiconductor storage device that operates suitably.SOLUTION: A semiconductor storage device includes a substrate, a first via wire extending in a first direction intersecting with a surface of the substrate, a plurality of first semiconductor layers arranged in the first direction and electrically connected to the first via wire, a memory part arranged in the first direction and electrically connected to the first semiconductor layers, a plurality of first gate electrodes arranged in the first direction and facing the first semiconductor layers, a plurality of first wires arranged in the first direction, extending in a second direction intersecting with the first direction, and electrically connected to the first gate electrodes, a plurality of second semiconductor layers arranged in the first direction and electrically connected to the first wires, a plurality of second gate electrodes arranged in the first direction and facing the second semiconductor layers, a second via wire extending in the first direction and electrically connected to the second gate electrodes, and a plurality of second wires arranged in the first direction, extending in a third direction that intersects with the first direction and the second direction, and electrically connected to the second semiconductor layers.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present embodiment relates to a semiconductor memory device. [Background technology]

[0002] 2. Description of the Related Art With the increasing integration density of semiconductor memory devices, studies on three-dimensional semiconductor memory devices are underway. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2022 / 0399340 [Patent Document 2] US Patent Application Publication No. 2022 / 0352169 [Patent Document 3] JP 2022-147872 A Summary of the Invention [Problem to be solved by the invention]

[0004] A semiconductor memory device that operates favorably is provided. [Means for solving the problem]

[0005] A semiconductor memory device according to one embodiment includes a substrate, a first via wiring extending in a first direction intersecting a surface of the substrate, a plurality of first semiconductor layers arranged in the first direction and electrically connected to the first via wiring, a memory section arranged in the first direction and electrically connected to the plurality of first semiconductor layers, a plurality of first gate electrodes arranged in the first direction and facing the plurality of first semiconductor layers, a plurality of first wirings arranged in the first direction and extending in a second direction intersecting the first direction and electrically connected to the plurality of first gate electrodes, a plurality of second semiconductor layers arranged in the first direction and electrically connected to the plurality of first wirings, a plurality of second gate electrodes arranged in the first direction and facing the plurality of second semiconductor layers, a second via wiring extending in the first direction and electrically connected to the plurality of second gate electrodes, and a plurality of second wirings arranged in the first direction and extending in a third direction intersecting the first and second directions and electrically connected to the plurality of second semiconductor layers. [Brief description of the drawings]

[0006] [Figure 1] 1 is a schematic circuit diagram showing a configuration of a portion of a semiconductor memory device according to a first embodiment. [Diagram 2] 11 is a schematic circuit diagram for illustrating a read operation of the semiconductor memory device. FIG. [Diagram 3] FIG. 2 is a schematic perspective view showing a configuration of a portion of the semiconductor memory device. [Figure 4] FIG. 2 is a schematic perspective view showing a configuration of a portion of the semiconductor memory device. [Diagram 5] 2 is a schematic XY cross-sectional view showing a configuration of a portion of the semiconductor memory device. FIG. [Figure 6] 2 is a schematic XY cross-sectional view showing a configuration of a portion of the semiconductor memory device. FIG. [Figure 7] FIG. 2 is a schematic cross-sectional view showing a configuration of a portion of the semiconductor memory device. [Figure 8] 2 is a schematic XY cross-sectional view showing a configuration of a portion of the semiconductor memory device. FIG. [Figure 9] FIG. 2 is a schematic cross-sectional view showing a configuration of a portion of the semiconductor memory device. [Figure 10]2 is a schematic XY cross-sectional view showing a configuration of a portion of the semiconductor memory device. FIG. [Figure 11] FIG. 2 is a schematic cross-sectional view showing a configuration of a portion of the semiconductor memory device. [Figure 12] 5A to 5C are schematic cross-sectional views for explaining a manufacturing method of the semiconductor memory device. [Figure 13] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 14] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 15] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 16] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 17] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 18] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 19] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 20] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 21] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 22] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 23] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 24] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Diagram 25] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 26] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 27] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 28] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 29] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Diagram 30] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Diagram 31] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Diagram 32] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Diagram 33] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Diagram 34] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Diagram 35] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Diagram 36] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 37] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 38] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 39] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Diagram 40] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Diagram 41] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Diagram 42] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Diagram 43] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Diagram 44] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Diagram 45] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Diagram 46] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 47]5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 48] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 49] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 50] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 51] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 52] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 53] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 54] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 55] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 56] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 57] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 58] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 59] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 60] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 61] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 62] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 63] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 64] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 65] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 66] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 67] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 68] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 69] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 70] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 71] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 72] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 73] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 74] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 75] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 76] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 77] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 78] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 79] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 80] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 81] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 82] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 83] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 84] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 85] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 86] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 87] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 88] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 89] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 90] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 91] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 92] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 93] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 94] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 95] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 96] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 97] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 98] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 99] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 100] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 101] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 102] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 103]5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 104] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 105] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Fig. 106] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 107] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 108] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Fig. 109] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 110] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 111] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 112] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 113] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Fig. 114] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 115] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Fig. 116] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 117] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Fig. 118] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 119] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 120] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 121] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 122] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 123] 1 is a schematic circuit diagram showing a configuration of a portion of a semiconductor memory device according to a comparative example. [Figure 124] 11 is a schematic circuit diagram for explaining a read operation of a semiconductor memory device according to a comparative example. FIG. [Fig. 125] 10 is a schematic XY cross-sectional view showing a configuration of a portion of a semiconductor memory device according to a second embodiment. FIG. [Fig. 126] 2 is a schematic XY cross-sectional view showing a configuration of a portion of the semiconductor memory device. FIG. [Figure 127] FIG. 2 is a schematic cross-sectional view showing a configuration of a portion of the semiconductor memory device. [Figure 128] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 129] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Fig. 130] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Fig. 131] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Fig. 132] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Fig. 133] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Fig. 134] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Fig. 135] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Fig. 136] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Fig. 137] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 138] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 139] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Fig. 140]5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Fig. 141] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Fig. 142] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Fig. 143] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Fig. 144] FIG. 11 is a schematic circuit diagram showing a configuration of a portion of a semiconductor memory device according to a third embodiment. [Fig. 145] 2 is a schematic XY cross-sectional view showing a configuration of a portion of the semiconductor memory device. FIG. [Fig. 146] FIG. 2 is a schematic cross-sectional view showing a configuration of a portion of the semiconductor memory device. [Fig. 147] FIG. 13 is a schematic circuit diagram showing a configuration of a portion of a semiconductor memory device according to a fourth embodiment. [Fig. 148] 2 is a schematic XY cross-sectional view showing a configuration of a portion of the semiconductor memory device. FIG. [Figure 149] FIG. 2 is a schematic cross-sectional view showing a configuration of a portion of the semiconductor memory device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Next, a semiconductor memory device according to an embodiment will be described in detail with reference to the drawings. Note that the following embodiment is merely an example, and is not intended to limit the present invention. Also, the following drawings are schematic, and for the sake of explanation, some configurations may be omitted. Also, parts common to multiple embodiments may be given the same reference numerals, and explanations may be omitted.

[0008] In addition, in this specification, the term "semiconductor memory device" may refer to a memory die, or may refer to a memory system including a controller die, such as a memory chip, a memory card, or an SSD (Solid State Drive). Furthermore, it may refer to a configuration including a host computer, such as a smartphone, a tablet terminal, or a personal computer.

[0009] In addition, in this specification, when it is said that a first configuration is "electrically connected" to a second configuration, the first configuration may be directly connected to the second configuration, or the first configuration may be connected to the second configuration via wiring, a semiconductor member, a transistor, etc. For example, when three transistors are connected in series, the first transistor is "electrically connected" to the third transistor even if the second transistor is in an OFF state.

[0010] Furthermore, in this specification, when it is said that a first configuration is "electrically connected between" a second configuration and a third configuration, it may mean that the first configuration, the second configuration, and the third configuration are connected in series, and that the second configuration is electrically connected to the third configuration via the first configuration.

[0011] In addition, in this specification, when it is said that a circuit or the like "conducts" two wirings or the like, it may mean, for example, that the circuit or the like includes a transistor or the like, that the transistor or the like is provided in a current path between the two wirings, and that the transistor or the like is in an ON state.

[0012] In this specification, a predetermined direction parallel to the upper surface of the substrate is called the X direction, a direction parallel to the upper surface of the substrate and perpendicular to the X direction is called the Y direction, and a direction perpendicular to the upper surface of the substrate is called the Z direction.

[0013] In this specification, a direction along a predetermined plane may be referred to as a first direction, a direction along this predetermined plane that intersects with the first direction may be referred to as a second direction, and a direction that intersects with this predetermined plane may be referred to as a third direction. These first, second, and third directions may or may not correspond to any of the X, Y, and Z directions.

[0014] In this specification, expressions such as "upper" and "lower" are based on the substrate. For example, the direction away from the substrate along the Z direction is called "up," and the direction toward the substrate along the Z direction is called "down." Furthermore, when referring to a certain configuration, the lower surface or lower end refers to the surface or end of the configuration facing the substrate, and when referring to the upper surface or upper end, refers to the surface or end of the configuration facing away from the substrate. Furthermore, surfaces that intersect with the X or Y direction are called side surfaces, etc.

[0015] Furthermore, in this specification, when we say the "center position" of a certain feature, it may mean, for example, the position of the center of the circumscribing circle of this feature, or it may mean the center of gravity of an image of this feature on a specified plane.

[0016] [First embodiment] [Circuit configuration] Fig. 1 is a schematic circuit diagram showing a configuration of a portion of a semiconductor memory device according to the first embodiment. As shown in Fig. 1, the semiconductor memory device according to this embodiment includes a memory cell array MCA. The memory cell array MCA includes a plurality of memory layers ML0 to ML3 (hereinafter, sometimes referred to as "memory layers ML"), a plurality of bit lines BL connected to the plurality of memory layers ML0 to ML3, a plurality of global bit lines GBL electrically connected to the plurality of bit lines BL, and a plate line PL connected to the plurality of memory layers ML0 to ML3.

[0017] Each of the memory layers ML0 to ML3 includes a plurality of word lines WL0 to WL2 (hereinafter sometimes referred to as "word lines WL") and a plurality of memory cells MC connected to the plurality of word lines WL0 to WL2. Each of the memory cells MC includes a transistor TrC and a capacitor CpC. One electrode of the transistor TrC is connected to a bit line BL. The other electrode of the transistor TrC is connected to the capacitor CpC. The one and the other electrodes of the transistor TrC function as a source electrode or a drain electrode depending on the voltage supplied to the transistor TrC. The gate electrode of the transistor TrC is connected to one of the word lines WL0 to WL2. One electrode of the capacitor CpC is connected to the other electrode of the transistor TrC. The other electrode of the capacitor CpC is connected to a plate line PL.

[0018] Each bit line BL is connected to a plurality of memory cells MC corresponding to the plurality of memory layers ML0 to ML3, and each bit line BL is connected to a global bit line GBL.

[0019] Moreover, the memory layers ML0 to ML3 each include a plurality of transistors TrR0a, TrR0b, TrR1a, TrR1b, TrR2a, TrR2b, TrR3a, and TrR3b (hereinafter, sometimes referred to as "transistors TrR") provided corresponding to a plurality of word lines WL0 to WL2. One electrode of the transistor TrR is connected to one of the word lines WL0 to WL2. The other electrode of the transistor TrR is connected to a layer selection line LL0a, LL0b, LL1a, LL1b, LL2a, LL2b, LL3a, and LL3b (hereinafter, sometimes referred to as "layer selection line LL"). The one and other electrodes of the transistor TrR function as a source electrode or a drain electrode depending on the voltage supplied to the transistor TrR. The gate electrodes of the transistors TrR are connected to word line selection lines LW0a, LW0b, LW1a, LW1b, LW2a, and LW2b (hereinafter, sometimes referred to as "word line selection lines LW").

[0020] The word line selection line LW is connected to a plurality of transistors TrR corresponding to a plurality of memory layers ML0 to ML3. The layer selection lines LL0a, LL1a, LL2a, and LL3a are connected in common to all of the transistors TrR0a, TrR1a, TrR2a, and TrR3a corresponding to the memory layers ML0 to ML3, respectively. Similarly, the layer selection lines LL0b, LL1b, LL2b, and LL3b are connected in common to all of the transistors TrR0b, TrR1b, TrR2b, and TrR3b corresponding to the memory layers ML0 to ML3, respectively.

[0021] [Read operation] FIG. 2 is a schematic circuit diagram for explaining the read operation of the semiconductor memory device according to the first embodiment.

[0022] In a read operation, one of the multiple memory layers ML0 to ML3 is selected. In the illustrated example, the memory layer ML0 is selected. When selecting the memory layers ML0 to ML3, for example, a voltage V ON and supplies the voltage V OFF In addition, for example, a voltage V OFF supplies.

[0023] Voltage V ON For example, the voltage V OFF For example, when the transistor TrC is an NMOS transistor, the voltage V ON is the voltage V OFF For example, if the transistor TrC is a PMOS transistor, the voltage V ON is the voltage V OFF Less than.

[0024] In addition, in a read operation, one of the multiple word lines WL0 to WL2 is selected. In the illustrated example, the word line WL0 is selected. When selecting the word line WL0 to WL2, for example, a voltage V ON ´ and supply voltage V OFF Further, a voltage V is supplied to the word line selection line LW0a corresponding to the word line WL0 that is the target of the read operation among the plurality of word line selection lines LW0b, LW1b, and LW2b. OFF ´ and supply voltage V ON ´ to supply.

[0025] Voltage V ON The voltage V′ has a magnitude sufficient to turn on the transistor TrR. OFF For example, when the transistor TrR is an NMOS transistor, the voltage V ON ´ is the voltage V OFF For example, if the transistor TrR is a PMOS transistor, the voltage V ON ´ is the voltage V OFF ´ is smaller than.

[0026] Here, a voltage V ON is supplied. As a result, the transistor TrC in the selected memory cell MC is turned on. As a result, the voltage of the global bit line GBL fluctuates or a current flows through the global bit line GBL. By detecting this voltage fluctuation or current, it is possible to read the data stored in the selected memory cell MC.

[0027] In addition, the unselected word line WL0 corresponding to the memory layers ML1, ML2, and ML3 different from the selected memory cell MC is supplied with a voltage V OFF As a result, the transistor TrC in the memory cell MC is turned off.

[0028] In addition, the unselected word lines WL1 and WL2 corresponding to the memory layers ML0, ML1, ML2, and ML3 are supplied with a voltage V OFF As a result, the transistor TrC in the memory cell MC is turned off.

[0029] In the following description, an example in which both the transistors TrC and TrR are NMOS transistors will be shown.

[0030] [structure] FIG. 3 is a schematic perspective view showing a configuration of a part of the semiconductor memory device according to the first embodiment. FIG. 4 is a schematic perspective view showing a configuration of a part of the semiconductor memory device, and shows an enlarged part of FIG. 3. FIG. 5 is a schematic XY cross-sectional view showing a configuration of a part of the semiconductor memory device. FIGS. 6, 8, and 10 are schematic XY cross-sectional views showing a configuration of a part of the semiconductor memory device, and each shows an enlarged part of FIG. 5. FIG. 7 is a schematic cross-sectional view showing a configuration of a part of the semiconductor memory device, and shows a configuration in which the structure shown in FIG. 6 is cut along line AA' and viewed along the direction of the arrow. FIG. 9 is a schematic cross-sectional view showing a configuration of a part of the semiconductor memory device, and shows a configuration in which the structure shown in FIG. 8 is cut along line BB' and viewed along the direction of the arrow. FIG. 11 is a schematic cross-sectional view showing a configuration of a part of the semiconductor memory device, and shows a configuration in which the structure shown in FIG. 10 is cut along line CC' and viewed along the direction of the arrow.

[0031] FIG. 3 shows a part of a semiconductor substrate Sub and a memory cell array MCA provided above the semiconductor substrate Sub.

[0032] The semiconductor substrate Sub is a semiconductor substrate such as silicon (Si) containing a P-type impurity such as boron (B). An insulating layer and an electrode layer (not shown) are provided on the upper surface of the semiconductor substrate Sub. The upper surface of the semiconductor substrate Sub and the insulating layer and electrode layer (not shown) constitute a peripheral circuit for controlling the semiconductor memory device according to the first embodiment. For example, a sense amplifier circuit is provided in a region directly below the memory cell array MCA. The sense amplifier circuit is electrically connected to the global bit line GBL. In a read operation, the sense amplifier circuit can read data stored in the selected memory cell MC by detecting a voltage fluctuation or a current of the bit line BL. The peripheral circuit also includes a sequencer that supplies a predetermined voltage at a predetermined timing to each wiring in the memory cell array MCA and each component in the sense amplifier circuit, thereby performing a read operation or the like.

[0033] The memory cell array MCA includes a plurality of memory layers ML arranged in the Z direction. In addition, insulating layers 103 such as silicon oxide (SiO2) are provided between the plurality of memory layers ML.

[0034] As shown in FIG. 5, the memory cell array MCA includes a memory cell region R MC and memory cell region R MC A transistor region R TrR and the transistor area R TrR The wiring area R is provided on one side of the Y direction. LL The memory cell array MCA is provided with a memory cell region R MC and the transistor area R TrR A connection wiring region R CL1 and the transistor area R TrR and the wiring area R LL A connection wiring region R CL2 Although not shown, the transistor region R TrR , wiring area R LL , the connection wiring area R CL1 and the connection wiring area R CL2is a memory cell region R in the Y direction. MC are provided on both sides of the

[0035] [Memory cell area R MC Structure of As shown in FIG. 5, the memory cell region R MC has a plurality of insulating layers 101 aligned in the X direction, and a conductive layer 102 provided between two insulating layers 101 adjacent to each other in the X direction. The insulating layers 101 and the conductive layers 102 extend in the Y direction and the Z direction, and divide the plurality of memory layers ML in the X direction.

[0036] The insulating layer 101 includes, for example, silicon oxide (SiO2).

[0037] The conductive layer 102 includes, for example, a stacked structure of titanium nitride (TiN) and silicon germanium (SiGe), etc. The conductive layer 102 functions as, for example, a plate line PL (FIG. 1).

[0038] In addition, the memory cell region R MC In the region between the insulating layer 101 and the conductive layer 102, a plurality of via wirings 104 are provided aligned in the Y direction. As shown in FIG. 3, each of the plurality of via wirings 104 extends in the Z direction, penetrating a plurality of memory layers ML.

[0039] 4, the via wiring 104 includes, for example, a conductive oxide film 104a including a conductive oxide, a barrier conductive film 104b such as titanium nitride (TiN), and a conductive member 104c such as tungsten (W). The via wiring 104 may include ruthenium (Ru), iridium (Ir), or other metals instead of the conductive oxide film 104a. The via wiring 104 may also include only a conductive oxide, or may include only ruthenium (Ru), iridium (Ir), or other metals.

[0040] As used herein, "conductive oxide" includes, for example, indium tin oxide (ITO), indium zinc oxide (IZO), ruthenium oxide (RuO2), iridium oxide (IrO2), or other conductive materials that contain oxygen.

[0041] The conductive member 104c has a substantially cylindrical shape extending in the Z direction. The barrier conductive film 104b has a substantially cylindrical shape extending in the Z direction along the outer circumferential surface of the conductive member 104c. The conductive oxide film 104a has a substantially cylindrical shape extending in the Z direction along the outer circumferential surface of the barrier conductive film 104b. The via wiring 104 functions as, for example, a bit line BL (FIG. 1).

[0042] As shown in FIG. 5, the memory layer ML includes a conductive layer 120 extending in the Y direction and provided between the insulating layer 101 and the multiple via wirings 104, a multiple number of transistor structures 110 arranged in the Y direction corresponding to the multiple via wirings 104, and a multiple number of capacitor structures 130 arranged between the conductive layer 102 and the multiple transistor structures 110 and arranged in the Y direction corresponding to the multiple via wirings 104.

[0043] As shown in FIG. 4, for example, the transistor structure 110 includes a semiconductor layer 111 connected to the outer peripheral surface of the via wiring 104 and extending in the X direction, an insulating layer 112 provided on an upper surface, a lower surface, both side surfaces in the Y direction, and one side surface in the X direction (the conductive layer 120 side) of the semiconductor layer 111, and a conductive layer 113 provided on an upper surface, a lower surface, both side surfaces in the Y direction, and one side surface in the X direction (the conductive layer 120 side) of the insulating layer 112.

[0044] 6, both side surfaces in the X direction of the semiconductor layer 111 may be formed along a circle centered on the central position of the via wiring 104. Similarly, the side surfaces on one side (conductive layer 120 side) of the insulating layer 112 and the conductive layer 113 in the X direction may be formed along a circle centered on the central position of the via wiring 104. Both side surfaces in the Y direction of the semiconductor layer 111, the insulating layer 112, and the conductive layer 113 may be formed linearly along the side surfaces of the insulating layer 115.

[0045] Note that both side surfaces of the semiconductor layer 111 in the X direction do not have to be formed along a circle. Even in such a case, for example, both side surfaces of the semiconductor layer 111 in the X direction may be curved when viewed from the Z direction. For example, the length of the semiconductor layer 111 in the X direction may differ depending on the position in the Y direction. For example, the length of the semiconductor layer 111 in the X direction at a position close to the insulating layer 115 may be shorter than the length of the semiconductor layer 111 in the X direction at a position far from the insulating layer 115.

[0046] The semiconductor layer 111 functions as, for example, a channel region of the transistor TrC (FIG. 1). The semiconductor layer 111 may be, for example, a semiconductor containing at least one element of gallium (Ga) and aluminum (Al), indium (In), zinc (Zn), and oxygen (O), or may be another oxide semiconductor. The multiple semiconductor layers 111 aligned in the Z direction are commonly connected to a via wiring 104 extending in the Z direction.

[0047] The insulating layer 112 functions as, for example, a gate insulating film of the transistor TrC (FIG. 1). The insulating layer 112 includes, for example, silicon oxide (SiO2).

[0048] The conductive layer 113 functions as, for example, a gate electrode of the transistor TrC (FIG. 1). The conductive layer 113 includes, for example, a conductive oxide such as titanium nitride (TiN) or indium tin oxide (ITO). As shown in FIG. 5, the multiple conductive layers 113 aligned in the Y direction are commonly connected to a conductive layer 120 extending in the Y direction. As shown in FIG. 6 and FIG. 7, the conductive layer 113 faces the upper surface, the lower surface, both side surfaces in the Y direction, and one side surface in the X direction (the conductive layer 120 side) of the semiconductor layer 111 via the insulating layer 112.

[0049] 5, an insulating layer 115 such as silicon oxide (SiO2) is provided between two semiconductor layers 111 adjacent to each other in the Y direction. The insulating layer 115 extends in the Z direction, penetrating the multiple memory layers ML.

[0050] The conductive layer 120 functions as, for example, a word line WL (FIG. 1). As described above, the conductive layer 120 extends in the Y direction. One side surface of the conductive layer 120 in the X direction is connected to a plurality of conductive layers 113 arranged in the Y direction. As shown in FIGS. 6 and 7, the conductive layer 120 includes, for example, a barrier conductive film 121 made of titanium nitride (TiN) or the like, and a conductive film 122 made of tungsten (W).

[0051] 6 and 7, the capacitor structure 130 includes a conductive layer 131, an insulating layer 132 provided on an upper surface, a lower surface, both side surfaces in the Y direction, and one side surface in the X direction (the transistor structure 110 side) of the conductive layer 131, a conductive layer 133 provided on an upper surface, a lower surface, both side surfaces in the Y direction, and one side surface in the X direction (the transistor structure 110 side) of the insulating layer 132, and an insulating layer 134 provided on an upper surface, a lower surface, and both side surfaces in the Y direction of the conductive layer 133.

[0052] The conductive layer 131 functions as one electrode of the capacitor CpC (FIG. 1). The conductive layer 131 includes, for example, a laminated structure of titanium nitride (TiN) and silicon germanium (SiGe). The conductive layer 131 is connected to the conductive layer 102.

[0053] The insulating layer 132 functions as an insulating layer for the capacitor CpC (FIG. 1). The insulating layer 132 may be, for example, zirconia (ZrO2), alumina (Al2O3), or other insulating metal oxide. The insulating layer 132 may also be, for example, a laminated film of multiple insulating metal oxides (for example, a laminated film of zirconia and alumina).

[0054] The conductive layer 133 functions as, for example, the other electrode of the capacitor CpC (FIG. 1). The conductive layer 133 includes, for example, a conductive oxide such as indium tin oxide (ITO). The conductive layer 133 is insulated from the conductive layer 131 via the insulating layer 132. The conductive layer 133 is connected to a side surface of the semiconductor layer 111 on one side in the X direction (the conductive layer 102 side).

[0055] The insulating layer 134 includes, for example, silicon oxide (SiO2), etc. In the illustrated example, the insulating layer 134 is continuous with the insulating layer 112.

[0056] [Transistor area R TrR Structure of As shown in Figure 5, the transistor region R TrR are provided with a plurality of insulating layers 201 aligned in the X direction corresponding to the plurality of insulating layers 101, and an insulating layer 202 provided between two insulating layers 201 adjacent to each other in the X direction. The insulating layers 201 and 202 extend in the Y direction and the Z direction, and divide the plurality of memory layers ML in the X direction. The insulating layers 201 and 202 include, for example, silicon oxide (SiO2) or the like.

[0057] In addition, the transistor region R TrR A plurality of via wirings 204 are provided in the region between the insulating layer 201 and the insulating layer 202. The plurality of via wirings 204 are aligned in the Y direction and extend in the Z direction, penetrating the plurality of memory layers ML, as shown in FIG.

[0058] The via wiring 204 includes, for example, a laminated structure of titanium nitride (TiN) and tungsten (W), etc. The via wiring 204 has a substantially cylindrical shape extending in the Z direction.

[0059] The via wirings 204 arranged in the Y direction function as, for example, one word line selection line LW (FIG. 1). As shown in FIG. 1, the word line selection line LW is provided in a plurality of lines corresponding to the word lines WL included in the memory layer ML.

[0060] The memory layer ML includes a portion of a plurality of transistor structures 210 corresponding to the plurality of conductive layers 120, a conductive layer 221 provided between the transistor structure 210 and the insulating layer 201, and a conductive layer 222 provided between the transistor structure 210 and the insulating layer 202.

[0061] As shown in Fig. 11, the transistor structure 210 includes a portion provided in the memory layer ML and a portion provided at a height position corresponding to the insulating layer 103. Of these, the portion provided in the memory layer ML includes a plurality of insulating layers 211 provided on the outer peripheral surfaces of a plurality of via wirings 204, a conductive layer 212 provided on the outer peripheral surfaces of the plurality of insulating layers 211 and extending in the Y direction, and a semiconductor layer 213 extending in the Y direction along a side surface on one side (the insulating layer 202 side) in the X direction of the conductive layer 212, as shown in Fig. 10. In addition, the portion provided at a height position corresponding to the insulating layer 103 includes an insulating layer 214 provided on the upper and lower surfaces of the conductive layer 212 and the semiconductor layer 213, and a conductive layer 215 provided on the upper and lower surfaces of the insulating layer 214, as shown in Fig. 11.

[0062] 10, both side surfaces in the X direction of the conductive layer 212 may be formed along multiple circles that overlap with each other and are centered on multiple central positions of the multiple via wirings 204. In addition, both side surfaces in the X direction of the semiconductor layer 213 may also be formed along multiple circles that overlap with each other and are centered on multiple central positions of the multiple via wirings 204.

[0063] The insulating layer 211 includes, for example, silicon oxide (SiO2) etc. The insulating layer 211 has a substantially cylindrical shape extending in the Z direction along a part of the outer circumferential surface of the via wiring 204. The insulating layer 211 is continuous with the insulating layer 214 (FIG. 11).

[0064] The conductive layer 212 includes, for example, a conductive oxide. Note that the conductive layer 212 may include ruthenium (Ru), iridium (Ir), or other metals instead of a conductive oxide. The conductive layer 212 may include only a conductive oxide, or may include only ruthenium (Ru), iridium (Ir), or other metals.

[0065] The semiconductor layer 213 functions as, for example, a channel region of the transistor TrR (FIG. 1). The semiconductor layer 213 may be, for example, a semiconductor containing at least one element of gallium (Ga) and aluminum (Al), indium (In), zinc (Zn), and oxygen (O), or may be another oxide semiconductor.

[0066] The insulating layer 214 functions as, for example, a gate insulating film of the transistor TrR (FIG. 1). The insulating layer 214 includes, for example, silicon oxide (SiO2).

[0067] The conductive layer 215 functions as, for example, a gate electrode of the transistor TrR (FIG. 1). The conductive layer 215 includes, for example, a laminated structure of titanium nitride (TiN) and tungsten (W). One side (insulating layer 201 side) of the conductive layer 215 in the X direction is connected to a plurality of via wirings 204 arranged in the Y direction. When focusing on two semiconductor layers 213 adjacent to each other in the Z direction, one conductive layer 215 provided between them faces the lower surface of the semiconductor layer 213 provided above and the upper surface of the semiconductor layer 213 provided below, via the insulating layer 214. The plurality of conductive layers 215 arranged in the Z direction are commonly connected to the via wirings 204 extending in the Z direction.

[0068] Note that when focusing on two conductive layers 215 adjacent to each other in the Z direction, these conductive layers 215 are connected only through the via wiring 204. That is, both ends of these two conductive layers 215 in the Y direction are spaced apart in the Z direction. Similarly, the ends of these two conductive layers 215 opposite the via wiring 204 are also spaced apart in the Z direction.

[0069] The conductive layer 221 is connected to one side surface (insulating layer 201 side) of the conductive layer 212 in the X direction. As shown in FIG. 5, the conductive layer 221 is TrR From the connection wiring area R CL2The conductive layer 221 extends in the Y direction from the first electrode 101 to the second electrode 102 and has a function of electrically connecting the other electrode of the transistor TrR (FIG. 1) to the layer selection line LL (FIG. 1). The conductive layer 221 includes, for example, a conductive oxide. The conductive layer 221 may include ruthenium (Ru), iridium (Ir) or other metals instead of a conductive oxide. The conductive layer 221 may include only a conductive oxide, or may include only ruthenium (Ru), iridium (Ir) or other metals.

[0070] 11, the conductive layer 221 may include a portion formed on the lower surface of the insulating layer 103, a portion formed on the upper surface of the insulating layer 103, and a portion formed on one side of the conductive layer 212 in the X direction (the insulating layer 201 side), as shown in FIG. 11. In addition, insulating layers 223 and 224 such as silicon oxide (SiO2) may be provided in the region surrounded by the conductive layer 221.

[0071] The conductive layer 222 is connected to the semiconductor layer 213. As shown in FIG. TrR From the connection wiring area R CL1 The conductive layer 222 extends in the Y direction from the first electrode of the transistor TrR (FIG. 1) to the word line WL (FIG. 1) and has a function of electrically connecting the one electrode of the transistor TrR (FIG. 1) to the word line WL (FIG. 1). The conductive layer 222 includes, for example, a conductive oxide. The conductive layer 222 may include ruthenium (Ru), iridium (Ir) or other metals instead of a conductive oxide. The conductive layer 222 may include only a conductive oxide, or may include only ruthenium (Ru), iridium (Ir) or other metals.

[0072] 11, the conductive layer 222 may include a portion formed on the lower surface of the insulating layers 103 and 214, a portion formed on the upper surface of the insulating layers 103 and 214, and a portion formed on the other side (insulating layer 202 side) in the X direction of the semiconductor layer 213. In addition, insulating layers 223 and 224 such as silicon oxide (SiO2) may be provided in the region surrounded by the conductive layer 222.

[0073] [Connection wiring area R CL1 Structure of As shown in Figure 5, the connection wiring area R CL1 Insulating layers 301 and 302 arranged side by side in the Y direction are provided in the memory cell region R. The insulating layer 301 is connected to an end of the insulating layer 101 in the Y direction. The insulating layer 302 is connected to an end of the insulating layer 301 in the Y direction. MC The insulating layer 302 is connected to an end of the insulating layer 202 in the Y direction. The insulating layers 301 and 302 extend in the X direction and the Z direction, and divide the multiple memory layers ML in the Y direction. The insulating layers 301 and 302 include, for example, silicon oxide (SiO2) or the like.

[0074] In addition, the connection wiring area R CL1 An insulating layer 304 made of silicon oxide (SiO2) or the like is provided in the region between the insulating layer 301 and the insulating layer 302. The insulating layer 304 extends in the Z direction, penetrating the multiple memory layers ML, as shown in FIG.

[0075] The memory layer ML includes a plurality of connection wiring parts 310 provided corresponding to the plurality of conductive layers 120.

[0076] As shown in FIG. 8, the connection wiring portion 310 includes a semiconductor layer 311 such as silicon (Si) provided on the outer peripheral surface of the insulating layer 304, and a conductive layer 312 provided on the upper, lower and outer peripheral surfaces of the semiconductor layer 311.

[0077] 8, both side surfaces in the X direction of the semiconductor layer 311 and the conductive layer 312 may be formed along a circle centered on the central position of the insulating layer 304. In addition, both side surfaces in the Y direction of the semiconductor layer 311 and the conductive layer 312 may be formed linearly along the side surfaces in the Y direction of the insulating layers 301, 302.

[0078] One side surface of the conductive layer 312 in the X direction is connected to the conductive layer 120. The other side surface of the conductive layer 312 in the X direction is connected to the conductive layer 222. The conductive layer 312 has a function of electrically connecting the one electrode of the transistor TrR (FIG. 1) and the word line WL (FIG. 1).

[0079] [Connection wiring area R CL2 Structure of As shown in Figure 5, the connection wiring area R CL2 Insulating layers 401 and 402 arranged in the Y direction are provided in the memory cell region R. MC The insulating layer 402 is connected to an end of the insulating layer 202 in the Y direction. The insulating layers 401 and 402 extend in the X direction and the Z direction, and divide the multiple memory layers ML in the Y direction. The insulating layers 401 and 402 include, for example, silicon oxide (SiO2) or the like.

[0080] In addition, the connection wiring area R CL2 An insulating layer 404 made of silicon oxide (SiO2) or the like is provided in the region between the insulating layer 401 and the insulating layer 402. The insulating layer 404 extends in the Z direction, penetrating the multiple memory layers ML.

[0081] The memory layer ML includes a plurality of connection wiring parts 410 provided corresponding to the plurality of conductive layers 120.

[0082] The connection wiring section 410 includes a semiconductor layer 411 such as silicon (Si) provided on the outer peripheral surface of the insulating layer 404 , and conductive layers 412 provided on the upper, lower and outer peripheral surfaces of the semiconductor layer 411 .

[0083] 5, both side surfaces in the X direction of the semiconductor layer 411 and the conductive layer 412 may be formed along a circle centered on the central position of the insulating layer 404. In addition, both side surfaces in the Y direction of the semiconductor layer 411 and the conductive layer 412 may be formed linearly along the side surfaces of the insulating layers 401, 402 in the Y direction.

[0084] One side surface of the conductive layer 412 in the X direction is connected to the conductive layer 221. The other side surface of the conductive layer 412 in the X direction is connected to the wiring region R LL The conductive layer 412 is connected to the conductive layer 501 in the middle. The conductive layer 412 has a function of electrically connecting the other electrode of the transistor TrR (FIG. 1) to the layer selection line LL (FIG. 1).

[0085] [Wiring area R LL Structure of The memory layer ML includes a conductive layer 501 extending in the X direction. The conductive layer 501 functions as, for example, a layer selection line LL (FIG. 1). The conductive layer 501 extends in the X direction. The conductive layers 501 are connected to a plurality of conductive layers 412 arranged in the X direction. The conductive layer 501 includes, for example, a stacked structure of titanium nitride (TiN) and tungsten (W).

[0086] [Manufacturing method] Figures 12 to 122 are schematic cross-sectional views for explaining the manufacturing method of the semiconductor memory device according to the first embodiment. Figures 12, 21, 23, 26, 28, 30, 33, 35, 38, 40, 42, 45, 47, 49, 51, 53, 55, 57, 107, 109, 111, 113, 115, 117, 119 and 121 show cross sections corresponding to Figure 6. 13, 22, 24, 25, 27, 29, 31, 32, 34, 36, 39, 41, 43, 46, 48, 50, 52, 54, 56, 58, 108, 110, 112, 114, 116, 118, 120 and 122 show cross sections corresponding to FIG. 7. 14, 37, 44 and 75 show cross sections corresponding to FIG. 5. 15, 17, 19, 76, 80, 88, 92, 96, 100, 102 and 104 show cross sections corresponding to FIG. 8. 16, 18, 20, 77, 81, 89, 93, 97, 101, 103, 105, and 106 show cross sections corresponding to FIG. 9. 59, 70, 78, 82, 84, 86, 90, 94, and 98 show cross sections corresponding to FIG. 10. 60, 66, 67, 68, 69, 71, 72, 73, 74, 79, 83, 85, 87, 91, 95, and 99 show cross sections corresponding to FIG. 11. 61, 62, 63, 64, and 65 show cross sections including the via wiring 204 and the insulating layer 201.

[0087] In this manufacturing method, for example, as shown in Fig. 13, a plurality of insulating layers 103 and a plurality of sacrificial layers MLA are alternately formed. The sacrificial layers MLA include, for example, silicon nitride (Si3N4) etc. This process is performed, for example, by CVD (Chemical Vapor Deposition) etc.

[0088] Next, as shown in Figs. 12 and 14, for example, insulating layers 115, 301, 302, 401, and 402 are formed. In this step, for example, openings are formed at positions corresponding to the insulating layers 115, 301, 302, 401, and 402. These openings extend in the X and Z directions, and divide the multiple insulating layers 103 and the multiple sacrificial layers MLA aligned in the Z direction in the Y direction. This step is performed by, for example, RIE or the like. After the openings are formed, the insulating layers 115, 301, 302, 401, and 402 are formed. This step is performed by, for example, CVD or the like.

[0089] 15 and 16, an opening 304A is formed at a position corresponding to the insulating layer 304. The opening 304A extends in the Z direction as shown in Fig. 16, and penetrates the multiple insulating layers 103 and the multiple sacrificial layers MLA aligned in the Z direction. This process is performed by, for example, RIE or the like.

[0090] Although not shown, the connection wiring portion 410 (FIG. 5) is formed in the same manner as the connection wiring portion 310. For example, in this process, an opening similar to the opening 304A is also formed in a position corresponding to the insulating layer 404 (FIG. 5). Similarly, in the following processes, the process corresponding to the connection wiring portion 310 is also performed in the position corresponding to the connection wiring portion 410.

[0091] 17 and 18, an opening 310A is formed at a position corresponding to the connection wiring portion 310. A part of the upper surface and a part of the lower surface of the insulating layer 103, a part of the side surface of the sacrificial layer MLA in the X direction, and a part of the side surface of the insulating layers 301 and 302 in the Y direction are exposed inside the opening 310A. In this step, for example, a part of the sacrificial layer MLA is selectively removed through the opening 304A. This step is performed by, for example, wet etching or the like.

[0092] 19 and 20, a sacrificial layer 304B made of silicon (Si) or the like is formed inside the opening 310A and the opening 304A. This process is performed by, for example, CVD or the like.

[0093] 21 and 22, an opening 104A is formed at a position corresponding to the via wiring 104. The opening 104A extends in the Z direction as shown in Fig. 22, and penetrates the multiple insulating layers 103 and the multiple sacrificial layers MLA aligned in the Z direction. This step is performed by, for example, RIE or the like.

[0094] 23 and 24, an opening 111A is formed at a position corresponding to the semiconductor layer 111. A part of the upper surface and a part of the lower surface of the insulating layer 103, a part of the side surface in the X direction of the sacrificial layer MLA, and a part of the side surface in the Y direction of the insulating layer 115 are exposed inside the opening 111A. In this step, for example, a part of the sacrificial layer MLA is selectively removed through the opening 104A. This step is performed by, for example, wet etching or the like.

[0095] 25, a part of the insulating layer 103 is removed. In this step, the width of the opening 111A in the Z direction is increased. This step is performed by, for example, wet etching.

[0096] 26 and 27, for example, an insulating layer 114A is formed on the inner circumferential surface of the opening 104A, the inner circumferential surface of the opening 111A, and the upper and lower surfaces of the insulating layer 103. The insulating layer 114A includes silicon oxide (SiO2) containing boron (B) or the like. This process is performed by, for example, CVD or the like.

[0097] 28 and 29, a conductive layer 113A and a sacrificial layer 111B such as silicon (Si) are formed inside the opening 111A and the opening 104A. The conductive layer 113A is formed on the upper surface, the lower surface, the surface exposed to the opening 104A, the surface exposed to the opening 111A, and both side surfaces in the Y direction of the insulating layer 114A. The opening 111A is filled with the sacrificial layer 111B, and the opening 104A is not filled with the sacrificial layer 111B. This process is performed by, for example, CVD or the like.

[0098] 30 and 31, a part of the sacrificial layer 111B is removed to expose a part of the conductive layer 113A provided at a height position corresponding to the insulating layer 103. This step is performed by, for example, wet etching or the like.

[0099] 32, the conductive layer 113A is removed at a height position corresponding to the insulating layer 103. This step is performed by, for example, wet etching.

[0100] Next, the sacrificial layer 111B is removed, for example, as shown in Figures 33 and 34. This step is performed by, for example, wet etching or the like.

[0101] 35 and 36, a sacrificial layer 104B made of silicon (Si) or the like is formed inside the opening 111A and the opening 104A. This process is performed by, for example, CVD or the like.

[0102] 37, an opening 101A is formed at a position corresponding to the insulating layer 101. The opening 101A extends in the Y and Z directions, and penetrates the insulating layers 103 and the sacrificial layers MLA arranged in the Z direction, dividing these structures in the X direction. This process is performed by, for example, RIE or the like.

[0103] Although not shown, the conductive layer 501 (FIG. 5) is formed in the same manner as the conductive layer 120. For example, in this process, an opening is also formed near the conductive layer 501 (FIG. 5). This opening extends in the X and Z directions, penetrates the multiple insulating layers 103 and the multiple sacrificial layers MLA aligned in the Z direction, and divides these structures in the Y direction. Similarly, in the following processes, the process corresponding to the conductive layer 120 is also performed at a position corresponding to the conductive layer 501.

[0104] Next, as shown in Fig. 38 and Fig. 39, an opening 120A is formed at a position corresponding to the conductive layer 120. A part of the upper surface and a part of the lower surface of the insulating layer 103, the side surface in the X direction of the insulating layer 114A, and the side surface in the X direction of the insulating layer 115 are exposed inside the opening 120A. In this step, for example, the sacrificial layer MLA is removed through the opening 101A. This step is performed by, for example, wet etching or the like.

[0105] 40 and 41, a part of the insulating layer 114A provided on the exposed surface of the conductive layer 113A in the X direction to the openings 120A and 101A is removed through the openings 120A and 101A. This step is performed by, for example, wet etching or the like.

[0106] Next, as shown in Figures 42 and 43, for example, the conductive layer 120 is formed. In this step, a barrier conductive film 121 and a conductive film 122 are formed inside the openings 120A and 101A by a method such as CVD. In this step, the opening 120A is filled with the barrier conductive film 121 and the conductive film 122, but the opening 101A is not filled. Next, a part of the barrier conductive film 121 and the conductive film 122 formed inside the opening 101A is removed by a method such as wet etching. Although not shown in the drawings, after this step is performed, an insulating layer 101 is formed inside the opening 101A.

[0107] 44 to 46, an opening 102A is formed at a position corresponding to the conductive layer 102. The opening 102A extends in the Y and Z directions, and penetrates the insulating layers 103 and the sacrificial layers MLA arranged in the Z direction, as well as the insulating layer 115, to divide these components in the X direction. This step is performed by, for example, RIE or the like.

[0108] 47 and 48, an opening 130A is formed at a position corresponding to the capacitor structure 130. In this step, the sacrificial layer MLA is removed through the opening 102A. This step is performed by, for example, wet etching or the like.

[0109] 49 and 50, the insulating layer 114 is formed. In this step, for example, a part of the insulating layer 114A provided on the side surface of the conductive layer 113A on the opening 102A side in the X direction is removed through the openings 102A and 130A. This step is performed by, for example, wet etching or the like.

[0110] Next, the conductive layer 113 is formed as shown in Fig. 51 and Fig. 52. In this step, for example, a part of the conductive layer 113A provided on the side surface of the sacrificial layer 104B on the opening 102A side in the X direction is removed through the openings 102A and 130A. This step is performed by, for example, wet etching or the like.

[0111] Next, the sacrificial layer 104B is removed as shown in Figures 53 and 54. This step is performed by, for example, wet etching.

[0112] Next, as shown in Fig. 55 and Fig. 56, for example, insulating layers 112, 134 and semiconductor layer 111C are formed inside openings 111A, 104A, 130A, 102A. Insulating layers 112, 134 are formed on the surface of conductive layer 113 exposed to opening 111A, part of the upper surface, part of the lower surface and the surface exposed to opening 102A of insulating layer 103, the surface of insulating layer 114 exposed to opening 104A, and part of the side surface in the Y direction of insulating layer 115. Also, opening 111A is filled with semiconductor layer 111C, and openings 104A, 130A, 102A are not filled with semiconductor layer 111C. This process is performed by, for example, CVD or the like.

[0113] 57 and 58, a sacrificial layer 104C made of silicon (Si) or the like is formed inside the opening 104A. Also, a sacrificial layer 102B made of silicon (Si) or the like is formed inside the opening 102A. This process is performed by, for example, CVD or the like.

[0114] Next, as shown in Fig. 59 and Fig. 60, for example, an opening 204A is formed at a position corresponding to the via wiring 204. The opening 204A extends in the Z direction as shown in Fig. 60, and penetrates the multiple insulating layers 103 and the multiple sacrificial layers MLA aligned in the Z direction. This process is performed by, for example, RIE or the like.

[0115] 61, an opening 201A is formed at a position corresponding to the insulating layer 201. The opening 201A extends in the Y and Z directions, and penetrates the insulating layers 103 and the sacrificial layers MLA arranged in the Z direction, dividing these structures in the X direction. This process is performed by, for example, RIE or the like.

[0116] Next, as shown in Fig. 62, insulating films 201B, 204B such as silicon oxide (SiO2) are formed inside the openings 201A, 204A. The openings 201A, 204A are not filled with the insulating films 201B, 204B. This process is performed by, for example, CVD or the like.

[0117] Next, the insulating film 201B is removed as shown in Fig. 63. This step is performed by, for example, wet etching.

[0118] Next, as shown in FIG. 64, a sacrificial layer 103B is formed. The sacrificial layer 103B includes silicon (Si) containing impurities such as boron (B). In this step, a part of the insulating layer 103 is removed through the opening 201A by a method such as wet etching. In addition, a sacrificial layer 103B is formed on a part of the upper surface, a part of the lower surface, and the surface exposed to the opening 201A of the sacrificial layer MLA by a method such as CVD. The opening 201A is not filled with the sacrificial layer 103B.

[0119] Next, the insulating film 204B is removed as shown in Fig. 65. This step is performed by, for example, wet etching.

[0120] Next, as shown in Fig. 66, an opening 215A is formed at a position corresponding to the conductive layer 215. A part of the upper surface and a part of the lower surface of the sacrificial layer MLA are exposed inside the opening 215A. In this step, for example, a part of the insulating layer 103 is selectively removed through the opening 204A. This step is performed by, for example, wet etching or the like.

[0121] 67, a part of the insulating layer 103 is removed. In this step, the width of the opening 215A in the Z direction is increased. This step is performed by, for example, wet etching.

[0122] Next, as shown in Fig. 68, a sacrificial layer 215B of silicon (Si) or the like is formed inside the opening 215A and the opening 204A. The opening 215A is filled with the sacrificial layer 215B. The opening 204A is not filled with the sacrificial layer 215B. This process is performed by a method such as CVD.

[0123] Next, a part of the sacrificial layer 215B is removed, for example, as shown in Fig. 69. In this step, the sacrificial layer MLA, 103B is exposed inside the opening 204A. This step is performed by, for example, wet etching or the like.

[0124] Next, as shown in Fig. 70 and Fig. 71, a conductive layer 212 is formed. In this step, a part of the sacrificial layer MLA is removed by a method such as wet etching. A conductive layer is also formed on a part of the upper surface, a part of the lower surface, and the surface exposed to the opening 204A of the sacrificial layers 103B and 215B by a method such as ALD (Atomic Layer Deposition). Next, a part of this conductive layer is removed by a method such as wet etching, and divided in the Z direction to form a plurality of conductive layers 212 aligned in the Z direction.

[0125] Next, the sacrificial layer 215B is removed, for example, as shown in Fig. 72. This step is performed by, for example, wet etching or the like.

[0126] 73, for example, the insulating layers 211 and 214, the conductive layer 215, and the via wiring 204 are formed inside the openings 215A and 204A. This process is performed by, for example, CVD or the like.

[0127] Next, the insulating layer 103 is formed, for example, as shown in Fig. 74. In this step, the sacrificial layer 103B is removed by a method such as wet etching. Also, the insulating layer 103 is formed by a method such as CVD.

[0128] Next, as shown in Fig. 75 to Fig. 79, an opening 202A is formed at a position corresponding to the insulating layer 202. The opening 202A extends in the Y and Z directions, and penetrates the insulating layers 103 and the sacrificial layers MLA arranged in the Z direction, dividing these structures in the X direction. This process is performed by, for example, RIE or the like.

[0129] Next, as shown in, for example, FIGS. 80 to 83, openings 221A, 222A, and 213A are formed at positions corresponding to the conductive layers 221 and 222 and the semiconductor layer 213. In the opening 221A, a part of the upper surface and a part of the lower surface of the insulating layer 103, one side surface of the conductive layer 212 in the X direction, and one side surface of the insulating layers 301 and 402 in the Y direction are exposed. In the opening 222A, a part of the upper surface and a part of the lower surface of the insulating layer 103, one side surface of the sacrificial layer 304B in the X direction, and one side surface of the insulating layers 301 and 402 in the Y direction are exposed. In the opening 213A, a part of the upper surface and a part of the lower surface of the insulating layer 214, the other side surface of the conductive layer 212 in the X direction, and one side surface of the insulating layers 301 and 402 in the Y direction are exposed. In this step, for example, a part of the sacrificial layer MLA is selectively removed through the openings 201A and 202A. This step is performed by, for example, wet etching or the like.

[0130] 84 and 85, a semiconductor layer 213B is formed inside the openings 213A, 222A, 202A, 221A, and 201A. The opening 213A is filled with the semiconductor layer 213B, and the openings 222A, 221A, 202A, and 201A are not filled with the semiconductor layer 213B. This process is performed by, for example, CVD or the like.

[0131] Next, the semiconductor layer 213 is formed, for example, as shown in Fig. 86 and Fig. 87. In this step, a part of the semiconductor layer 213B is removed by a method such as wet etching. Specifically, of the semiconductor layer 213B, a part formed inside the opening 213A is left, and the other part is removed.

[0132] Next, as shown in, for example, FIG. 88 to FIG. 91, a conductive layer 222B, an insulating layer 223A, and a sacrificial layer 224A are formed inside the openings 222A and 202A. The conductive layer 222B is formed on a part of the upper surface, a part of the lower surface, and the surface exposed to the opening 202A of the insulating layer 103, the surface exposed to the opening 222A of the sacrificial layer 304B, a part of the upper surface and a part of the lower surface of the insulating layer 214, one side surface in the X direction of the semiconductor layer 213, and one side surface in the Y direction of the insulating layers 301 and 402. The opening 222A is filled with the insulating layer 223A and the sacrificial layer 224A, and the opening 202A is not filled with the insulating layer 223A and the sacrificial layer 224A. This process is performed by, for example, ALD, CVD, or the like.

[0133] Moreover, inside the openings 221A and 201A, a conductive layer 221B, an insulating layer 223A, and a sacrificial layer 224A are formed. The conductive layer 221B is formed on a part of the upper surface, a part of the lower surface, and the surface exposed to the opening 201A of the insulating layer 103, one side surface in the X direction of the conductive layer 212, and one side surface in the Y direction of the insulating layers 301 and 402. The opening 221A is filled with the insulating layer 223A and the sacrificial layer 224A, and the opening 201A is not filled with the insulating layer 223A and the sacrificial layer 224A. This process is performed by, for example, ALD, CVD, or the like.

[0134] Next, as shown in Figs. 92 to 95, the conductive layers 221 and 222 and the insulating layer 223 are formed. In this step, among the conductive layers 221B and 222B, the insulating layer 223A and the sacrificial layer 224A, the portions formed on the surfaces of the insulating layer 103 exposed to the openings 201A and 202A are removed to expose the insulating layer 103 to the openings 201A and 202A. As a result, the conductive layers 221B and 222B and the insulating layer 223A are divided in the Z direction to form the conductive layers 221 and 222 and the insulating layer 223. This step is performed by, for example, wet etching or the like.

[0135] 96 to 99, the sacrificial layer 224A is removed. This step is performed by, for example, wet etching, etc. Furthermore, an insulating layer 224 is formed in the openings 221A and 222A.

[0136] Next, the sacrificial layer 304B is removed as shown in Figures 100 and 101. This step is performed by, for example, wet etching.

[0137] 102 and 103, for example, a conductive layer 312B and a semiconductor layer 311B are formed inside the openings 311A ​​and 304A. The conductive layer 312B is formed on a part of the upper surface, a part of the lower surface, and the surface exposed to the opening 304A of the insulating layer 103, one side surface in the X direction of the conductive layer 222, and one side surface in the X direction of the conductive layer 120. The opening 311A ​​is filled with the semiconductor layer 311B, and the opening 304A is not filled with the semiconductor layer 311B. This process is performed by, for example, CVD or the like.

[0138] Next, as shown in Fig. 104 and Fig. 105, the semiconductor layer 311 is formed. In this step, a part of the semiconductor layer 311 formed on the inner circumferential surface of the insulating layer 103 toward the opening 304A is removed to expose a part of the conductive layer 312B in the opening 304A. As a result, the semiconductor layer 311 is divided in the Z direction to form a plurality of semiconductor layers 311 aligned in the Z direction. This step is performed by, for example, wet etching or the like.

[0139] Next, as shown in FIG. 106, a conductive layer 312 is formed. In this step, a portion of the conductive layer 312B formed on the inner circumferential surface of the insulating layer 103 toward the opening 304A is removed to expose the insulating layer 103 in the opening 304A. As a result, the conductive layer 312B is divided in the Z direction to form a plurality of conductive layers 312 aligned in the Z direction. This step is performed by, for example, wet etching. Furthermore, an insulating layer 304 is formed in the opening 304A.

[0140] Next, the sacrificial layer 102B is removed, for example, as shown in Figures 107 and 108. This step is performed by, for example, wet etching or the like.

[0141] Next, the semiconductor layer 111 is formed as shown in Fig. 109 and Fig. 110. In this step, a part of the semiconductor layer 111C formed on the surface exposed to the openings 130A and 102A of the insulating layer 134 is removed to divide the semiconductor layer 111C in the Y direction. This step is performed by, for example, wet etching or the like.

[0142] 111 and 112, a conductive layer 133A, an insulating layer 130B, and a sacrificial layer 130C are formed on one side surface in the X direction of the semiconductor layer 111 (the side surface on the opening 102A side) and on the exposed surface of the insulating layer 134 to the openings 130A, 102A. This process is performed by, for example, ALD, CVD, or the like.

[0143] Next, as shown in Fig. 113 and Fig. 114, a part of the sacrificial layer 130C is removed through the opening 102A. In this step, for example, a part of the insulating layer 130B corresponding to the side surfaces in the X direction of the insulating layer 115 and the insulating layer 103 is exposed. This step is performed by, for example, wet etching or the like.

[0144] Next, as shown in Fig. 115 and Fig. 116, a part of the insulating layer 130B is removed through the opening 102A. In this step, for example, a part of the conductive layer 133A corresponding to the side surfaces of the insulating layer 115 and the insulating layer 103 in the X direction is exposed. This step is performed by, for example, wet etching or the like.

[0145] Next, the conductive layer 133 is formed as shown in Fig. 117 and Fig. 118. In this step, for example, the portions of the conductive layer 133A provided on the side surfaces of the insulating layer 115 and the insulating layer 103 in the X direction are removed, and the conductive layer 133A is divided in the Y direction and the Z direction. This step is performed by, for example, wet etching or the like.

[0146] Next, the sacrificial layer 130C and the insulating layer 130B are removed through the opening 102A as shown in Figures 119 and 120. This step is performed by, for example, wet etching.

[0147] 121 and 122, the capacitor structure 130 and the conductive layer 102 are formed. In this step, for example, the insulating layer 132 and the conductive layers 131 and 102 are formed on the upper surface, the lower surface, one side surface in the X direction (the side surface on the opening 102A side) and both side surfaces in the Y direction of the conductive layer 133, and the X direction side surface of the insulating layer 134. This step is performed by, for example, CVD or the like.

[0148] Thereafter, the sacrificial layer 104C is removed and the via wiring 104 and the like are formed, thereby completing the manufacture of the semiconductor memory device according to the first embodiment.

[0149] [Comparative Example] FIG. 123 is a schematic circuit diagram showing a configuration of a portion of a semiconductor memory device according to a comparative example.

[0150] A plurality of memory layers ML0' to ML3' (hereinafter, sometimes referred to as "memory layers ML'") included in a memory cell array MCA' of a semiconductor memory device according to a comparative example does not include a transistor TrR, and instead includes transistors TrL0a, TrL0b, TrL1a, TrL1b, TrL2a, TrL2b, TrL3a, and TrL3b (hereinafter, sometimes referred to as "transistors TrL"). One electrode of the transistor TrL is connected to one of the word lines WL0 to WL2. The other electrode of the transistor TrL is connected to a word line selection line LW, respectively. The one and other electrodes of the transistor TrL function as a source electrode or a drain electrode depending on the voltage supplied to the transistor TrL. The gate electrodes of the transistor TrL are each connected to a layer selection line LL.

[0151] FIG. 124 is a schematic circuit diagram for illustrating a read operation of the semiconductor memory device according to the comparative example.

[0152] In the read operation of the semiconductor memory device according to the comparative example, a voltage V ON Instead, the voltage V ON In addition, the voltage V OFF Instead, the voltage V OFF In addition, for example, among the multiple layer selection lines LL0b, LL1b, LL2b, and LL3b, a voltage V OFF Instead, the voltage V OFF In addition, the voltage V OFF Instead, the voltage V ON ´ to supply.

[0153] In addition, among the multiple word line selection lines LW0a, LW1a, and LW2a, a voltage V ON´, but voltage V ON In addition, the voltage V OFF ´, but voltage V OFF In addition, a voltage V OFF ´,Voltage V ON ´, but voltage V OFF supplies.

[0154] In the read operation of the semiconductor memory device according to the comparative example, a voltage V ON In addition, a voltage V OFF is supplied.

[0155] In a read operation, a voltage V ON In order to transfer data at high speed, it is desirable to keep the gate-source voltage of the transistor TrL corresponding to the selected memory cell MC sufficiently higher than the threshold voltage of the transistor TrL and increase the current flowing through the transistor TrL. ON ´) to a large value.

[0156] However, when the gate voltage of the transistor TrL is set to a large value, the gate-source voltage of some of the transistors TrL becomes large, and it becomes necessary to configure the transistor TrL so that it can withstand a higher voltage. To achieve this, it is possible to thicken the gate insulating film of the transistor TrL. However, since the gate voltage of the transistor TrL differs for each memory layer ML', it is necessary to provide an independent gate electrode for each memory layer ML'. For this reason, if the gate insulating film of the transistor TrL is thickened, the length of the entire memory layer ML' in the Z direction increases, which hinders high integration of semiconductor memory devices.

[0157] [effect] As described with reference to Fig. 1, in the semiconductor memory device according to the first embodiment, the gate voltage of the transistor TrR is common among the multiple memory layers ML. With this configuration, as described with reference to Fig. 11, the conductive layer 215 functioning as the gate electrode of the transistor TrR can be provided at a height position corresponding to the insulating layer 103 to serve as a common gate electrode for two transistors TrR adjacent in the Z direction. This makes it possible to thicken the gate insulating film of the transistor TrR without impeding the high integration of the semiconductor memory device.

[0158] In the transistor structure 110 according to this embodiment, the conductive layer 113 faces the upper surface, the lower surface, and both side surfaces in the Y direction of the semiconductor layer 111.

[0159] In such a configuration, it is possible to suppress interference of electric fields between the multiple semiconductor layers 111 arranged in the Z direction. Therefore, even when the memory cell array MCA is highly integrated in the Z direction, it is possible to provide a semiconductor memory device that can appropriately control the semiconductor layers 111 to be in the ON state or OFF state and operates appropriately.

[0160] Furthermore, when the transistor TrC is turned on, channels are formed on the upper surface, the lower surface, and both side surfaces in the Y direction of the semiconductor layer 111. This allows the ON current of the transistor TrC to be relatively large, thereby enabling faster and more stable operation.

[0161] In this embodiment, the conductive layer 120 functioning as the word line WL is provided on the opposite side of the plate line PL with respect to the transistor structure 110, and is provided at a position not overlapping with the transistor structure 110 when viewed from the Z direction. Therefore, the conductive layer 120 and the transistor structure 110 can be formed independently, and can be manufactured relatively easily. In addition, it is possible to make the wiring resistance of the conductive layer 120 a relatively small value while suppressing the width of the memory layer ML in the Z direction.

[0162] [Second embodiment] [structure] Next, a semiconductor memory device according to the second embodiment will be described with reference to Figs. 125 to 127. Fig. 125 is a schematic XY cross-sectional view showing a partial configuration of the semiconductor memory device according to the second embodiment. Fig. 126 is a schematic XY cross-sectional view showing a partial configuration of the same semiconductor memory device, and shows an enlarged view of a part of Fig. 125. Fig. 127 is a schematic cross-sectional view showing a partial configuration of the same semiconductor memory device, showing a configuration in which the structure shown in Fig. 126 is cut along line CC' and viewed along the direction of the arrow.

[0163] The semiconductor memory device according to the second embodiment is basically configured in the same manner as the semiconductor memory device according to the first embodiment. However, as shown in FIG. 125, the semiconductor memory device according to the second embodiment has a transistor region R TrR Instead of the transistor area R TrR2 Equipped with.

[0164] Transistor region R TrR2 is basically the transistor area R TrR However, the transistor region R TrR2 2, the memory layer ML includes a part of a transistor structure 610 instead of a part of the transistor structure 210.

[0165] As shown in Fig. 127, the transistor structure 610 includes a portion provided in the memory layer ML and a portion provided at a height position corresponding to the insulating layer 103. Of these, the portion provided in the memory layer ML includes a plurality of insulating layers 611 provided on the outer peripheral surfaces of the plurality of via wirings 204, and a semiconductor layer 613 provided on the outer peripheral surfaces of the plurality of insulating layers 611 and extending in the Y direction, as shown in Fig. 126. Also, the portion provided at a height position corresponding to the insulating layer 103 includes insulating layers 614 provided on the upper and lower surfaces of the semiconductor layer 613, and conductive layers 615 provided on the upper and lower surfaces of the insulating layer 614, as shown in Fig. 127.

[0166] In the XY cross section as illustrated in FIG. 126, both side surfaces of the semiconductor layer 613 in the X direction may be formed along multiple overlapping circles centered on multiple central positions of the multiple via wirings 204.

[0167] The insulating layer 611 includes, for example, silicon oxide (SiO2) etc. The insulating layer 611 has a substantially cylindrical shape extending in the Z direction along a part of the outer circumferential surface of the via wiring 204. The insulating layer 611 is continuous with the insulating layer 614 (FIG. 127).

[0168] The semiconductor layer 613 functions as, for example, a channel region of the transistor TrR (FIG. 1). The semiconductor layer 613 may be, for example, a semiconductor containing at least one element of gallium (Ga) and aluminum (Al), indium (In), zinc (Zn), and oxygen (O), or may be another oxide semiconductor.

[0169] The insulating layer 614 functions as, for example, a gate insulating film of the transistor TrR (FIG. 1). The insulating layer 614 includes, for example, silicon oxide (SiO2).

[0170] The conductive layer 615 functions as, for example, a gate electrode of the transistor TrR (FIG. 1). The conductive layer 615 includes, for example, a laminated structure of titanium nitride (TiN) and tungsten (W). The conductive layer 615 is connected to a plurality of via wirings 204 arranged in the Y direction. When focusing on two semiconductor layers 613 adjacent to each other in the Z direction, one conductive layer 615 provided between them faces the lower surface of the semiconductor layer 613 provided above and the upper surface of the semiconductor layer 613 provided below, via an insulating layer 614. The plurality of conductive layers 615 arranged in the Z direction are commonly connected to the via wirings 204 extending in the Z direction.

[0171] In addition, when focusing on two conductive layers 615 adjacent to each other in the Z direction, these conductive layers 615 are connected only through the via wiring 204. That is, both ends of these two conductive layers 615 in the Y direction are spaced apart in the Z direction. Similarly, both ends of these two conductive layers 615 in the X direction are also spaced apart in the Z direction.

[0172] [Manufacturing method] Figures 128 to 143 are schematic cross-sectional views for explaining the manufacturing method of the semiconductor memory device according to the second embodiment. Figures 128, 129, 131, 133, 135, 137, 139, 141, and 143 show cross sections corresponding to Figure 127. Figures 130, 132, 134, 136, 138, 140, and 142 show cross sections corresponding to Figure 126.

[0173] In this manufacturing method, for example, the steps up to the steps described with reference to FIGS. 59 and 60 in the manufacturing method of the semiconductor memory device according to the first embodiment are carried out.

[0174] Next, as shown in Fig. 128, an opening 615A is formed at a position corresponding to the conductive layer 615. A part of the upper surface and a part of the lower surface of the sacrificial layer MLA are exposed inside the opening 615A. In this step, for example, a part of the insulating layer 103 is selectively removed through the opening 204A. This step is performed by, for example, wet etching or the like.

[0175] 129, a part of the insulating layer 103 is removed. In this process, the width of the opening 615A in the Z direction is increased. This process is performed by, for example, wet etching.

[0176] 130 and 131, the insulating layers 611 and 614, the conductive layer 615, and the via wiring 204 are formed inside the openings 615A and 204A. This process is performed by, for example, CVD or the like.

[0177] Next, as shown in, for example, FIG. 132 and FIG. 133, openings 221A, 222A, and 613A are formed at positions corresponding to the conductive layers 221 and 222 and the semiconductor layer 613. In the opening 221A, a part of the upper surface and a part of the lower surface of the insulating layer 103, and a part of the side surface of the insulating layers 301 and 402 on one side in the Y direction are exposed. In the opening 222A, a part of the upper surface and a part of the lower surface of the insulating layer 103, and a part of the side surface of the insulating layers 301 and 402 on one side in the Y direction are exposed. In the opening 613A, an upper surface and a part of the lower surface of the insulating layer 614, an outer peripheral surface of the insulating layer 611, and a part of the side surface of the insulating layers 301 and 402 on one side in the Y direction are exposed. In this step, for example, a part of the sacrificial layer MLA is selectively removed through the openings 221A and 222A. This step is performed, for example, by wet etching or the like.

[0178] 134 and 135, a semiconductor layer 613B is formed inside the openings 613A, 222A, 202A, 221A, and 201A. The opening 613A is filled with the semiconductor layer 613B, and the openings 222A, 202A, 221A, and 201A are not filled with the semiconductor layer 613B. This process is performed by, for example, CVD or the like.

[0179] Next, the semiconductor layer 613 is formed, for example, as shown in Fig. 136 and Fig. 137. In this step, a part of the semiconductor layer 613B is removed by a method such as wet etching. Specifically, of the semiconductor layer 613B, a part formed inside the opening 613A is left, and the other part is removed.

[0180] Next, as shown in, for example, Figs. 88, 89, 138 and 139, a conductive layer 222B, an insulating layer 223A and a sacrificial layer 224A are formed inside the openings 222A and 202A. The conductive layer 222B is formed on a part of the upper surface, a part of the lower surface and the surface exposed to the opening 202A of the insulating layer 103, a part of the upper surface and a part of the lower surface of the insulating layer 614, the outer peripheral surface of the semiconductor layer 613, and one side surface in the Y direction of the insulating layers 301 and 402. The opening 222A is filled with the insulating layer 223A and the sacrificial layer 224A, and the opening 202A is not filled with the insulating layer 223A and the sacrificial layer 224A. This process is performed by, for example, ALD, CVD or the like.

[0181] Further, inside the openings 221A and 201A, a conductive layer 221B, an insulating layer 223A, and a sacrificial layer 224A are formed. The conductive layer 221B is formed on a part of the upper surface, a part of the lower surface, and the surface exposed to the opening 201A of the insulating layer 103, a part of the upper surface and a part of the lower surface of the insulating layer 614, the outer peripheral surface of the semiconductor layer 613, and one side surface in the Y direction of the insulating layers 301 and 402. The opening 221A is filled with the insulating layer 223A and the sacrificial layer 224A, and the opening 201A is not filled with the insulating layer 223A and the sacrificial layer 224A. This process is performed by, for example, ALD, CVD, or the like.

[0182] Next, as shown in Figures 92, 93, 140 and 141, conductive layers 221 and 222 and an insulating layer 223 are formed. This step is performed in the same manner as the steps described with reference to Figures 92 to 95, for example.

[0183] Next, as shown in Fig. 96, Fig. 97, Fig. 142 and Fig. 143, the sacrificial layer 224A is removed. This step is performed by, for example, wet etching or the like.

[0184] Thereafter, for example, the steps subsequent to the steps described with reference to FIGS. 100 and 101 in the method for manufacturing the semiconductor memory device according to the first embodiment are performed.

[0185] [Third embodiment] In order to connect the layer selection lines LL to the peripheral circuits, for example, it is possible to provide terrace portions in the conductive layers 501 (FIG. 5) and connect via contact electrodes to the terrace portions. The terrace portion is, for example, a portion of the upper surface of the conductive layer 501 that does not overlap with other conductive layers when viewed from above. In the memory cell array MCA, the more memory layers ML arranged in the Z direction, the more terrace portions are required.

[0186] As described with reference to FIG. 2, in the read operation of the semiconductor memory device according to the first embodiment, a common voltage V OFF is supplied. Therefore, for example, by shorting the layer selection lines LL0b, LL1b, LL2b, and LL3b, it is possible to omit the terrace portions of the layer selection lines LL0b, LL1b, LL2b, and LL3b and reduce the circuit area. Hereinafter, such a configuration will be described as a semiconductor memory device according to a third embodiment.

[0187] FIG. 144 is a schematic circuit diagram showing a configuration of a portion of the semiconductor memory device according to the third embodiment.

[0188] The semiconductor memory device according to the third embodiment is basically configured similarly to the semiconductor memory device according to the first embodiment. However, as shown in the figure, the semiconductor memory device according to the third embodiment includes a wiring LLc instead of the layer selection lines LL0b, LL1b, LL2b, and LL3b. The wiring LLc is commonly connected to the transistors TrR0b, TrR1b, TrR2b, and TrR3b corresponding to the word lines WL0, WL1, and WL2.

[0189] Fig. 145 is a schematic XY cross-sectional view showing a configuration of a portion of the semiconductor memory device according to the third embodiment. Fig. 146 is a schematic cross-sectional view showing a configuration of a portion of the semiconductor memory device, in which the structure shown in Fig. 145 is cut along line DD' and viewed in the direction of the arrow.

[0190] The structure of the semiconductor memory device according to the third embodiment is basically the same as that of the semiconductor memory device according to the first embodiment. However, as shown in FIG. 145, the semiconductor memory device according to the third embodiment has a wiring region R LL Instead of the wiring area R LLc The wiring area R LLc is formed across two memory cell arrays MCA adjacent to each other in the Y direction.

[0191] Although not shown, the memory cell region R MC In the region on one side in the Y direction, similarly to the first embodiment, a wiring region R LL is provided.

[0192] Wiring area R LLc A conductive layer 503 is provided in the memory layer ML. The conductive layer 503 extends in the X direction and the Z direction, and divides the multiple memory layers ML in the Y direction as shown in FIG. 146. The conductive layer 503 includes, for example, a stacked structure of titanium nitride (TiN) and tungsten (W). The conductive layer 503 functions as, for example, the wiring LLc (FIG. 144).

[0193] In addition, the wiring area R LLc 145, the memory layer ML includes a conductive layer 502 extending in the X direction. The conductive layers 502 are connected to a plurality of conductive layers 412 (FIG. 145) arranged in the X direction. The conductive layer 502 is also connected to a conductive layer 503. The conductive layer 502 includes, for example, a stacked structure of titanium nitride (TiN) and tungsten (W).

[0194] In addition, the semiconductor memory device according to the third embodiment has a transistor region R TrR Instead of the transistor region R according to the second embodiment, TrR2 (Figure 125) may also be provided.

[0195] [Fourth embodiment] As described with reference to FIG. 2, during the read operation of the semiconductor memory device according to the first embodiment, a common voltage VOFF In such a configuration, for example, not only the layer selection lines LL0b, LL1b, LL2b, and LL3b but also the transistors TrR0b, TrR1b, TrR2b, and TrR3b can be omitted to further reduce the circuit area. Hereinafter, such a configuration will be described as a semiconductor memory device according to a fourth embodiment.

[0196] FIG. 147 is a schematic circuit diagram showing a configuration of a portion of the semiconductor memory device according to the fourth embodiment.

[0197] The semiconductor memory device according to the fourth embodiment is basically configured similarly to the semiconductor memory device according to the third embodiment. However, as shown in the figure, the semiconductor memory device according to the fourth embodiment includes a resistor R instead of the transistors TrR0b, TrR1b, TrR2b, and TrR3b. The resistor R is provided in a current path between a plurality of word lines WL and a wiring LLc.

[0198] Fig. 148 is a schematic XY cross-sectional view showing a partial configuration of the semiconductor memory device according to the fourth embodiment. Fig. 149 is a schematic cross-sectional view showing a partial configuration of the same semiconductor memory device, in which the structure shown in Fig. 148 is cut along line DD' and viewed in the direction of the arrow.

[0199] The structure of the semiconductor memory device according to the fourth embodiment is basically the same as that of the semiconductor memory device according to the third embodiment. However, as shown in FIG. 148, the semiconductor memory device according to the fourth embodiment has a transistor region R TrR , wiring area R LLc , and the connection wiring area R CL1 ,R CL2 Instead of the wiring area R LLc2 The wiring area R LLc2 is formed across two memory cell arrays MCA adjacent to each other in the Y direction.

[0200] Although not shown, the memory cell region R MC In the region on one side in the Y direction, as in the first embodiment, a transistor region RTrR , wiring area R LL , and the connection wiring area R CL1 ,R CL2 is provided.

[0201] Wiring area R LLc2 A conductive layer 513 is provided in the memory layer ML. The conductive layer 513 extends in the X direction and the Z direction, and divides the multiple memory layers ML in the Y direction as shown in FIG. 149. The conductive layer 513 includes, for example, a stacked structure of titanium nitride (TiN) and tungsten (W). The conductive layer 513 functions as, for example, the wiring LLc (FIG. 147).

[0202] In addition, the wiring area R LLc2 In the memory layer ML, the memory layer ML includes a conductive layer 512 extending in the X direction. The conductive layers 512 are connected to a plurality of conductive layers 120 arranged in the X direction. The conductive layer 512 includes, for example, a stacked structure of titanium nitride (TiN) and tungsten (W).

[0203] In addition, the wiring area R LLc2 149, the semiconductor layer 514 may have a portion provided in the memory layer ML. The semiconductor layer 514 is connected to the conductive layer 513 and the conductive layer 512. The semiconductor layer 514 functions as, for example, a resistor R (FIG. 147). The semiconductor layer 514 may have a portion extending in the Z direction, as shown in FIG. 149, for example. However, the configuration of the semiconductor layer 514 can be appropriately adjusted. For example, it is possible to omit one of the portion provided in the memory layer ML and the portion extending in the Z direction of the semiconductor layer 514.

[0204] In addition, the semiconductor memory device according to the fourth embodiment has a transistor region R TrR Instead of the transistor region R according to the second embodiment, TrR2 (Figure 125) may also be provided.

[0205] [Other embodiments] The semiconductor memory devices according to the first to fourth embodiments have been described above. However, the semiconductor memory devices according to these embodiments are merely examples, and the specific configurations and the like can be appropriately adjusted.

[0206] For example, in the semiconductor memory devices according to the first to fourth embodiments, the via wiring 104 functioning as a bit line contains a conductive oxide such as indium tin oxide (ITO). However, such a conductive oxide may be included in the transistor structure 110, not in the via wiring 104 extending in the Z direction. In addition, the via wiring 104 and the transistor structure 110 may contain other materials.

[0207] Furthermore, in the semiconductor memory devices according to the first to fourth embodiments, the conductive layers 113, 215, 615 functioning as the gate electrodes of the transistors TrC, TrR may face only one of the upper and lower surfaces of the semiconductor layers 111, 213, 613 functioning as the channel regions of the transistors TrC, TrR.

[0208] In addition, in the semiconductor memory devices according to the first to fourth embodiments, the semiconductor layers 111, 213, 613 functioning as channel regions of the transistors TrC and TrR may face the upper and lower surfaces of the conductive layers 113, 215, 615 functioning as gate electrodes of the transistors TrC and TrR.

[0209] In the above description, an example has been described in which a capacitor CpC is adopted as the memory unit connected to the transistor structure 110. However, the memory unit does not have to be the capacitor CpC. For example, the memory unit may include a ferroelectric material, a ferromagnetic material, a chalcogen material such as GeSbTe, or other material, and may record data by utilizing the properties of these materials. For example, in any of the structures described above, the insulating layer between the electrodes that forms the capacitor CpC may include any of these materials.

[0210] Furthermore, the methods for manufacturing the semiconductor memory device according to the first to fourth embodiments can also be adjusted as appropriate. For example, the order of any two of the above-described steps can be changed, or any two of the above-described steps can be performed simultaneously.

[0211] [others] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0212] Sub...semiconductor substrate, ML...memory layer, BL...bit line, WL...word line, PL...plate line, TrC, TrR...transistor, CpC...capacitor, 101...insulating layer, 102...conductive layer, 104, 204...via wiring, 110, 210...transistor structure, 111, 213...semiconductor layer, 112, 214...insulating layer, 113, 215...conductive layer, 120, 501...conductive layer, 130...capacitor structure.

Claims

1. A substrate; a first via wiring extending in a first direction intersecting a surface of the substrate; a plurality of first semiconductor layers arranged in the first direction and electrically connected to the first via wiring; a memory section arranged in the first direction and electrically connected to the plurality of first semiconductor layers; a plurality of first gate electrodes arranged in the first direction and facing the plurality of first semiconductor layers; a plurality of first wirings arranged in the first direction, extending in a second direction intersecting the first direction, and electrically connected to the plurality of first gate electrodes; a plurality of second semiconductor layers arranged in the first direction and electrically connected to the plurality of first wirings; a plurality of second gate electrodes arranged in the first direction and facing the plurality of second semiconductor layers; a second via wiring extending in the first direction and electrically connected to the second gate electrodes; a plurality of second wirings arranged in the first direction, extending in a third direction intersecting the first direction and the second direction, and electrically connected to the plurality of second semiconductor layers; A semiconductor memory device comprising:

2. Among the plurality of second gate electrodes, two adjacent ones in the first direction have ends in the second direction spaced apart from each other in the first direction.

2. The semiconductor memory device according to claim 1.

3. a plurality of insulating layers arranged alternately with the plurality of second semiconductor layers in the first direction; The second gate electrodes are provided at positions in the first direction corresponding to the insulating layers, respectively.

2. The semiconductor memory device according to claim 1.

4. One of the plurality of second gate electrodes is provided between two second semiconductor layers adjacent to each other in the first direction among the plurality of second semiconductor layers, and faces the two second semiconductor layers.

2. The semiconductor memory device according to claim 1.

5. The second semiconductor layer includes at least one element of gallium (Ga) and aluminum (Al), indium (In), zinc (Zn), and oxygen (O).

2. The semiconductor memory device according to claim 1.

6. The first gate electrode faces one and the other surfaces of the first semiconductor layer in the first direction and one and the other surfaces of the first semiconductor layer in the second direction.

2. The semiconductor memory device according to claim 1.

7. The memory unit includes: A first electrode electrically connected to the first semiconductor layer; a second electrode facing the first electrode; an insulating layer provided between the first electrode and the second electrode; 2. The semiconductor memory device according to claim 1, comprising:

8. The first semiconductor layer includes at least one element of gallium (Ga) and aluminum (Al), indium (In), zinc (Zn), and oxygen (O).

2. The semiconductor memory device according to claim 1.

9. a plurality of third semiconductor layers arranged in the first direction and electrically connected to the plurality of first wirings; a plurality of third gate electrodes arranged in the first direction and facing the plurality of third semiconductor layers; a third via wiring extending in the first direction and electrically connected to the third gate electrodes; Equipped with A position of the first via wiring in the second direction is between a position of the second via wiring in the second direction and a position of the third via wiring in the second direction.

2. The semiconductor memory device according to claim 1.

10. a plurality of third wirings arranged in the first direction, extending in the third direction, and electrically connected to the plurality of third semiconductor layers; 10. The semiconductor memory device according to claim 9.

11. a fourth wiring extending in the first direction and the third direction and electrically connected to the third semiconductor layers; 10. The semiconductor memory device according to claim 9.

12. Among the plurality of third gate electrodes, two adjacent ones in the first direction have ends in the second direction spaced apart from each other in the first direction.

10. The semiconductor memory device according to claim 9.

13. a plurality of insulating layers arranged alternately with the plurality of third semiconductor layers in the first direction; The third gate electrodes are provided at positions in the first direction corresponding to the insulating layers, respectively.

10. The semiconductor memory device according to claim 9.

14. One of the plurality of third gate electrodes is provided between two third semiconductor layers adjacent to each other in the first direction among the plurality of third semiconductor layers, and faces the two third semiconductor layers.

10. The semiconductor memory device according to claim 9.

15. The third semiconductor layer includes at least one element of gallium (Ga) and aluminum (Al), indium (In), zinc (Zn), and oxygen (O).

10. The semiconductor memory device according to claim 9.

16. a fifth wiring extending in the first direction and the third direction and electrically connected to the first wirings; a resistor provided in a current path between the plurality of first wirings and the fifth wiring; Equipped with A position of the first via wiring in the second direction is between a position of the second via wiring in the second direction and a position of the fifth wiring in the second direction.

2. The semiconductor memory device according to claim 1.

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