Semiconductor memory device

Abstract

To provide a memory whose cell size can be reduced.SOLUTION: A memory comprises a laminate body including first conductive films and first insulating films which are laminated alternately in a first direction. A first columnar body includes a first semiconductor part, a first insulator part, a second insulator part, a third insulator part, and a fourth insulator part which extend in the first direction in the laminate body. The second insulator part includes a first portion provided between the first insulator part and the first conductive film, and a second portion provided between the first insulator part and the first insulating film and smaller in thickness in a second direction orthogonal to the first direction than the first portion. The plurality of first insulating films are laminated films of the second insulating films and the third insulating films, or are constituted of the third insulating films.SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] The present embodiment relates to a semiconductor memory device. [Background technology]

[0002] Semiconductor memory devices such as NAND flash memories may have a three-dimensional memory cell array in which multiple memory cells are arranged three-dimensionally. In such a three-dimensional memory cell array, charge leakage between adjacent memory cells sharing a charge trapping film has been a problem. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Patent Publication No. 2021 / 0265372 [Patent Document 2] U.S. Patent Publication No. 2021 / 0265385 [Patent Document 3] U.S. Patent Publication No. 2021 / 0296354 [Patent Document 4] U.S. Patent Publication No. 2018 / 0151588 [Patent Document 5] US Patent Publication No. 2017 / 0069647 [Patent Document 6] U.S. Patent Publication No. 2021 / 0391352 Summary of the Invention [Problem to be solved by the invention]

[0004] A semiconductor memory device capable of suppressing charge leakage between memory cells and reducing the cell size is provided. [Means for solving the problem]

[0005] The semiconductor memory device according to the present embodiment includes a stack including a plurality of first conductive films and a plurality of first insulating films alternately stacked in a first direction. The plurality of first columnar bodies include a first semiconductor portion extending in the stack in the first direction, a first insulator portion provided between the first semiconductor portion and the stack, a second insulator portion provided between the first insulator portion and the stack, a third insulator portion provided between the second insulator portion and the plurality of first conductive films, and a fourth insulator portion provided between the second insulator portion and the plurality of first insulating films. The second insulator portion includes a first portion provided between the first insulator portion and the first conductive film, and a second portion provided between the first insulator portion and the first insulating film and having a thickness smaller than that of the first portion in a second direction perpendicular to the first direction. The plurality of first insulating films are a stack of the second insulating film and the third insulating film, or are composed of the third insulating film. [Brief description of the drawings]

[0006] [Figure 1] 1 is a cross-sectional view showing an example of the configuration of a semiconductor memory device according to a first embodiment. [Diagram 2] FIG. [Diagram 3] FIG. 1 is a schematic cross-sectional view illustrating a memory cell array. [Figure 4] Cross-sectional view taken along line 4-4 in Figure 3. [Diagram 5] Cross-sectional view taken along line 5-5 in Figure 3. [Figure 6] FIG. 4 is an enlarged cross-sectional view of the portion enclosed by the dashed line in FIG. 3 . [Figure 7] FIG. 13 is a schematic cross-sectional view illustrating a memory cell array according to a second embodiment. [Figure 8] FIG. 13 is a schematic cross-sectional view illustrating a memory cell array according to a third embodiment. [Figure 9] FIG. 13 is a schematic cross-sectional view illustrating a memory cell array according to a fourth embodiment. [Figure 10] FIG. 13 is a schematic cross-sectional view illustrating a memory cell array according to a fifth embodiment. [Figure 11] FIG. 13 is a schematic cross-sectional view illustrating a memory cell array according to a sixth embodiment. [Figure 12]FIG. 23 is a schematic cross-sectional view illustrating a memory cell array according to a seventh embodiment. [Figure 13] 20 is a schematic cross-sectional view illustrating a staircase portion 2s of a memory cell array according to an eighth embodiment. FIG. [Figure 14] 3A to 3C are cross-sectional views showing an example of a method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 15] 15 is a cross-sectional view showing an example of a manufacturing method of the semiconductor memory device following FIG. 14. [Figure 16] 16 is a cross-sectional view showing an example of a manufacturing method of the semiconductor memory device subsequent to FIG. 15. [Figure 17] 17 is a cross-sectional view showing an example of a manufacturing method of the semiconductor memory device subsequent to FIG. 16. [Figure 18] 18 is a cross-sectional view showing an example of a manufacturing method of the semiconductor memory device following FIG. 17. [Figure 19] 19 is a cross-sectional view showing an example of a manufacturing method of the semiconductor memory device subsequent to FIG. 18. [Figure 20] 19 is a cross-sectional view showing an example of a manufacturing method of the semiconductor memory device, subsequent to FIG. 19. [Figure 21] 13A to 13C are cross-sectional views showing an example of a method for manufacturing the semiconductor memory device according to the sixth embodiment. [Figure 22] FIG. 13 is a schematic cross-sectional view illustrating a memory cell array according to a ninth embodiment. [Figure 23] FIG. 23 is a schematic cross-sectional view illustrating a memory cell array according to a tenth embodiment. [Figure 24] 13A to 13C are cross-sectional views showing an example of a method for manufacturing the semiconductor memory device according to the ninth embodiment. [Diagram 25] 25 is a cross-sectional view showing an example of a manufacturing method of the semiconductor memory device subsequent to FIG. 24. [Figure 26] 26 is a cross-sectional view showing an example of a manufacturing method of the semiconductor memory device subsequent to FIG. 25. [Figure 27] 27 is a cross-sectional view showing an example of a manufacturing method of the semiconductor memory device subsequent to FIG. 26. [Figure 28] 28 is a cross-sectional view showing an example of a manufacturing method of the semiconductor memory device subsequent to FIG. 27. [Figure 29] FIG. 23 is a schematic cross-sectional view illustrating a memory cell array according to an eleventh embodiment. [Diagram 30]3 is a cross-sectional view showing a configuration example of a lower end portion of a pillar according to the first embodiment. FIG. [Diagram 31] 13 is a cross-sectional view showing another example of the configuration of the lower end portion of the columnar body. FIG. [Diagram 32] 13 is a cross-sectional view showing another example of the configuration of the lower end portion of the columnar body. FIG. [Diagram 33] FIG. 13 is a cross-sectional view showing a configuration example in which configuration example 1 of the lower end portion of a columnar body is applied to the ninth embodiment. [Diagram 34] FIG. 13 is a cross-sectional view showing a configuration example in which Configuration Example 2 of the lower end portion of a columnar body is applied to the ninth embodiment. [Diagram 35] FIG. 13 is a cross-sectional view showing a configuration example in which Configuration Example 2 of the lower end portion of a columnar body is applied to the ninth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The present invention is not limited to the embodiment. The drawings are schematic or conceptual. In the specification and the drawings, the same elements are given the same reference numerals.

[0008] (First embodiment) 1 is a cross-sectional view showing an example of the configuration of a semiconductor memory device 1 according to the first embodiment. Hereinafter, the stacking direction of the stacked body 20 is defined as the Z direction. A direction that intersects with, for example, is perpendicular to, the Z direction is defined as the Y direction. A direction that intersects with, for example, is perpendicular to each of the Z direction and the Y direction is defined as the X direction. In this specification, the Z direction is an example of the first direction. The X direction or the Y direction is an example of the second direction.

[0009] The semiconductor memory device 1 includes an array chip 2 having a memory cell array, and a CMOS chip 3 having a CMOS circuit. The array chip 2 and the CMOS chip 3 are bonded together at a bonding surface B1, and are electrically connected to each other via wiring joined at the bonding surfaces. Fig. 1 shows a state in which the array chip 2 is mounted on the CMOS chip 3.

[0010] The CMOS chip 3 includes a substrate 30, a transistor 31, a via 32, wirings 33 and 34, and an interlayer insulating layer 35.

[0011] The substrate 30 is, for example, a semiconductor substrate such as a silicon substrate. The transistor 31 is an NMOS or PMOS transistor provided on the substrate 30. The transistor 31 constitutes, for example, a CMOS circuit that controls a memory cell array of the array chip 2. The multiple transistors 31 constitute logic circuits such as a sense amplifier, a row decoder, a column decoder, etc. Semiconductor elements such as resistor elements and capacitor elements other than the transistors 31 may be formed on the substrate 30.

[0012] The via 32 electrically connects the transistor 31 and the wiring 33, or the wiring 33 and the wiring 34. The wirings 33 and 34 form a multi-layer wiring structure in the interlayer insulating layer 35. The wiring 34 is embedded in the interlayer insulating layer 35 and is exposed almost flush with the surface of the interlayer insulating layer 35. The wirings 33 and 34 are electrically connected to the transistor 31 and the like. The via 32 and the wirings 33 and 34 are made of low-resistance metals such as copper and tungsten. The interlayer insulating layer 35 covers and protects the transistor 31, the via 32, and the wirings 33 and 34. The interlayer insulating layer 35 is made of an insulating layer such as a silicon oxide film containing silicon and oxygen.

[0013] The array chip 2 includes a stack 20, columns CL, slits ST (LI), source layers BSL, a metal layer 40, contacts CCw, contact plugs 29, and bonding pads 50.

[0014] The stacked body 20 is provided above the transistor 31 and is located in the Z direction with respect to the substrate 30. The stacked body 20 is configured by alternately stacking a plurality of conductive films 21 and a plurality of insulating films 22 along the Z direction. The stacked body 20 configures a memory cell array. The conductive film 21 is made of a conductive metal such as tungsten. The insulating film 22 is made of an insulating layer such as a silicon oxide film containing silicon and oxygen. The insulating film 22 insulates the conductive films 21 from each other. That is, the plurality of conductive films 21 are stacked in an insulated state from each other. The number of stacked conductive films 21 and insulating films 22 is arbitrary. The insulating film 22 may be, for example, a porous insulating layer or an air gap.

[0015] One or more conductive films 21 at the top and bottom ends of the stack 20 in the Z direction function as a source side select gate SGS and a drain side select gate SGD, respectively. The conductive film 21 between the source side select gate SGS and the drain side select gate SGD functions as a word line WL. The word line WL is the gate electrode of the memory cell MC. The drain side select gate SGD is the gate electrode of the drain side select transistor. The source side select gate SGS is provided in an upper region of the stack 20. The drain side select gate SGD is provided in a lower region of the stack 20. The upper region refers to the region of the stack 20 closer to the CMOS chip 3, and the lower region refers to the region of the stack 20 farther from the CMOS chip 3 (closer to the metal layer 40).

[0016] The semiconductor memory device 1 has a plurality of memory cells MC connected in series between a source-side select transistor and a drain-side select transistor. A structure in which the source-side select transistor, the memory cells MC, and the drain-side select transistor are connected in series is called a "memory string" or a "NAND string." The memory string is connected to a bit line BL, for example, through a via 28. The bit line BL is a wiring 23 provided under (on the upper region side of) the stacked body 20 and extending in the X direction.

[0017] A plurality of pillars CL are provided in the stack 20. The pillars CL extend in the stacking direction (Z direction) of the stack 20 so as to penetrate the stack 20, and are provided from a via 28 connected to the bit line BL to the source layer BSL. The internal structure of the pillars CL will be described later. In this embodiment, since the pillars CL have a high aspect ratio, they are formed in two stages in the Z direction. However, there is no problem if the pillars CL are in one stage or three or more stages.

[0018] Although not shown in FIG. 1, a plurality of slits ST (see FIG. 2) are provided in the stacked body 20. The slits ST extend in the Y direction and penetrate the stacked body 20 in the stacking direction (Z direction) of the stacked body 20. The slits ST are filled with an insulating material such as a silicon oxide film containing silicon and oxygen, and the insulating material is configured in a plate shape. The slits ST electrically separate the conductive films 21 of the stacked body 20. Alternatively, the inner wall of the slits ST may be covered with an insulating layer such as a silicon oxide film, and a conductive material may be further embedded inside the insulating layer. In this case, the conductive material also functions as a source wiring that reaches the source layer BSL.

[0019] A source layer BSL is provided on the upper side (lower region side) of the stacked body 20. The source layer BSL is an example of a first semiconductor layer. The source layer BSL is provided corresponding to the stacked body 20. The source layer BSL has a first face F1 and a second face F2 opposite to the first face F1. The stacked body 20 (memory cell array) is provided on the first face F1 side of the source layer BSL, and a metal layer 40 is provided on the second face F2 side. The source layer BSL is commonly connected to one end of the plurality of pillars CL, and applies a common source potential to the plurality of pillars CL in the same memory cell array 2m. That is, the source layer BSL functions as a common source electrode of the memory cell array 2m. For the source layer BSL, a conductive material such as doped polysilicon is used. For the metal layer 40, a metal material having a lower resistance than the source layer BSL, such as copper, aluminum, or tungsten, is used. Note that 2s is a step portion of the conductive film 21 provided to connect a contact to each conductive film 21. The staircase portion 2s will be described later with reference to FIG.

[0020] On the other hand, a bonding pad 50 is provided on the stacked body 20 in a region where the source layer BSL is not provided. The bonding pad 50 is connected to a metal wire or the like (not shown) and receives a power supply or a signal from outside the semiconductor memory device 1. The bonding pad 50 is provided so as to be connected to one end of the contact plug 29 in the Z direction. The bonding pad 50 is connected to the transistor 31 of the CMOS chip 3 via the contact plug 29, the wiring 24, and the wiring 34. Therefore, the external power supply supplied from the bonding pad 50 is supplied to the transistor 31. Alternatively, a signal is supplied to the transistor 31 or the memory cell array 2m via the bonding pad 50.

[0021] The contact CCw is provided on the periphery of the stacked body 20 and extends in the Z direction within the interlayer insulating layer 25. The contact CCw is electrically connected between the conductive film 21 (word line WL) and the wiring 24. The contact CCw is provided in a staircase portion 2s formed in a staircase shape at the end of the stacked body 20 and is electrically connected to each conductive film 21. The contact CCw is provided to transmit the word line voltage from the CMOS chip 3 to each conductive film 21. The contact CCw is made of a low-resistance metal such as copper or tungsten.

[0022] The contact plug 29 is provided on the periphery of the laminate 20, and extends in the Z direction through the interlayer insulating layer 25. The contact plug 29 is a contact plug provided from the wiring 24 to the bonding pad 50.

[0023] The contact plug 29 is electrically connected between the bonding pad 50 and the wiring 24. The contact plug 29 is used to supply a power supply voltage or a signal from the bonding pad 50 to the array chip 2 or the CMOS chip 3. For example, a low-resistance metal such as copper or tungsten is used for the contact plug 29. The power supply voltage may be a high-level power supply voltage VDD or a low-level reference voltage (for example, a ground voltage) VSS. The signal may be an external control signal or write data or read data.

[0024] In this embodiment, the array chip 2 and the CMOS chip 3 are formed separately and are bonded together at a bonding surface B1. Therefore, the array chip 2 does not include a transistor 31. The CMOS chip 3 does not include a stacked body 20 (memory cell array). The transistor 31 and the stacked body 20 are both on the first surface F1 side of the source layer BSL. The transistor 31 is on the opposite side to the second surface F2 of the source layer BSL on which the metal layer 40 is located.

[0025] Below the stacked body 20 (on the upper region side), a via 28, a wiring 23, and a wiring 24 are provided. The wirings 23 and 24 are embedded in an interlayer insulating layer 25. The wiring 24 is exposed to the surface of the interlayer insulating layer 25 in a substantially flush manner. The wirings 23 and 24 are electrically connected to the semiconductor body 210 of the columnar body CL, etc. The via 28, the wiring 23, and the wiring 24 are made of a low-resistance metal such as copper or tungsten. The interlayer insulating layer 25 covers and protects the stacked body 20, the via 28, the wiring 23, and the wiring 24. The interlayer insulating layer 25 is made of an insulating layer such as a silicon oxide film containing silicon and oxygen.

[0026] The interlayer insulating layer 25 and the interlayer insulating layer 35 are bonded to each other at a bonding surface B1, and the wiring 24 and the wiring 34 are also bonded to each other at a substantially flush surface B1. As a result, the array chip 2 and the CMOS chip 3 are electrically connected to each other via the wiring 24 and the wiring 34.

[0027] FIG. 2 is a schematic plan view showing the stack 20. The stack 20 includes a staircase portion 2s and a memory cell array 2m. The staircase portion 2s is provided at an end of the stack 20. The memory cell array 2m is sandwiched or surrounded by the staircase portion 2s. The slit ST(LI) is provided from the staircase portion 2s at one end of the stack 20 through the memory cell array 2m to the staircase portion 2s at the other end of the stack 20. The slit SHE is provided at least in the memory cell array 2m. The slit SHE is shallower than the slit ST(LI) and extends approximately parallel to the slit ST(LI). The slit SHE is provided to electrically separate the conductive film 21 for each drain side selection gate SGD. Alternatively, the slit ST may be a source wiring LI that is electrically separated from the conductive film 21 of the stack 20 and electrically connected to the source layer BSL. That is, the slit ST may be a source wiring LI that is electrically isolated from the conductive film 21 of the stacked body 20 that constitutes the memory cell array and is electrically connected to the source layer BSL.

[0028] The portion of the stack 20 sandwiched between the two slits ST shown in FIG. 2 is called a block. The block constitutes, for example, the minimum unit of data erasure. The slit SHE is provided within the block. The stack 20 between the slit ST and the slit SHE is called a finger. The drain side selection gate SGD is divided into each finger. Therefore, when writing and reading data, one finger in the block can be selected by the drain side selection gate SGD.

[0029] Fig. 3 is a schematic cross-sectional view illustrating a memory cell array. Fig. 4 shows a cross-section taken along line 4-4 in Fig. 3, and Fig. 5 shows a cross-section taken along line 5-5 in Fig. 3. Fig. 6 shows an enlarged cross-section of a portion enclosed by a dashed line 6 in Fig. 3.

[0030] As shown in FIG. 3, each of the multiple pillars CL is provided in a memory hole MH provided in the stack 20. Each pillar CL penetrates the stack 20 from the upper end of the stack 20 along the Z direction and is provided in the stack 20 and the source layer BSL. Each of the multiple pillars CL includes a semiconductor body 210, a memory film 220, and a core layer 230. The pillar CL includes a core layer 230 provided in the center thereof, a semiconductor body (semiconductor layer) 210 provided around the core layer 230, and a memory film 220 provided around the semiconductor body 210. The semiconductor body 210 extends in the stacking direction (Z direction) in the stack 20. The semiconductor body 210 is electrically connected to the source layer BSL. The memory film 220 is provided between the semiconductor body 210 and the conductive film 21, and has a charge trapping film. A plurality of pillars CL selected one by one from each finger are commonly connected to one bit line BL through the via 28 in Fig. 1. Each of the pillars CL is provided, for example, in the region of the memory cell array 2m.

[0031] As shown in FIG. 3 and FIG. 6, a block insulating layer 21a and a barrier film 21b constituting a part of the memory film 220 are provided between the conductive film 21 and the insulating film 22 and between the conductive film 21 and the block insulating layer 224. The block insulating layer 21a as a third insulator is provided between the conductive film 21 and the insulating film 22 and between the conductive film 21 and the block insulating layer 224 or the charge trapping film 222. The block insulating layer 21a is, for example, a silicon oxide or a metal oxide. One example of the metal oxide is an aluminum oxide containing aluminum and oxygen. The block insulating layer 21a suppresses back tunneling of charges from the conductive film 21 to the memory film 220. When the conductive film 21 is tungsten, for example, a laminated film of titanium nitride and titanium is selected as the barrier film 21b. The barrier film 21b is a conductive material that improves the adhesion between the conductive film 21 and the block insulating layer 21a. The barrier film 21b includes, for example, a conductive metal compound such as a laminated film of titanium nitride and titanium.

[0032] 4 and 5, the shape of the memory hole MH in the XY plane is, for example, a circle or an ellipse. The memory hole MH has a core layer 230 at the center thereof, and the semiconductor body 210 and the memory film 220 are provided around the core layer 230.

[0033] The semiconductor body 210 has, for example, a cylindrical shape. The semiconductor body 210 is made of, for example, polysilicon. The semiconductor body 210 is, for example, undoped silicon. The semiconductor body 210 may also be p-type silicon. The semiconductor body 210 becomes the channels of the drain side select transistor STD, the memory cell MC, and the source side select transistor STS. One end of the multiple semiconductor bodies 210 in the same memory cell array 2m is electrically connected in common to the source layer BSL.

[0034] The memory film 220 is provided between the inner wall of the memory hole MH and the semiconductor body 210. The memory film 220 has, for example, a cylindrical shape. The memory cells MC have a storage area between the semiconductor body 210 and the conductive film 21 serving as the word line WL, and are stacked in the Z direction. The memory film 220 includes, for example, a block insulating layer 224 in FIG. 4, a cover insulating layer 221 in FIG. 5, a charge trapping film 222 (222a, 222b), and a tunnel insulating layer 223. Each of the semiconductor body 210, the charge trapping film 222, and the tunnel insulating layer 223 extends in the Z direction.

[0035] 6, the cover insulating layer 221 as the fourth insulator is provided between a part (222a) of the charge trapping film 222 as the second insulator and the multiple insulating films 22. The cover insulating layer 221 is provided intermittently in the Z direction. Adjacent cover insulating layers 221 in the Z direction are separated by a block insulating layer 224 and a part (222b) of the charge trapping film 222.

[0036] In the memory hole MH, a cover insulating layer 221 and a block insulating layer 224 are provided around the charge trapping film 222. The cover insulating layer 221 is a film different from the charge trapping film, and an insulating layer such as silicon oxide containing silicon and oxygen, HfO, ZrO, etc. is used for the cover insulating layer 221.

[0037] The cover insulating layer 221 is provided between the block insulating layers 224 adjacent in the Z direction and between the second charge trapping films 222b adjacent in the Z direction. The cover insulating layer 221 is thicker than the block insulating layer 224 in the thickness in the X direction or Y direction.

[0038] The block insulating layer 224 is provided between the conductive film 21 and the charge trapping film 222. For example, an insulating layer such as a silicon oxide containing silicon and oxygen is used for the block insulating layer 224. The block insulating layer 224, together with the block insulating layer 21a, suppresses back tunneling of charges from the conductive film 21 to the memory film 220 side.

[0039] The charge trapping film 222 as the second insulator is provided between the stack 20 and the tunnel insulating layer 223. The charge trapping film 222 is provided between the cover insulating layer 221 and the tunnel insulating layer 223, and between the block insulating layer 224 and the tunnel insulating layer 223. The charge trapping film 222 includes a first charge trapping film 222a and a second charge trapping film 222b. The first charge trapping film 222a is provided between the second charge trapping film 222b or the cover insulating layer 221 and the tunnel insulating layer 223, and extends continuously in the Z direction. The second charge trapping film 222b is provided between the conductive film 21 or the block insulating layer 224 and the first charge trapping film 222a, and is provided intermittently in the Z direction. For the first and second charge trapping films 222a and 222b, for example, an insulating layer such as silicon nitride containing silicon and nitrogen is used.

[0040] The first and second charge trapping films 222a and 222b each have a trap site that traps a charge in the film. That is, the first and second charge trapping films 222a and 222b are configured as one charge trapping film 222. Of the charge trapping film 222, a first portion 222_1 sandwiched between the conductive film 21 (including the barrier film 21b) that becomes the word line WL and the semiconductor body 210 and / or between the block insulating layer 21a and the semiconductor body 210 is configured of the first and second charge trapping films 222a and 222b. The first portion 222_1 corresponding to each memory cell MC accumulates charges and functions as a storage area for each memory cell MC. Of the charge trapping film 222, a second portion 222_2 provided between the insulating film 22 (cover insulating layer 221) and the tunnel insulating layer 223 is configured of the first charge trapping film 222a. The second portion 222_2 is provided between the first portions 222_1 adjacent in the Z direction. The thickness T2 of the second portion 222_2 of the charge trapping film 222 in the Y or X direction is thinner than the thickness T1 of the first portion 222_1 in the Y or X direction by the thickness of the second charge trapping film 222b. This separates the first portions 222_1 of the memory cells MC adjacent in the Z direction, and the charge stored in the charge trapping film can be prevented from moving in the first portions 222_1 adjacent in the Z direction. This prevents interference of data between the memory cells MC adjacent in the Z direction. In addition, by making the capacitance of the first portion 222_1 larger than that of the second portion 222_2, each memory cell MC can store a large amount of charge. The threshold voltage of the memory cell MC changes depending on the presence or absence of charge in the first portion 222_1 of the charge trapping film 222, or the amount of charge trapped in the first portion 222_1. This allows the memory cell MC to hold information.

[0041] The tunnel insulating layer 223 as the first insulating body is provided between the stack 20 and the semiconductor body 210. More specifically, the tunnel insulating layer 223 is provided between the semiconductor body 210 and the charge trapping film 222. For example, an insulating layer such as a silicon oxide film containing silicon and oxygen or a silicon oxynitride film containing silicon oxide and silicon nitride is used for the tunnel insulating layer 223. The tunnel insulating layer 223 is a potential barrier between the semiconductor body 210 and the charge trapping film 222. For example, when electrons are injected from the semiconductor body 210 to the charge trapping film 222 (write operation), and when holes are injected from the semiconductor body 210 to the charge trapping film 222 (erase operation), the electrons and holes pass through (tunnel) the potential barrier of the tunnel insulating layer 223.

[0042] The core layer 230 fills the internal space of the cylindrical semiconductor body 210. The core layer 230 has, for example, a columnar shape. The core layer 230 is made of, for example, an insulating material such as silicon oxide containing silicon and oxygen.

[0043] A block insulating layer 21a serving as a fifth insulator portion is provided between the block insulating layer 224 and the barrier film 21b or the conductive film 21. The block insulating layer 21a is also provided between the insulating film 22 and the barrier film 21b or the conductive film 21. The block insulating layer 21a is made of an insulating material (high-k material) having a higher dielectric constant than the block insulating layer 224. For example, an aluminum oxide film (Al2O3) having a higher dielectric constant than a silicon oxide film is used for the block insulating layer 21a.

[0044] The barrier film 21b is provided between the conductive film 21 and the block insulating layer 21a. As described above, when the conductive film 21 is made of tungsten, for example, a laminated film of titanium nitride and titanium is selected for the barrier film 21b. The barrier film 21b is very thin compared to the conductive film 21, and may be considered to function as a part of the conductive film 21. Therefore, the conductive film 21 may include the barrier film 21b.

[0045] If the boundary between block insulating layer 21a and block insulating layer 224 is B21a_224 and the boundary between insulating film 22 and cover insulating layer 221 is B22_221, as shown in Fig. 6, boundary B21a_224 is located at the same position as boundary B22_221 or closer to the inside (center) of memory hole MH in the XY plane than boundary B22_221. That is, radius R21a_224 (see Fig. 4) of memory hole MH or columnar body CL at boundary B21a_224 is equal to or smaller than radius R22_221 (see Fig. 5) of memory hole MH or columnar body CL at boundary B22_221 in the XY plane. Note that when boundary B21a_224 and boundary B22_221 are in the same position, boundary B21a_224 overlaps boundary B22_221 in the XY plane.

[0046] According to this embodiment, the boundary B21a_224 overlaps with the boundary B22_221 in the XY plane or is closer to the center Cmh of the memory hole MH than the boundary B22_221. This allows the conductive film 21 to protrude toward the memory hole MH and the columnar body CL, and the charge stored in the first portion 222_1 of the charge trapping film 222 can be well controlled. In addition, since the conductive film 21 protrudes toward the center Cmh of the memory hole MH from the side surface (boundary B22_221) of the memory hole MH at the time of its formation, the embeddability of the metal material of the conductive film 21 does not deteriorate even if the distance between adjacent memory holes MH in the same WL plane is reduced. Therefore, even if the interval between adjacent memory holes MH in the XY plane is narrowed, the material of the conductive film 21 can be embedded in the space between the insulating films 22, and the replacement process is not adversely affected. As a result, the cell size of the memory cell array 2m can be reduced. The manufacturing method of this embodiment will be described later.

[0047] Second embodiment FIG. 7 is a schematic cross-sectional view illustrating a memory cell array according to the second embodiment. In the seventh embodiment, the insulating film 22 is composed of a stacked film of insulating films 22a and 22b. The insulating film 22a as the second insulating film is provided in the center of the insulating film 22 and is composed of an insulating material such as a silicon oxide film. The insulating films 22b are provided on both sides of the insulating film 22a in the Z direction so as to sandwich the insulating film 22a. For example, an insulating material such as SiOC, which is a silicon oxide film containing carbon, is used for the insulating film 22b. When SiOC is used as the insulating film 22b, the element ratio of carbon can be adjusted so that the etching rate by hydrofluoric acid is lower than that of a silicon oxide film. The carbon density in SiOC is, for example, 5E20 to 1E22 atom / cm 3 It is.

[0048] 7, the insulating film 22a is sandwiched between insulating films 22b above and below in the Z direction. The insulating film 22b is provided between the insulating film 22a and the block insulating layer 21a.

[0049] Other configurations of the second embodiment may be the same as those of the first embodiment. Therefore, the second embodiment can obtain the same effects as those of the first embodiment. The manufacturing method of the second embodiment will be described later.

[0050] Third embodiment 8 is a schematic cross-sectional view illustrating a memory cell array according to the third embodiment. In the third embodiment, the entire insulating film 22 is made of the material of the insulating film 22b. For example, the insulating film 22 is made of an insulating material such as SiOC, which is a silicon oxide film containing carbon.

[0051] Other configurations of the third embodiment may be the same as those of the first embodiment. Therefore, the third embodiment can obtain the same effects as those of the first embodiment. The manufacturing method of the third embodiment will be described later.

[0052] (Fourth embodiment) 9 is a schematic cross-sectional view illustrating a memory cell array according to the fourth embodiment. In the fourth embodiment, the insulating film 22b is provided at the center of the insulating film 22. The insulating films 22a are provided on both sides of the insulating film 22b in the Z direction so as to sandwich the insulating film 22b. The insulating film 22a is provided around the insulating film 22b. The materials of the insulating films 22a and 22b may be the same as those of the second embodiment.

[0053] 9, the insulating film 22b is sandwiched between the insulating films 22a above and below in the Z direction. The insulating film 22a is provided between the insulating film 22b and the block insulating layer 21a.

[0054] In this manner, in the insulating film 22, the insulating film 22b may be sandwiched between the insulating films 22a above and below in the Z direction.

[0055] Other configurations of the fourth embodiment may be the same as those of the first embodiment. Therefore, the fourth embodiment can obtain the same effects as those of the first embodiment. The manufacturing method of the fourth embodiment will be described later.

[0056] Fifth embodiment 10 is a schematic cross-sectional view illustrating a memory cell array according to the fifth embodiment. In the fifth embodiment, the first charge trapping film 222a is not provided. Therefore, the charge trapping film 222 is provided between the conductive film 21 or the block insulating layer 21a and the tunnel insulating layer 223, but is not provided between the insulating film 22 or the cover insulating layer 221 and the tunnel insulating layer 223. As a result, the charge trapping film 222 is completely separated for each memory cell MC by the cover insulating layer 221 in the Z direction. This makes it possible to more reliably suppress the movement of charges in the charge trapping films 222 of multiple memory cells MC adjacent in the Z direction.

[0057] On the other hand, instead of the first charge trapping film 222a, a seed insulating film 223a is provided between the charge trapping film 222 and the tunnel insulating layer 223. The seed insulating film 223a may be a part of the tunnel insulating layer 223, and is made of a high dielectric material such as an aluminum oxide film. Other configurations of the fifth embodiment may be the same as those of the first embodiment. Therefore, the fifth embodiment can obtain the same effects as those of the first embodiment. Furthermore, the fifth embodiment may be combined with any of the second to fourth embodiments. As a result, the fifth embodiment can obtain the effects of any of the second to fourth embodiments.

[0058] Sixth embodiment FIG. 11 is a schematic cross-sectional view illustrating a memory cell array according to a sixth embodiment. In the sixth embodiment, in a cross section in the Z direction, the cover insulating layer 221 has a T-shape with the -Y direction as the top. Accordingly, the second charge trapping film 222b has a T-shape with the +Y direction as the top. Therefore, in a cross section in the Z direction, the length La of the boundary between the first portion 222_1 of the charge trapping film 222 and the block insulating layer 224 is longer than the length Lb of the first portion 222_1 on the extension line of the boundary between the second portion 222_2 of the charge trapping film 222 and the cover insulating layer 221. In addition, the length Lc of the boundary between the first portion 222_1 and the tunnel insulating layer 223 is longer than the above-mentioned length Lb. One end of the length Lc is located at the boundary between the insulating film 22 and the block insulating layer 21a in the Z direction, and the other end is located at the boundary between the insulating film 22 adjacent thereto and the block insulating layer 21a. In this manner, the side surface of the first portion 222_1 in the Z direction has a recess, and a part of the cover insulating layer 221 fits into the recess.

[0059] This partially widens the distance between adjacent CTs, which has the effect of reducing the parasitic capacitance generated between adjacent charge storage layers 222b.

[0060] Other configurations of the sixth embodiment may be the same as those of the first embodiment. Therefore, the sixth embodiment can obtain the same effects as those of the first embodiment. Moreover, the sixth embodiment may be combined with any of the second to fifth embodiments. As a result, the sixth embodiment can obtain the effects of any of the second to fifth embodiments.

[0061] Seventh embodiment 12 is a schematic cross-sectional view illustrating a memory cell array according to the seventh embodiment. In the seventh embodiment, the cover insulating layer 221 is composed of a laminated film of a plurality of insulating layers 221a and 221b. The insulating layers 221a and 221b may be made of different materials. For example, the insulating layer 221a may be a silicon oxide film containing silicon and oxygen, a hafnium oxide film containing hafnium and oxygen, or a zirconium oxide film containing zirconium and oxygen. The insulating layer 221b may be an aluminum oxide film containing aluminum and oxygen, or a hafnium oxide film containing hafnium and oxygen.

[0062] Other configurations of the seventh embodiment may be the same as those of the first embodiment. Therefore, the seventh embodiment can obtain the same effects as those of the first embodiment. Furthermore, the seventh embodiment may be combined with any of the second to sixth embodiments. As a result, the seventh embodiment can obtain the effects of any of the second to sixth embodiments.

[0063] Eighth embodiment FIG. 13 is a schematic cross-sectional view illustrating a staircase portion 2s of a memory cell array according to the eighth embodiment. The staircase portion 2s of the eighth embodiment corresponds to the staircase portion 2s of the memory cell array of the second embodiment. In the staircase portion 2s, a conductive film 21 and an insulating film 22 are formed in a staircase shape. At each step surface (contact region of the contact CCw) STP of the staircase portion 2s, the insulating film 22 covers the conductive film 21. The insulating film 22a of the insulating film 22 is provided in the center of the insulating film 22 in the Z direction. The insulating films 22b are provided on both sides of the insulating film 22a in the Z direction so as to sandwich the insulating film 22a therebetween. The materials of the insulating films 22a and 22b may be the same as those in FIG. 7.

[0064] In the stepped portion 2s, the multiple contacts CCw penetrate the multiple insulating films 22 in the contact regions exposed from the stack 20, and are connected to the multiple conductive films 21 located underneath the insulating films 22, respectively.

[0065] The insulating film 22b includes insulating films 22b_1 and 22b_2 sandwiching the insulating film 22a from both sides in the Z direction. The insulating film 22b_1 is provided between the conductive film 21 and the insulating film 22a. The insulating film 22b_2 is provided on the insulating film 22a and between the insulating film 22a and the interlayer insulating layer 25. The insulating film 22b_2 is etched when the step portion 2s is formed, and is therefore thinner than the insulating film 22b_1. That is, the insulating film 22b_1 is thicker than the insulating film 22b_2.

[0066] Next, a manufacturing method for the above embodiment will be described.

[0067] 14 to 20 are cross-sectional views showing an example of a method for manufacturing the semiconductor memory device according to the first embodiment.

[0068] First, as shown in FIG. 14, sacrificial films 21s and insulating films 22 are alternately laminated in the Z direction on a semiconductor substrate 10 by using, for example, a chemical vapor deposition (CVD) method. This forms a laminate 20 laminated in the Z direction. The sacrificial films 21s are, for example, insulating films such as silicon nitride films containing silicon and nitrogen. The sacrificial films 21s are replaced with the material of the conductive films 21 in a later process. The insulating films 22 become interlayer insulating layers between the conductive films 21. The insulating films 22 are laminated films in which an insulating film 22a is sandwiched between two insulating films 22b. The insulating films 22a are, for example, silicon oxide films containing silicon and oxygen. The insulating films 22b are, for example, SiOC films containing silicon, oxygen, and carbon. When the sacrificial films 21s and the insulating films 22 are alternately laminated, the sacrificial film 21s and the insulating films 22a and 22b are deposited in the following order: 22b, 22a, 22b, 21s, 22b, 22a, 22b, 21s . . .

[0069] 15, for example, a lithography technique and a RIE (Reactive Ion Etching) method are used to form a memory hole MH extending along the Z direction in the stacked body 20. The memory hole MH penetrates the stacked body 20 that constitutes the insulating film 22 and the sacrificial film 21s.

[0070] Next, as shown in FIG. 16, a cover insulating layer 221, a charge trapping film 222a, a tunnel insulating layer 223, and a semiconductor body 210 are deposited on the inner wall of the memory hole MH by using an ALD (Atomic Layer Deposition) method or a CVD method. A core layer 230 is embedded inside the semiconductor body 210 in the memory hole MH. The charge trapping film 222a is an insulating film such as a silicon nitride film containing silicon and nitrogen, and functions as a seed for the charge trapping film 222b to be selectively grown later. The cover insulating layer 221 and the tunnel insulating layer 223 are insulating layers such as a silicon oxide film containing silicon and oxygen. The tunnel insulating layer 223 may be a silicon oxynitride layer containing silicon, oxygen, and nitrogen. The semiconductor body 210 is a semiconductor layer containing a semiconductor such as polysilicon.

[0071] Next, the process of replacing the sacrificial film 21s begins. As shown in Fig. 17, the sacrificial film 21s is selectively etched and removed using a solution or gas containing phosphoric acid. The removal of the sacrificial film 21s is performed through a slit ST (see Fig. 2) formed in the laminate 20. As a result, the cover insulating layer 221 is exposed in the space 21h after the removal of the sacrificial film 21s.

[0072] 18, the cover insulating layer 221 is isotropically etched using a solution or gas containing hydrofluoric acid, thereby exposing the charge trapping film 222a to the space 21h.

[0073] 19, the charge trapping film 222b is grown on the surface of the charge trapping film 222a using the charge trapping film 222a exposed in the space 21h as a seed. As a result, the charge trapping film 222 becomes thicker than the charge trapping film 222a between the cover insulating layer 221 and the tunnel insulating layer 223 in the space 21h, which is the formation region of the conductive film 21.

[0074] Next, as shown in FIG. 20, a block insulating layer 224 is formed on the charge trapping film 222b.

[0075] Next, using the ALD method or the CVD method, a block insulating layer 21a (e.g., an insulating layer such as an aluminum oxide film containing aluminum and oxygen) and a barrier film 21b (e.g., a laminated film of titanium nitride and titanium, or a single layer film) are deposited on the inner wall of the space 21h. Furthermore, a conductive film 21 (e.g., tungsten) is embedded inside the barrier film 21b. By such a replacement process, the sacrificial film 21s is replaced with the conductive film 21. As a result, the structure shown in FIG. 7 is obtained. The slit ST is embedded with a silicon oxide film, or with a silicon oxide film and a metal material.

[0076] 1 are formed, and the array chip 2 is completed. A CMOS chip 3 is formed separately from the array chip 2. The array chip 2 and the CMOS chip 3 are bonded together at a bonding surface B1. Furthermore, a metal layer 40, a bonding pad 50, and the like are formed, and the semiconductor memory device 1 is completed.

[0077] The inner wall surface during the formation of the memory hole MH is the boundary between the cover insulating layer 221 and the insulating film 22. Therefore, the diameter of the memory hole MH may be said to be the diameter of the boundary between the cover insulating layer 221 and the insulating film 22. In contrast, the conductive film 21, the barrier film 21b, and the block insulating layer 21a formed in the space 21h protrude toward the center Cmh of the memory hole MH from the boundary between the cover insulating layer 221 and the insulating film 22, as shown in FIG. 6. In this case, as shown in FIG. 20, the space 21h can be kept large in the replacement process, and the material of the conductive film 21 can be easily filled into the space 21h. Therefore, the interval between adjacent memory holes MH can be narrowed. As a result, the cell size of the memory cell array 2m can be reduced.

[0078] In the semiconductor memory device according to the third embodiment, the insulating film 22 may be entirely made of the insulating film 22b (for example, a SiOC film) in the process described with reference to Fig. 14. The other processes of the third embodiment may be the same as those of the first embodiment.

[0079] In the semiconductor memory device according to the fourth embodiment, the insulating film 22 may be entirely made of the insulating film 22b (e.g., a SiOC film) in the process described with reference to Fig. 14. Furthermore, a part of the insulating film 22b may be oxidized. The other processes of the fourth embodiment may be the same as those of the first embodiment.

[0080] In the semiconductor memory device according to the fifth embodiment, the charge trapping film 222a (seed of the charge trapping film 222b) is omitted and a seed insulating film 223a is formed in the process described with reference to Fig. 16. In this case, there is no seed for the charge trapping film 222b in Fig. 18 and Fig. 19, but instead, the seed insulating film 223a in Fig. 10 may be provided. The other processes of the fifth embodiment may be the same as those of the first embodiment.

[0081] In the semiconductor memory device according to the sixth embodiment, in the process described with reference to FIG. 18, the cover insulating layer 221 on the charge trapping film 222a in the space 21h is not completely removed, but a part of it is left. FIG. 21 is a cross-sectional view showing an example of a manufacturing method of the semiconductor memory device according to the sixth embodiment. In etching the cover insulating layer 221, as shown in FIG. 21, the cover insulating layer 221 is removed first in the center of the space 21h in the Z direction. The etching is stopped in a state where the cover insulating layer 221 remains at the end of the space 21h in the Z direction. Thereafter, the structure shown in FIG. 11 is obtained by going through the process from FIG. 19 onwards. The other processes of the sixth embodiment may be the same as those of the first embodiment.

[0082] In the semiconductor memory device according to the seventh embodiment, the cover insulating layer 221 may be a laminated film of a plurality of insulating layers 221a, 221b made of different materials in the process described with reference to Fig. 16. The other processes of the seventh embodiment may be the same as those of the first embodiment.

[0083] Ninth embodiment FIG. 22 is a schematic cross-sectional view illustrating a memory cell array according to a ninth embodiment. In the ninth embodiment, the cover insulating layer 221 is composed of a laminated film of a plurality of insulating layers 221a, 221b, and 221c. The insulating layer 221b is sandwiched between the insulating layer 221a and the insulating layer 221c, and is made of a different material from the insulating layers 221a and 221c. For example, the insulating layer 221b is made of Al2O3 or HfO. For example, the insulating layers 221a and 221c are made of SiO2, HfO, ZrO, or the like. For example, the charge trapping film 222 is made of a silicon nitride film containing silicon and nitrogen.

[0084] The insulating layers 221b and 221c are shorter in length in the Z direction than the insulating layer 221a. Both side surfaces in the Z direction of the insulating layer 221a are in contact with the block insulating layer 224. On the other hand, both side surfaces in the Z direction of the insulating layers 221b and 221c are in contact with the charge trapping film 222b (first portion 222_1).

[0085] Furthermore, the length (thickness) in the Z direction of the conductive film 21, the barrier film 21b, and the block insulating layer 21a is equal to or shorter than the length in the Z direction of the charge trapping film 222b, which allows the charge trapping film 222 to store more charges.

[0086] Between the charge trapping films 222b adjacent in the Z direction, an insulating layer 221b having a higher dielectric constant than the charge trapping films 222b is provided.

[0087] Other configurations of the ninth embodiment may be the same as those of the first embodiment. Therefore, the ninth embodiment can obtain the same effects as those of the first embodiment. Furthermore, the ninth embodiment may be combined with any of the second to sixth embodiments. As a result, the ninth embodiment can obtain the effects of any of the second to sixth embodiments.

[0088] Tenth embodiment 23 is a schematic cross-sectional view illustrating a memory cell array according to the tenth embodiment. In the tenth embodiment, the cover insulating layer 221 is composed of a laminated film of a plurality of insulating layers 221a and 221b. The insulating layer 221b is sandwiched between the insulating layer 221a and the charge trapping film 222a, and is made of a material different from that of the insulating layer 221a. The insulating layer 221b is made of a material having a higher dielectric constant than the insulating layer 221a and the charge trapping film 222. For example, the materials of the insulating layers 221a and 221b may be the same as those of the ninth embodiment.

[0089] The insulating layer 221b is shorter in length in the Z direction than the insulating layer 221a. Both side surfaces in the Z direction of the insulating layer 221a are in contact with the block insulating layer 224. Both side surfaces in the Z direction of the insulating layer 221b are in contact with the charge trapping film 222b.

[0090] Between the charge trapping films 222b adjacent in the Z direction, an insulating layer 221b having a higher dielectric constant than the charge trapping films 222b is provided.

[0091] Other configurations of the tenth embodiment may be the same as those of the first embodiment. Therefore, the tenth embodiment can obtain the same effects as the first embodiment. Furthermore, the tenth embodiment may be combined with any of the second to sixth embodiments. As a result, the tenth embodiment can obtain the effects of any of the second to sixth embodiments.

[0092] Next, a manufacturing method of the ninth embodiment will be described.

[0093] 24 to 28 are cross-sectional views showing an example of a method for manufacturing the semiconductor memory device according to the ninth embodiment.

[0094] First, the steps described with reference to FIGS. 14 and 15 are performed.

[0095] 24, a cover insulating layer 221 is deposited on the inner wall of the memory hole MH by ALD or CVD. At this time, the cover insulating layer 221 is deposited on the inner wall of the memory hole MH in the order of the insulating layers 221a, 221b, and 221c.

[0096] Next, the charge trapping film 222a and the like are deposited on the inner wall of the memory hole MH in the same manner as in the first embodiment.

[0097] Next, the process of replacing the sacrificial film 21s begins. As shown in Fig. 25, the sacrificial film 21s is selectively etched and removed using a solution or gas containing phosphoric acid. The removal of the sacrificial film 21s is performed through a slit ST (see Fig. 2) formed in the laminate 20. As a result, the insulating layer 221a is exposed in the space 21h after the removal of the sacrificial film 21s.

[0098] Next, as shown in FIG. 26, the insulating layer 221a is isotropically etched. As a result, the insulating layer 221a exposed in the space 21h is selectively removed. At this time, the insulating layer 221b functions as an etching stopper. Note that the processing performed in the space 21h is performed through the slit ST.

[0099] Next, as shown in FIG. 27, the insulating layer 221b is further isotropically etched. This removes the insulating layer 221b exposed in the space 21h. At this time, the insulating layer 221c functions as an etching stopper. The insulating layer 221b is recessed in the Z direction, and its length in the Z direction is shorter than that of the insulating layer 221a.

[0100] 28, the insulating layer 221c is further isotropically etched. As a result, the insulating layer 221c exposed in the space 21h is removed. The insulating layer 221c is etched using the insulating layer 221b as a mask, and becomes shorter in length in the Z direction than the insulating layer 221a. As a result, the cover insulating layer 221 exposed in the space 21h is removed, and the charge trapping film 222a is exposed in the space 21h.

[0101] 19 and 20, the semiconductor memory device 1 shown in Fig. 22 is completed. When the charge trapping film 222b is selectively grown on the charge trapping film 222a used as a seed, the side surfaces of the insulating layers 221b and 221c come into contact with the charge trapping film 222b.

[0102] If the insulating layer 221c of the cover insulating layer 221 is omitted, the semiconductor memory device 1 shown in FIG. 23 can be formed.

[0103] According to the ninth embodiment, the cover insulating layer 221 is composed of a laminated film of insulating layers 221a to 221c. The insulating layer 221b functions as an etching stopper in the etching process of the insulating layer 221a. The insulating layer 221c functions as an etching stopper in the etching process of the insulating layer 221b.

[0104] Eleventh embodiment 29 is a schematic cross-sectional view illustrating a memory cell array according to an eleventh embodiment. In the eleventh embodiment, in the structure of FIG. 22, the insulating film 22 is composed of a stacked film of insulating films 22a and 22b. The insulating film 22a is provided in the center of the insulating film 22 and is composed of an insulating material such as a silicon oxide film. The insulating films 22b are provided on both sides of the insulating film 22a in the Z direction so as to sandwich the insulating film 22a. For example, an insulating material such as SiOC, which is a silicon oxide film containing carbon, is used for the insulating film 22b.

[0105] Other configurations of the eleventh embodiment may be the same as those of the ninth embodiment, and therefore the eleventh embodiment can achieve the same effects as the ninth embodiment.

[0106] (Example 1 of the structure of the lower end of the columnar body) Next, the configuration of the bottom end of the columnar body CL will be described.

[0107] 30 is a cross-sectional view showing a configuration example of the bottom end CLb of the pillar CL according to the first embodiment. The configuration of the memory cell MC may be the same as that of the memory cell MC of the first embodiment. The bottom end CLb of the pillar CL reaches into the source layer BSL. The semiconductor body 210 of the pillar CL is electrically connected to the source layer BSL at the bottom end CLb of the pillar CL. The source layer BSL is, for example, doped polysilicon, and is directly connected to the semiconductor body 210.

[0108] In configuration example 1, the cover insulating layer 221, the charge trapping film 222a, and the tunnel insulating layer 223 are laterally removed through the slit ST to expose the semiconductor body 210. Then, a conductive material such as doped polysilicon is embedded through the slit ST to form the source layer BSL.

[0109] As described above, the radius R21a_224 of the memory hole MH or the pillar CL at the boundary B21a_224 in FIG. 6 is equal to or smaller than the radius R22_221 of the memory hole MH or the pillar CL at the boundary B22_221.

[0110] 30, if the radius of the memory hole MH or the pillar CL at the bottom end CLb is Rbsl_221, the radius R21a_224 is equal to or smaller than the radius Rbsl_221. Since the pillar CL tapers closer to the bottom end CLb, at least in the memory cell MC closest to the bottom end CLb, the diameter R21a_224×2 of the pillar CL is equal to or smaller than the diameter Rbsl_221×2 of the periphery of the cover insulating layer 221 at the bottom end CLb.

[0111] When the diameter R21a_224×2 of the columnar body CL in the memory cell MC is small, the space 21h can be kept large in the replacement process, and therefore the interval between adjacent memory holes MH can be narrowed, leading to a reduction in the memory cell array 2m.

[0112] The configuration in FIG. 30 can be applied to any of the second to tenth embodiments.

[0113] (Example 2 of the structure of the lower end of the columnar body) 31 and 32 are cross-sectional views showing other configuration examples of the bottom end CLb of the columnar body CL. The configuration of the memory cell MC may be the same as that of the memory cell MC of the first embodiment. In configuration example 2, the source layer BLS is made of a conductive metal material such as tungsten. The barrier metal BM is made of a conductive metal compound such as a laminated film of titanium nitride and titanium. The barrier metal BM may be referred to as the source layer BSL, integrally with the source layer BSL.

[0114] The lower end of the columnar body CL is removed, and a part of the core layer 230 is removed from the lower end. The source layer BSL and the barrier metal BM intrude into the region of the core layer 230 in the memory hole MH. This allows the semiconductor body 210 to be electrically connected to the source layer BSL.

[0115] In configuration example 2, the cover insulating layer 221, the charge trapping film 222a, the tunnel insulating layer 223, and the semiconductor body 210 are removed from the lower end of the columnar body CL, and a part of the core layer 230 inside the semiconductor body 210 is etched. This exposes the semiconductor body 210 inside the memory hole MH. Next, materials of the barrier metal BM and the source layer BSL are embedded inside the memory hole MH, thereby connecting the semiconductor body 210 to the barrier metal BM and the source layer BSL.

[0116] Also in configuration example 2, the radius R21a_224 of the memory hole MH or the pillar CL at the boundary B21a_224 in FIG. 6 is equal to or smaller than the radius R22_221 of the memory hole MH or the pillar CL at the boundary B22_221.

[0117] 32 is a cross-sectional view showing another example of the configuration of the bottom end CLb of the dummy column CLd. The dummy column CLd as a second column has basically the same configuration as the column CL. However, the semiconductor body 210 is electrically isolated from the source layer BSL thereunder. Therefore, the dummy column CLd is not used for storing data. That is, the bottom end of the dummy column CLd is not etched, unlike the column CL in FIG. 31. The source layer BSL is in contact with the cover insulating layer 221.

[0118] Also in the case of the dummy columnar body CLd, the radius R21a_224 of the memory hole MH or the columnar body CL at the boundary B21a_224 in FIG. 6 is equal to or smaller than the radius R22_221 of the memory hole MH or the columnar body CL at the boundary B22_221.

[0119] 32, if the radius of the memory hole MH or the pillar CL at the bottom end CLb of the dummy pillar CLd is R22_221, the radius R21a_224 is equal to or smaller than the radius R22_221. Since the pillar CL is tapered closer to the bottom end CLb, at least in the memory cell MC closest to the bottom end CLb, the diameter R21a_224×2 of the pillar CL is equal to or smaller than the diameter R22_221×2 at the bottom end CLb.

[0120] Furthermore, when the radius of the conductor (i.e., the source layer BSL and the barrier metal BM) protruding in the -Z direction directly below the dummy column CLd is Rbsl_22 and the radius of the memory hole MH is equal to Rbsl_22, in the memory cell MC closest to the bottom end CLb, the diameter R21a_224×2 of the column CL is equal to or smaller than the diameter Rbsl_22×2.

[0121] When the diameter R21a_224×2 of the columnar body CL in the memory cell MC is small, the space 21h can be kept large in the replacement process, and therefore the interval between adjacent memory holes MH can be narrowed, leading to a reduction in the memory cell array 2m.

[0122] The configuration in FIG. 32 can be applied to any of the second to tenth embodiments.

[0123] When Configuration Example 1 and Configuration Example 2 of the lower end of the pillar are applied to the ninth embodiment, the lower end of the pillar has the configuration shown in FIGS.

[0124] (Example 3 of the structure of the lower end of the columnar body) 33 is a cross-sectional view showing a configuration example in which the configuration example 1 of the lower end of the columnar body is applied to the ninth embodiment. In this case, the cover insulating layer 221 is a laminated film of insulating layers 221a to 221c. The other configurations of the configuration example 3 may be the same as those of the configuration example 1.

[0125] (Example 4 of the structure of the lower end of the columnar body) 34 and 35 are cross-sectional views showing a configuration example in which configuration example 2 of the lower end of a column is applied to the ninth embodiment. Fig. 34 shows the configuration of a column CL, and Fig. 35 shows the configuration of a dummy column CLd. In this case, the cover insulating layer 221 is a laminated film of insulating layers 221a to 221c. The other configurations of configuration example 4 may be the same as those of configuration example 2.

[0126] Although not shown, configuration example 1 and configuration example 2 can also be applied to embodiment 10. In this case, the cover insulating layer 221 is a laminated film of insulating layers 221a and 221b.

[0127] (Additional Note) (17) a laminate including a plurality of first conductive films and a plurality of first insulating films alternately laminated in a first direction; a plurality of first columnar bodies including a first semiconductor portion extending in the first direction within the stack, a first insulator portion provided between the first semiconductor portion and the stack, a ninth insulator portion provided between the first insulator portion and the stack, second and third insulator portions provided between the ninth insulator portion and the plurality of first conductive films, and a fourth insulator portion provided between the ninth insulator portion and the plurality of first insulating films; a fifth insulator portion provided between the plurality of first insulating films and the plurality of first conductive films and between the third insulator portion and the plurality of first conductive films, the fifth insulator portion having a higher dielectric constant than the first insulating films and the third insulator portion; the second insulator portion is separated by the fourth insulator portion in the first direction, a diameter of the first columns at a boundary between the fifth insulator portion and the third insulator portion closest to the bottom ends of the first columns is equal to or smaller than a diameter of an outer periphery of the fourth insulator portion at the bottom ends of the first columns.

[0128] (18) a second pillar having the same configuration as the first pillar, the first semiconductor portion being not electrically connected to a source layer located under the stack, the plurality of first insulating films are a stacked film of a second insulating film and a third insulating film, or are composed of a third insulating film; 17. The semiconductor memory device of claim 15, wherein a diameter of the second columnar body at a boundary between the fifth insulator portion and the third insulator portion that is closest to a bottom end of the second columnar body is equal to or smaller than a diameter of an outer periphery of a conductor protruding in the first direction immediately below the second columnar body in the source layer.

[0129] (19) the third insulating film is provided on both sides of the second insulating film in the first direction so as to sandwich the second insulating film therebetween, or the third insulating film is provided at a center of the second insulating film in the first direction so as to be sandwiched between the second insulating films; 17. A semiconductor memory device as described in claim 17, wherein, in a cross section perpendicular to the first direction, a diameter of a boundary between the fifth insulator portion and the third insulator portion is equal to or smaller than a diameter of a boundary between the first insulating film and the fourth insulator portion.

[0130] (20) a plurality of contacts penetrating the plurality of first insulating films in a contact region exposed from the stack and connected to the plurality of first conductive films respectively covered by the plurality of first insulating films; the third insulating film is provided on both sides of the second insulating film in the first direction so as to sandwich the second insulating film therebetween, in the contact region, the third insulating film includes a fourth insulating film between the plurality of first conductive films and the second insulating film, and a fifth insulating film on the second insulating film; The fourth insulating film is thicker than the fifth insulating film, the second insulator portion includes a first portion provided between the first insulator portion and the first conductive film, and a second portion provided between the first insulator portion and the first insulating film, the second portion having a smaller thickness in a second direction perpendicular to the first direction than the first portion; A semiconductor memory device as described in (17), wherein, in a cross section in the first direction, a first length in the first direction of a boundary between the first portion and the third insulating portion is longer than a second length of the first portion on an extension line of a boundary between the second portion and the fourth insulating portion.

[0131] (twenty one) a plurality of contacts penetrating the plurality of first insulating films in a contact region exposed from the stack and connected to the plurality of first conductive films respectively covered by the plurality of first insulating films; the third insulating film is provided at a center of the second insulating film so as to be sandwiched between the second insulating films in the first direction, the second insulator portion includes a first portion provided between the first insulator portion and the first conductive film, and a second portion provided between the first insulator portion and the first insulating film, the second portion having a smaller thickness in a second direction perpendicular to the first direction than the first portion; A semiconductor memory device as described in (17), wherein, in a cross section in the first direction, a length in the first direction of a boundary between the first portion and the third insulating portion and a third length of the boundary of the first portion in the first direction between the first portion and the first insulating portion are longer than a second length of the first portion on an extension line of the boundary between the second portion and the fourth insulating portion.

[0132] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope of the invention and its equivalents described in the claims, as well as in the scope and spirit of the invention. [Explanation of symbols]

[0133] 1. Semiconductor memory device 2. Array chip 3. CMOS chip 20 Laminate 21 Conductive film 22 Insulating film CL columnar body ST(LI) Slit BSL Source Layer CCw Contact 210 Semiconductor Body 220 Memory Film 230 Core Layer 224,21a Block insulation layer 221 Cover insulation layer 222 Charge trapping film 223 Tunnel Insulation Layer 21b Barrier film

Claims

1. a stack including a plurality of first conductive films and a plurality of first insulating films alternately stacked in a first direction; a first semiconductor portion extending in the first direction within the stack, a first insulator portion provided between the first semiconductor portion and the stack, a second insulator portion provided between the first insulator portion and the stack, a third insulator portion provided between the second insulator portion and the plurality of first conductive films, and a fourth insulator portion provided between the second insulator portion and the plurality of first insulating films; the second insulator portion includes a first portion provided between the first insulator portion and the first conductive film, and a second portion provided between the first insulator portion and the first insulating film, the second portion having a smaller thickness in a second direction perpendicular to the first direction than the first portion; The semiconductor memory device, wherein the plurality of first insulating films are a laminated film of a second insulating film and a third insulating film, or are composed of the third insulating film.

2. 2. The semiconductor memory device according to claim 1, wherein said third insulating film is an insulating film containing carbon.

3. 3. The semiconductor memory device according to claim 2, wherein said third insulating film is an insulating film containing SiOC.

4. a fifth insulator portion provided between the third insulator portion and the first conductive films and having a dielectric constant higher than that of the third insulator portion; 2. The semiconductor memory device of claim 1, wherein a diameter of the first columns at a boundary between the third insulator portion and the fifth insulator portion closest to the bottom ends of the first columns is equal to or smaller than a diameter of an outer periphery of the fourth insulator portion at the bottom ends of the first columns.

5. a second pillar having the same configuration as the first pillar, the first semiconductor portion being electrically isolated from a source layer located below the stack; 2. The semiconductor memory device of claim 1, wherein a diameter of the second pillar at a boundary between the fifth insulator portion closest to a bottom end of the second pillar and the third insulator portion is equal to or smaller than a diameter of an outer periphery of a conductor protruding in the first direction directly below the second pillar in the source layer.

6. a fifth insulator portion provided between the third insulator portion and the first conductive films and having a dielectric constant higher than that of the third insulator portion; 2. The semiconductor memory device of claim 1, wherein in a cross section perpendicular to the first direction, a diameter of the first columnar body at a boundary between the third insulator portion and the fifth insulator portion is equal to or smaller than a diameter of the first columnar body at a boundary between the plurality of first insulating films and the fourth insulator portion.

7. 2. The semiconductor memory device according to claim 1, wherein the third insulating film is provided on both sides of the second insulating film in the first direction so as to sandwich the second insulating film, or the third insulating film is provided at the center of the second insulating film in the first direction so as to be sandwiched by the second insulating films.

8. a plurality of contacts each penetrating the plurality of first insulating films in a contact region exposed from the stack and connected to the plurality of first conductive films respectively covered by the plurality of first insulating films; in the contact region, the third insulating film includes a fourth insulating film between the plurality of first conductive films and the second insulating film, and a fifth insulating film on the second insulating film; 2. The semiconductor memory device according to claim 1, wherein said fourth insulating film is thicker than said fifth insulating film.

9. a stack including a plurality of first conductive films and a plurality of first insulating films alternately stacked in a first direction; a first semiconductor portion extending in the first direction within the stack, a first insulator portion provided between the first semiconductor portion and the stack, a second insulator portion provided between the first insulator portion and the stack, a third insulator portion provided between the second insulator portion and the plurality of first conductive films, and a fourth insulator portion provided between the second insulator portion and the plurality of first insulating films; the second insulator portion includes a first portion provided between the first insulator portion and the first conductive film, and a second portion provided between the first insulator portion and the first insulating film, the second portion having a smaller thickness in a second direction perpendicular to the first direction than the first portion; the plurality of first insulating films are a stacked film of a second insulating film and a third insulating film, or are composed of the third insulating film; A semiconductor memory device, wherein, in a cross section in the first direction, a first length in the first direction of a boundary between the first portion and the third insulating portion is longer than a second length of the first portion on an extension line of the boundary between the second portion and the fourth insulating portion.

10. 10. The semiconductor memory device according to claim 9, wherein in a cross section in the first direction, a third length in the first direction of the first portion at a boundary between the first portion and the first insulating body portion is longer than the second length.

11. a stack including a plurality of first conductive films and a plurality of first insulating films alternately stacked in a first direction; a first semiconductor portion extending in the first direction within the stack, a first insulator portion provided between the first semiconductor portion and the stack, a second insulator portion provided between the first insulator portion and the stack, a third insulator portion provided between the second insulator portion and the plurality of first conductive films, and a fourth insulator portion provided between the second insulator portion and the plurality of first insulating films; the second insulator portion includes a first portion provided between the first insulator portion and the first conductive film, and a second portion provided between the first insulator portion and the first insulating film, the second portion having a smaller thickness in a second direction perpendicular to the first direction than the first portion; the plurality of first insulating films are a stacked film of a second insulating film and a third insulating film, or are composed of the third insulating film; The fourth insulator portion includes a sixth insulator portion and a seventh insulator portion stacked in the second direction and made of different materials.

12. a fifth insulator portion provided between the third insulator portion and the first conductive films and having a dielectric constant higher than that of the third insulator portion; 12. The semiconductor memory device of claim 11, wherein a diameter of the first columns at a boundary between the third insulator portion and the fifth insulator portion closest to the bottom ends of the first columns is equal to or smaller than a diameter of an outer periphery of the fourth insulator portion at the bottom ends of the first columns.

13. a fifth insulator portion provided between the third insulator portion and the first conductive films and having a dielectric constant higher than that of the third insulator portion; a second pillar having the same configuration as the first pillar, the first semiconductor portion being not electrically connected to a source layer located under the stack, 12. The semiconductor memory device of claim 11, wherein at a position of the first conductive film closest to a bottom end of the second columnar body, a diameter of the second columnar body at a boundary between the fifth insulator portion and the third insulator portion is equal to or smaller than a diameter of an outer periphery of the fourth insulator portion at the bottom end of the second columnar body.

14. a fifth insulator portion provided between the third insulator portion and the first conductive films and having a dielectric constant higher than that of the third insulator portion; 12. The semiconductor memory device according to claim 11, wherein in a cross section perpendicular to the first direction, a diameter of a boundary between the fifth insulator portion and the third insulator portion is equal to or smaller than a diameter of a boundary between the first insulating film and the fourth insulator portion.

15. the fourth insulator portion includes sixth and seventh insulator portions stacked in the second direction, The semiconductor memory device according to claim 11 , wherein the sixth insulator portion and the seventh insulator portion are made of different materials.

16. the fourth insulator portion includes sixth to eighth insulator portions stacked in the second direction, 12. The semiconductor memory device according to claim 11, wherein the sixth and eighth insulator portions and the seventh insulator portion are made of different materials.

17. a fifth insulator portion provided between the first insulating films and the first conductive films and between the third insulator portion and the first conductive films, the fifth insulator portion having a higher dielectric constant than the first insulating films and the third insulator portion; 12 . The semiconductor memory device according to claim 11 , wherein a length in the first direction of a laminate structure of said first conductive film and said fifth insulating body portion is equal to or shorter than a length in the first direction of said first portion.

18. 12. The semiconductor memory device according to claim 11, wherein the seventh insulator portion is in contact with the first portion in the first direction.

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