Semiconductor memory device and manufacturing method thereof

Abstract

To suppress deterioration of pressure resistance performance while reducing deflection and inclination of layers.SOLUTION: A semiconductor memory device according to an embodiment includes a first laminate in which a first conductive layer and a first insulating layer are alternately stacked one by one, and the first conductive layer includes a first staircase portion processed into a staircase shape, a second laminate that is provided above a first interlayer insulating film covering the first staircase portion and the first laminate and in which a second conductive layer and a second insulating layer are alternately stacked one by one, and the second conductive layer includes a second staircase portion processed into the staircase shape, a second interlayer insulating film covering the second staircase portion, first and second plate-shaped portions penetrating the first and second laminates, respectively, in a stacking direction, and first and second bridging portions disposed at the upper ends of the first and second plate-shaped portions, respectively, and connecting the first and second interlayer insulating films on both sides. The lower ends of the first and second bridging portions are located above the first and second conductive layers in the uppermost layers of the first and second laminates, respectively.SELECTED DRAWING: Figure 2B

Description

[Technical field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor memory device and a method for manufacturing a semiconductor memory device. [Background technology]

[0002] For example, some semiconductor memory devices, such as three-dimensional nonvolatile memories, have a laminate in which multiple conductive layers and multiple insulating layers are alternately stacked one by one. Such a laminate is formed by forming grooves in an insulating layer and a sacrificial layer, each of which is made of a different material, and allowing a treatment liquid to permeate through the grooves to replace the sacrificial layer with a conductive layer.

[0003] However, in the process of forming such a semiconductor memory device, bending and tilting of layers may occur due to stresses generated in various materials. In order to reduce such bending and tilting, a bridge capable of supporting the materials on both sides may be formed on the upper part of the groove. As the number of layers in the stack increases, the stress generated in the layers increases, so there is a demand for a thicker bridge.

[0004] However, if the bridge portion becomes thick to the depth where the conductive layer is formed, the conductive layer may not be formed properly when the sacrificial layer is replaced with the conductive layer, which may result in a decrease in the distance between the metal layer and the conductive layer formed in the groove, resulting in a decrease in the voltage resistance. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2022-146608 A Summary of the Invention [Problem to be solved by the invention]

[0006] One embodiment provides a semiconductor memory device capable of suppressing deterioration in withstand voltage performance while reducing warping and tilting of layers, and a method for manufacturing the semiconductor memory device. [Means for solving the problem]

[0007] The semiconductor memory device of the embodiment includes a first stacked body in which a plurality of first conductive layers and a plurality of first insulating layers are alternately stacked one by one, the plurality of first conductive layers including a first staircase portion processed into a staircase shape extending in a first direction intersecting a stacking direction of the first conductive layers, a first interlayer insulating film covering the first staircase portion, and a second stacked body provided above the first stacked body in which a plurality of second conductive layers and a plurality of second insulating layers are alternately stacked one by one, the plurality of second conductive layers including a second staircase portion processed into a staircase shape continuing from the first staircase portion in the first direction, a second interlayer insulating film covering the second staircase portion, and a second stacked body provided above the first stacked body in which a plurality of second conductive layers and a plurality of second insulating layers are alternately stacked one by one, the plurality of second conductive layers including a second staircase portion processed into a staircase shape continuing from the first staircase portion in the first direction, a first plate-shaped portion extending along the first direction and penetrating the first laminate in the stacking direction, a second plate-shaped portion extending along the first direction and penetrating the second laminate in the stacking direction to connect to an upper end of the first plate-shaped portion, a first bridging portion arranged at the upper end of the first plate-shaped portion and connecting the first interlayer insulating film on both sides of the first plate-shaped portion, and a second bridging portion arranged at the upper end of the second plate-shaped portion and connecting the second interlayer insulating film on both sides of the second plate-shaped portion, wherein the lower ends of the first and second bridging portions are located above the first and second conductive layers which are the uppermost layers of the first and second laminates, respectively. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a partial top view showing a schematic configuration of a semiconductor memory device according to a first embodiment. [Figure 2A] FIG. 2 is a cross-sectional view showing a detailed configuration of a cell array region according to the first embodiment. [Figure 2B] FIG. 4 is a cross-sectional view showing a detailed configuration of a staircase region according to the first embodiment. [Diagram 3] FIG. 3 is a diagram for explaining the positional relationship between a first cross-linking portion and a second cross-linking portion according to the first embodiment. [Figure 4] 2A to 2C are diagrams illustrating a part of a procedure of a method for forming a semiconductor memory device according to the first embodiment. [Diagram 5]2A to 2C are diagrams illustrating a part of a procedure of a manufacturing method of a semiconductor memory device according to the first embodiment. [Figure 6] 2A to 2C are diagrams illustrating a part of a procedure of a manufacturing method of a semiconductor memory device according to the first embodiment. [Figure 7] 2A to 2C are diagrams illustrating a part of a procedure of a manufacturing method of a semiconductor memory device according to the first embodiment. [Figure 8] 2A to 2C are diagrams illustrating a part of a procedure of a manufacturing method of a semiconductor memory device according to the first embodiment. [Figure 9] 2A to 2C are diagrams illustrating a part of a procedure of a manufacturing method of a semiconductor memory device according to the first embodiment. [Figure 10] 2A to 2C are diagrams illustrating a part of a procedure of a manufacturing method of a semiconductor memory device according to the first embodiment. [Figure 11] 1 is a cross-sectional view showing a detailed configuration of a cell array region of a semiconductor memory device according to a comparative example. [Figure 12] FIG. 11 is a cross-sectional view showing a detailed configuration of a cell array region of a semiconductor memory device according to a modified example of the first embodiment. [Figure 13] 6A to 6C are diagrams illustrating a part of a procedure of a manufacturing method of a semiconductor memory device according to a modified example of the first embodiment. [Figure 14A] FIG. 11 is a partial top view illustrating a configuration example of a semiconductor memory device according to a second embodiment. [Figure 14B] FIG. 11 is a cross-sectional view illustrating a configuration example of a semiconductor memory device according to a second embodiment. [Figure 15] FIG. 11 is a diagram for explaining the positional relationship between a first bridge portion and a second bridge portion according to the second embodiment. [Figure 16] 10A to 10C are diagrams illustrating a part of a procedure of a method for manufacturing a semiconductor memory device according to a second embodiment. [Figure 17] 10A to 10C are diagrams illustrating a part of a procedure of a method for manufacturing a semiconductor memory device according to a second embodiment. [Figure 18] 10A to 10C are diagrams illustrating a part of a procedure of a method for manufacturing a semiconductor memory device according to a second embodiment. [Figure 19] 10A to 10C are diagrams illustrating a part of a procedure of a method for manufacturing a semiconductor memory device according to a second embodiment. [Figure 20]10A to 10C are diagrams illustrating a part of a procedure of a method for manufacturing a semiconductor memory device according to a second embodiment. [Figure 21] FIG. 13 is a diagram showing an example of the arrangement of first bridge portions according to Modification 1 of Embodiment 2. [Figure 22] FIG. 13 is a diagram showing an example of the arrangement of first bridge portions according to Modification 2 of Embodiment 2. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, non-limiting exemplary embodiments of the present invention will be described with reference to the accompanying drawings. In all the accompanying drawings, the same or corresponding members or parts are denoted by the same or corresponding reference numerals, and duplicated descriptions are omitted. In addition, the drawings are not intended to show the relative ratio between members or parts or between the thicknesses of various layers, and therefore specific thicknesses and dimensions may be determined by those skilled in the art in light of the following non-limiting embodiments.

[0010] (Embodiment 1) An example of the configuration of a semiconductor memory device 1 according to the embodiment 1 will be described with reference to Figures 1 to 3. The semiconductor memory device 1 according to the embodiment has a cell array region and a staircase region.

[0011] Fig. 1 is a partial top view showing a schematic configuration of a semiconductor memory device 1 according to embodiment 1. Fig. 1 shows a part of each of a cell array region CA and a staircase region SA of the semiconductor memory device 1. Upper wiring, plugs, etc. are provided above the cell array region CA and the staircase region SA, but are not shown in Fig. 1.

[0012] In this specification, the x-direction and the y-direction are both directions along the direction of the surfaces of the conductive layers described below, and are perpendicular to each other. The direction intersecting the x-direction and the y-direction, i.e., the stacking direction of the conductive layers, is defined as the z-direction. The x-direction is an example of a first direction, and the y-direction is an example of a second direction.

[0013] The cell array region CA has a laminate (described later) in which multiple conductive layers and multiple insulating layers are alternately stacked one by one, and multiple memory pillars MP that penetrate the laminate in the z direction. The memory pillars MP are arranged in a lattice pattern in the xy plane in the figure and extend in the z direction in the figure.

[0014] The staircase region SA has a staircase portion SR. In this embodiment, the staircase portion SR has a predetermined length in the x direction. In the y direction, a plurality of staircase portions SR extending in the x direction are arranged at a predetermined distance from each other.

[0015] In the staircase portion SR, the laminate is processed in a staircase shape so that each of the multiple conductive layers forms a terrace surface (step surface), and a second interlayer insulating film 40 is formed at least above the staircase portion SR. The second interlayer insulating film 40 is, for example, a silicon oxide layer. In addition, in the staircase portion SR, a contact CC is provided that penetrates the second interlayer insulating film 40 and connects to the terrace surface. In this specification, the direction in which the terrace surface of each step of the staircase portion SR faces is defined as the upward direction.

[0016] A plurality of plate-like parts STL are formed in the cell array region CA and the staircase region SA, dividing the cell array region CA and the staircase region SA. Each of the plate-like parts STL crosses the cell array region CA and the staircase region SA in the x direction, extends in the z direction in the figure, and terminates in a source line (described later). Each of the plate-like parts STL has a liner layer LL and a conductive part EC inside the liner layer LL. The liner layer LL is, for example, a silicon oxide layer. The conductive part EC is, for example, a tungsten layer, a tungsten nitride layer, a titanium layer, a titanium nitride layer, a molybdenum layer, or a molybdenum nitride layer, as a conductive material. The plate-like part STL connected to the source line (described later) in the conductive part EC functions as a source line contact. Each of the plate-like parts STL has, at its upper end, a plurality of second bridge parts BT2 intermittently provided in the longitudinal direction (x direction) of the plate-like part STL.

[0017] Next, the details of the cell array region CA and the staircase region SA will be described with reference to Fig. 2A and Fig. 2B. Fig. 2A is a cross-sectional view showing the detailed configuration of the cell array region CA according to the first embodiment. More specifically, Fig. 2A is a yz cross-sectional view taken along the line L1-L1 in Fig. 1. Also, Fig. 2B is a cross-sectional view showing the detailed configuration of the staircase region SA according to the first embodiment. More specifically, Fig. 2B(a) is a yz cross-sectional view taken along the line L2a-L2a in Fig. 1, and Fig. 2B(b) is a yz cross-sectional view taken along the line L2b-L2b in Fig. 1.

[0018] As shown in FIGS. 2A and 2B, the semiconductor memory device 1 has a first stacked body LM1 on the source line SL, and has a second stacked body LM2 above the first stacked body LM1.

[0019] The source line SL is, for example, a conductive polycrystalline silicon layer. The source line SL is disposed on the electrode film EL via an insulating layer 50. A plurality of plugs (not shown) are disposed in the insulating layer 50, and the source line SL and the electrode film EL are kept electrically conductive via the plugs. This allows a source potential to be applied to the source line SL from outside the semiconductor memory device 1 via the electrode film EL and the plugs.

[0020] The first laminate LM1 has a configuration in which a plurality of conductive layers WL1 and a plurality of insulating layers OL1 are alternately stacked one by one, and the second laminate LM2 has a configuration in which a plurality of conductive layers WL2 and a plurality of insulating layers OL2 are alternately stacked one by one. The conductive layers WL1 and WL2 are, for example, a tungsten layer, a tungsten nitride layer, a titanium layer, a titanium nitride layer, a molybdenum layer, a molybdenum nitride layer, or the like. The insulating layers OL1 and OL2 are, for example, a silicon oxide layer or an aluminum oxide layer, or the like. The conductive layer WL1 is an example of a first conductive layer, and the insulating layer OL1 is an example of a first insulating layer. The conductive layer WL2 is an example of a second conductive layer, and the insulating layer OL2 is an example of a second insulating layer.

[0021] 2A and 2B, the number of conductive layers WL1 and WL2 and the number of insulating layers OL1 and OL2 are shown as appropriate for the explanation, but the number of conductive layers WL1 and WL2 is not limited to the illustrated example and may be appropriately determined. For example, 48 conductive layers, 64 conductive layers, or 96 conductive layers may be formed.

[0022] Between the first laminate LM1 and the second laminate LM2, an insulating layer 31, an insulating layer 32, and an insulating layer 33 are formed in this order so as to cover the first laminate LM1. The insulating layers 31 to 33 are configured to include an insulating material such as a silicon oxide layer. Moreover, above the second laminate LM2, an insulating layer 41 and an insulating layer 42 are formed in this order so as to cover the second laminate LM2. The insulating layers 41 to 42 are configured to include an insulating material such as a silicon oxide layer.

[0023] As shown in FIG. 2A, in the cell array region CA, a memory pillar MP and a plate-shaped portion STL are formed.

[0024] The memory pillar MP penetrates the first laminate LM1, the insulating layers 31 to 33, the second laminate LM2, and the insulating layer 41 in the z direction and terminates in the source line SL. The memory pillar MP has a substantially cylindrical shape, and includes a core layer COR, a channel layer CHN, and a memory film MEM formed concentrically from the center to the outside, and a cap layer CAP on the upper part. Here, the core layer COR is, for example, silicon oxide, and the channel layer CHN and the cap layer CAP are, for example, conductive polycrystalline silicon or amorphous silicon. The memory film MEM also includes a tunnel insulating layer, a charge storage layer, and a block insulating layer (not shown) formed in sequence along a direction from the center of the memory pillar MP to the outside. The tunnel insulating layer and the block insulating layer are, for example, a silicon oxide layer, and the charge storage layer is, for example, a silicon nitride layer.

[0025] A memory cell (not shown) is formed in a portion where the conductive layer WL1 and the conductive layer WL2 face the memory film MEM of the memory pillar MP. In this case, the conductive layer WL1 and the conductive layer WL2 function as a word line. However, the portion where the bottom and top conductive layers of the multiple conductive layers WL1 and WL2 face the memory pillar MP may function as a selection transistor. Therefore, for example, the top conductive layer WL2 in the second stack LM2 may function as a drain-side selection gate line SGD.

[0026] A plug PG is provided on the memory pillar MP. The plug PG penetrates the insulating layer 42 and connects to the upper wiring ML. The upper wiring ML is connected to a transistor Tr formed on a substrate SB1 such as a silicon wafer through a via V. The upper wiring ML, the via V, the transistor Tr, and the like are covered with an insulating layer 50 such as silicon oxide, and control the memory cells as a peripheral circuit unit PER. Note that in the explanations from FIG. 2B onwards, for convenience, illustration of a part of the peripheral circuit unit PER may be omitted.

[0027] The plate-shaped portion STL penetrates the first laminate LM1, the second laminate LM2, the insulating layers 31-33, and the insulating layers 41-42 in the z direction and terminates within the source line SL. Specifically, the plate-shaped portion STL has a first plate-shaped portion ST1 that extends along the x direction and penetrates the first laminate LM1 and the insulating layers 31-33 in the z direction, and a second plate-shaped portion ST2 that extends along the x direction and penetrates the second laminate LM2 and the insulating layers 41-42 in the z direction to connect to an upper end portion of the first plate-shaped portion ST1.

[0028] The first plate-shaped member ST1 is provided with, from the inside, a conductive part EC containing a conductive material and a liner layer LL. The second plate-shaped member ST2 is also provided with a conductive part EC and a liner layer LL from the inside. The upper end of the conductive part EC of the second plate-shaped member ST2 is connected to the lower end of the conductive part EC of the first plate-shaped member ST1.

[0029] As shown in FIG. 2B(a), the first bridged portion BT1 and the second bridged portion BT2 are formed on the upper end portions of the first plate-shaped portion ST1 and the second plate-shaped portion ST2 extending in the x direction. In contrast, as shown in FIG. 2B(b), the first bridged portion BT1 and the second bridged portion BT2 are not formed on the other part of the upper end portions of the first plate-shaped portion ST1 and the second plate-shaped portion ST2. This is because the first bridged portion BT1 and the second bridged portion BT2 are each intermittently arranged in the x direction. The specific positional relationship between the first bridged portion BT1 and the second bridged portion BT2 will be described later with reference to FIG. 3.

[0030] The first bridge portion BT1 has an upper structure BTU1 that reaches a predetermined depth from the top surface of the first interlayer insulating film 30, and a lower structure BTB1 that penetrates the first interlayer insulating film 30 from a predetermined depth of the first interlayer insulating film 30 to a predetermined depth of the first plate-shaped portion ST1. The lower structure BTB1 is located above the uppermost conductive layer WL1 in the first stacked body LM1. The width of the lower structure BTB1 in the y direction is approximately equal to the width of the first plate-shaped portion ST1 in the y direction and is narrower than the width of the upper structure BTU1 in the y direction. The first bridge portion BT1 is, for example, a silicon oxide layer.

[0031] The upper structure BTU1 of the first bridge portion BT1 is formed with a joint portion BTO1. The joint portion BTO1 also has, in order from the inside, a conductive portion EC containing a conductive material and a liner layer LL. The width in the y direction of the conductive portion EC of the joint portion BTO1 is at least wider than the width in the y direction of the lower end portion of the second plate-shaped portion ST2, and is connected to the lower end portion of the conductive portion EC of the second plate-shaped portion ST2. The width in the y direction of the conductive portion EC of the joint portion BTO1 may be wider than the width in the y direction of the conductive portion EC of the first plate-shaped portion ST1.

[0032] The second bridge portion BT2 has an upper structure BTU2 that reaches a predetermined depth from the upper surface of the second interlayer insulating film 40, and a lower structure BTB2 that penetrates the second interlayer insulating film 40 from a predetermined depth of the second interlayer insulating film 40 to a predetermined depth of the second plate-shaped portion ST2. The lower structure BTB2 is located above the uppermost conductive layer WL2 in the second stacked body LM2, that is, the drain side selection gate line SGD. The width of the lower structure BTB2 in the y direction is approximately equal to the width of the second plate-shaped portion ST2 in the y direction and is narrower than the width of the upper structure BTU2 in the y direction. The second bridge portion BT2 is, for example, a silicon oxide layer.

[0033] As shown in FIGS. 2B(a) and 2B(b), a first staircase portion SR1, a second staircase portion SR2, a contact CC, and a columnar portion HR are formed in the staircase region SA.

[0034] The first staircase portion SR1 and the second staircase portion SR2 are formed by processing the first laminate LM1 and the second laminate LM2 into a staircase shape, respectively. Specifically, as shown in Fig. 2B(a), the first staircase portion SR1 is included in the first laminate LM1, and a plurality of conductive layers WL1 are processed into a staircase shape extending in the x-direction. Also, as shown in Fig. 2B(b), the second staircase portion SR2 is included in the second laminate LM2, and a plurality of conductive layers WL2 are processed into a staircase shape continuing from the first staircase portion SR1 in the x-direction.

[0035] 2B(a) shows the bottom of the first staircase portion SR1, that is, the part where the conductive layer WL1 of the bottom layer of the first laminate LM1 is processed into a staircase shape. That is, in FIG. 2B(a), the first staircase portion SR1 extends toward the front side of the paper. Also, dummy staircase portions are formed on both sides in the y direction of the first staircase portion SR1 extending in the x direction. These dummy staircase portions are formed together when forming the first staircase portion SR1, and do not have the function of electrically drawing out the conductive layer WL1 of each layer, as the regular first staircase portion SR1 does.

[0036] 2B(b) shows the bottom of the second staircase portion SR2, that is, the part where the conductive layer WL2 of the bottom layer of the second laminate LM2 is processed into a staircase shape. That is, in FIG. 2B(b), the second staircase portion SR2 also extends toward the front side of the paper. Also, dummy staircase portions that do not function as regular second staircase portions SR2 are formed on both sides in the y direction of the second staircase portion SR2 extending in the x direction.

[0037] At the height position of the first laminated body LM1, the first step portion SR1 is covered with an insulating layer 34, and the insulating layers 31 to 33 are formed on the insulating layer 34. The insulating layer 34 is, for example, a silicon oxide layer. Therefore, the insulating layers 31 to 34 are substantially integrated. In the following description, the insulating layers 31, 32, and 34 may be collectively referred to as the first interlayer insulating film 30. At the height position of the second laminated body LM2, the second step portion SR2 is covered with an insulating layer 43, and the insulating layers 41 to 42 are formed on the insulating layer 43. The insulating layer 43 is, for example, a silicon oxide layer. Therefore, the insulating layers 41 to 43 are substantially integrated. In the following description, the insulating layers 41 to 43 may be collectively referred to as the second interlayer insulating film 40.

[0038] Some of the contacts CC penetrate the first interlayer insulating film 30 and the second interlayer insulating film 40, and are connected to the conductive layer WL1 constituting each step of the first staircase portion SR1. Other parts of the contacts CC penetrate the second interlayer insulating film 40, and are connected to the conductive layer WL2 constituting each step of the second staircase portion SR2. FIGS. 2B(a) and (b) show the contacts CC connected to the first staircase portion SR1 and the bottom step of the second staircase portion SR2, respectively. The contacts CC are connected to upper wiring not shown in FIGS. 2B(a) and (b). This allows the conductive layers WL1 and WL2 of each layer to be electrically drawn out.

[0039] The columnar portion HR penetrates the first stacked body LM1, the insulating layers 31-33, the second stacked body LM2, and the insulating layer 41 in the z-direction, and terminates in the source line SL. In this embodiment, the columnar portion HR has a layer structure similar to that of the memory pillar MP, for example, in which the same materials as the core layer COR, the channel layer CHN, the memory film MEM, and the cap layer CAP are filled in a hole, but does not contribute to the function of the semiconductor memory device 1. The columnar portion HR supports the configuration of the first stacked body LM1 and the second stacked body LM2 when these components are formed from a stacked body (described later) in which a sacrificial layer and an insulating layer are stacked.

[0040] Fig. 3 is a diagram for explaining the positional relationship between the first bridge portion BT1 and the second bridge portion BT2 according to the first embodiment. Fig. 3(a) is an xy cross-sectional view along the line L3-L3 in Fig. 2B(a), and Fig. 3(b) is an xy cross-sectional view along the line L4-L4 in Fig. 2B(a). That is, Figs. 3(a) and (b) are top views in the extending direction of the first plate-shaped portion ST1 and the second plate-shaped portion ST2. Also, for example, like the line L2a-L2a shown in Fig. 1, the yz cross-section along the line L2a-L2a shown in Figs. 3(a) and (b) corresponds to the surface shown in Fig. 2B(a).

[0041] 3(a) and 3(b), the first bridge portion BT1 and the second bridge portion BT2 are provided intermittently at the upper end portions of the first plate portion ST1 and the second plate portion ST2 extending in the x direction. The first bridge portion BT1 and the second bridge portion BT2 are formed so as to straddle the first plate portion ST1 and the second plate portion ST2 in the y direction. Also, when viewed from the z direction, the first bridge portion BT1 and the second bridge portion BT2 are arranged to be shifted from each other in the x direction.

[0042] Specifically, when the position in the x direction is position R1 in FIG. 3, the first bridge portion BT1 and the second bridge portion BT2 are arranged so as to overlap each other. When the position in the x direction is position R4, neither the first bridge portion BT1 nor the second bridge portion BT2 is arranged. At such position R4, the shape of each of the first plate-shaped portion ST1 and the second plate-shaped portion ST2 is a shape that does not have either the first bridge portion BT1 or the second bridge portion BT2 at their upper end portions, as shown in FIG. 2A. At positions R2 and R3, either the first bridge portion BT1 or the second bridge portion BT2 is arranged on either side of the first plate-shaped portion ST1 or the second plate-shaped portion ST2, but these first bridge portions BT1 and second bridge portions BT2 do not overlap each other when viewed from the z direction.

[0043] 3 is merely an example and is not limited thereto. The positional relationship, x-direction length, adjacent interval, number, etc., of the first cross-linking portion BT1 and the second cross-linking portion BT2 may be appropriately determined.

[0044] Hereinafter, a method for forming each component in the cell array region CA and the staircase region SA of the first embodiment will be described with reference to Figs. 4 to 10. Figs. 4 to 10 are diagrams illustrating a part of the procedure of the method for manufacturing the semiconductor memory device 1 according to the first embodiment. Figs. 4(Aa) to 10(Ap) are yz cross-sectional views taken along the line L1-L1 in Fig. 1, and correspond to the cross-section shown in Fig. 2A. Figs. 4(Ba) to 10(Bp) are yz cross-sectional views taken along the line L2a-L2a in Fig. 1, and correspond to the cross-section shown in Fig. 2B(a).

[0045] In Fig. 4(Aa) and (Ba), a first laminated body LMs1 and an insulating layer 31 are formed in this order on a substrate SB2 such as a silicon wafer. The first laminated body LMs1 is formed by alternately laminating a plurality of insulating layers OL1 and a plurality of sacrificial layers SN1 one by one. As shown in Fig. 4(Ba), the first laminated body LMs1 and a part of the insulating layer 31 are processed into a first staircase portion SR1 by a series of steps including forming a mask with a photoresist, etching using the mask, slimming the mask, and etching using the slimmed mask. The first staircase portion SR1 is formed by forming a plurality of sacrificial layers SN1 in a staircase shape extending in the x direction. At this time, the mask is slimmed not only in the x direction but also in the y direction by slimming, so that dummy staircase portions are formed on both sides of the first staircase portion SR1 in the y direction. After this, the first staircase portion SR1 is covered with an insulating layer 34.

[0046] The insulating layer OL1 is an example of a first insulating layer, and the sacrificial layer SN1 is an example of a second insulating layer. The insulating layer OL1 is, for example, a silicon oxide layer, and the sacrificial layer SN1 is, for example, a silicon nitride layer.

[0047] 4(Ab) and (Bb), a memory hole MHA1 and a hole HRA1 are formed penetrating the first laminate LMs1, the insulating layer 31, and the insulating layer 34. The memory hole MHA1 and the hole HRA1 are provided to form the memory pillar MP and the columnar portion HR, respectively. Next, amorphous carbon is embedded in the memory hole MHA1 and the hole HRA1. At this time, the amorphous carbon deposited on the insulating layer 31 and the insulating layer 34 is removed by, for example, a chemical mechanical polishing (CMP) method.

[0048] 4(Ac) and (Bc), an insulating layer 32 is formed on an insulating layer 31 and an insulating layer 34. In this way, the first step portion SR1 is covered with a first interlayer insulating film 30. Next, a slit STA1 is formed that penetrates the first stacked body LMs1 and the first interlayer insulating film 30 and terminates at the substrate SB2. The slit STA1 is an example of a first groove portion, and is configured to later become the first plate-shaped portion ST1. Therefore, the slit STA1 also extends in the x-direction.

[0049] Next, an oxide layer BO is formed at the bottom of the slit STA1. After that, amorphous silicon is filled into the slit STA1. This allows the oxide layer BO to function as an etching stopper when the amorphous silicon is later removed from the slit STA1.

[0050] Next, as shown in the cross section of FIG. 4(Bd), in the region where the first bridge portion BT1 and the second bridge portion BT2 will be disposed later, a photoresist film RF is applied onto the insulating layer 32, and the photoresist film RF is opened by exposure and development so that the upper portion of the slit STA1 is exposed. Using the photoresist film RF as a mask, the insulating layer 32 is dry etched to a depth that does not penetrate the insulating layer 32. As a result, an opening OPA is formed at the upper end of the slit STA1. The opening OPA is a portion that will later become the upper structure BTU1 of the first bridge portion BT1.

[0051] In the above, the photoresist film RF is opened so that the width of the opening OPA in the y direction is wider than the width of the slit STA1 in the y direction. This ensures a wide tolerance for the positional deviation of the opening of the photoresist film RF relative to the slit STA1, so that the first bridge portion BT1 can be more reliably formed on the upper end of the first plate-shaped portion ST1.

[0052] In contrast, as shown in the cross section of Figure 4(Ad), in areas where the first bridging portion BT1 and the second bridging portion BT2 will not be later arranged, no opening is formed in the photoresist film RF, and therefore no opening OPA is formed.

[0053] Next, as shown in the cross section of FIG. 5(Be), in the region where the first bridge portion BT1 and the second bridge portion BT2 will be disposed later, after the opening portion OPA is formed, the amorphous silicon exposed at the bottom of the opening portion OPA is dry etched to a predetermined depth using a gas different from the etching gas for processing the opening portion OPA. The predetermined depth is a depth above the sacrificial layer SN1 of the top layer of the first laminated body LMs1. As a result, an opening portion OPB is formed at the bottom of the opening portion OPA. The opening portion OPB is a portion that will later become the lower structure BTB1 of the first bridge portion BT1. In contrast, as shown in the cross section of FIG. 5(Ae), in the region where the first bridge portion BT1 and the second bridge portion BT2 will not be disposed later, the opening portion OPB is not formed.

[0054] 5(Bf), after removing the photoresist film RF, an insulating layer 33 is deposited on the insulating layer 32. The insulating layer 33 is deposited on the bottom and side walls of the openings OPA and OPB. When the insulating layer 33 is deposited in each of the above-mentioned parts and reaches a predetermined film thickness, the opening OPB is almost completely filled with the insulating layer 33, and a lower structure BTB1 of the first bridging portion BT1 is formed.

[0055] At this time, an opening OPC is formed inside the opening OPA covered with the insulating layer 33. At this time, the insulating layer 33 is formed so as to maintain a state in which the width in the y direction at the opening OPC is wider than the width in the y direction at the lower end of the slit STA2 to be formed later. This makes it possible to ensure a wide tolerance for misalignment of the slit STA2 to be formed later with respect to the opening OPC.

[0056] In contrast, in FIG. 5(Af), an insulating layer 33 is simply deposited on the insulating layer 32.

[0057] In Fig. 5(Bg), the opening OPC is filled with an amorphous carbon layer CB. The amorphous carbon layer CB functions as an etching stopper when processing the second plate-shaped portion ST2 later. In contrast, in Fig. 5(Ag), the amorphous carbon layer CB is not formed.

[0058] Hereinafter, Fig. 6(Bh) shows how the second laminated body LMs2 and the second staircase portion SR2 are formed. Note that Fig. 6(Bh) shows a cross section different from the other drawings from Fig. 4(Ba) to Fig. 10(Bp) in order to show the second staircase portion SR2.

[0059] As shown in FIG. 6(Bh), a second laminate LMs2 and an insulating layer 41 are formed in this order on the insulating layer 33. The second laminate LMs2 is formed by alternately laminating a plurality of insulating layers OL2 and a plurality of sacrificial layers SN2 one by one. The second laminate LMs2 and a part of the insulating layer 41 are processed into a second staircase portion SR2, for example, by a process similar to that for the first staircase portion SR1. The second staircase portion SR2 is formed by processing a plurality of sacrificial layers SN2 into a staircase shape that is continuous with the first staircase portion SR1 in the x direction.

[0060] 6Bh shows the bottom step of the second staircase, that is, the part where the sacrificial layer SN2, the bottom layer of the second laminate LMs2, is processed into a staircase shape. When forming the second staircase SR2, dummy staircases are formed on both sides of the second staircase SR2 in the y direction, similarly to the formation of the first staircase SR1.

[0061] Thereafter, the second stepped portion SR2 is covered with an insulating layer 43.

[0062] The insulating layer OL2 is an example of a third insulating layer, and the sacrificial layer SN2 is an example of a fourth insulating layer. The insulating layer OL2 is, for example, a silicon oxide layer, and the sacrificial layer SN2 is, for example, a silicon nitride layer.

[0063] 6(Ai) and 6(Bi), memory holes MHA2 and holes HRA2 are formed penetrating the second laminate LMs2, the insulating layer 41, and the insulating layer 43. The memory holes MHA2 and holes HRA2 are connected to the upper ends of the memory holes MHA1 and holes HRA1 formed in the first laminate LMs1, respectively. Next, the amorphous carbon embedded in the memory holes MHA1 and holes HRA1 is removed by ashing or the like via the memory holes MHA2 and holes HRA2.

[0064] 7(Aj) and (Bj), a memory film MEM, a channel layer CHN, and a core layer COR are formed in this order inside the memory holes MHA1 and MHA2. Next, the core layer COR is recessed by dry etching, and a cap layer CAP is embedded. This forms a memory pillar MP. At the same time as the formation of the memory pillar MP, the holes HRA1 and HRA2 are also subjected to a similar process, and a columnar portion HR is formed.

[0065] 7(Ak) and (Bk), an insulating layer 42 is formed on the insulating layers 41 and 43 that cover the memory pillar MP, the first stacked body LMs1 in which the columnar portion HR is formed, and the second stacked body LMs2. In this manner, the second stepped portion SR2 is covered with the second interlayer insulating film 40. Next, a slit STA2 is formed that has an opening at a position overlapping with the slit STA1 formed in the first stacked body LMs1 in the z direction and penetrates the second stacked body LMs2 and the second interlayer insulating film 40. The slit STA2 is provided to form the second plate-shaped portion ST2. The slit STA2 is an example of a second groove portion.

[0066] As shown in the cross section of Figure 7 (Ak), in the region where the first bridging portion BT1 and the second bridging portion BT2 will not be arranged later, the slit STA2 extends along the x direction and penetrates the insulating layer 33 covering the slit STA1 to connect with the upper end of the slit STA1.

[0067] Specifically, as shown in Fig. 7(Ak), in a portion where the opening OPC filled with the lower structure BTB1 of the first bridge portion BT1 and the amorphous carbon layer CB is not formed at the upper end of the slit STA1, the slit STA2 directly connects to the upper end opening of the slit STA1. On the other hand, as shown in Fig. 7(Bk), in a portion where the lower structure BTB1 of the first bridge portion BT1 and the opening OPC filled with the amorphous carbon layer CB are formed at the upper end of the slit STA1, the slit STA2 connects to the amorphous carbon layer CB formed at the opening OPC.

[0068] At this time, the etching conditions of the slit STA2, like the insulating layer 33, have no selectivity with respect to the silicon oxide layer or the like constituting the lower structure BTB1 of the first bridge portion BT1 provided at the upper end of the slit STA1. By providing the amorphous carbon layer CB above the lower structure BTB1, the etching of the slit STA2 can be stopped on the amorphous carbon layer CB, and the lower end of the slit STA2 is prevented from penetrating the lower structure BTB1. This maintains the function of the first bridge portion BT1, which will be formed later, connecting the first interlayer insulating films 30 on both sides in the y direction above the first plate-shaped portion ST1, which will be formed later.

[0069] Furthermore, as described above, the amorphous carbon layer CB is formed to be wider than the width of the lower end of the slit STA2 in the y direction, so that the allowable range of positional deviation of the slit STA2 with respect to the amorphous carbon layer CB is secured widely, and the lower end of the slit STA2 can be made to reach the plane of the amorphous carbon layer CB more reliably. Therefore, the amorphous carbon layer CB can more reliably stop etching of the lower end of the slit STA2.

[0070] Although not shown in FIG. 7Bk, the amorphous carbon layer CB is removed by ashing or the like after the slit STA2 is formed, and the opening OPC is exposed again in the portion from which the amorphous carbon layer CB has been removed.

[0071] Next, as shown in Figs. 8(Al) and (Bl), amorphous silicon is filled into the slit STA2 and the opening OPC, and a silicon nitride layer NI is deposited on the insulating layer 42. As shown in the cross section of Fig. 8(Bl), in the region where the first bridge portion BT1 and the second bridge portion BT2 will be disposed later, a process corresponding to the process of Figs. 4(Bd) and (Be) is performed on the silicon nitride layer NI to form an opening OPD having a width in the y direction wider than the slit STA2 in the silicon nitride layer NI above the slit STA2, and further, an opening OPE having a width in the y direction substantially equal to that of the slit STA2 and reaching a predetermined depth of the slit STA2 is formed. The opening OPE is formed at a depth above the sacrificial layer SN2, which is the top layer of the second laminated body LMs2. Also, the silicon nitride layer NI functions as a CMP stopper when the second bridge portion BT2 is formed in the opening OPD. On the other hand, as shown in the cross section of Fig. 8(Al), in the region where the first bridge portion BT1 and the second bridge portion BT2 will not be disposed later, the openings OPD and OPE are not formed.

[0072] In FIG. 8(Bm), silicon oxide is embedded in the openings OPD and OPE. The silicon oxide deposited on the silicon nitride layer NI is removed by, for example, the CMP method. As a result, the second bridge portion BT2 is formed in the openings OPD and OPE. In this manner, the second bridge portion BT2 connects the second interlayer insulating film 40 on both sides of the slit STA1. As described above, the lower end of the opening OPE is located above the uppermost sacrificial layer SN2 of the second laminated body LMs2. Therefore, the lower end of the second bridge portion BT2 is also located above the uppermost sacrificial layer SN2.

[0073] Next, when the silicon nitride layer NI is removed by dry etching or the like, as shown in FIG. 8(Am), the portion at the upper end of the slit STA2 where the second bridge portion BT2 is not formed is opened. Next, the amorphous silicon filled in the slit STA1, the opening OPC, and the slit STA2 is removed by wet etching. The processing liquid enters from the upper end opening of the slit STA2 (the portion where the second bridge portion BT2 is not formed), and reaches the opening OPC from below the second bridge portion BT2, or passes through the upper end opening of the slit STA1 (the portion where the lower structure BTB1 of the first bridge portion BT1 and the opening OPC filled with amorphous silicon are not formed), and diffuses to the lower end of the slit STA1. As a result, the amorphous silicon is removed from the slit STA1, the opening OPC, and the slit STA2.

[0074] 9(An) and 9(Bn), conductive layers WL1 and WL2 are formed in the portions of the first laminate LMs1 and the second laminate LMs2 where the sacrificial layers SN1 and SN2 were, to form the first laminate LM1 and the second laminate LM2. Specifically, the sacrificial layers SN1 and SN2 are first removed by wet etching. As described above, the processing liquid enters from the upper end opening of the slit STA2, passes through the opening OPC and the upper end opening of the slit STA1, and diffuses to the lower end. As a result, the sacrificial layers SN1 and SN2 exposed on the side surfaces of the slits STA1 and STA2 are removed in the x and y directions, and a space (not shown) is formed between the insulating layers OL1 and OL2 that extends on the xy plane and is arranged in layers in the z direction.

[0075] Next, an insulating layer such as aluminum oxide is formed in the space through the slits STA1 and STA2 by, for example, atomic layer deposition (ALD), and then a metal layer such as tungsten or molybdenum is filled in, to obtain conductive layers WL1 and WL2. That is, the sacrificial layers SN1 and SN2 are replaced with the conductive layers WL1 and WL2 to form the first laminate LM1 and the second laminate LM2. Next, the metal layer remaining on the sidewalls of the slits STA1 and STA2 is removed by a wet etching process. Note that such a process of replacing the sacrificial layers SN1 and SN2 with the conductive layers WL1 and WL2 is sometimes referred to as a replacement process.

[0076] 9(Ao) and (Bo), a liner layer LL and a conductive part EC are formed in this order inside the slits STA1 and STA2. The raw material gases of the liner layer LL and the conductive part EC enter from the upper end opening of the slit STA2 and reach the opening OPC, or diffuse through the upper end opening of the slit STA1 to the lower end of the slit STA1, like the above-mentioned processing liquid. This forms a first plate-shaped part ST1 and a second plate-shaped part ST2. Also, a joint part BTO1 is formed in the opening OPC, and a first bridge part BT1 having the joint part BTO1 is formed at the upper end of the slit STA1. Also, contacts CC reaching the conductive layers WL1 and WL2 may be formed here.

[0077] The first bridge portion BT1 connects the first interlayer insulating film 30 on both sides of the slit STA1.

[0078] 10(Ap) and (Bp), the plug PG, the bit line BL, the upper layer wiring ML0, the via V1, and the upper wiring ML1 connected to the memory pillar MP or the contact CC are formed on the upper surface of the insulating layer 42, and these are covered with the insulating layer 51. The upper wiring ML1 is exposed on the surface of the insulating layer 51. Meanwhile, the transistor Tr, the via V2, and the upper wiring ML2 are formed on the substrate SB1 different from the substrate SB2, and these are covered with the insulating layer 52. The upper wiring ML2 is exposed on the surface of the insulating layer 52. The substrates SB1 and SB2 are bonded together so that the upper wiring ML1 and the upper wiring ML2 are vertically overlapped. The insulating layers 51 and 52 are, for example, silicon oxide layers, and the insulating layers 51 and 52 are substantially integrated.

[0079] Next, the substrate SB2 is polished from below the first laminate LM1 to expose the memory pillar MP, the columnar portion HR, and the lower end portion of the first plate-shaped portion ST1, and the source line SL, the insulating layer 50, and the electrode film EL are formed on the exposed surface in this order. This connects the conductive portion EC formed on the first plate-shaped portion ST1 and the second plate-shaped portion ST2 to the source line SL. Also, the channel layer CHN of the memory pillar MP and the source line SL are connected. In this manner, the semiconductor memory device 1 is manufactured.

[0080] (Comparative Example) Fig. 11 is a cross-sectional view showing a detailed configuration of a cell array region of a semiconductor memory device 1x according to a comparative example. The semiconductor memory device 1x of the comparative example differs from the semiconductor memory device 1 of the first embodiment in the number and positions of the bridge portions. Fig. 11(a) is a diagram explaining the state of the stack LMsx before the replacement process. Figs. 11(b) and (c) are diagrams explaining the state of the stack LMx during the replacement process. Fig. 11(d) is a diagram explaining the state of the stack LMx after the replacement process.

[0081] 11(a), when the distance L in the y direction from the slit STAx to the memory pillar MP is different on both sides in the y direction of the slit STAx extending in the cell array region in the x direction, a difference may occur in the contraction stress of the stack LMsx divided by the slit STAx on both sides in the y direction of the slit STAx. In addition, the step portion (not shown) is covered with a thick interlayer insulating film, and different stresses, that is, expansion stress and contraction stress, may occur between such a thick interlayer insulating film and the stack having a stacked structure of different layers.

[0082] As a result, bending or tilting may occur in the laminate LMsx and the memory pillars and columnar portions, etc., provided in the laminate LMsx. If bending or tilting occurs in the laminate LMsx, the laminate LMsx may collapse, and the spaces between the insulating layers OL may be blocked, resulting in poor formation of the conductive layers WL. If bending or tilting occurs in the memory pillars and columnar portions, etc., there is a risk of contact with the slits STAx or contacts formed in the staircase portions.

[0083] In order to reduce such bending and inclination, a bridge portion BTx that connects the interlayer insulating films on both sides of the slit STAx in the y direction to each other may be formed above the slit STAx. This makes it possible to reduce the stress difference on both sides of the slit STAx in the y direction via the bridge portion BTx.

[0084] In recent years, the number of layers in the laminate LMx has been increasing with the increase in memory capacity of semiconductor memory devices. As the number of layers in the laminate LMx increases, the stress generated within the layers increases, so there is a demand for thicker bridging portions BTx. However, if the thickness of the bridging portions BTx is increased, the bridging portions BTx may be formed to a depth that faces the sacrificial layer SN of the laminate LMsx.

[0085] Here, during the replacement process, the raw material gas of the conductive layer WL tends to stagnate immediately below the bridge portion BTx, and a thick metal layer MT may be formed on the lower surface of the bridge portion BTx in the slit STAx. As shown in Fig. 11(b), if the bridge portion BTx is formed to a depth facing the sacrificial layer SN of the laminate LMsx, the metal layer MT is locally formed thick on the exposed surface A exposed in the slit STAx of the conductive layer WL formed immediately below the bridge portion BTx.

[0086] As shown in Fig. 11(c), the metal layer MT formed thickly on the exposed surface A may remain directly under the bridge portion BTx even after the metal layer is removed from the sidewall portion of the slit STAx after the replacement process is completed. As a result, as shown in Fig. 11(d), the conductive portion EC of the plate-shaped portion STx, which later functions as a source line contact, and the metal layer MT added to the exposed surface A of the conductive layer WL may come close to each other, resulting in a decrease in the breakdown voltage performance. On the other hand, if excessive processing is performed to remove such a metal layer MT, the metal layer of the conductive layer WL may dissolve more than necessary.

[0087] According to the semiconductor memory device 1 of embodiment 1, there is provided a first bridging portion BT1 arranged at the upper end of the first plate-shaped portion ST1 and connecting the first interlayer insulating film 30 on both sides of the first plate-shaped portion ST1, and a second bridging portion BT2 arranged at the upper end of the second plate-shaped portion ST2 and connecting the second interlayer insulating film 40 on both sides of the second plate-shaped portion ST2.

[0088] In this way, by providing the first bridging portion BT1 and the second bridging portion BT2 on the first plate-shaped portion ST1 and the second plate-shaped portion ST2, respectively, the first interlayer insulating film 30 and the second interlayer insulating film 40 can be more firmly connected on both sides of the first plate-shaped portion ST1 and the second plate-shaped portion ST2, respectively, compared to, for example, the case where a bridging portion is provided only at the upper end portion of the second plate-shaped portion ST2, and therefore the deflection and tilt of the first laminate LM1 and the second laminate LM2 are reduced.

[0089] According to the semiconductor memory device 1 of embodiment 1, the lower ends of the first bridge portion BT1 and the second bridge portion BT2 are each located above the uppermost conductive layers WL1 and WL2 in the first laminate LM1 and the second laminate LM2, respectively.

[0090] As described above, the first bridge portion BT1 and the second bridge portion BT2 corresponding to the first laminate LM1 and the second laminate LM2 are provided, so that the first bridge portion BT1 and the second bridge portion BT2 can be formed thin. This makes it possible to prevent the metal layer MT formed thickly directly below the first bridge portion BT1 and the second bridge portion BT2 from being added to the exposed surfaces of the conductive layers WL1 and WL2 directly below the first bridge portion BT1 and the second bridge portion BT2. As a result, it is possible to prevent a decrease in the withstand voltage performance between the conductive layers WL1 and WL2 and the first plate-shaped portion ST1 and the second plate-shaped portion ST2.

[0091] According to the semiconductor memory device 1 of embodiment 1, the first bridging portion BT1 comprises an upper structure BTU1 whose width in the y direction is wider than the width in the y direction of the first plate-shaped portion ST1, and a lower structure BTB1 whose width in the y direction is narrower than the width in the y direction of the upper structure BTU1 and connects the upper structure BTU1 and the first plate-shaped portion ST1.

[0092] In this way, since the first bridging portion BT1 has the upper structure BTU1, it is possible to secure a wide tolerance for misalignment with the first plate-shaped portion ST1 when forming the first bridging portion BT1. Therefore, the first bridging portion BT1 can more reliably connect the first interlayer insulating film 30 on both sides of the first plate-shaped portion ST1 in the y direction.

[0093] According to the semiconductor memory device 1 of embodiment 1, the joint BTO1 of the upper structure BTU1 of the first bridge portion BT1 has a conductive portion EC whose width in the y direction is wider than the width in the y direction of the lower end portion of the second plate-shaped portion ST2.

[0094] As described above, when the slit STA2 that will later become the second plate-shaped portion ST2 is formed, the conductive portion EC of the joint portion BTO1 is filled with the amorphous carbon layer CB that serves as an etching stopper for processing the slit STA2. By forming the width of the amorphous carbon layer CB in the y direction wider than the width of the lower end of the slit STA2 in the y direction, a wide tolerance for misalignment between the slit STA2 and the amorphous carbon layer CB can be secured, and the etching of the slit STA2 can be more reliably stopped on the amorphous carbon layer CB.

[0095] In the above-described first embodiment, the first cross-linking portion BT1 and the second cross-linking portion BT2 are arranged to be shifted from each other in the x direction when viewed from the z direction. More specifically, the first cross-linking portion BT1 and the second cross-linking portion BT2 are arranged so that, at a predetermined position in the x direction, there are a portion where both the first cross-linking portion BT1 and the second cross-linking portion BT2 are arranged, a portion where neither is arranged, and a portion where either the first cross-linking portion BT1 or the second cross-linking portion BT2 is arranged.

[0096] However, the arrangement of the first cross-linking portion BT1 and the second cross-linking portion BT2 having a shift in the x direction is not limited to the above. The first cross-linking portion BT1 and the second cross-linking portion BT2 may be arranged so that the end of the first cross-linking portion BT1 and the end of the second cross-linking portion BT2 overlap each other when viewed from the z direction, so that there is no portion where neither the first cross-linking portion BT1 nor the second cross-linking portion BT2 is not arranged. In addition, the first cross-linking portion BT1 and the second cross-linking portion BT2 may be arranged so that there is no portion where the first cross-linking portion BT1 and the second cross-linking portion BT2 overlap each other in the z direction at any position in the x direction.

[0097] Alternatively, the first cross-linking portion BT1 and the second cross-linking portion BT2 may be arranged so that they overlap each other in the z direction, that is, so that there is no misalignment in the x direction. In this way, by arbitrarily determining the arrangement of the first cross-linking portion BT1 and the second cross-linking portion BT2, the cross-linking strength of each of the first cross-linking portion BT1 and the second cross-linking portion BT2 can be appropriately adjusted, and the deflection and inclination of the first laminate LM1 and the second laminate LM2 can be further suppressed.

[0098] (Modification) 12 and 13, a semiconductor memory device according to a modification of the embodiment 1 will be described. In the semiconductor memory device according to the modification, the width in the y direction of the conductive portion EC formed in the first bridge portion BT11 is different from that of the above-described embodiment 1.

[0099] Fig. 12 is a cross-sectional view showing a detailed configuration of a cell array region CA of a semiconductor memory device 2 according to a modified example of embodiment 1. Fig. 12(a) is a yz cross-sectional view of a portion of the first plate-shaped portion ST11 where the first bridging portion BT11 is not formed, and Fig. 12(b) is a yz cross-sectional view of a portion of the first plate-shaped portion ST11 where the first bridging portion BT11 is formed.

[0100] As shown in FIG. 12(a), the first plate-shaped part ST11 has a conductive part EC and a liner layer LL formed in this order from the inside, and the conductive part EC at the upper end of the first plate-shaped part ST11 has a width L1 in the y direction. On the other hand, as shown in FIG. 12(b), the first bridge part BT11 includes a lower structure BTB11 configured similarly to the lower structure BTB1 of the above-mentioned embodiment 1, and an upper structure BTU11 having a joint BTO11 different from the joint BTO1 of the above-mentioned embodiment 1. The upper structure BTU11 of the modified example has a joint BTO11 in which the conductive part EC and the liner layer LL are formed, and the conductive part EC at the joint BTO11 has a width L2 in the y direction. The width L2 in the y direction of the conductive part EC formed in the first bridge part BT11 is equal to or smaller than the width L1 in the y direction of the upper end of the conductive part EC formed in the first plate-shaped part ST11. This ensures a wide distance L3 between the end in the y direction of the conductive portion EC formed in the first bridge portion BT11 and the memory pillar MP.

[0101] However, even in the modified example, it is preferable that the y-direction width L2 of the conductive portion EC formed in the first bridging portion BT11 is wider than the y-direction width of the upper end portion of the conductive portion EC formed in the second plate-shaped portion ST12.

[0102] Next, a method for forming a cell array region CA of the modified example will be described with reference to Fig. 13. Fig. 13 is a diagram illustrating a part of the procedure of a method for manufacturing a semiconductor memory device 2 according to a modified example of the first embodiment. Prior to the process of Fig. 13, the modified example also performs processes corresponding to the processes of Fig. 4(Aa) to Fig. 5(Af) of the above-mentioned embodiment. At this point, it is assumed that a lower structure BTB11 and an opening OPC above the lower structure BTB11 are formed at a position where the first bridge portion BT11 is to be formed.

[0103] 13(a), a sidewall layer 35 such as an amorphous silicon layer is deposited on an insulating layer 33. The sidewall layer 35 is deposited on the bottom surface and side walls of the opening OPC. When the sidewall layer 35 is deposited in each of the above-mentioned portions and reaches a predetermined film thickness, the opening OPC is filled with the sidewall layer 35.

[0104] 13(b), when the sidewall layer 35 is etched back until the bottom of the opening OPC is exposed, the bottom surface of the opening OPC is exposed and part of the sidewall layer 35 remains on the side surface of the opening OPC, forming a sidewall 35w. Due to the sidewall 35w covering the side surface of the opening OPC, the exposed width of the bottom surface of the opening OPC in the y direction becomes narrower than the original width of the opening OPC in the y direction.

[0105] 13(c), when the insulating layer 33 is etched back over the entire surface, the sidewall 35w serves as a mask and the bottom surface of the opening OPC exposed from the sidewall 35w is etched away. As a result, an opening OPF is formed extending in the depth direction from the bottom of the opening OPC. Also, the thickness of the insulating layer 33 is reduced overall.

[0106] 13(d), the sidewall 35w is removed by wet etching, and the process corresponding to FIG. 5(Ag) is performed to fill the opening OPE with an amorphous carbon layer CB. Thereafter, the process corresponding to the process from FIG. 6(Ah) onward in the above embodiment is performed to form the first bridge portion BT11 of the semiconductor memory device 2 of the modified example.

[0107] According to the semiconductor memory device 2 of the modified example, the width L2 in the y direction of the conductive portion EC formed on the first bridge portion BT11 is equal to or smaller than the width L1 in the y direction of the conductive portion EC formed on the upper end portion of the first plate-shaped portion ST11. This makes it possible to ensure a wide distance between the conductive portion EC formed on the first bridge portion BT11 and the memory pillar MP, thereby improving the withstand voltage performance between the memory pillar MP and the conductive portion EC of the first bridge portion BT11. The semiconductor memory device 2 of the modified example otherwise exhibits the same effects as the semiconductor memory device 1 of the above-mentioned embodiment 1.

[0108] (Embodiment 2) Next, a semiconductor memory device according to a second embodiment will be described with reference to Fig. 14A to Fig. 20. The semiconductor memory device according to the second embodiment differs from the above-described embodiments and modifications in the shape of the plate-shaped portion, the timing of forming the plate-shaped portion, the material of the bridge portion, and the like.

[0109] FIG. 14A is a partial top view for explaining a configuration example of the semiconductor memory device 10 according to the second embodiment. More specifically, FIG. 14A is a partial top view showing a schematic configuration of the semiconductor memory device 10 according to the second embodiment, and corresponds to the example of FIG. 1. Also, FIG. 14B is a cross-sectional view for explaining a configuration example of the semiconductor memory device 10 according to the second embodiment. More specifically, FIG. 14B(a) is a view showing a detailed configuration of the staircase region SA according to the second embodiment, and is a yz cross-sectional view along the line L5a-L5a in FIG. 14A. Also, FIG. 14B(b) is a yz cross-sectional view along the line L5b-L5b in FIG. 14A.

[0110] As shown in Fig. 14A, the cell array region CA and the staircase region SA are formed with a plurality of plate-like portions STJ that divide the cell array region CA and the staircase region SA. Each of the plate-like portions STJ crosses the cell array region CA and the staircase region SA in the x direction, extends in the z direction in the figure, and terminates in a source line (described later). In each of the plate-like portions STJ, both side surfaces in the y direction are formed in a waveform shape having periodicity in the x direction. The plate-like portion STJ also has a plurality of second bridge portions BT22 intermittently provided in the longitudinal direction (x direction) of the plate-like portion STJ.

[0111] As shown in FIG. 14B(a), the plate-shaped portion STJ has a first plate-shaped portion ST21 extending along the x direction and penetrating the first laminate LM1 and the insulating layers 31, 32, 34, and 36 in the z direction, and a second plate-shaped portion ST22 extending along the x direction and penetrating the second laminate LM2 and the second interlayer insulating film 40 in the z direction to connect to the upper end of the first plate-shaped portion ST21.

[0112] The first plate-shaped portion ST21 and the second plate-shaped portion ST22 each have a first bridge portion BT21 and a second bridge portion BT22 at a portion of the upper end. The first bridge portion BT21 includes at least one of polysilicon and silicon carbonitride. The second bridge portion BT22 includes at least one of silicon oxide, polysilicon, and silicon carbonitride. In this case, the first bridge portion BT21 and the second bridge portion BT22 may be made of the same material or different materials.

[0113] 14B(b), the first bridged portion BT21 and the second bridged portion BT22 are not formed on other parts of the upper end portions of the first plate-shaped portion ST21 and the second plate-shaped portion ST22 because the first bridged portion BT21 and the second bridged portion BT22 are each arranged intermittently in the x direction.

[0114] Fig. 15 is a diagram for explaining the positional relationship between the first bridge portion BT21 and the second bridge portion BT22 according to the second embodiment. Fig. 15(a) is an xy cross-sectional view along the line L7-L7 in Fig. 14B(a), and Fig. 15(b) is an xy cross-sectional view along the line L8-L8 in Fig. 14B(a). That is, Figs. 15(a) and (b) are top views in the extending direction of the first plate-shaped portion ST21 and the second plate-shaped portion ST22. Also, for example, like the line L5a-L5a shown in Fig. 14A, the yz cross-section along L5a-L5a shown in Figs. 15(a) and (b) corresponds to the surface shown in Fig. 14B(a).

[0115] As shown in Fig. 15(a) and (b), the side surfaces in the y direction of the first plate-shaped portion ST21 and the second plate-shaped portion ST22 are formed in a wave shape having periodicity in the x direction. Specifically, each of the first plate-shaped portion ST21 and the second plate-shaped portion ST22 has a side portion Sb in which a plurality of columnar portions S, each having a substantially cylindrical shape extending in the z direction, are connected to each other in the x direction, and the side surfaces on both sides in the y direction of each columnar portion S are connected in a wave shape. In addition, the liner layer LL of the first plate-shaped portion ST21 and the second plate-shaped portion ST22 is also formed along such a wave-shaped side wall, and thus has a wave-shaped shape. Furthermore, the conductive portion EC of the first plate-shaped portion ST21 and the second plate-shaped portion ST22 is filled inside the wave-shaped liner layer LL, and thus has a wave-shaped shape on both side walls in the y direction.

[0116] As shown in Fig. 15(b), the first bridging portions BT21 are disposed at equal intervals so as to cover the connection portions of the individual columnar portions S in the first plate-shaped portion ST21. On the other hand, as shown in Fig. 15(a), the second bridging portion BT22 is provided so as to continuously cover the tops of the multiple columnar portions S in the second plate-shaped portion ST22.

[0117] Hereinafter, a method for forming each component in the cell array region CA and the staircase region SA of the second embodiment will be described with reference to Figs. 16 to 20. Figs. 16 to 20 are diagrams illustrating a part of the procedure of the manufacturing method of the semiconductor memory device 10 according to the second embodiment. Figs. 16(Aa) to 20(Aj) are yz cross-sectional views taken along the line L6-L6 in Fig. 14A. Figs. 16(Ba) to 20(Bj) are yz cross-sectional views taken along the line L5a-L5a in Fig. 14A, and correspond to the cross section shown in Fig. 14B(a). Figs. 16(Cb), (Cc), Fig. 17(Ce), and Fig. 19(Ch) are partial top views of the corresponding views in Figs. 16 to 19.

[0118] 16(Aa) and 16(Ba), also in the embodiment 2, a process corresponding to the process of FIG. 4(Aa) and 4(Ba) in the embodiment 1 is performed. At this point, it is assumed that the first laminated body LMs1 is formed.

[0119] 16A, a memory hole MHA1 is formed penetrating the first stacked body LMs1 and the insulating layer 31. Next, amorphous carbon is embedded in the memory hole MHA1. In contrast, in FIG. 16B, unlike the first embodiment, a hole HRA1 is not formed.

[0120] Next, an insulating layer 32 is formed on the insulating layer 31 and the insulating layer 34, and holes STH1 and HRA1 are formed penetrating the first laminate LMs1 and the insulating layers 31, 32, and 34, as shown in FIG. 16(Bb). The holes STH1 and HRA1 are circular holes that terminate at the substrate SB2. The diameters of the holes STH1 and HRA1 are larger than the diameter of the memory hole MHA1. The diameter of the hole STH1 may be approximately equal to the diameter of the hole HRA1, or may be slightly larger than the diameter of the hole HRA1. As shown in FIG. 16(Cb), the multiple holes STH1 are arranged at a predetermined interval in the x direction. Next, amorphous carbon is filled into the holes STH1 and HRA1.

[0121] In contrast, Fig. 16(Ab) shows a cross section between a plurality of holes STH1 arranged at a predetermined interval in the x direction, and the holes STH1 are not provided in the cross section of Fig. 16(Ab). That is, as illustrated in Fig. 16(Cb), the holes STH1 are arranged at a predetermined interval in the x direction, so when the yz cross section is viewed, a cross section with holes STH1 and a cross section without holes STH1 are seen as in Figs. 16(Ab) and (Bb). Moreover, such holes STH1 are provided later to form the slits STA1 and the first plate-shaped portion ST21.

[0122] Next, as shown in FIG. 16(Ac) and (Bc), an insulating layer 36 is formed to cover the holes STH1, the holes HRA1, and the insulating layer 32. The insulating layer 36 is, for example, a silicon oxide layer. Next, a photoresist film (not shown) is applied onto the insulating layer 36, and the photoresist film is opened so that the portions between the holes STH1 are exposed. Using the photoresist film as a mask, the insulating layers 32 and 36 are dry-etched to a depth that does not reach the lower surface of the insulating layer 31. At least one of polysilicon and silicon carbonitride is embedded in the formed opening. This forms the first bridge portion BT21. As shown in FIG. 16(Cc), the first bridge portion BT21 is disposed in the portion between the holes STH1, and is not disposed above the holes STH1. That is, as shown in the cross section of FIG. 16(Bc), the first bridge portion BT21 is not formed at the position where the holes STH1 are disposed.

[0123] At this time, it is preferable that the width L4 in the x direction of the first bridge portion BT21 disposed in the portion between the holes STH1 is small. This is because the smaller the width L4, the less likely the first bridge portion BT21 will overlap the opening of the hole STH1, and the less likely the hole STH1 will be almost or completely covered by the first bridge portion BT21. If the first bridge portion BT21 covers most or all of the hole STH1, the first bridge portion BT21 may hinder dry etching when forming the hole STH2 on the hole STH1 later, and the hole STH1 and the hole STH2 may not be connected. As a result, the formation of the plate-like portion STJ may be hindered.

[0124] Next, the second laminated body LMs2 and the insulating layer 41 are formed in this order on the insulating layer 36, and as shown in Fig. 17(Bd), the second staircase portion SR2 and the insulating layer 43 covering the second staircase portion SR2 are formed. As shown in Fig. 17(Ad), a memory hole (not shown) is formed that penetrates the second laminated body LMs2 and the insulating layer 41 and connects to the memory hole MHA1, and a memory pillar MP is formed through a predetermined process.

[0125] Next, an insulating layer 42 is formed to cover the insulating layers 41 and 43, and holes STH2 and HRA2 are formed to penetrate the second laminate LMs2 and the insulating layers 41 to 43 as shown in FIG. 17(Be). At this time, the etching conditions for the holes STH2 and HRA2 have high selectivity for polysilicon or silicon carbonitride that constitutes the first bridge portion BT21. However, as described above, the first bridge portion BT21 is formed so as not to completely block the hole STH1, so the holes STH2 and HRA2 are connected to the upper ends of the holes STH1 and HRA1, respectively. The diameters of the holes STH2 and HRA2 are approximately equal to the diameters of the holes STH1 and HRA1, respectively. The hole STH2 is provided to later form the slit STA2 and the second plate-shaped portion ST22. In contrast, the hole STH2 is not formed in the cross section of FIG. 17(Ae).

[0126] Next, the amorphous carbon filled in the holes STH1 and HRA1 is removed by ashing or the like.

[0127] Next, as shown in FIG. 18(Bf), an insulating layer 70 is formed to cover the side walls of the holes STH1 and STH2, as well as the holes HRA1 and HRA2. The insulating layer 70 is, for example, a silicon oxide layer. Next, a silicon nitride layer NA is formed to cover the upper part of the hole STH2. The silicon nitride layer NA is formed to have a covering property to such an extent that it does not fill the inside of the hole STH2. Next, an insulating layer 44 is embedded in the holes HRA1 and HRA2 that are not covered by the silicon nitride layer NA. The insulating layer 44 is, for example, a silicon oxide layer. The silicon nitride layer NA is formed in a plate shape to cover the holes STH2 in the staircase region SA and the cell array region CA. Therefore, as in the cross section of FIG. 18(Af), the silicon nitride layer NA is formed even in the cross section where the hole STH2 is not formed, and the insulating layer 44 is further deposited.

[0128] 18(Ag) and (Bg), the insulating layer 44 deposited on the insulating layer 42 is removed by, for example, the CMP method, and then the silicon nitride layer NA is removed by a wet etching process. As a result, a hole STH2 is opened in the surface of the insulating layer 42. At this time, the sacrificial layers SN1 and SN2 are protected from the above-mentioned processing liquid by the insulating layer 70.

[0129] In FIG. 19(Ah) and (Bh), a silicon nitride layer NB having an opening OPG above the hole STH2 is formed on the insulating layer 42, and a processing liquid for wet etching is allowed to permeate through the opening OPG. The processing liquid enters through the opening OPG, passes through the hole STH2, and permeates to the lower end of the hole STH1. At this time, as described above, since the first bridge portion BT21 is formed so as not to completely block the hole STH1, the processing liquid can be allowed to permeate from the lower end of the hole STH2 to the hole SRH1. For this wet etching, a processing liquid having high selectivity to polysilicon and silicon carbonitride is selected, thereby preventing dissolution of the first bridge portion BT21.

[0130] As a result, the insulating layer 70, the sacrificial layers SN1 and SN2, and the insulating layers OL1 and OL2 exposed on the side walls of the holes STH1 and STH2 are dissolved, and the diameters of the holes STH1 and STH2 are expanded in the x and y directions. As a result, as shown in FIG. 19(Ch), the holes STH1 and STH2 adjacent to each other in the x direction are joined to form slits STA21 and STA22 extending in the x direction.

[0131] Also, as described above, the first bridge portion BT21 is formed so as not to completely block the hole STH1, so that the upper end of the slit STA21 and the lower end of the slit STA22 are connected from the lower end of the hole STH2 to the hole STH1.

[0132] At this time, it is preferable to form the silicon nitride layer NB thick. This allows the silicon nitride layer NB to remain on the insulating layer 42 until the slits STA21 and STA22 are formed, thereby protecting the insulating layer 42 from the above-mentioned processing liquid. In addition, the first bridge portion BT21 in Fig. 19(Ah) has resistance to the above-mentioned processing liquid, and therefore will remain until the slits STA21 and STA22 are formed.

[0133] In FIG. 19(Ai) and (Bi), amorphous carbon is filled into the slits STA21 and STA22, and then an insulating layer NC is formed to cover the slits STA21 and STA22 and the silicon nitride layer NB. The insulating layer NC is made of at least one of silicon oxide, polysilicon, and silicon carbonitride. Next, a photoresist film (not shown) is applied onto the insulating layer NC, and the photoresist film is opened at a position overlapping with the slit STA22 in the z direction. The opening of the photoresist film extends in the x direction so as to overlap a plurality of holes STH2 constituting the slit STA22. Using the photoresist film as a mask, the insulating layer NC is dry-etched to a depth that does not reach the bottom surface of the insulating layer NC, and then the photoresist film is removed by ashing. At this time, a part of the insulating layer NC remains on the top surface of the slit STA22 at the opening of the insulating layer NC, so that the amorphous carbon filled into the slits STA21 and STA22 is protected by the insulating layer NC and is not lost by ashing.

[0134] Next, the remaining film of the insulating layer NC is dry-etched until the amorphous carbon embedded in the slit STA22 is exposed, and then the etching gas is switched, and the silicon nitride layer NB, the insulating layer 42, and the amorphous carbon are dry-etched to a depth that does not reach the lower surface of the insulating layer 42, using the insulating layer NC in the region other than the opening as a mask. As a result, an opening OPH is formed at the upper end of the slit STA22 as shown in FIG. 19(Bi). In contrast, as shown in the cross section of FIG. 19(Ai), the opening OPH is not formed in the region where the second bridge portion BT22 is not formed. At this time, by using the insulating layer NC, which is a material different from the silicon nitride layer NB, as a mask, it is possible to reduce the risk of the silicon nitride layer NB being over-etched, even if, for example, the timing of switching the etching gas after the exposure of the amorphous carbon is shifted and etching continues with the gas before switching for a short time after the exposure of the amorphous carbon.

[0135] In Fig. 20(Bj), the opening OPH is filled with at least one of silicon oxide, polysilicon, and silicon carbonitride, which is the same material as the insulating layer NC. The deposits deposited on the insulating layer NC are removed together with the insulating layer NC, for example, by the CMP method. This forms the second bridge portion BT22. In contrast, Fig. 20(Aj) is a cross section in which the second bridge portion BT22 is not formed, as described above. In the portion in which the second bridge portion BT22 is not formed, amorphous carbon is exposed at the upper end of the slit STA2.

[0136] 20(Aj) and (Bj), the silicon nitride layer NB is removed by dry etching, and the amorphous carbon filled in the slits STA21 and STA22 is removed by ashing, etc. Thereafter, the semiconductor memory device 10 of the second embodiment is formed by performing processes corresponding to the processes in and after FIG.

[0137] According to the semiconductor memory device 10 of the second embodiment, the side surfaces in the y direction of the first and second plate-shaped portions ST21, ST22 have a waveform shape having periodicity in the x direction. As described above, the first and second plate-shaped portions ST21, ST22 are configured by connecting a plurality of holes STH1, STH2 and having a waveform shape in the y direction, whereby the holes STH1, STH2 that are the bases for forming the first and second plate-shaped portions ST21, ST22 and the holes HRA1, HRA2 that are the bases for forming the columnar portions HR can be formed collectively.

[0138] Here, the memory holes MHA1, MHA2 are processed under etching conditions suitable for processing the first and second laminates LMs1, LMs2 in which the sacrificial layers SN1, SN2 and the insulating layers OL1, OL2 are laminated. On the other hand, when forming a slit penetrating not only the first and second laminates LMs1, LMs2 but also the first and second interlayer insulating films 30, 40, as in the slits STA1, STA2 of the first embodiment, etching conditions different from the etching conditions of the memory holes MHA1, MHA2 are required. In addition, the columnar portion HR has a role of supporting the first and second laminates LMs1, LMs2 during the replacement process and does not contribute to the function of the semiconductor memory device 10, so it does not require precise processing like the memory holes MHA1, MHA2.

[0139] Therefore, by forming the memory holes MHA1, MHA2 separately, which require precise processing of the first and second laminates LMs1, LMs2, and forming the holes STH1, STH2 for processing the first and second plate-shaped portions ST21, ST22 in parallel with the holes HRA1, HRA2 for processing the columnar portion HR, the manufacturing load of the semiconductor memory device 10 can be reduced, and the manufacturing costs can be cut.

[0140] In this embodiment, the first bridge portion BT21 includes at least one of polysilicon and silicon carbonitride, and the second bridge portion BT22 includes at least one of silicon oxide, polysilicon, and silicon carbonitride. However, the materials used for the first bridge portion BT21 and the second bridge portion BT22 are not limited to the above examples. For example, any combination may be used as long as the first bridge portion BT21 has resistance to the processing liquid used when forming the slits STA21 and STA22.

[0141] (Variation 1) In the configuration of Modification 1 of Embodiment 2, a first plate-shaped portion ST31 and a first bridging portion BT31 are used instead of the first plate-shaped portion ST21 and the first bridging portion BT21 of Embodiment 2. Fig. 21 shows an example of the arrangement of the first bridging portion BT31 according to Modification 1 of Embodiment 2. The first bridging portion BT31 is arranged at an interval different from that of the first bridging portion BT21 on the upper end portion of the first plate-shaped portion ST31.

[0142] 21, the first bridge portion BT31 includes a plurality of first bridge portions BT31 arranged in the x direction. At least some of the plurality of first bridge portions BT31 are arranged at different intervals. Specifically, for example, the first bridge portions BT31 may be arranged to cover a part of the upper end portion of the first plate-shaped portion ST31 with the plurality of columnar portions S sandwiched therebetween, rather than being arranged at equal intervals so as to cover the connecting portions of the individual columnar portions S.

[0143] In this way, by appropriately varying the arrangement density of the first bridging portion BT31 according to the bridging strength required for the first bridging portion BT31, it is possible to reduce the manufacturing load of the semiconductor memory device 10 and cut manufacturing costs without forming an excessive number of the first bridging portion BT31.

[0144] (Variation 2) In the above-described second embodiment, the holes STH2 and HRA2 are formed using etching conditions that have selectivity with the first bridging portion BT21. However, the holes STH2 and HRA2 may be formed using etching conditions that do not have selectivity with the first bridging portion BT21.

[0145] In this case, when the first bridge portion BT21 is initially formed, the first bridge portion BT21 may be formed so as to cover the upper end portion of the hole STH1. This is because when the hole STH2 is formed at a position overlapping with the hole STH1 in the z direction, the lower end portion of the hole STH2 penetrates the first bridge portion BT21 covering the upper end portion of the hole STH1 and is connected to the hole STH1.

[0146] In the configuration of Modification 2 of Embodiment 2, a first plate-shaped portion ST41 and a first bridging portion BT41 are used instead of the first plate-shaped portion ST21 and the first bridging portion BT21 of Embodiment 2. Fig. 22 is a diagram showing an example of the arrangement of the first bridging portion BT41 according to Modification 2. The first bridging portion BT41 covers not only the connecting portion of the columnar portion S but also the columnar portion S at the upper end of the first plate-shaped portion ST41.

[0147] As shown in FIG. 22, the first bridge portion BT41 is disposed so as to straddle a plurality of columnar portions S. Here, the holes STH1 in the layer of the first bridge portion BT41 are not connected in the x direction even after the hole STH1 and hole STH2 are connected. This is because the material constituting the first bridge portion BT41 is not dissolved in the wet etching process that connects the holes STH1 and STH2. Therefore, after the plurality of columnar portions S having the liner layer LL and the conductive portion EC therein are formed, the portion of the hole STH1 extending in the layer of the first bridge portion BT41 becomes a plurality of columnar portions Z that are not connected to each other. The columnar portion Z has a liner layer LL and a conductive portion EC therein, like the columnar portion S. However, unlike the liner layer LL and the conductive portion EC of the columnar portion S, the liner layer LL of the columnar portion Z has a shape that is closed in a circular ring shape independent of each other, and the conductive layer EC exists independently of each other within the circular ring of the liner layer LL. Further, the columnar portion Z is connected at its lower end to the first plate-shaped portion ST21, and is connected at its upper end to the lower end of the second plate-shaped portion ST22.

[0148] In this way, by adopting etching conditions that have no selectivity with respect to the first bridging portion BT21 as the processing conditions for hole STH2 and hole HRA2, the alignment accuracy of the first bridging portion BT21 relative to hole STH1 can be reduced, thereby reducing the manufacturing load of the semiconductor memory device 10 and reducing manufacturing costs.

[0149] Furthermore, compared with the first bridge portion BT21 according to the second embodiment, which covers the tops of the side portions Sb individually, the first bridge portion BT41, which is disposed so as to straddle a plurality of columnar portions S, has a larger installation volume, and therefore improves the support strength of the insulating layer 32. As a result, it becomes possible to further suppress the bending and inclination of the layer.

[0150] 20 and 21 are merely examples and are not intended to be limiting. The x-direction length, adjacent interval, number, etc. of the first cross-linking portion BT31 and the first cross-linking portion BT41 may be appropriately determined.

[0151] (Other embodiments) In the above-mentioned first and second embodiments and their modifications, the semiconductor memory device has a two-tier stack structure including a first stack body LM1 and a second stack body LM2. However, the semiconductor memory device may have a three-tier or more stack structure. In a multi-tier type semiconductor memory device, it is easy to further increase the number of stacks of the conductive layers WL.

[0152] In the above-mentioned first and second embodiments and their modified examples, the plate-shaped parts STL and STJ have the conductive parts EC, but are not limited thereto. For example, the plate-shaped parts STL and STJ may be entirely made of an insulating material such as silicon oxide. In this case, such plate-shaped parts STL and STJ do not function as source line contacts.

[0153] Specifically, the first plate-shaped portion ST21 extends along the x direction, penetrates the laminate LM1 in the z direction, and has silicon oxide, while the second plate-shaped portion ST22 extends along the x direction, penetrates the laminate LM2 in the z direction, connects to the upper end of the first plate-shaped portion ST21, and has silicon oxide. The first bridge portion BT21 is disposed at the upper end of the first plate-shaped portion ST21, has a material different from silicon oxide, and connects the first interlayer insulating film 30 on both sides of the first plate-shaped portion ST21. Silicon oxide is an example of a first insulating material.

[0154] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0155] 1, 1x, 2, 10...semiconductor memory device, 30...first interlayer insulating film, 40...second interlayer insulating film, 31, 32, 33, 34, 41, 42, 43, 44, 50, 51, 52, 70...insulating layer, 35...sidewall layer, BTx...bridge portion, BT1, BT11, BT21...first bridge portion, BT2, BT22...second bridge portion, CA...cell array region, CC...contact, HRA1, HRA2...hole, LMs1, LM1...first stacked body, LMs2, LM2...second stacked body, MP...memory pillar -, NA, NB...silicon nitride layer, NC...insulating layer, OL1...insulating layer, OL2...insulating layer, PER...peripheral circuit section, SA...staircase region, SB1, SB2...substrate, SN1...sacrificial layer, SN2...sacrificial layer, SR...staircase section, SR1...first staircase section, SR2...second staircase section, ST1, ST21...first plate-shaped section, ST2, ST22...second plate-shaped section, STA1, STA2, STA21, STA22, STAx...slit, Tr...transistor, V, V1, V2...via, WL1...conductive layer, WL2...conductive layer.

Claims

1. a first laminate in which a plurality of first conductive layers and a plurality of first insulating layers are alternately laminated one by one, and the plurality of first conductive layers include a first step portion processed into a step shape extending in a first direction intersecting a lamination direction of the first conductive layers; a first interlayer insulating film covering the first step portion; a second laminate provided above the first laminate, in which a plurality of second conductive layers and a plurality of second insulating layers are alternately laminated one by one, and the plurality of second conductive layers include a second step portion processed into a step shape that is continuous with the first step portion in the first direction; a second interlayer insulating film covering the second step portion; a first plate-shaped portion extending along the first direction and penetrating the first stack in the stacking direction; a second plate-shaped portion extending along the first direction and penetrating the second stack in the stacking direction to connect to an upper end of the first plate-shaped portion; a first bridge portion disposed on an upper end of the first plate-shaped portion and connecting the first interlayer insulating film on both sides of the first plate-shaped portion; a second bridge portion disposed on an upper end of the second plate-shaped portion and connecting the second interlayer insulating film on both sides of the second plate-shaped portion; Equipped with Lower ends of the first and second bridge portions are located above the first and second conductive layers which are uppermost layers of the first and second laminates, respectively. Semiconductor memory device.

2. the first and second plate-like portions and at least a portion of the first bridge portion have a conductive portion containing a conductive material, a width in a second direction intersecting the first direction and the stacking direction of the conductive portion of the first bridge portion is equal to or smaller than a width in the second direction of the conductive portion of an upper end portion of the first plate-shaped portion; 2. The semiconductor memory device according to claim 1.

3. The side surfaces of the first and second plate-shaped portions in the second direction have a wave shape having periodicity in the first direction.

3. The semiconductor memory device according to claim 2.

4. The first and second plate-like portions have a shape in which a plurality of columnar portions extending in the stacking direction are connected to each other in the first direction.

4. The semiconductor memory device according to claim 3.

5. the first bridge portion includes at least one material selected from the group consisting of polysilicon and silicon carbonitride; The second bridge portion contains at least one material selected from the group consisting of silicon oxide, polysilicon, and silicon carbonitride.

4. The semiconductor memory device according to claim 3.

6. the first bridge portion includes a plurality of first bridge portions aligned in the first direction, The intervals between the plurality of first cross-linking portions are at least partially different.

2. The semiconductor memory device according to claim 1.

7. At least a portion of the first bridge portion does not overlap with at least a portion of the second bridge portion in the stacking direction.

2. The semiconductor memory device according to claim 1.

8. the first bridge portion is disposed so as to straddle the plurality of columnar portions in the first direction, and the first bridge portion has a plurality of columnar portions that are not connected to each other and are connected to the first and second plate-like portions in the stacking direction; 5. The semiconductor memory device according to claim 4.

9. a first laminate in which a plurality of first conductive layers and a plurality of first insulating layers are alternately laminated one by one, and the plurality of first conductive layers include a first step portion processed into a step shape extending in a first direction intersecting a lamination direction of the first conductive layers; a first interlayer insulating film covering the first step portion; a second laminate provided above the first laminate, in which a plurality of second conductive layers and a plurality of second insulating layers are alternately laminated one by one, and the plurality of second conductive layers include a second step portion processed into a step shape that is continuous with the first step portion in the first direction; a second interlayer insulating film covering the second step portion; a first plate-shaped portion extending along the first direction, penetrating the first laminate in the stacking direction, and having a first insulating material; a second plate-shaped portion extending along the first direction, penetrating the second laminate in the stacking direction, connected to an upper end of the first plate-shaped portion, and having the first insulating material; a bridge portion that is disposed on an upper end of the first plate-shaped portion, has a material different from the first insulating material, and connects the first interlayer insulating film on both sides of the first plate-shaped portion; Equipped with side surfaces of the first and second plate-like portions in a second direction intersecting the first direction and the stacking direction have a wave-shaped shape having periodicity in the first direction, a lower end portion of the bridge portion is located above the first conductive layer which is an uppermost layer in the first laminate; Semiconductor memory device.

10. a first laminate including a plurality of first insulating layers and a plurality of second insulating layers alternately laminated one by one, the plurality of second insulating layers including a first staircase portion processed into a staircase shape extending in a first direction intersecting a lamination direction of the second insulating layers; forming a first interlayer insulating film covering the first step portion; a first groove portion is formed penetrating the first laminate in a stacking direction and extending along the first direction; forming a first bridge portion at an upper end of the first trench portion, the first bridge portion connecting both sides of the first trench portion to the first interlayer insulating film and having a lower end portion located above the second insulating layer; a second laminate is formed above the first laminate, in which a plurality of third insulating layers and a plurality of fourth insulating layers are alternately laminated one by one in the lamination direction, and the plurality of fourth insulating layers include the first staircase portion and a second staircase portion processed into a staircase shape continuous with the first direction; forming a second interlayer insulating film covering the second step portion; a second groove portion is formed penetrating the second laminate in a stacking direction and extending along the first direction; forming a second bridge portion at an upper end of the second trench portion, the second bridge portion connecting both sides of the second interlayer insulating film to the second trench portion, and the lower end of the second bridge portion being located above the fourth insulating layer; A method for manufacturing a semiconductor memory device.

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