Semiconductor device

Abstract

To prevent an increase of on-resistance and improve avalanche resistance.SOLUTION: A semiconductor device comprises: a first electrode and a second electrode provided respectively on a first principal surface and a second principal surface of a semiconductor layer; a first semiconductor region of a first conductivity type provided in the semiconductor layer; a plurality of insulating regions reaching the first semiconductor region from the first principal surface, and extending in a second direction orthogonal to a first direction directed from the second electrode to the first electrode; a plurality of third electrodes provided in the plurality of insulating regions and extending in the second direction; a second semiconductor region of a second conductivity type sandwiched between the plurality of insulating regions, located on the first semiconductor region, and extending in the second direction; a third semiconductor region of the first conductivity type located between the second semiconductor region and the first electrode; and a carrier conducting part extending in the second direction in the second semiconductor region, and electrically connected to the first electrode through a connection part not penetrating the third semiconductor region.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] Power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) are used in inverters for driving motors, etc. Power MOSFETs need to have avalanche resistance so that the elements are not destroyed by the back electromotive force generated during switching operations.

[0003] One method for improving the avalanche resistance is to suppress the operation of the parasitic bipolar of the MOSFET. Since the parasitic bipolar is easily activated by the minority carriers accumulated in the base region, the avalanche resistance can be improved by discharging the minority carriers accumulated in the base region to the outside. Therefore, for example, a contact made of a p-type semiconductor region or a metal material is formed so as to penetrate from the source electrode through the source region to the base layer. However, since such a contact is provided so as to penetrate the source region, the area of ​​the source region is reduced, and the on-resistance of the semiconductor device is increased. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent Publication No. 2022-49656 [Patent Document 2] JP 2022-97649 A [Patent Document 3] JP 2022-139078 A [Patent Document 4] International Publication No. 2021 / 100206 Brochure [Patent Document 5] JP 2019-186459 A [Patent Document 6] JP 2018-46256 A Summary of the Invention [Problem to be solved by the invention]

[0005] An embodiment of the present invention provides a semiconductor device capable of improving avalanche resistance while suppressing an increase in on-resistance. [Means for solving the problem]

[0006] The semiconductor device according to this embodiment includes a semiconductor layer having a first main surface and a second main surface, a first electrode provided on the first main surface, a second electrode provided on the second main surface, a first semiconductor region of a first conductivity type provided in the semiconductor layer and located on the second electrode, a plurality of insulating regions provided in the semiconductor layer, extending from the first main surface to the first semiconductor region and in a second direction perpendicular to a first direction from the second electrode to the first electrode, a plurality of third electrodes provided in the plurality of insulating regions and extending in the second direction, a second semiconductor region of a second conductivity type sandwiched between the plurality of insulating regions in the semiconductor layer, located on the first semiconductor region, and extending in the second direction, a third semiconductor region of the first conductivity type provided in the semiconductor layer and located between the second semiconductor region and the first electrode, and a carrier conducting portion provided in the second semiconductor region so as to extend in the second direction, the carrier conducting portion being electrically connected to the first electrode via a connection portion that does not penetrate the third semiconductor region. [Brief description of the drawings]

[0007] [Figure 1] 1 is a plan view of a semiconductor device according to a first embodiment. [Diagram 2] 2 is a cross-sectional view of the semiconductor device according to the first embodiment, taken along line II in FIG. [Diagram 3] 2 is another cross-sectional view of the semiconductor device according to the first embodiment, showing a part of the cross section taken along line II-II in FIG. [Figure 4A] 2A to 2C are cross-sectional views illustrating an example of a manufacturing process for the semiconductor device according to the first embodiment. [Figure 4B] 4B is a cross-sectional view illustrating an example of a manufacturing process of the semiconductor device according to the first embodiment, subsequent to FIG. 4A. [Figure 4C] 4B, a cross-sectional view for explaining an example of a manufacturing process of the semiconductor device according to the first embodiment. FIG. [Figure 4D] 4D is a cross-sectional view illustrating an example of a manufacturing process of the semiconductor device according to the first embodiment, subsequent to FIG. 4C. [Diagram 5] 2 is a cross-sectional view of the semiconductor device according to the second embodiment, taken along line II in FIG. 1. [Figure 6] 1. FIG. 4 is another cross-sectional view of the semiconductor device according to the second embodiment, showing a part of the cross section taken along line II-II in FIG. [Figure 7A] 10A to 10C are cross-sectional views for explaining an example of a manufacturing process of the semiconductor device according to the second embodiment. [Figure 7B] 7B is a cross-sectional view illustrating an example of a manufacturing process of the semiconductor device according to the second embodiment, subsequent to FIG. 7A. [Figure 7C] 7B; and FIG. 8 is a cross-sectional view illustrating an example of a manufacturing process of the semiconductor device according to the second embodiment. [Figure 7D] 7D is a cross-sectional view illustrating an example of a manufacturing process of the semiconductor device according to the second embodiment, subsequent to FIG. 7C. [Figure 7E] 7D, a cross-sectional view illustrating an example of a manufacturing process of the semiconductor device according to the second embodiment. FIG. [Figure 8] FIG. 11 is a plan view of a semiconductor device according to a third embodiment. [Figure 9] 9 is a cross-sectional view of the semiconductor device according to the third embodiment, taken along line III-III in FIG. 8. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The embodiment does not limit the present invention. The drawings are schematic or conceptual, and the ratio of each part is not necessarily the same as the actual one. In the specification and drawings, elements similar to those described above with respect to the previous drawings are given the same reference numerals, and detailed descriptions are omitted as appropriate.

[0009] For convenience of explanation, an XYZ orthogonal coordinate system is adopted as shown in Figs. 1 to 3. The Z-axis direction is the stacking direction (thickness direction) of the semiconductor device. In addition, in the Z-axis direction, the source electrode side is also called "upper" and the drain electrode side is also called "lower". However, this expression is for convenience and has no relation to the direction of gravity. The X-axis direction is the second direction in the claims. The Z-axis direction is the first direction in the claims.

[0010] In the following description, n + , n, n - , and p + , p, p - In some cases, the notation n + has a relatively higher n-type impurity concentration than n, - indicates that the n-type impurity concentration is relatively lower than that of n. + has a relatively higher p-type impurity concentration than p, - indicates that the p-type impurity concentration is relatively lower than p. These notations indicate the relative highs and lows of the net impurity concentration after the impurities compensate for each other when both p-type and n-type impurities are contained in each region. n-type, n + Shape and n - The p-type is an example of the first conductivity type in the claims. + Shape and p - The n-type is an example of the second conductivity type in the claims. In the following description, the n-type and p-type may be reversed. In other words, the first conductivity type may be the p-type.

[0011] (First embodiment) <Semiconductor device> A semiconductor device 1 according to a first embodiment will be described with reference to Fig. 1 to Fig. 3. Fig. 1 is a plan view of the semiconductor device according to the first embodiment. Fig. 2 is a cross-sectional view of the semiconductor device according to the first embodiment, taken along line II in Fig. 1. Fig. 3 is another cross-sectional view of the semiconductor device according to the first embodiment, taken along line II-II in Fig. 1.

[0012] The semiconductor device 1 according to this embodiment is a vertical MOSFET, etc. Below, a case where the semiconductor device 1 is a vertical MOSFET will be described.

[0013] As shown in Fig. 2, the semiconductor device 1 includes a semiconductor layer 2, a source electrode 11 provided on an upper surface (first main surface) 2a of the semiconductor layer 2, and a drain electrode 12 provided on a lower surface (second main surface) 2b of the semiconductor layer 2. Note that the source electrode 11 provided on the upper surface 2a of the semiconductor layer 2 and an interlayer insulating film 32 described below are omitted in Fig. 1. In addition, in order to make the drawing easier to understand, only one of a plurality of carrier conduction portions 41 is illustrated in Fig. 1. For convenience of explanation, the upper surface 2a and the lower surface 2b of the semiconductor layer 2 are approximately planar, but this does not limit the shape of the semiconductor layer 2.

[0014] The semiconductor layer 2 is disposed on the drain electrode 12. The semiconductor layer 2 may be an epitaxial layer, a semiconductor substrate, or a semiconductor substrate and an epitaxial layer disposed thereon. In this embodiment, the semiconductor layer 2 is silicon (Si). In this case, for example, arsenic (As), phosphorus (P), or antimony (Sb) is used as the n-type impurity, and for example, boron (B) is used as the p-type impurity. The semiconductor layer 2 may be made of a compound semiconductor such as silicon carbide (SiC) or gallium nitride (GaN).

[0015] The source electrode 11 is an electrode that functions as a source electrode of the MOSFET. The source electrode 11 is made of, for example, copper (Cu), titanium (Ti), tungsten (W), aluminum (Al), etc. The source electrode 11 is an example of a first electrode in the claims.

[0016] The drain electrode 12 is an electrode that functions as a drain electrode of the MOSFET. The drain electrode 12 is made of a metal such as copper, titanium, tungsten, aluminum, etc. The drain electrode 12 is an example of a second electrode in the claims.

[0017] The semiconductor layer 2 includes a drift region 21, a drain region 24, a gate insulating film 31, a gate electrode 13, a base region 221, a connection region 222, a connection region 223, and a source region 23. An interlayer insulating film 32 is provided on a part of an upper surface 2a of the semiconductor layer 2. Each component provided in the semiconductor layer 2 will be described below.

[0018] The drift region 21 is a semiconductor region that functions as a drift region of the MOSFET. The drift region 21 is disposed above the drain region 24 (above the drain electrode 12). The drift region 21 is, for example, an n - The n-type impurity concentration of the drift region 21 is, for example, 1×10 15 cm -3 More than 2×10 16 cm -3 The drift region 21 is an example of a first semiconductor region in the claims.

[0019] The drain region 24 is disposed between the drift region 21 and the drain electrode 12. The drain region 24 is a semiconductor region that functions as a drain region of the MOSFET. The drain region 24 is, for example, an n + The n-type impurity concentration of the drain region 24 is, for example, 1×10 18 cm -3 More than 1×10 21 cm -3The drain region 24 is an example of a first semiconductor region in the claims.

[0020] It should be noted that the first semiconductor region in the claims may include both the drift region 21 and the drain region 24, or may include either the drift region 21 or the drain region 24.

[0021] As shown in FIG. 3, a plurality of gate insulating films 31 are provided so as to reach the drift region 21 from the upper surface 2a of the semiconductor layer 2. As shown in FIG. 1, each gate insulating film 31 extends in the X direction. The gate insulating film 31 is made of a dielectric material covering the side walls of a plurality of gate trenches provided in the upper surface 2a of the semiconductor layer 2 so as to extend in the X direction. The gate insulating film 31 is made of a dielectric material such as silicon oxide or silicon nitride. The gate insulating film 31 is an example of an insulating region in the claims. In this embodiment, the gate trenches are provided in the upper surface 2a of the semiconductor layer 2, but this does not limit the shape of the semiconductor layer 2.

[0022] As shown in FIG. 3, a gate electrode 13 is provided in each gate insulating film 31. The gate electrode 13 functions as a gate electrode of a MOSFET. Each gate electrode 13 extends in the X direction. The gate electrode 13 is electrically insulated from the semiconductor layer 2 by the gate insulating film 31. In the example shown in FIG. 3, the upper end of the gate electrode 13 is located higher than the upper end of a base region 221 described later, and the lower end of the gate electrode 13 is located lower than the lower end of the base region 221. The gate electrode 13 is disposed adjacent to (facing) the base region 221 via the gate insulating film 31. The gate electrode 13 is made of, for example, polysilicon containing p-type or n-type impurities. The gate electrode 13 is an example of a third electrode in the claims.

[0023] Although not shown, a field plate (FP) electrode may be provided below the gate electrode 13 in each gate insulating film 31. Each FP electrode is electrically connected to the source electrode 11. By providing such an FP electrode, when the MOSFET is in an off state, a depletion layer extends into the drift region 21 around the FP electrode due to a voltage applied between the source electrode 11 and the drain electrode 12. This depletion layer connects with the depletion layer extending around the adjacent FP electrode, and the breakdown voltage of the semiconductor device 1 can be improved.

[0024] As shown in FIG. 3, the base regions 221 are provided so as to be sandwiched between the gate insulating films 31. As shown in FIG. 2, the base regions 221 are located on the drift regions 21 and extend in the X-axis direction. The base regions 221 are semiconductor regions that function as the base regions of the MOSFET. When a voltage is applied to the gate electrode 13, a channel is formed in the base regions 221, and carriers flow between the drift regions 21 and the source regions 23. The base regions 221 are, for example, p-type semiconductor regions. The p-type impurity concentration of the base regions 221 is, for example, 1×10 16 cm -3 More than 1×10 20 cm -3 The base region 221 is an example of a second semiconductor region in the claims.

[0025] As shown in FIG. 2, a connection region 222 and a connection region 223 are provided between both ends of the base region 221 in the X-axis direction and the source electrode 11. More specifically, the connection region 222 extends along the Z-axis direction from one end of the base region 221 in the X-axis direction (the left end in FIG. 2) to the source electrode 11, and connects the base region 221 and the source electrode 11. The connection region 223 extends along the Z-axis direction from the other end of the base region 221 in the X-axis direction (the right end in FIG. 2) to the source electrode 11, and connects the base region 221 and the source electrode 11. The connection region 222 is an example of a first connection region in the claims. The connection region 223 is an example of a second connection region in the claims.

[0026] The connection region 222 and the connection region 223 separate the drift region 21 from a source region 23 described later, and separate the drift region 21 from a connection portion 42 described later. In this embodiment, the connection region 222 and the connection region 223 are p-type semiconductor regions having the same impurity concentration as the base region 221. This allows the base region 221, the connection region 222, and the connection region 223 to be formed collectively. Note that either or both of the connection region 222 and the connection region 223 may be p-type semiconductor regions having a different impurity concentration from the base region 221, or may be insulating regions made of an insulating material such as silicon oxide or silicon nitride.

[0027] In addition, in this embodiment, the connection regions 222 and 223 have the same width in the X-axis direction, but the connection regions 222 and 223 may have different widths in the X-axis direction.

[0028] A carrier conducting portion 41 is provided in each base region 221. As shown in FIG. 1 and FIG. 2, the carrier conducting portion 41 extends in the X-axis direction. As shown in FIG. 3, the carrier conducting portion 41 is provided at a position equidistant from adjacent gate electrodes 13 in the Y-axis direction, and is located at the center of the base region 221 in the Z-axis direction. The position of the carrier conducting portion 41 in the Y-axis direction may be biased toward one of the adjacent gate electrodes 13 as long as it is within a range where it does not contact the gate insulating film 31. The position of the carrier conducting portion 41 in the Z-axis direction may not be located at the center of the base region 221 as long as it is within a range where it does not contact the drift region 21. For example, the upper end of the carrier conducting portion 41 may be at approximately the same height as the upper end of the base region 221.

[0029] The carriers stored in the base region 221 are conducted inside the carrier conduction region 41. In this embodiment, the carrier conduction region 41 has a p + The p-type impurity concentration of the carrier conduction portion 41 is, for example, 5×10 18 cm -3 More than 1×10 22cm -3 In this manner, carrier conduction portion 41 has a higher p-type impurity concentration than base region 221, so that carriers move more easily in carrier conduction portion 41 than in base region 221.

[0030] Moreover, the carrier conducting portion 41 is electrically connected to the source electrode 11 through a connection portion that does not penetrate the source region 23 (is not sandwiched between the source regions 23). The minority carriers injected from the base region 221 into the carrier conducting portion 41 pass through this connection portion and are conducted toward the source electrode 11. As shown in FIG. 2, in this embodiment, the connection portion 42 is provided in each of the connection regions 222 and 223, and electrically connects the carrier conducting portion 41 and the source electrode 11. More specifically, the connection portion 42 in the connection region 222 electrically connects one end (the left end in FIG. 2) of the carrier conducting portion 41 to the source electrode 11. The connection portion 42 in the connection region 223 electrically connects the other end (the right end in FIG. 2) of the carrier conducting portion 41 to the source electrode 11. None of the connection portions 42 penetrate the source region 23. As a result, the carriers that move in the carrier conducting portion 41 and reach both ends of the carrier conducting portion 41 pass through the connection portion 42 and are discharged to the source electrode 11. The connection portion 42 includes a metal or polysilicon doped with an impurity. The connection portion 42 may be formed of a semiconductor region of the second conductivity type. The connection portion 42 in the connection region 222 is an example of a connection portion in the claims. The connection portion 42 in the connection region 223 is an example of a second connection portion in the claims.

[0031] It is to be noted that either connection region 222 or connection region 223 may be omitted. In this case, carrier conducting portion 41 and source electrode 11 are electrically connected by connection portion 42 provided in the remaining other connection region.

[0032] As shown in FIG. 2, the connection portion 42 in the connection region 222 is located at the center of the connection region 222 in the X-axis direction. That is, the width W1 of the connection region 222 between the connection portion 42 and the source region 23 is approximately equal to the width W2 of the connection region 222 between the connection portion 42 and the drift region 21. Also, the connection portion 42 in the connection region 223 is located at the center of the connection region 223 in the X-axis direction. That is, the width W3 of the connection region 223 between the connection portion 42 and the source region 23 is approximately equal to the width W4 of the connection region 223 between the connection portion 42 and the drift region 21. Note that, in order to secure a margin for misalignment of the connection portion 42 in the X-axis direction, the width W1 may be larger than the width W2, the width W3 may be larger than the width W4, or conversely, the width W2 may be larger than the width W1, and the width W4 may be larger than the width W3.

[0033] 2, a source region 23 is provided between the base region 221 and the source electrode 11. The source region 23 is a semiconductor region that functions as a source region of the MOSFET. The source region 23 is, for example, an n + The source region 23 has an n-type impurity concentration of, for example, 1×10 18 cm -3 More than 1×10 22 cm -3 The source region 23 is an example of a third semiconductor region in the claims.

[0034] 1, a gate pad 50 and a gate wiring 51 connected to the gate pad 50 are provided on the upper surface 2a of the semiconductor layer 2. The multiple gate electrodes 13 are electrically connected to the gate pad 50 via the gate wiring 51.

[0035] The planar shape of the semiconductor device 1, that is, the arrangement of the components on the upper surface 2a of the semiconductor layer 2, is not limited to the example shown in FIG. 1, and may be arbitrary.

[0036] <Method of Manufacturing Semiconductor Device> Next, an example of a method for manufacturing the semiconductor device 1 according to this embodiment will be described with reference to Figures 4A to 4D. Figures 4A to 4D are process cross-sectional views for explaining the method for manufacturing the semiconductor device 1, and correspond to a part of the cross section taken along line II-II in Figure 1.

[0037] First, as shown in FIG. 4A, a semiconductor layer is prepared, which includes a drift region 21, a gate insulating film 31 extending from an upper surface 2a to the drift region 21, a plurality of gate electrodes 13 provided in each gate insulating film 31, and a plurality of base regions 221 sandwiched between the gate insulating films 31.

[0038] This semiconductor layer is obtained, for example, as follows. First, a semiconductor layer including a drift region 21 is prepared. Then, a gate trench is formed from the upper surface 2a of the semiconductor layer by reactive ion etching (RIE) or the like. Then, an insulating material is deposited in the gate trench by chemical vapor deposition (CVD) or the like to form a gate insulating film 31. Then, a part of the gate insulating film 31 is removed by RIE or the like.

[0039] Thereafter, a conductive material such as polysilicon is deposited by CVD or the like, and the excess conductive material is etched back to form the gate electrode 13. Thereafter, an insulating material is deposited by CVD or the like to bury the gate electrode 13.

[0040] Thereafter, p-type impurities are ion-implanted into the upper surface 2a of the semiconductor layer to form the base region 221, the connection region 222, and the connection region 223. More specifically, the base region 221 is formed by ion-implanting p-type impurities into the surface of the upper surface 2a of the semiconductor layer that is sandwiched between the gate insulating film 31. The connection region 222 and the connection region 223 are formed by ion-implanting p-type impurities into the periphery of both ends of the gate insulating film 31 in the X-axis direction of the upper surface 2a of the semiconductor layer. The connection region 222 and the connection region 223 may be formed in the same ion implantation process as the base region 221.

[0041] Through the above steps, the semiconductor layer shown in FIG. 4A is formed.

[0042] Next, as shown in FIG. 4B, p-type impurities are ion-implanted into base region 221 to form carrier conduction portion 41.

[0043] Next, as shown in Fig. 4C, n-type impurities are ion-implanted into carrier conduction section 41 from upper surface 2a, thereby reducing the p-type impurity concentration in the upper part of carrier conduction section 41. In the example shown in Fig. 4C, the p-type impurity concentration in the upper part of carrier conduction section 41 is reduced to the same level as that of base region 221. Note that the resist or the like used in forming carrier conduction section 41 may be used as is for the ion implantation in this step.

[0044] Next, as shown in FIG. 4D, an n-type impurity is ion-implanted into the base region 221 from the upper surface 2a to form the source region 23.

[0045] Next, although not shown, trenches are formed in the connection regions 222 and 223 by RIE or the like, so as to extend from the upper surface 2a to the carrier conduction portion 41. Thereafter, a conductive material is deposited by CVD, physical vapor deposition (PVD), or the like so as to fill the trenches, thereby forming the connection portions 42. The conductive material is, for example, a metal material containing copper, titanium, tungsten, aluminum, or the like, or polysilicon. In the case of polysilicon, it may contain p-type or n-type impurities.

[0046] Next, an interlayer insulating film 32 for insulating the source electrode 11 from the drift region 21 is formed on a part of the upper surface 2a of the semiconductor layer 2. Thereafter, the source electrode 11 is formed so as to be buried in the interlayer insulating film 32 and to be in contact with the source region 23.

[0047] Next, an n-type impurity is ion-implanted into the lower surface 2b of the semiconductor layer 2 to form a drain region 24. Thereafter, the drain electrode 12 is formed so as to cover the lower surface 2b of the semiconductor layer 2.

[0048] Through the above steps, the semiconductor device 1 is manufactured.

[0049] As described above, the semiconductor device 1 according to this embodiment includes carrier conducting portion 41 that is provided to extend in the X-axis direction in base region 221 and is electrically connected to source electrode 11 via connecting portion 42 that does not penetrate source region 23. This allows minority carriers remaining in base region 221 to be quickly discharged to source electrode 11 by carrier conducting portion 41 and connecting portion 42 while maintaining the area of ​​source region 23 on upper surface 2a of semiconductor layer 2.

[0050] Therefore, according to this embodiment, the avalanche resistance of the semiconductor device 1 can be improved while suppressing an increase in the on-resistance.

[0051] In addition, when a contact is provided from the upper surface 2a of the semiconductor layer 2 to the base region 221 instead of providing the carrier conduction portion 41 in the base region 221, the contact needs to extend in the X-axis direction in order to fully discharge the minority carriers remaining in the base region 221. However, when forming such a contact, there is a possibility that misalignment in the Y-axis direction occurs, and the position of the contact is shifted in the Y-axis direction from the center of the source region 23. In this case, the area of ​​a part of the source region 23 on the upper surface 2a of the semiconductor layer 2 becomes smaller, which increases the resistance, and therefore the on-resistance of the semiconductor device may increase. In addition, when the contact is made of a p-type semiconductor region, the base region 221 between the contact and the gate insulating film 31 becomes narrow, making it difficult to form a channel. As a result, there is a possibility that the threshold voltage of the MOSFET is affected.

[0052] On the other hand, in the semiconductor device 1 according to this embodiment, the carrier conducting portion 41 is embedded in the base region 221 and is formed independently of (without interfering with) the source region 23. This makes it possible to suppress the influence of the positional deviation of the carrier conducting portion 41 in the Y-axis direction on the source region 23. For example, even if the position of the carrier conducting portion 41 is deviated in the Y-axis direction, it is possible to suppress the occurrence of a conductive path with high resistance in the source region 23, and to suppress an increase in the on-resistance of the semiconductor device 1. In addition, the influence on the threshold voltage can also be suppressed.

[0053] Second Embodiment A semiconductor device 1A according to the second embodiment will be described with reference to Fig. 5 and Fig. 6. Fig. 5 is a cross-sectional view of the semiconductor device 1A according to the second embodiment, showing a part of the cross section taken along line II in Fig. 1. Fig. 6 is another cross-sectional view of the semiconductor device 1A according to the second embodiment, showing a part of the cross section taken along line II-II in Fig. 1.

[0054] One of the differences between the second embodiment and the first embodiment is the material constituting the carrier conduction portion. The following describes a semiconductor device 1A according to this embodiment, focusing on the differences from the first embodiment.

[0055] 5 and 6, the semiconductor device 1A according to this embodiment includes a carrier conducting portion 43 instead of the carrier conducting portion 41 of the first embodiment. The carrier conducting portion 43 is a conductor including a metal or polysilicon doped with an impurity. This makes it easier for carriers to move in the carrier conducting portion 43 than in the base region 221, as in the first embodiment.

[0056] 6 within a range where carrier conduction portion 43 does not contact drift region 21. For example, the upper end of carrier conduction portion 43 may be at approximately the same height as the upper end of base region 221.

[0057] <Manufacturing method of the second embodiment> Next, an example of a method for manufacturing the semiconductor device 1A according to this embodiment will be described with reference to Fig. 4A and Fig. 7A to Fig. 7E. Fig. 7A to Fig. 7E are process cross-sectional views for explaining the method for manufacturing the semiconductor device 1A, and correspond to a part of the cross section taken along line II-II in Fig. 1.

[0058] First, similarly to the first embodiment, a semiconductor layer shown in FIG. 4A is prepared.

[0059] 7A, the base region 221 is partially removed by RIE or the like to form a trench T1. In this embodiment, trenches (not shown) are also formed in the connection region 222 and the connection region 223 at the same time as the trench T1 is formed.

[0060] 7B, a conductive material is deposited by CVD, PVD, or the like to fill trench T1, thereby forming carrier conduction portion 43. In this embodiment, simultaneously with the formation of carrier conduction portion 43, a conductive material is also deposited in connection region 222 and the trench formed in connection region 223, thereby forming connection portion 42. The conductive material is, for example, a metal material containing copper, titanium, tungsten, aluminum, or the like, or polysilicon, or the like.

[0061] 7C, a portion of the deposited carrier conduction portion 43 is removed by wet etching or the like to form a trench T2 on carrier conduction portion 43. Note that connection portion 42 is not removed in connection region 222 and connection region 223.

[0062] 7D, a p-type epitaxial layer is grown to embed carrier conduction portion 43 in base region 221. Note that the p-type epitaxial layer is also formed on base region 221 of upper surface 2a of the semiconductor layer, but this portion is removed by RIE, CMP (Chemical Mechanical Polishing), or the like.

[0063] Next, as shown in FIG. 7E, an n-type impurity is ion-implanted into the upper part of the base region 221 to form the source region 23.

[0064] Next, in the same manner as in the first embodiment, the interlayer insulating film 32, the drain region 24 and the drain electrode 12 are formed.

[0065] Through the above steps, the semiconductor device 1A is manufactured.

[0066] As described above, according to the semiconductor device 1A of the second embodiment, like the first embodiment, it is possible to improve the avalanche resistance while suppressing an increase in the on-resistance of the semiconductor device 1A.

[0067] In addition, in this embodiment, because carrier conducting portion 43 is a conductor, even if carrier conducting portion 43 is shifted in the Y-axis direction, it is unlikely to hinder the formation of a channel in base region 221. Therefore, carrier conducting portion 43 in this embodiment is allowed to be shifted in the Y-axis direction more than carrier conducting portion 41 in the first embodiment. This can facilitate the manufacture of, for example, semiconductor device 1A.

[0068] Furthermore, in this embodiment, carrier conducting portion 43 and connecting portion 42 can be formed simultaneously, which simplifies the manufacturing process.

[0069] The regrowth of the epitaxial layer described in Fig. 7D can also be applied to the manufacturing method of the first embodiment. In this case, after carrier conduction portion 41 is formed in Fig. 4B, the upper portion of carrier conduction portion 41 is removed by RIE or the like to form a trench. Then, the epitaxial layer is regrown to form a p-type semiconductor region similar to base region 221 in the trench. With such a process, a configuration similar to that of Fig. 4C can be obtained.

[0070] (Third embodiment) A semiconductor device 1B according to a third embodiment will be described with reference to Fig. 8 and Fig. 9. Fig. 8 is a plan view of the semiconductor device 1B according to the third embodiment. Fig. 9 is a cross-sectional view of the semiconductor device 1B according to the third embodiment, taken along line III-III in Fig. 8.

[0071] One of the differences between the third embodiment and the first embodiment is the number of connecting parts. The following describes a semiconductor device 1B according to this embodiment, focusing on the differences from the first embodiment.

[0072] 8 and 9, the semiconductor device 1B according to this embodiment further includes two connection regions 224 located between the connection region 222 and the connection region 223 in the X-axis direction and sandwiched between the source regions 23. The connection region 224 extends along the Z-axis direction from the base region 221 to the source electrode 11 and connects the base region 221 and the source electrode 11. The connection region 224 is an example of a third connection region in the claims. Note that the number of connection regions 224 located between the connection region 222 and the connection region 223 in the X-axis direction is not limited to two and may be any number.

[0073] In this embodiment, the connection region 224 is a p-type semiconductor region having the same impurity concentration as the base region 221, the connection region 222, and the connection region 223. This allows the base region 221, the connection region 222, the connection region 223, and the connection region 224 to be formed collectively. Note that the connection region 224 may be a p-type semiconductor region having a different impurity concentration from the base region 221, the connection region 222, and the connection region 223, or may be an insulating region made of an insulating material such as silicon oxide or silicon nitride.

[0074] A connection portion 44 is provided in the connection region 224 to electrically connect the carrier conduction portion 41 and the source electrode 11. The connection portion 44 includes a metal or polysilicon doped with an impurity. The connection portion 44 may be formed of a semiconductor region of the second conductivity type. The connection portion 44 is an example of a third connection portion in the claims.

[0075] Thus, the semiconductor device 1B according to this embodiment further includes at least one connection region 224 located between the connection region 222 and the connection region 223 and sandwiched between the source regions 23, and a connection portion 44 is provided in the connection region 224. This allows carriers remaining in the base region 221 to be discharged more quickly. As a result, although the on-resistance of the semiconductor device 1 is increased by the connection region 224, the avalanche resistance of the semiconductor device 1B can be further improved.

[0076] In semiconductor device 1B according to this embodiment, similarly to the second embodiment, carrier conduction portion 41 which is a semiconductor region may be replaced by carrier conduction portion 43 which is a conductor.

[0077] In addition, in each of the above-mentioned embodiments, the configuration for electrically connecting the carrier conducting portions 41 and 43 and the source electrode 11 is not limited to the examples shown in FIG. 2, FIG. 5, and FIG. 9, and may be any. For example, the connection region 222 and the connection region 223 may be provided on the inner side of the base region 221, rather than on both ends of the base region 221. As another example, one or more connection regions extending from any part of the base region 221 in the X-axis direction to the source electrode 11 may be provided, and the carrier conducting portion 41 and the source electrode 11 may be electrically connected via one or more connection parts provided in each of the connection regions. As yet another example, a connection region extending from the base region 221 to the side surface of the semiconductor layer 2 may be provided, and the carrier conducting portions 41 and 43 may be electrically connected to the source electrode 11 via a connection part provided in the connection region and a separate wiring or the like.

[0078] Although the embodiment of the present invention has been described, the embodiment and examples are presented as examples and are not intended to limit the scope of the invention. The embodiment and examples can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the gist of the invention. These embodiments and examples and their modifications are included in the scope of the invention and its equivalents described in the claims, as well as in the scope and gist of the invention. [Explanation of symbols]

[0079] 1 Semiconductor device 11 Source electrode 12 Drain electrode 13 Gate electrode 21 Drift Region 221 Base Area 222,223,224 Connection Area 23 Source Region 24 Drain Region 31 Gate insulating film 32 Interlayer insulating film 41,43 Carrier Conduction Section 42,44 Connection 50 Gate Pad 51 Gate wiring

Claims

1. a semiconductor layer having a first major surface and a second major surface; A first electrode provided on the first main surface; a second electrode provided on the second main surface; a first semiconductor region of a first conductivity type provided in the semiconductor layer and located above the second electrode; a plurality of insulating regions provided in the semiconductor layer, the insulating regions extending from the first major surface to the first semiconductor region and extending in a second direction perpendicular to a first direction from the second electrode to the first electrode; a plurality of third electrodes provided in the plurality of insulating regions and extending in the second direction; a second semiconductor region of a second conductivity type disposed in the semiconductor layer, sandwiched between the insulating regions, located on the first semiconductor region, and extending in the second direction; a third semiconductor region of the first conductivity type provided in the semiconductor layer and located between the second semiconductor region and the first electrode; a carrier conduction portion provided in the second semiconductor region so as to extend in the second direction, the carrier conduction portion being electrically connected to the first electrode via a connection portion that does not penetrate the third semiconductor region; A semiconductor device comprising:

2. The semiconductor device according to claim 1 , wherein the carrier conduction portion includes a semiconductor of a second conductivity type having a higher impurity concentration than the second semiconductor region.

3. The semiconductor device according to claim 1 , wherein the carrier conducting portion includes a metal or polysilicon.

4. The semiconductor device according to claim 1 , wherein said carrier conducting portions are provided at positions equidistant from adjacent ones of said third electrodes.

5. the connection portion is connected to one end of the carrier conduction portion and is provided in a first connection region which is a semiconductor region of a second conductivity type; The semiconductor device according to any one of claims 1 to 4, wherein the first connection region is provided within the semiconductor layer and extends along the first direction from one end of the second semiconductor region in the second direction to the first electrode.

6. a second connection portion that does not penetrate the third semiconductor region, electrically connects the other end of the carrier conduction portion and the first electrode, and is provided in a second connection region that is a semiconductor region of a second conductivity type; 6. The semiconductor device according to claim 5, wherein the second connection region is provided in the semiconductor layer and extends along the first direction from the other end of the second semiconductor region in the second direction to the first electrode.

7. 7. The semiconductor device according to claim 6, wherein said first connection region and said second connection region include a semiconductor of a second conductivity type having an impurity concentration equal to that of said second semiconductor region.

8. a third connection region provided in the semiconductor layer, located between the first connection region and the second connection region and sandwiched between the third semiconductor regions; The semiconductor device according to claim 6 , further comprising a third connection portion provided in said third connection region and electrically connecting said carrier conducting portion and said first electrode.

9. The semiconductor device according to claim 1 , wherein the connection portion includes a metal or polysilicon.

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