Semiconductor storage device

Abstract

To provide a semiconductor storage device that operates suitably.SOLUTION: A semiconductor storage device includes a plurality of first semiconductor layers, a first wire, a plurality of second semiconductor layers stacked between the first semiconductor layers and the first wire, a first via wire connected to the first and second semiconductor layers, a plurality of first memory parts connected to the first semiconductor layers, a plurality of first gate electrodes facing the first semiconductor layers, a plurality of second wires connected to the first gate electrodes, a plurality of first connection electrodes stacked between the first memory parts and the first wire, and connected to the second semiconductor layers, a plurality of second gate electrodes stacked between the first gate electrodes and the first wire and facing the second semiconductor layers, a plurality of third wires stacked between the second wires and the first wire and connected to the second gate electrodes, a fourth wire connected in common to the first memory parts, and a fifth wire connected in common to the first connection electrodes.SELECTED DRAWING: Figure 10

Description

[Technical field]

[0001] The present embodiment relates to a semiconductor memory device. [Background technology]

[0002] 2. Description of the Related Art With the increasing integration density of semiconductor memory devices, studies on three-dimensional semiconductor memory devices are underway. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2022 / 0068933 [Patent Document 2] US Patent Application Publication No. 2020 / 0303400 [Patent Document 3] US Patent Application Publication No. 2022 / 0005830 Summary of the Invention [Problem to be solved by the invention]

[0004] A semiconductor memory device that operates favorably is provided. [Means for solving the problem]

[0005] A semiconductor memory device according to one embodiment includes a plurality of first semiconductor layers stacked in a stacking direction, a first wiring provided on one side of the plurality of first semiconductor layers in the stacking direction and extending in a first direction intersecting the stacking direction, a plurality of second semiconductor layers provided between the plurality of first semiconductor layers and the first wiring and stacked in the stacking direction, a first via wiring extending in the stacking direction and electrically connected to the plurality of first semiconductor layers and the plurality of second semiconductor layers, a plurality of first memory units stacked in the stacking direction and electrically connected to the plurality of first semiconductor layers, a plurality of first gate electrodes stacked in the stacking direction and facing the plurality of first semiconductor layers, and a plurality of first gate electrodes stacked in the stacking direction and extending in a second direction intersecting the stacking direction and the first direction. a plurality of second wirings electrically connected to the plurality of second semiconductor layers, a plurality of first connection electrodes provided between the plurality of first memory units and the first wirings, stacked in the stacking direction, and electrically connected to the plurality of second semiconductor layers, a plurality of second gate electrodes provided between the plurality of first gate electrodes and the first wirings, stacked in the stacking direction, and facing the plurality of second semiconductor layers, a plurality of third wirings provided between the plurality of second wirings and the first wirings, stacked in the stacking direction, extending in the second direction, and electrically connected to the plurality of second gate electrodes respectively, a fourth wiring extending in the stacking direction and electrically connected in common to the plurality of first memory units, and a fifth wiring extending in the stacking direction and electrically connected in common to the plurality of first connection electrodes. [Brief description of the drawings]

[0006] [Figure 1] 1 is a schematic exploded perspective view showing a configuration example of a semiconductor memory device according to a first embodiment. [Diagram 2] FIG. 2 is a schematic circuit diagram showing a configuration of the semiconductor memory device. [Diagram 3] FIG. 2 is a schematic perspective view showing a configuration of a portion of the semiconductor memory device. [Figure 4] 2 is a schematic XY cross-sectional view showing a configuration of a part of the memory layer ML. FIG. [Diagram 5] 2 is a schematic XY cross-sectional view showing a configuration of a part of a transistor layer TL. FIG. [Figure 6]2 is a schematic XY cross-sectional view showing a configuration of a part of the memory layer ML. FIG. [Figure 7] 7 is a cross-sectional view of the structure shown in FIG. 6 taken along line CC' and viewed in the direction of the arrows. [Figure 8] 2 is a schematic XY cross-sectional view showing a configuration of a part of a transistor layer TL. FIG. [Figure 9] 9 is a cross-sectional view of the structure shown in FIG. 8 taken along line DD' and viewed in the direction of the arrow. [Figure 10] 1 is a schematic cross-sectional view showing a configuration of a semiconductor memory device according to a first embodiment. [Figure 11] FIG. 2 is a schematic cross-sectional view showing the configuration of the semiconductor memory device. [Figure 12] 5A to 5C are schematic cross-sectional views for explaining a manufacturing method of the semiconductor memory device. [Figure 13] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 14] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 15] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 16] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 17] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 18] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 19] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 20] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 21] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 22] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 23] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 24]5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Diagram 25] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 26] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 27] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 28] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 29] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Diagram 30] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Diagram 31] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Diagram 32] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Diagram 33] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Diagram 34] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Diagram 35] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Diagram 36] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 37] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 38] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 39] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Diagram 40] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Diagram 41] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Diagram 42] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Diagram 43] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Diagram 44] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Diagram 45] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 46] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 47] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 48] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 49] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 50] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 51] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 52] 11 is a schematic cross-sectional view showing a configuration of a portion of a semiconductor memory device according to a second embodiment. FIG. [Figure 53] FIG. 2 is a schematic cross-sectional view showing a configuration of a portion of the semiconductor memory device. [Figure 54] FIG. 11 is a schematic cross-sectional view showing a configuration of a portion of a semiconductor memory device according to a third embodiment. [Figure 55] FIG. 2 is a schematic cross-sectional view showing a configuration of a portion of the semiconductor memory device. [Figure 56] FIG. 2 is a schematic cross-sectional view showing a configuration of a portion of the semiconductor memory device. [Figure 57] FIG. 11 is a schematic cross-sectional view showing a configuration of a portion of a semiconductor memory device according to a fourth embodiment. [Figure 58] FIG. 2 is a schematic cross-sectional view showing a configuration of a portion of the semiconductor memory device. [Figure 59] FIG. 2 is a schematic cross-sectional view showing a configuration of a portion of the semiconductor memory device. [Figure 60] FIG. 13 is a schematic cross-sectional view showing a configuration of a portion of a semiconductor memory device according to a fifth embodiment. [Figure 61] FIG. 2 is a schematic cross-sectional view showing a configuration of a portion of the semiconductor memory device. [Figure 62] FIG. 2 is a schematic cross-sectional view showing a configuration of a portion of the semiconductor memory device. [Figure 63] FIG. 11 is a schematic cross-sectional view showing a configuration of a portion of a semiconductor memory device according to another embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Next, a semiconductor memory device according to an embodiment will be described in detail with reference to the drawings. Note that the following embodiment is merely an example, and is not intended to limit the present invention. Also, the following drawings are schematic, and for the sake of explanation, some configurations may be omitted. Also, parts common to multiple embodiments may be given the same reference numerals, and explanations may be omitted.

[0008] In addition, in this specification, the term "semiconductor memory device" may refer to a memory die, or may refer to a memory system including a controller die, such as a memory chip, a memory card, or an SSD (Solid State Drive). Furthermore, it may refer to a configuration including a host computer, such as a smartphone, a tablet terminal, or a personal computer.

[0009] In addition, in this specification, when it is said that a first configuration is "electrically connected" to a second configuration, the first configuration may be directly connected to the second configuration, or the first configuration may be connected to the second configuration via wiring, a semiconductor member, a transistor, etc. For example, when three transistors are connected in series, the first transistor is "electrically connected" to the third transistor even if the second transistor is in an OFF state.

[0010] Furthermore, in this specification, when it is said that a first configuration is "electrically connected between" a second configuration and a third configuration, it may mean that the first configuration, the second configuration, and the third configuration are connected in series, and that the second configuration is electrically connected to the third configuration via the first configuration.

[0011] In addition, in this specification, when it is said that a circuit or the like "conducts" two wirings or the like, it may mean, for example, that the circuit or the like includes a transistor or the like, that the transistor or the like is provided in a current path between the two wirings, and that the transistor or the like is in an ON state.

[0012] In this specification, a predetermined direction parallel to the upper surface of the substrate is called the X direction, a direction parallel to the upper surface of the substrate and perpendicular to the X direction is called the Y direction, and a direction perpendicular to the upper surface of the substrate is called the Z direction.

[0013] In this specification, the direction intersecting with the surface of the substrate may be referred to as the stacking direction. Also, the direction along a specific plane intersecting with the stacking direction may be referred to as the first direction, and the direction intersecting with the first direction along this plane may be referred to as the second direction. The stacking direction may or may not match the Z direction. Also, the first and second directions may or may not correspond to either the X direction or the Y direction.

[0014] Furthermore, in this specification, the "center position" of a certain feature may mean, for example, the center position of the circumscribing circle of this feature, or may mean the center of gravity of this feature on an image.

[0015] [First embodiment] [Memory die MD structure] FIG. 1 is a schematic exploded perspective view showing a configuration example of a semiconductor memory device according to a first embodiment. As shown in FIG. 1, a memory die MD includes a chip C M And Chip C P Chip C M The chip C includes a memory cell array MCA. Pincludes peripheral circuits and the like connected to the memory cell array MCA.

[0016] Chip C M On one surface of the X Also, chip C M On the other surface of the I1 Also, chip C P On one surface of the I2 The following is Chip C M Regarding the first bonding electrodes P I1 The surface on which the external pad electrodes P X The surface on which the chip C is provided is called the back surface. P Regarding the second bonding electrodes P I2 The surface on which the is provided is called the front surface, and the surface opposite to the front surface is called the back surface.

[0017] Chip C M and Chip C P is Chip C M Surface and chip C P The first bonding electrodes P I1 A plurality of second bonding electrodes P I2 , and a plurality of second bonding electrodes P I2 The first bonding electrode P I1 and the second bonded electrode P I2 What is Chip C? M and Chip C P The laminate functions as a laminate electrode for bonding the two and electrically connecting them.

[0018] In the example of FIG. 1, chip C M The corners a1, a2, a3, and a4 of the chip C P These correspond to corners b1, b2, b3, and b4.

[0019] [Circuit configuration] 2 is a schematic circuit diagram showing the configuration of the semiconductor memory device according to the first embodiment. The memory cell array MCA includes a plurality of memory layers ML, a plurality of transistor layers TL, a plurality of bit lines BL connected to the plurality of memory layers ML and the plurality of transistor layers TL, a plurality of global bit lines GBL electrically connected to the plurality of bit lines BL via the plurality of transistor layers TL, and a plate line PL connected to the plurality of memory layers ML.

[0020] Each of the memory layers ML includes a plurality of word lines WL0 to WL2 (hereinafter sometimes referred to as "word lines WL") and a plurality of memory cells MC connected to the plurality of word lines WL0 to WL2. Each of the memory cells MC includes a transistor TrC and a capacitor CpC. One electrode of the transistor TrC is connected to a bit line BL. The other electrode of the transistor TrC is connected to the capacitor CpC. The one and the other electrodes of the transistor TrC function as a source electrode or a drain electrode depending on the voltage supplied to the transistor TrC. The gate electrode of the transistor TrC is connected to one of the word lines WL0 to WL2. One electrode of the capacitor CpC is connected to the other electrode of the transistor TrC. The other electrode of the capacitor CpC is connected to a plate line PL.

[0021] Each bit line BL is connected to a plurality of memory cells MC corresponding to a plurality of memory layers ML.

[0022] The memory layer ML also includes a plurality of transistors TrLa, TrLb (hereinafter, sometimes referred to as "transistors TrL") provided corresponding to the plurality of word lines WL0 to WL2. One electrode of the transistor TrL is connected to one of the word lines WL0 to WL2. The other electrode of the transistor TrL is connected to a word line selection line LW0a, LW0b, LW1a, LW1b, LW2a, or LW2b (hereinafter, sometimes referred to as "word line selection line LW"). The one and other electrodes of the transistor TrL function as a source electrode or a drain electrode depending on the voltage supplied to the transistor TrL. The gate electrodes of the transistor TrL are connected to layer selection lines LLa, LLb (hereinafter, sometimes referred to as "layer selection line LL").

[0023] The word line selection line LW is connected to a plurality of transistors TrL corresponding to a plurality of memory layers ML. The layer selection line LLa is connected in common to all the transistors TrLa corresponding to the plurality of memory layers ML. Similarly, the layer selection line LLb is connected in common to all the transistors TrLb corresponding to the plurality of memory layers ML.

[0024] The transistor layer TL includes a plurality of bit line selection lines LB0 to LB2 (hereinafter sometimes referred to as "bit line selection lines LB") and a plurality of transistors TrB connected to the plurality of bit line selection lines LB0 to LB2. One electrode of the transistor TrB is connected to a global bit line GBL via an electrode Cn1. The other electrode of the transistor TrB is connected to a bit line BL. The one and other electrodes of the transistor TrB function as a source electrode or a drain electrode depending on the voltage supplied to the transistor TrB. The gate electrode of the transistor TrB is connected to any one of the bit line selection lines LB0 to LB2.

[0025] In addition, one electrode of each of the plurality of transistors TrB is connected to the same bit line BL, while the other electrodes are connected to the same global bit line GBL via an electrode Cn1. These plurality of transistors TrB are connected in parallel between the bit line BL and the global bit line GBL.

[0026] The bit line selection lines LB0 to LB2 are, for example, I1 and second laminated electrode P I2 (Figure 1) via chip C P The signal processing circuit is connected to a driving circuit etc. provided in the signal processing circuit.

[0027] [Chip C P Structure of Chip C P (FIG. 1) is provided with a control circuit, a drive circuit, and the like for controlling the memory cell array MCA. For example, the control circuit includes a sense amplifier circuit. The sense amplifier circuit is electrically connected to the bit line BL via the global bit line GBL. In a read operation, the sense amplifier circuit is capable of reading data stored in a selected memory cell MC by detecting a voltage fluctuation or current of the bit line BL.

[0028] [Chip C M Structure of FIG. 3 is a schematic perspective view showing a configuration of a part of the semiconductor memory device according to the present embodiment. M 1 shows a structure of a part of a memory cell array MCA provided in the memory cell array MCA.

[0029] In the following description, expressions such as "upper" and "lower" are based on the global bit line GBL. For example, the direction away from the global bit line GBL along the Z direction is called "down," and the direction approaching the global bit line GBL along the Z direction is called "up." Furthermore, when referring to a certain configuration, the upper surface or upper end refers to the surface or end of the configuration on the global bit line GBL side, and when referring to the lower surface or lower end, refers to the surface or end of the configuration on the opposite side to the global bit line GBL. Furthermore, a surface that intersects with the X direction or Y direction is called a side surface, etc.

[0030] The memory cell array MCA includes a plurality of memory layers ML stacked in the Z direction, and a plurality of transistor layers TL provided between the memory layers ML and the global bit lines GBL and stacked in the Z direction. The length of the memory layers ML in the Z direction and the length of the transistor layers TL in the Z direction are approximately the same.

[0031] Between the plurality of memory layers ML and between the plurality of transistor layers TL, silicon oxide (SiO 2 An insulating layer 103 such as silicon oxide (SiO 2 ) or the like is provided on the insulating layer 203. The length of the insulating layer 203 in the Z direction is greater than the length of the insulating layer 103 in the Z direction.

[0032] [Structure of memory layer ML and transistor layer TL] Next, the structures of the memory layer ML and the transistor layer TL will be described with reference to FIGS. 4 to 11 in addition to FIG.

[0033] FIG. 4 is a schematic XY cross-sectional view showing a part of the configuration of the memory layer ML. FIG. 5 is a schematic XY cross-sectional view showing a part of the configuration of the transistor layer TL. FIG. 6 is a schematic XY cross-sectional view showing a part of the configuration of the memory layer ML, and shows an enlarged part of FIG. 4. FIG. 7 is a schematic XY cross-sectional view showing a part of the configuration of the transistor layer TL, cut along the CC' line and viewed along the direction of the arrow. FIG. 8 is a schematic XY cross-sectional view showing a part of the configuration of the transistor layer TL, and shows an enlarged part of FIG. 5. FIG. 9 is a schematic cross-sectional view showing a part of the configuration of the semiconductor memory device according to this embodiment, cut along the DD' line and viewed along the direction of the arrow. FIG. 10 and FIG. 11 are schematic cross-sectional views showing a configuration of the semiconductor memory device according to this embodiment. FIG. 10 shows a cross-section of the structure shown in FIG. 4 and FIG. 5 cut along the A1-A1' line and viewed along the direction of the arrow. FIG. 11 shows a cross-section of the structure shown in FIG. 4 and FIG. 5 cut along the B1-B1' line and viewed along the direction of the arrow.

[0034] 4, the memory layer ML includes a plurality of insulating layers 101 arranged in the X direction, and a conductive layer 102 provided between two insulating layers 101 adjacent to each other in the X direction. The insulating layers 101 and the conductive layers 102 extend in the Y direction and the Z direction, and divide the memory layers ML in the X direction (see FIG. 10).

[0035] As shown in FIG. 5, the transistor layer TL includes contacts GBLC and silicon oxide (SiO 2 ) and other insulating layers 106 are provided. The contacts GBLC and the insulating layers 106 extend in the Z direction and divide the multiple transistor layers TL in the X direction (see FIG. 10).

[0036] The insulating layer 101 is, for example, silicon oxide (SiO 2 ) etc.

[0037] The conductive layer 102 includes, for example, a laminated structure of titanium nitride (TiN) and silicon germanium (SiGe). The conductive layer 102 may include, for example, a laminated structure of titanium nitride (TiN) and tungsten (W), or may include a laminated structure of titanium nitride (TiN), silicon germanium (SiGe), and tungsten (W). The conductive layer 102 functions, for example, as a plate line PL (FIG. 2).

[0038] A plurality of via wirings 104 are provided in the regions between the insulating layer 101 and the conductive layer 102 (FIG. 4) and between the insulating layer 101 and the contact GBLC and the insulating layer 106 (FIG. 5). The plurality of via wirings 104 are aligned in the Y direction and extend in the Z direction, penetrating the plurality of transistor layers TL and the plurality of memory layers ML, as shown in FIGS. 3 and 10, for example.

[0039] As shown in FIG. 6 and FIG. 8, the via wiring 104 includes, for example, a conductive oxide film 104b including a conductive oxide, and a conductive member 104c. The conductive member 104c may have a laminated structure including, for example, titanium nitride (TiN) and tungsten (W). The conductive member 104c has a substantially cylindrical shape extending in the Z direction. The conductive oxide film 104b has a substantially cylindrical shape extending in the Z direction along the outer circumferential surface of the conductive member 104c. The via wiring 104 may include ruthenium (Ru), iridium (Ir), or other metals instead of the conductive oxide film 104b. The via wiring 104 may also include only a conductive oxide, or may only include ruthenium (Ru), iridium (Ir), or other metals.

[0040] In this specification, the term "conductive oxide" includes, for example, indium tin oxide (ITO), indium zinc oxide (IZO), ruthenium oxide (RuO2), iridium oxide (IrO2), or other conductive materials containing oxygen.

[0041] The via wiring 104 functions as, for example, a bit line BL (FIG. 2). As shown in FIG. 2, a plurality of bit lines BL are provided corresponding to a plurality of transistors TrC included in the memory layer ML and a plurality of transistors TrB included in the transistor layer TL.

[0042] The memory layer ML and the transistor layer TL include a plurality of transistor structures 110 provided corresponding to the plurality of via wirings 104, and a conductive layer 120 provided on the opposite side of the conductive layer 102 with respect to the plurality of transistor structures 110. The memory layer ML also includes a plurality of capacitor structures 130 provided between the plurality of transistor structures 110 and the conductive layer 102. The transistor layer TL also includes a plurality of electrode structures 130c provided between the plurality of transistor structures 110 and the plurality of contacts GBLC.

[0043] As shown in FIGS. 6 to 9 , the transistor structure 110 includes a semiconductor layer 111 connected to the outer peripheral surface of the via wiring 104 and extending in the X direction, an insulating layer 112 provided on an upper surface, a lower surface, both side surfaces in the Y direction, and one side surface in the X direction (the conductive layer 120 side) of the semiconductor layer 111, and a conductive layer 113 provided on an upper surface, a lower surface, both side surfaces in the Y direction, and one side surface in the X direction (the conductive layer 120 side) of the insulating layer 112.

[0044] 6 and 8, a side surface on one side in the X direction of the semiconductor layer 111 (the conductive layer 120 side) may be formed along a circle centered on the central position of the via wiring 104. In addition, side surfaces on the other side in the X direction of the semiconductor layer 111, the insulating layer 112, and the conductive layer 113 (the conductive layer 102 side) may be formed linearly along the side surface of the conductive layer 102. In addition, both side surfaces in the Y direction of the semiconductor layer 111, the insulating layer 112, and the conductive layer 113 may be formed linearly along the side surface of the insulating layer 115.

[0045] The semiconductor layer 111 functions as, for example, a channel region of the transistors TrC and TrB (FIG. 2). The semiconductor layer 111 may be, for example, a semiconductor containing at least one element of gallium (Ga) and aluminum (Al), indium (In), zinc (Zn), and oxygen (O), or may be another oxide semiconductor. The multiple semiconductor layers 111 aligned in the Z direction are commonly connected to a via wiring 104 extending in the Z direction.

[0046] The insulating layer 112 functions as, for example, a gate insulating film for the transistors TrC and TrB (FIG. 2). The insulating layer 112 is made of, for example, silicon oxide (SiO 2 ) etc.

[0047] The conductive layer 113 functions as, for example, the gate electrodes of the transistors TrC and TrB (FIG. 2). The conductive layer 113 includes, for example, a conductive oxide such as titanium nitride (TiN) or indium tin oxide (ITO). The multiple conductive layers 113 aligned in the Y direction are commonly connected to the conductive layer 120 extending in the Y direction (see FIGS. 4 and 5). The conductive layer 113 faces the upper surface, the lower surface, both side surfaces in the Y direction, and one side surface in the X direction (the conductive layer 120 side) of the semiconductor layer 111 via the insulating layer 112.

[0048] Between two semiconductor layers 111 adjacent to each other in the Y direction, a silicon oxide (SiO 2 ) or the like is provided. The insulating layer 115 extends in the Z direction, penetrating the plurality of transistor layers TL and the plurality of memory layers ML.

[0049] The conductive layer 120 functions as, for example, a word line WL in the memory layer ML and as a bit line selection line LB (FIG. 2) in the transistor layer TL. The conductive layer 120 extends in the Y direction and is connected to a plurality of conductive layers 113 arranged in the Y direction. The conductive layer 120 includes, for example, a barrier conductive film 121 such as titanium nitride (TiN) and a conductive film 122 of tungsten (W).

[0050] As shown in FIGS. 6 and 7 , the capacitor structure 130 includes a conductive layer 131, an insulating layer 132 provided on an upper surface, a lower surface, both side surfaces in the Y direction, and one side surface in the X direction (the transistor structure 110 side) of the conductive layer 131, and a conductive layer 133 provided on an upper surface, a lower surface, both side surfaces in the Y direction, and one side surface in the X direction (the transistor structure 110 side) of the insulating layer 132.

[0051] The conductive layer 131 functions as one electrode of the capacitor CpC (FIG. 2). The conductive layer 131 includes, for example, a laminated structure of titanium nitride (TiN) and silicon germanium (SiGe). The conductive layer 131 may include, for example, a laminated structure of titanium nitride (TiN) and tungsten (W), or a laminated structure of titanium nitride (TiN), silicon germanium (SiGe), and tungsten (W). The conductive layer 131 is continuous with the conductive layer 102.

[0052] The insulating layer 132 functions as an insulating layer for the capacitor CpC (FIG. 2). The insulating layer 132 is made of, for example, zirconia (ZrO 2 ), Alumina (Al 2 O 3 ) or other insulating metal oxides. The insulating layer 132 may be, for example, a laminated film of a plurality of insulating metal oxides (for example, a laminated film of zirconia and alumina).

[0053] The conductive layer 133 functions as, for example, the other electrode of the capacitor CpC (FIG. 2). The conductive layer 133 includes, for example, a conductive oxide such as indium tin oxide (ITO). The conductive layer 133 is insulated from the conductive layer 131 via the insulating layer 132. The conductive layer 133 is connected to the side surface of the semiconductor layer 111 in the X direction. The conductive layer 133 is insulated from the conductive layer 102 via the insulating layer 132.

[0054] As shown in FIGS. 8 and 9, for example, the electrode structure 130c includes a conductive layer 131c, an insulating layer 132c provided on an upper surface, a lower surface, both side surfaces in the Y direction, and one side surface in the X direction (the transistor structure 110 side) of the conductive layer 131c, and a conductive layer 133c provided on an upper surface, a lower surface, both side surfaces in the Y direction, and one side surface in the X direction (the transistor structure 110 side) of the insulating layer 132c.

[0055] The conductive layer 131c contains the same material as the conductive layer 131. One side of the conductive layer 131c in the X direction (the contact GBLC side) is in contact with the contact GBLC.

[0056] The insulating layer 132c contains the same material as the insulating layer 132. One side in the X direction of the insulating layer 132c (the contact GBLC side) is in contact with the contact GBLC.

[0057] The conductive layer 133c functions as, for example, a conductive member of the electrode Cn1 (FIG. 2). The conductive layer 133c includes the same material as the conductive layer 133. A side surface on one side in the X direction (the transistor structure 110 side) of the conductive layer 133c is connected to a side surface in the X direction of the semiconductor layer 111. A side surface on the other side in the X direction of the conductive layer 133c (the contact GBLC side) is connected to the contact GBLC. The conductive layer 133c is electrically connected to the contact GBLC.

[0058] As shown in, for example, FIGS. 8 to 10, the contact GBLC includes a barrier conductive film 206 such as titanium nitride (TiN) and a conductive film 207 such as tungsten (W) or indium tin oxide (ITO). The barrier conductive film 206 and the conductive film 207 may include a conductive oxide such as indium tin oxide (ITO). The contact GBLC is commonly connected on both side surfaces in the X direction to the conductive layers 133c included in the multiple electrode structures 130c arranged in the Z direction. The contact GBLC is connected to the global bit line GBL on the upper surface. The contact GBLC functions as an electrode that connects, for example, multiple transistors TrB to the global bit line GBL via the electrode Cn1.

[0059] 10, the upper portion of the contact GBLC may include a portion P10 that is wider in the X direction at the upper portion. A part of the lower surface of the portion P10 may be in contact with a part of the upper surface of the conductive layer 133c included in the first electrode structure 130c from the top.

[0060] The width of the contact GBLC in the Y direction is approximately the same as the width of the global bit line GBL in the Y direction, as shown in FIG.

[0061] Between the contact GBLC and the conductive layer 102, as shown in FIG. 2 ) is provided. The contact GBLC is insulated from the conductive layer 102 (PL) via the insulating layer 205.

[0062] 3, 5, 10, and 11, the global bit lines GBL extend in the X direction and are arranged in a line in the Y direction. The global bit lines GBL include, for example, a barrier conductive film 208 made of titanium nitride (TiN) or the like, and a conductive film 209 made of tungsten (W).

[0063] 5, the global bit lines GBL are provided above the transistor structures 110. The global bit lines GBL are arranged in the Y direction at a pitch equal to the pitch at which the transistor structures 110 are arranged in the Y direction. The width of the global bit lines GBL in the Y direction is approximately the same as the width of the transistor structures 110 in the Y direction, for example.

[0064] A plurality of global bit lines GBL aligned in the Y direction are connected to a plurality of contacts GBLC aligned in the Y direction, respectively.

[0065] [Details of conductive layer 102 (PL)] Next, the detailed structure of the conductive layer 102 will be described with reference to FIG.

[0066] In the following description, the first and second memory layers ML from the top may be referred to as memory layers ML1 and ML2, respectively, as shown in Fig. 10. Also, the first and second transistor layers from the bottom may be referred to as transistor layers TL1 and TL2, respectively.

[0067] The conductive layer 102 has the following structures that are electrically connected to the plurality of capacitor structures 130 and are not electrically connected to the plurality of electrode structures 130c.

[0068] The conductive layer 102 has a surface SU10 on its upper surface (FIG. 10). The conductive layer 102 is provided such that the surface SU10 is between the upper surface of the capacitor structure 130 included in the memory layer ML1 and the lower surface of the electrode structure 130c included in the transistor layer TL1.

[0069] The capacitor structure 130 included in the memory layer ML1 has a surface SUm1 on its upper surface. The surface SUm1 coincides with, for example, the upper surface of the conductive layer 133 included in the memory layer ML1. The electrode structure 130c included in the transistor layer TL1 has a surface SUC1 on its lower surface. The surface SUC1 coincides with, for example, the lower surface of the conductive layer 133c included in the transistor layer TL1.

[0070] The surface SU10 is provided above the surface SUm1 and below the surface SUC1. The surface SU10 is closer to the global bit line GBL than the surface SUm1. The surface SU10 is farther from the global bit line GBL than the surface SUC1.

[0071] [Details of contact GBLC and via wiring 104 (BL)] Next, the detailed structures of the contact GBLC and the via wiring 104 (BL) will be described with reference to FIG.

[0072] The contact GBLC is electrically connected to the plurality of electrode structures 130c and is not electrically connected to the plurality of capacitor structures 130, and has the following structure.

[0073] The contact GBLC has a surface SU40 on its lower surface (FIG. 10). The contact GBLC is provided so that the surface SU40 is located above the upper surface of the capacitor structure 130 included in the memory layer ML1 and below the upper surface of the electrode structure 130c included in the transistor layer TL1.

[0074] The electrode structure 130c included in the transistor layer TL1 has a surface SUC2 on its upper surface. The surface SU40 is closer to the global bit line GBL than the surface SUm1. The surface SU40 is farther from the global bit line GBL than the surface SUC2.

[0075] The via wiring 104(BL) has a surface SU20 on its upper surface (FIG. 10). The contact GBLC has a surface SU30 on its upper surface (FIG. 10). The surface SU30 of the contact GBLC is located higher than the surface SU20 of the via wiring 104. The surface SU30 is closer to the global bit line GBL than the surface SU20.

[0076] [Insulating layer 103 and insulating layer 203] The length in the Z direction of the insulating layer 103 provided between the capacitor structure 130 included in the memory layer ML1 and the capacitor structure 130 included in the memory layer ML2 is length T10. The length in the Z direction of the insulating layer 103 provided between the electrode structure 130c included in the transistor layer TL1 and the electrode structure 130c included in the transistor layer TL2 is length T20. The length in the Z direction of the insulating layer 203 provided between the capacitor structure 130 included in the memory layer ML1 and the electrode structure 130c included in the transistor layer TL1 is length T30. The length T30 is greater than the length T10 and greater than the length T20.

[0077] [Manufacturing method] 12 to 51 are schematic cross-sectional views illustrating the method for manufacturing the semiconductor memory device according to the first embodiment.

[0078] 12, 14, 16, 18, 20, 22, 24, 26, 28, 30, 32, 34, 36, 38, and 40 show cross sections corresponding to FIGS. 6 and 8.

[0079] 42, 44, 46, 48 and 50 show cross sections corresponding to FIG.

[0080] Figures 13, 15, 17, 19, 21, 23, 25, 27, 29, 31, 33, 35, 37, 39, 41, 43, 45, 47, 49, and 51 show cross sections corresponding to a part of Figure 10.

[0081] In this manufacturing method, as shown in FIG. 13, for example, a plurality of insulating layers 103 and 203 and a plurality of sacrificial layers MLA are alternately formed on the upper surface of a substrate Sub. The substrate Sub may be a semiconductor substrate such as silicon (Si) containing a P-type impurity such as boron (B), or may be a substrate containing other impurities or materials. The sacrificial layer MLA may be, for example, a silicon nitride (Si 3 N 4 This process is performed by, for example, CVD (Chemical Vapor Deposition) or the like.

[0082] Next, as shown in FIG. 12, an insulating layer 115 is formed. In this step, for example, an opening is formed at a position corresponding to the insulating layer 115. This opening extends in the Z direction and penetrates the multiple insulating layers 103, the insulating layer 203, and the multiple sacrificial layers MLA stacked in the Z direction. This step is performed by, for example, RIE (Reactive Ion Etching) or the like. After the opening is formed, the insulating layer 115 is formed. This step is performed by, for example, CVD or the like.

[0083] Next, as shown in Figures 14 and 15, for example, an opening 104A is formed at a position corresponding to the via wiring 104. The opening 104A extends in the Z direction as shown in Figures 14 and 15, and penetrates the multiple insulating layers 103, the insulating layer 203, and the multiple sacrificial layers MLA stacked in the Z direction. This step is performed by, for example, RIE or the like.

[0084] Next, an opening 111A is formed as shown in, for example, Fig. 16 and Fig. 17. Parts of the upper and lower surfaces of the insulating layers 103 and 203, and part of the side surface in the X direction of the sacrificial layer MLA are exposed in the opening 111A. In this step, for example, a part of the sacrificial layer MLA is selectively removed through the opening 104A. This step is performed, for example, by wet etching or the like.

[0085] Next, as shown in, for example, FIGS. 18 and 19, a conductive layer 113' is formed inside the opening 111A, and a sacrificial layer 104Sc' is formed inside the openings 104A and 111A. In this step, for example, a conductive film such as titanium nitride (TiN) is formed inside the openings 104A and 111A. Next, a part of the conductive film (a part formed on the side surface of the insulating layers 103 and 203) is removed inside the opening 104A, and the conductive film is divided in the Z direction to form the conductive layer 113'. Next, silicon (Si) or the like is filled into the openings 104A and 111A to form a sacrificial layer 104Sc'. This step is performed by, for example, CVD, RIE, or the like.

[0086] Next, as shown in Fig. 20 and Fig. 21, for example, openings 101A and openings 120A are formed at positions corresponding to the insulating layer 101 and the conductive layer 120. Parts of the upper and lower surfaces of the insulating layers 103 and 203, and the X-direction side surface of the conductive layer 113' are exposed in the opening 120A. In this step, for example, after the opening 101A is formed, a part of the sacrificial layer MLA is selectively removed through the opening 101A. This step is performed by, for example, RIE, wet etching, or the like.

[0087] Next, as shown in, for example, FIGS. 22 and 23, a conductive layer 120 and an insulating layer 101 are formed inside the opening 120A and the opening 101A. In this step, for example, a conductive film containing the same material as the conductive layer 120 is formed inside the openings 120A and 101A. Next, inside the opening 101A, a part of the conductive film (a part formed on the side surface of the insulating layers 103 and 203) is removed, and the conductive film is divided in the Z direction to form the conductive layer 120. Next, the insulating layer 101 is embedded in the opening 101A. This step is performed by, for example, a method such as CVD and RIE.

[0088] 24 and 25, an opening 102A is formed at a position corresponding to a part of the conductive layer 102, the insulating layer 205, and the contact GBLC. The opening 102A extends in the Z direction and penetrates the multiple insulating layers 103, the insulating layer 203, and the multiple sacrificial layers MLA stacked in the Z direction. This process is performed by, for example, RIE or the like.

[0089] 24 and 25, an opening 130A is formed. Part of the upper surface and part of the lower surface of the insulating layers 103 and 203, and part of the side surface in the X direction of the conductive layer 113' are exposed in the opening 130A. In this step, for example, a part of the sacrificial layer MLA is selectively removed through the opening 102A. This step is performed by, for example, wet etching or the like.

[0090] 26 and 27, a part of the upper surface and a part of the lower surface of the insulating layers 103 and 203 exposed in the opening 130A, and a part of the side surface in the X direction of the conductive layer 113' are removed. This process increases the width of the opening 130A in the Z direction. This process is performed by, for example, wet etching.

[0091] 26 and 27, the sacrificial layer 104Sc' is removed to form the openings 104A and 111A. This process allows the openings 102A, 104A, 111A, and 130A to communicate with each other. This process is performed by, for example, wet etching or the like.

[0092] 28 and 29, the insulating layer 112 is formed inside the openings 102A, 104A, 111A, and 130A. This process is performed by, for example, CVD or the like.

[0093] Next, as shown in, for example, FIGS. 30 and 31, silicon nitride (Si 3 N 4A sacrificial layer 111Sc' made of titanium nitride (TiN) or the like is formed. In this step, the opening 111A is filled with the sacrificial layer 111Sc', and the openings 102A, 104A, and 130A are not filled with the sacrificial layer 111Sc'. This step is performed by, for example, CVD or the like.

[0094] Next, as shown in, for example, FIGS. 32 and 33, a part of the sacrificial layer 111Sc′ is removed through the openings 102A and 104A, and the sacrificial layer 111Sc′ is divided in the Z direction to form silicon nitride (Si 3 N 4 A sacrificial layer 111Sc made of, for example, titanium nitride (TiN) is formed. This step is performed by, for example, wet etching.

[0095] 34 and 35, silicon (Si) or the like is embedded in the opening 104A to form a sacrificial layer 104Sc. In this process, for example, silicon (Si) or the like is embedded in the openings 102A and 104A, and then the silicon (Si) or the like embedded in the opening 102A is removed. This process is performed by, for example, CVD, wet etching, or the like.

[0096] Next, as shown in Figures 36 and 37, conductive layers 133 and 133c are formed inside the opening 130A. In this process, a conductive oxide layer such as indium tin oxide (ITO) is formed inside the openings 102A and 130A. Next, inside the opening 102A, a part of the conductive oxide layer (a part formed on the side surface of the insulating layers 103 and 203) is removed, and the conductive oxide layer is divided in the Z direction to form the conductive layers 133 and 133c. This process is performed by, for example, CVD, RIE, or the like.

[0097] 38 and 39, an insulating layer 132' containing a material similar to that of the insulating layer 132 is formed inside the openings 102A and 130A and on the upper surface of the structure shown in Fig. 37. This step is performed by, for example, CVD or the like.

[0098] 40 and 41, a conductive layer 131' containing a material similar to that of the conductive layer 131 is formed inside the openings 102A and 130A, and then a conductive layer 102' containing a material similar to that of the conductive layer 102 is formed inside the opening 102A. In this process, the opening 130A is filled with the conductive layer 131', and the opening 102A is not filled with the conductive layer 131'. This process is performed by, for example, CVD or the like.

[0099] 42 and 43, the conductive layer 102', the conductive layer 131', and parts of the insulating layer 132' are removed to form the conductive layers 131 and 131c, the insulating layers 132 and 132c, the conductive layer 102, and the opening 205A. This step is performed by, for example, RIE or the like.

[0100] Next, as shown in Figures 44 and 45, for example, an insulating layer 106 is formed inside the opening 205A and on the upper surface of the structure shown in Figure 43. Next, a portion of the insulating layer 106 located above the sacrificial layer 104Sc is removed to form an opening 106A, and the sacrificial layers 104Sc and 111Sc are removed through the opening 106A to form openings 104A and 111A. This process is performed by, for example, CVD, RIE, wet etching, or the like.

[0101] 46 and 47, for example, a semiconductor layer 111 is formed inside the openings 104A and 111A. The opening 111A is filled with the semiconductor layer 111. On the other hand, the opening 104A is not filled with the semiconductor layer 111. This step is performed by, for example, ALD (Atomic Layer Deposition) or the like.

[0102] 46 and 47, for example, inside the openings 104A and 106A, the via wiring 104 (conductive oxide film 104b and conductive member 104c) is formed, and after the upper surface is planarized, an insulating layer 107 is formed on the upper surfaces of the insulating layer 106 and the via wiring 104. This process is performed by a method such as CVD or CMP (Chemical Mechanical Polishing).

[0103] 48 and 49, the portions of the insulating layers 107, 106, and 103 that correspond to the contact GBLC are removed to form the insulating layer 205 and the opening 207 A. This step is performed by, for example, RIE or the like.

[0104] In this step, a part of the insulating layer 112 in contact with the top surface of the first electrode structure 130c from the top is simultaneously removed to expose a part of the top surface of the conductive layer 133c included in the first electrode structure 130c from the top.

[0105] 50 and 51, the contact GBLC (the barrier conductive film 206 and the conductive film 207) is formed inside the opening 207A. This process is performed by, for example, CVD and CMP.

[0106] Next, the global bit line GBL (barrier conductive film 208 and conductive film 209) is formed on the upper surface of the structure shown in FIG. 51. In addition, the structure above the global bit line GBL is formed, and then the chip C M On the surface of the substrate, a plurality of first bonding electrodes P as shown in FIG. I1 Form.

[0107] Next, the chip C on which the memory cell array MCA is formed in the above steps M and a wafer including a chip C P The wafer is bonded to the wafer as shown in FIG. 1, and then a plurality of external pad electrodes P X etc. are formed.

[0108] As a result, the structure described with reference to FIGS. 1 to 11 is formed.

[0109] [effect] In the semiconductor memory device according to this embodiment, multiple transistors TrB are connected in parallel between the bit line BL and the global bit line GBL. By simultaneously turning on the multiple transistors TrB connected in parallel to make the bit line BL and the global bit line GBL conductive, the total value of the current flowing from the bit line BL to the global bit line GBL during conduction can be increased. With this configuration, it is possible to transfer a voltage to the selected bit line BL and global bit line GBL at high speed.

[0110] In addition, in this embodiment, the structure in the transistor layer TL is configured similarly to the structure in the memory layer ML. Therefore, the semiconductor memory device according to this embodiment can be realized at low cost without increasing the number of manufacturing steps.

[0111] [Second embodiment] Figures 52 and 53 are schematic cross-sectional views showing a configuration of a portion of a semiconductor memory device according to the second embodiment. Figure 53 shows a cross section of the structure shown in Figure 52 taken along line B2-B2' and viewed in the direction of the arrows. In the following description, parts similar to those in the first embodiment are given the same reference numerals and description thereof will be omitted.

[0112] The semiconductor memory device according to the second embodiment is basically configured similarly to the semiconductor memory device according to the first embodiment, except that the semiconductor memory device according to the second embodiment includes global bit lines GBL2a and GBL2b arranged alternately in the Y direction, instead of the global bit line GBL.

[0113] The global bit lines GBL2a and GBL2b are basically configured in the same manner as the global bit line GBL, except that the width of the global bit lines GBL2a and GBL2b in the Y direction is, for example, about half the width of the transistor structure 110 in the Y direction.

[0114] The global bit line GBL2a is provided, for example, above the transistor structure 110. The global bit line GBL2b is provided, for example, above the insulating layer 115. The global bit lines GBL2a and GBL2b are alternately arranged in the Y direction at a pitch that is half the pitch at which the transistor structures 110 are arranged in the Y direction.

[0115] 52, the multiple global bit lines GBL2a aligned in the Y direction are connected to the multiple contacts GBLC aligned in the Y direction, respectively. On the other hand, in the region shown in FIG. 52, the multiple global bit lines GBL2b aligned in the Y direction are not connected to the contacts GBLC.

[0116] [Third embodiment] 54 to 56 are schematic cross-sectional views showing a configuration of a portion of the semiconductor memory device according to the third embodiment. Fig. 55 shows a cross section of the structure shown in Fig. 54 taken along line A3-A3' and viewed in the direction of the arrows. Fig. 56 shows a cross section of the structure shown in Fig. 54 taken along line B3-B3' and viewed in the direction of the arrows. In the following description, parts similar to those in the first embodiment are given the same reference numerals and description thereof will be omitted.

[0117] The semiconductor memory device according to the third embodiment is basically configured similarly to the semiconductor memory device according to the first embodiment, except that the semiconductor memory device according to the third embodiment includes contacts GBLC3 instead of contacts GBLC, and global bit lines GBL3a and GBL3b arranged alternately in the Y direction instead of global bit lines GBL.

[0118] The contact GBLC3 is basically configured in the same manner as the contact GBLC. However, the contact GBLC3 has a smaller width in the X direction and the Y direction than the contact GBLC. The width in the Y direction of the contact GBLC3 is about half the width in the Y direction of the transistor structure 110, for example, as shown in FIG.

[0119] 54, the contacts GBLC3 are arranged side by side in the Y direction, shifted alternately to the positive side and the negative side in the X direction. The contact GBLC3 arranged on the negative side in the X direction is arranged on the positive side in the Y direction with respect to the via wiring 104, and the contact GBLC3 arranged on the positive side in the X direction is arranged on the negative side in the Y direction with respect to the via wiring 104.

[0120] Further, as shown in FIG. 55, for example, the contact GBLC3 is commonly connected to a plurality of electrode structures 130c arranged in the Y direction on a side surface on one side in the X direction (the via wiring 104 side).

[0121] The global bit lines GBL3a and GBL3b are basically configured in the same manner as the global bit line GBL.

[0122] 54 and 56, the global bit lines GBL3a, GBL3b are provided above and across the Y-direction region in which the transistor structures 110 and the insulating layer 150 are provided. The global bit lines GBL3a, GBL3b are alternately arranged in the Y-direction at a pitch that is half the pitch at which the transistor structures 110 are arranged in the Y-direction. The width of the global bit lines GBL3a, GBL3b in the Y-direction is, for example, about half the width of the transistor structures 110 in the Y-direction.

[0123] For example, in the region shown in FIG. 54, a plurality of global bit lines GBL3a, GBL3b aligned in the Y direction are connected to a plurality of contacts GBLC3 aligned in the Y direction, respectively.

[0124] [Fourth embodiment] 57 to 59 are schematic cross-sectional views showing a configuration of a portion of the semiconductor memory device according to the fourth embodiment. Fig. 58 shows a cross section of the structure shown in Fig. 57 taken along line A4-A4' and viewed in the direction of the arrows. Fig. 59 shows a cross section of the structure shown in Fig. 57 taken along line B4-B4' and viewed in the direction of the arrows. In the following description, parts similar to those in the third embodiment are given the same reference numerals and description thereof will be omitted.

[0125] The semiconductor memory device according to the fourth embodiment is basically configured similarly to the semiconductor memory device according to the third embodiment, except that the semiconductor memory device according to the fourth embodiment includes a contact GBLC4 instead of the contact GBLC3.

[0126] The contact GBLC4 is basically configured in the same manner as the contact GBLC3.

[0127] However, the contact GBLC4 is provided inside the insulating layer 115 in the transistor layer TL as shown in Fig. 57 and Fig. 59. The contact GBLC4 is connected to the electrode structure 130c from one side in the Y direction (the positive side in the Y direction or the negative side in the Y direction) as shown in Fig. 59, for example.

[0128] 59, the upper portion of the contact GBLC4 may include a portion P14 that is wider in the Y direction. A part of the lower surface of the portion P14 may be in contact with a part of the upper surface of the conductive layer 133c included in the first electrode structure 130c from the top.

[0129] The contact GBLC4 has a surface SU44 on its lower surface (FIG. 59). The contact GBLC4 is provided so that the surface SU44 is located above the upper surface of the capacitor structure 130 included in the memory layer ML1 and below the upper surface of the electrode structure 130c included in the transistor layer TL1.

[0130] [Fifth embodiment] 60 to 62 are schematic cross-sectional views showing a configuration of a portion of the semiconductor memory device according to the fifth embodiment. Fig. 61 shows a cross section of the structure shown in Fig. 60 taken along line A5-A5' and viewed in the direction of the arrows. Fig. 62 shows a cross section of the structure shown in Fig. 60 taken along line B5-B5' and viewed in the direction of the arrows. In the following description, parts similar to those in the third embodiment are given the same reference numerals and description thereof will be omitted.

[0131] The semiconductor memory device according to the fifth embodiment is basically configured similarly to the semiconductor memory device according to the third embodiment, except that the semiconductor memory device according to the fifth embodiment includes a contact GBLC5 instead of the contact GBLC3.

[0132] The contact GBLC5 is basically configured in the same manner as the contact GBLC3.

[0133] However, the contact GBLC5 is provided inside the electrode structure 130c in the transistor layer TL as shown in Fig. 60. The contact GBLC5 is provided so as to penetrate the electrode structure 130c provided in the transistor layer TL2 and so that a surface SU45, which is the lower surface of the contact GBLC5, is connected to the conductive layer 133c included in the electrode structure 130c provided in the transistor layer TL1 as shown in Fig. 61 and Fig. 62.

[0134] In the transistor layer TL2, the contact GBLC5 has both side surfaces in the X direction and the Y direction connected to the conductive layer 133c of the electrode structure 130c included in the transistor layer TL2. In the transistor layer TL1, the contact GBLC5 is connected from the positive side in the Z direction to the conductive layer 133c of the electrode structure 130c included in the transistor layer TL1.

[0135] [Other embodiments] The semiconductor memory devices according to the first to fifth embodiments have been described above. However, the semiconductor memory devices according to these embodiments are merely examples, and the specific configurations and the like can be appropriately adjusted.

[0136] For example, in the semiconductor memory devices according to the first to fifth embodiments, two transistor layers TL aligned in the Z direction have been exemplified. However, three or more transistor layers TL may be aligned in the Z direction. The three or more transistors TrB provided in the three or more transistor layers TL may be connected in parallel between the via wiring 104(BL) and the global bit line GBL.

[0137] Also, for example, in the semiconductor memory devices according to the first to third embodiments, both side surfaces in the X direction of the contacts GBLC and GBLC2 and one side surface in the X direction of the contact GBLC3 may partially have a shape as shown for the contact GBLCa in Fig. 63. Fig. 63 is a schematic cross-sectional view showing a configuration of a portion of a semiconductor memory device according to another embodiment.

[0138] One side surface of the contact GBLCa in the X direction (the side surface on the negative side in the X direction) is provided so as to extend into the electrode structure 130c. The contact GBLCa is in contact with not only the side surface in the X direction of each of the conductive layers 133c included in the multiple electrode structures 130c, but also a part of the upper surface and the lower surface of the conductive layer 133c.

[0139] Similarly, in the semiconductor memory device according to the fourth embodiment, the contact GBLC4 may have one side surface in the Y direction extending into the electrode structure 130c and partially in contact with the upper and lower surfaces of the electrode structure 130c.

[0140] In addition, in the manufacturing method of the contact GBLCa, when removing portions of the insulating layers 107, 106, and 103 in the process described with reference to Figures 48 and 49, a portion of the insulating layer 103 located between the layers corresponding to the transistor layer TL is also removed, and then, in the process described with reference to Figures 50 and 51, a barrier conductive film 206 and a conductive film 207 are formed.

[0141] In the above description, an example has been described in which a capacitor CpC is adopted as the memory unit connected to the transistor structure 110. However, the memory unit does not have to be the capacitor CpC. For example, the memory unit may include a ferroelectric material, a ferromagnetic material, a chalcogen material such as GeSbTe, or other material, and may record data by utilizing the properties of these materials. For example, in any of the structures described above, the insulating layer between the electrodes that forms the capacitor CpC may include any of these materials.

[0142] Furthermore, the methods for manufacturing the semiconductor memory devices according to the first to fifth embodiments can also be adjusted as appropriate. For example, the order of any two of the above-described steps can be changed, or any two of the above-described steps can be performed simultaneously.

[0143] [others] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0144] 102...conductive layer, 104...via wiring, 111...semiconductor layer, 113...conductive layer, 120...conductive layer, 130...capacitor structure, 130c...electrode structure, BL...bit line, Cn1...electrode, CpC...capacitor, GBL...global bit line, GBLC...contact, PL...plate line, WL...word line.

Claims

1. A plurality of first semiconductor layers stacked in a stacking direction; a first wiring provided on one side of the plurality of first semiconductor layers in the stacking direction and extending in a first direction intersecting the stacking direction; a plurality of second semiconductor layers provided between the plurality of first semiconductor layers and the first wiring and stacked in the stacking direction; a first via wiring extending in the stacking direction and electrically connected to the first semiconductor layers and the second semiconductor layers; a plurality of first memory units stacked in the stacking direction and electrically connected to the plurality of first semiconductor layers, respectively; a plurality of first gate electrodes stacked in the stacking direction and facing the plurality of first semiconductor layers, respectively; a plurality of second wirings stacked in the stacking direction, extending in a second direction intersecting the stacking direction and the first direction, and electrically connected to the plurality of first gate electrodes, respectively; a plurality of first connection electrodes provided between the plurality of first memory units and the first wiring, stacked in the stacking direction, and electrically connected to the plurality of second semiconductor layers, respectively; a plurality of second gate electrodes provided between the plurality of first gate electrodes and the first wiring, stacked in the stacking direction, and facing the plurality of second semiconductor layers, respectively; a plurality of third wirings provided between the plurality of second wirings and the first wirings, stacked in the stacking direction, extending in the second direction, and electrically connected to the plurality of second gate electrodes, respectively; a fourth wiring extending in the stacking direction and electrically connected in common to the plurality of first memory units; a fifth wiring extending in the stacking direction and electrically connected in common to the plurality of first connection electrodes; Equipped Semiconductor memory device.

2. the plurality of first memory units includes a second memory unit closest to the plurality of first connection electrodes; the plurality of first connection electrodes include second connection electrodes closest to the plurality of first memory units; The fourth wiring has a first surface on a side closer to the first wiring in the stacking direction. the first surface is closer to the first wiring than a surface of the second memory unit on the second connection electrode side; The first surface is farther from the first wiring than a surface of the second connection electrode on the second memory unit side.

2. The semiconductor memory device according to claim 1.

3. the first via wiring has a second surface on a side closer to the first wiring in the stacking direction; the fifth wiring has a third surface on a side closer to the first wiring in the stacking direction; The third surface is closer to the first wiring than the second surface.

2. The semiconductor memory device according to claim 1.

4. The third surface is in contact with the first wiring.

4. The semiconductor memory device according to claim 3.

5. The fifth wiring is electrically connected to the first wiring.

2. The semiconductor memory device according to claim 1.

6. the fifth wiring has a fourth surface on a side farther from the first wiring in the stacking direction; the fourth surface is closer to the first wiring than a surface of the second memory unit on the second connection electrode side; The fourth surface is farther from the first wiring than a surface of the second connection electrode opposite to the second memory unit.

3. The semiconductor memory device according to claim 2.

7. the plurality of first memory units includes a third memory unit that is second closest to the plurality of first connection electrodes; the plurality of first connection electrodes include a third connection electrode that is second closest to the plurality of first memory units; a first insulating layer provided between the second memory portion and the third memory portion; a second insulating layer provided between the second connection electrode and the third connection electrode; a third insulating layer provided between the second memory portion and the second connection electrode; Equipped with a thickness of the third insulating layer in the stacking direction is greater than a thickness of the first insulating layer in the stacking direction; The thickness of the third insulating layer in the stacking direction is greater than the thickness of the second insulating layer in the stacking direction.

3. The semiconductor memory device according to claim 2.

8. The fifth wiring is provided between the fourth wiring and the first wiring.

2. The semiconductor memory device according to claim 1.

9. a plurality of third semiconductor layers stacked in the stacking direction and spaced apart from the plurality of first semiconductor layers in the first direction; a plurality of fourth semiconductor layers stacked in the stacking direction and spaced apart from the plurality of second semiconductor layers in the first direction; a second via wiring extending in the stacking direction and electrically connected to the third semiconductor layers and the fourth semiconductor layers; a plurality of fourth memory units stacked in the stacking direction and electrically connected to the plurality of third semiconductor layers, respectively; a plurality of fourth connection electrodes provided between the plurality of fourth memory units and the first wiring, stacked in the stacking direction, and electrically connected to the plurality of fourth semiconductor layers, respectively; Equipped with The fifth wiring is electrically connected in common to the plurality of fourth connection electrodes.

2. The semiconductor memory device according to claim 1.

10. The fifth wiring is provided between the plurality of first memory units and the first wiring.

2. The semiconductor memory device according to claim 1.

11. The first semiconductor layers and the second semiconductor layers each contain at least one element of gallium (Ga) and aluminum (Al), indium (In), zinc (Zn), and oxygen (O).

2. The semiconductor memory device according to claim 1.

12. At least one of the plurality of first memory units is a capacitor.

2. The semiconductor memory device according to claim 1.

13. the first gate electrodes face one or both of a surface on one side and a surface on the other side in the stacking direction of the first semiconductor layers, the first memory units are provided on one side in the second direction with respect to the one semiconductor layers, The second wirings are provided on the other side of the first semiconductor layers in the second direction.

2. The semiconductor memory device according to claim 1.

14. A first chip and a second chip are attached to each other via a plurality of attached electrodes, The first chip includes: The plurality of first semiconductor layers; A plurality of the first wirings; The plurality of second semiconductor layers; A plurality of the first via wirings; the plurality of first memory units; the plurality of first gate electrodes; The plurality of second wirings; The plurality of first connection electrodes; the plurality of second gate electrodes; The plurality of third wirings; The fourth wiring; A plurality of the fifth wirings; Equipped with The second chip is a control circuit electrically connected to the plurality of first wirings; 2. The semiconductor memory device according to claim 1.

15. forming a first opening at a position corresponding to the fourth wiring; forming a second opening at a position corresponding to a fifth memory unit, which is at least one of the plurality of first memory units, through the first opening; forming one electrode of the fifth memory unit inside the second opening; forming an insulating film inside the first opening and the second opening, the insulating film covering one electrode of the fifth memory unit inside the second opening; forming a conductive layer covering the insulating film inside the first opening and the second opening; removing a portion of the conductive layer to form the other electrode of the fifth memory unit and the plurality of first connection electrodes; forming the first via wiring; The fifth wiring is formed.

2. The method for manufacturing a semiconductor memory device according to claim 1.

Images