Semiconductor device and control method for semiconductor device

Abstract

To reduce noise on an SOI (Silicon On Insulator) substrate where transistors are formed.SOLUTION: A semiconductor device includes a transistor, a body bias generation circuit, a connection switch, and a control circuit. The transistor is formed in a predetermined well inside an SOI substrate. The body bias generation circuit generates a body bias to be applied to the well. The connection switch opens and closes a path between the well and the body bias generation circuit. The control circuit controls switching.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present technology relates to a semiconductor device, and more particularly to a semiconductor device in which an insulating film is formed under a channel of a transistor, and a method for controlling the semiconductor device. [Background technology]

[0002] Conventionally, MOS (Metal-Oxide-Semiconductor) transistors have been used in various elements and devices such as CIS (CMOS Image Sensors). For example, an imaging device has been proposed in which a MOS type amplifying transistor is formed on a substrate with an SOI (Silicon On Insulator) structure, and the well and source of the transistor are connected (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2013-118273 A Summary of the Invention [Problem to be solved by the invention]

[0004] In the above-mentioned conventional technology, the well and source of the amplifier transistor are connected to improve the gain of the output voltage of the amplifier transistor. However, in the above-mentioned imaging device, noise may be transmitted from the circuit that operates in synchronization with the clock signal to the analog circuit, and it is difficult to reduce the noise.

[0005] The present technology was developed in light of these circumstances, and aims to reduce noise in semiconductor devices that include SOI substrates. [Means for solving the problem]

[0006] The present technology has been made to solve the above-mentioned problems, and a first aspect thereof is a semiconductor device including a transistor formed in a predetermined well in an SOI (Silicon On Insulator) substrate, a body bias generating circuit that generates a body bias to be applied to the well, a connection switch that opens and closes a path between the well and the body bias generating circuit, and a control circuit that controls the connection switch, and a control method thereof, which brings about an effect of reducing noise.

[0007] In addition, in the first aspect, the control circuit may control the connection switch to an off state during a CDS period in which a CDS (Correlated Double Sampling) process is performed on an analog signal, and control the connection switch to an on state outside the CDS period, thereby providing an effect of suppressing noise propagation during the CDS period.

[0008] In addition, in this first aspect, the level of the analog signal may include a reset level and a signal level, the CDS period may include a sampling period of the reset level and a sampling period of the signal level, and the control circuit may control the connection switch to an off state during the sampling period of the CDS period and control the connection switch to an on state outside the sampling period, thereby providing an effect of suppressing noise propagation during the sampling period.

[0009] In addition, in this first aspect, the transistor may include an nMOS transistor formed in an N well and a pMOS transistor formed in a P well, and the connection switch may include an N-side connection switch that opens and closes a path between the N well and the body bias generating circuit, and a P-side connection switch that opens and closes a path between the P well and the body bias generating circuit, thereby providing an effect that the body biases of the pMOS transistor and the nMOS transistor are individually controlled.

[0010] In addition, in the first aspect, a pull-down switch may be further provided for opening and closing a path between a path between the connection switch and the well and a predetermined reference potential, thereby providing an effect of suppressing potential fluctuations.

[0011] Also, in this first aspect, the transistor may include an nMOS transistor formed in an N-well and a pMOS transistor formed in a P-well, the connection switch may include an N-side connection switch that opens and closes a path between the N-well and the body bias generating circuit and a P-side connection switch that opens and closes a path between the P-well and the body bias generating circuit, and the pull-down switch may include an N-side pull-down switch that opens and closes a path between the N-side connection switch and the N-well and the reference potential, and a P-side pull-down switch that opens and closes a path between the P-side connection switch and the P-well and the reference potential. This provides an effect that the body biases of the pMOS transistor and the nMOS transistor are individually controlled, suppressing potential fluctuations.

[0012] In addition, in the first aspect, the semiconductor device may further include a clock generating unit that generates a predetermined clock signal and supplies the clock signal to the body bias generating unit, thereby providing an effect that the body bias is generated in synchronization with the clock signal.

[0013] In addition, in the first aspect, the clock generating unit may generate the clock signal having a frequency that does not correspond to a predetermined shared frequency, thereby providing an effect of reducing noise.

[0014] In addition, in this first aspect, the control circuit may control the clock generating unit to generate the clock signal having a frequency higher than a predetermined value during a CDS period in which a CDS process is performed on an analog signal, and to generate the clock signal having a frequency lower than the predetermined value outside the CDS period, thereby providing an effect of suppressing noise propagation during the CDS period. [Brief description of the drawings]

[0015] [Figure 1] 1 is a block diagram showing an example of a configuration of an imaging device according to a first embodiment of the present technology. [Diagram 2] 1 is a block diagram showing a configuration example of a solid-state imaging element according to a first embodiment of the present technology. [Diagram 3] 2 is a block diagram showing a configuration example of a logic circuit and a body bias control unit according to a first embodiment of the present technology. FIG. [Figure 4] 2 is a block diagram showing a configuration example of a body-bias generation block according to a first embodiment of the present technology; FIG. [Diagram 5] FIG. 11 is a cross-sectional view showing an example of a bulk structure in a comparative example. [Figure 6] 1 is a cross-sectional view showing an example of a structure of an SOI (Silicon On Insulator) substrate according to a first embodiment of the present technology. [Figure 7] 4 is a timing chart showing an example of an operation of the solid-state imaging element according to the first embodiment of the present technology. [Figure 8] 6 is a timing chart showing another example of the operation of the solid-state imaging element according to the first embodiment of the present technology. [Figure 9] 2 is an example of a state transition diagram of a solid-state imaging element according to the first embodiment of the present technology. [Figure 10] 4] FIG. 4 is a diagram showing an example of control content for each mode in the first embodiment of the present technology. [Figure 11] 5 is a flowchart showing an example of an operation of the solid-state imaging element according to the first embodiment of the present technology. [Figure 12] 11 is a block diagram showing a configuration example of a body-bias generation block in a modified example of the first embodiment of the present technology. FIG. [Figure 13] 13 is a timing chart showing an example of an operation of a solid-state imaging element according to a modified example of the first embodiment of the present technology. [Figure 14]13 is a timing chart showing another example of the operation of the solid-state imaging element in the modified example of the first embodiment of the present technology. [Figure 15] 13 is a block diagram showing a configuration example of a body-bias generation block according to a second embodiment of the present technology. FIG. [Figure 16] 13 is a graph showing an example of noise characteristics in the second embodiment of the present technology. [Figure 17] 13 is a timing chart showing an example of an operation of a solid-state imaging element according to the second embodiment of the present technology. [Figure 18] 13 is a timing chart showing an example of an operation of a solid-state imaging element according to a modified example of the second embodiment of the present technology. [Figure 19] 1 is a block diagram showing a schematic configuration example of a vehicle control system; [Figure 20] FIG. 4 is an explanatory diagram showing an example of an installation position of an imaging unit. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] Hereinafter, modes for carrying out the present technology (hereinafter, referred to as embodiments) will be described. The description will be made in the following order. 1. First embodiment (example of controlling a connection switch) 2. Second embodiment (example of controlling the frequency of a clock signal) 3. Application examples for mobile objects

[0017] <1. First embodiment> [Example of imaging device configuration] 1 is a block diagram showing a configuration example of an imaging device 100 according to a first embodiment of the present technology. The imaging device 100 is a device for capturing image data, and includes an optical unit 110, a solid-state imaging element 200, and a DSP (Digital Signal Processing) circuit 120. The imaging device 100 further includes a display unit 130, an operation unit 140, a bus 150, a frame memory 160, a storage unit 170, and a power supply unit 180. The imaging device 100 may be a digital camera or an electronic device having an imaging function (such as a smartphone or a personal computer). The imaging device 100 is an example of a semiconductor device described in the claims.

[0018] The optical unit 110 collects light from a subject and guides it to the solid-state imaging element 200. The solid-state imaging element 200 generates image data by photoelectric conversion. The solid-state imaging element 200 generates the image data and supplies it to the DSP circuit 120 via a signal line 209. The solid-state imaging element 200 is also called a photodetector.

[0019] The DSP circuit 120 executes a predetermined signal processing on the image data and outputs the processed image data to a frame memory 160 or the like via a bus 150.

[0020] The display unit 130 displays image data. For example, a liquid crystal panel or an organic EL (Electro Luminescence) panel is assumed as the display unit 130. The operation unit 140 generates an operation signal in accordance with a user's operation.

[0021] The bus 150 is a common path for the optical unit 110, the solid-state imaging device 200, the DSP circuit 120, the display unit 130, the operation unit 140, the frame memory 160, the storage unit 170 and the power supply unit 180 to exchange data with one another.

[0022] The frame memory 160 holds image data. The storage unit 170 stores various data such as image data. The power supply unit 180 supplies power to the solid-state imaging element 200, the DSP circuit 120, the display unit 130, and the like.

[0023] [Example of the configuration of a solid-state imaging element] 2 is a block diagram showing a configuration example of a solid-state imaging element 200 according to the first embodiment of the present technology. The solid-state imaging element 200 includes an analog circuit 210, logic circuits 230, 240, and 250, and a body bias control unit 300. These circuits are provided on a single SOI substrate, for example. The circuits in the solid-state imaging element 200 can also be distributed and arranged on a plurality of semiconductor substrates including an SOI substrate.

[0024] A plurality of pixels 211 are arranged in a two-dimensional lattice in the analog circuit 210. Each of the pixels 211 photoelectrically converts incident light and generates an analog signal as a pixel signal Ain.

[0025] Furthermore, an ADC 220 is arranged for each column of the pixels 211. Each of the ADCs 220 includes a comparator 221 and a counter 222. For example, the comparator 221 is disposed in the analog circuit 210, and the counter 222 is disposed in the logic circuit 230.

[0026] The comparator 221 compares the pixel signal Ain from the corresponding column with the ramp signal Rmp, and supplies the comparison result to the counter 222. The counter 222 counts a count value over a period until the comparison result is inverted, and outputs a digital signal Dout indicating the count value. The pixel signal Ain is AD-converted by the comparator 221 and the counter 222.

[0027] The level of the pixel signal Ain includes a reset level and a signal level, where the reset level is the level when the pixel 211 is initialized, and the signal level is the level according to the amount of exposure when the charge is transferred within the pixel 211.

[0028] The counter 222 counts down during the sampling period of the reset level and counts up during the sampling period of the signal level, thereby performing AD conversion as well as CDS processing to find the difference between the reset level and the signal level.

[0029] It should be noted that the ADC 220 performs AD conversion and CDS processing, but is not limited to this configuration. The ADC 220 may perform only AD conversion, and a subsequent circuit may execute CDS processing.

[0030] The logic circuits 230, 240, and 250 perform various signal processing on the digital signal Dout. The logic circuit 250 outputs image data in which the processed digital signal Dout is arranged to the DSP circuit 120. In the SOI substrate, the wells in which the logic circuits 230, 240, and 250 are formed are assumed to be separated from each other.

[0031] The body bias control unit 300 controls the body bias, which is a voltage applied to each of the wells of the logic circuits 230 , 240 , and 250 .

[0032] [Example of logic circuit and body bias control unit configuration] FIG. 3 is a block diagram showing an example configuration of the logic circuit 230 and the body bias control unit 300 according to the first embodiment of the present technology.

[0033] The body bias control unit 300 includes a regulator circuit 310 , power switches 321 to 324 , body bias generation blocks 330 , 340 , 350 and 360 , and a control circuit 370 .

[0034] The regulator circuit 310 generates a constant output voltage V LDO The output voltage V LDO are supplied to each of the power switches 321 to 324.

[0035] The power switch 321 opens and closes a path between the output node of the regulator circuit 310 and the body bias generation block 330 in accordance with a control signal SW 1 from the logic circuit 230 .

[0036] The power switch 322 opens and closes the path between the output node of the regulator circuit 310 and the body bias generation block 340 in accordance with a control signal SW2 from the logic circuit 230.

[0037] The power switch 323 opens and closes the path between the output node of the regulator circuit 310 and the body bias generation block 350 in accordance with a control signal SW 3 from the logic circuit 230 .

[0038] The power switch 324 opens and closes the path between the output node of the regulator circuit 310 and the body bias generation block 360 in accordance with a control signal SW 4 from the logic circuit 230 .

[0039] The body bias generation block 330 generates a body bias V PW1 and V NW1 The output voltage V LDO It is generated from

[0040] The circuit configuration of the body-bias generation blocks 340, 350, and 360 is similar to that of the body-bias generation block 330. The output nodes of the body-bias generation blocks 330 and 340 are shorted and commonly connected to the logic circuit 230. When the circuit scale of the logic circuit is large, a plurality of body-bias generation blocks can be connected as shown in the figure to reduce the load of each block.

[0041] The body bias generation block 350 generates a body bias V PW3 and V NW3 The output voltage V LDO The body bias generation block 360 generates the body bias V PW4 and V NW4 The output voltage V LDO Generated from

[0042] The control circuit 370 controls the output operations of the body bias generation blocks 330, 340, 350 and 360 by control signals EN1 to EN4.

[0043] The logic circuit 230 includes an OTP (One Time Programmable) memory 231, a register circuit 232, and a clock generating unit 233.

[0044] The OTP (One Time Programmable) memory 231 holds the setting values ​​of the control signals SW1 to SW4, the control signals CNT1 to CNT4, and the frequency of the clock signal CK. Note that any memory other than the OTP memory 231 may be used as long as it is non-volatile.

[0045] The respective setting values ​​of the control signals SW1 to SW4 and the frequency are appropriately set according to the usage method of the imaging device 100. Furthermore, the control signals CNT1 to CNT4 are signals indicating the values ​​of the body bias, and are set in advance by a test circuit (not shown), for example, before the solid-state imaging element 200 starts an imaging operation.

[0046] The test circuit, for example, generates a test signal in the logic circuit 230 or the like, and sets the values ​​of the control signals CNT1 to CNT4 for each substrate based on the result of comparing the value of the test signal with a reference value. These set values ​​can suppress fluctuations in the threshold voltage of the transistors caused by process variations.

[0047] The register circuit 232 reads out and holds the set value from the OTP memory 231. The register circuit 232 supplies a control signal of the held set value to the body bias control unit 300, and supplies the frequency set value to the clock generation unit 233.

[0048] The clock generating unit 233 generates a clock signal CK in accordance with the set value of the register circuit 232, and supplies the clock signal CK to the body bias control unit 300. The clock generating unit 233 may be a phase-locked loop circuit or the like.

[0049] Although the body bias control unit 300 controls only the body bias of the logic circuit, it can also control the body bias of both the analog circuit and the logic circuit, and it can also control only the body bias of the analog circuit.

[0050] [Example of body-bias generation block configuration] 4 is a block diagram showing an example of a configuration of a body bias generation block 330 according to the first embodiment of the present technology. The body bias generation block 330 includes a body bias generation unit 400, a P-side connection switch 331, and an N-side connection switch 332. The logic circuit 230 includes a predetermined number of pMOS transistors such as a pMOS transistor 234, and a predetermined number of nMOS transistors such as an nMOS transistor 235.

[0051] The body bias generating unit 400 generates a body bias V PW1 and V NW1 The output voltage V LDOThe body bias V PW1 is output to the P-side connection switch 331, and the body bias V NW1 is output to the N-side connection switch 332.

[0052] The P-side connection switch 331 opens and closes a path between the body bias generation unit 400 and a well in which a pMOS transistor is formed, in accordance with a control signal EN_PW1 from the control circuit 370. One end of the P-side connection switch 331 is connected to the body bias generation unit 400, and the other end is connected to a well on the pMOS transistor side via a signal line 408. Note that the P-side connection switch 331 is not limited to the illustrated nMOS transistor, and any switching element such as a pMOS transistor, a shared switching element of an nMOS transistor and a pMOS transistor, a bipolar transistor, or an IGBT (Insulated Gate Bipolar Transistor) can be applied.

[0053] The N-side connection switch 332 opens and closes a path between the body bias generation unit 400 and a well in which an nMOS transistor is formed, in accordance with a control signal EN_NW1 from the control circuit 370. One end of the N-side connection switch 332 is connected to the body bias generation unit 400, and the other end is connected to a well on the nMOS transistor side via a signal line 409. Note that the N-side connection switch 332 is not limited to the illustrated nMOS transistor, and any switching element such as a pMOS transistor, a shared switching element of an nMOS transistor and a pMOS transistor, a bipolar transistor, or an IGBT (Insulated Gate Bipolar Transistor) can be applied.

[0054] The control signals EN_PW1 and EN_NW1 in the figure are signals within the above-mentioned control signal EN1.

[0055] The body bias generating unit 400 includes a P-side charge pump 410 , an N-side charge pump 420 , a control block 430 , a P-side voltage adjusting unit 440 , and an N-side voltage adjusting unit 450 .

[0056] The P-side charge pump 410 turns on and off an internal switch (not shown) in synchronization with a clock signal CK to generate an output voltage V LDO and supplies it to P-side voltage adjustment unit 440.

[0057] The N-side charge pump 420 turns on and off an internal switch (not shown) in synchronization with a clock signal CK to generate an output voltage V LDO and supplies it to the N-side voltage adjustment unit 450.

[0058] The P-side voltage regulator 440 regulates the voltage from the P-side charge pump 410 under the control of the control block 430, and generates a body bias V PW1 The body bias V PW1 For example, a negative voltage is used as the voltage.

[0059] The N-side voltage regulator 450 regulates the voltage from the N-side charge pump 420 under the control of the control block 430, and generates a body bias V NW1 The body bias V NW1 For example, a positive voltage is used as the input voltage.

[0060] The control block 430 controls the amount of voltage adjustment of each of the P-side voltage adjustment unit 440 and the N-side voltage adjustment unit 450 based on a control signal CNT 1 from the register circuit 232 .

[0061] With the above-described configuration, the body bias generating unit 400 applies a body bias V PW1 and V NW1The P-side connection switch 331 and the N-side connection switch 332 open and close a path between the body bias generation unit 400 and the well. The control circuit 370 controls these switches.

[0062] For example, the control circuit 370 controls both the P-side connection switch 331 and the N-side connection switch 332 to the OFF state during a CDS period in which the CDS process is performed, and controls both of them to the ON state outside the CDS period. This control makes it possible to prevent noise from being propagated from the P-side charge pump 410 and the N-side charge pump 420 to the analog circuit 210.

[0063] During the period in which the P-side connection switch 331 and the N-side connection switch 332 are in the off state, the body bias is sampled and held by the parasitic capacitance in the SOI substrate. In the figure, the capacitance indicated by the dotted line represents the parasitic capacitance.

[0064] Here, a device using a general bulk structure without an insulating film is considered as a comparative example.

[0065] 5 is a cross-sectional view showing an example of a bulk structure in a comparative example. The semiconductor substrate in the comparative example includes a P substrate 501. A deep N well 502 is formed in this P substrate 501.

[0066] In the deep N well 502, N - Layers 511 and P - A layer 521 is formed. - In layer 511, P + Layer 512 and N + A source 513 and a drain 515 of the layer are formed. - In the layer 521, N + Layer 522 and P + A source 523 and a drain 525 of layers are formed.

[0067] P + A body bias of ground potential VSS is applied to layer 512, and N +A body bias of the power supply potential VDD is applied to layer 522. A gate 514 is formed between source 513 and drain 515, which function as an nMOS transistor. A gate 524 is formed between source 523 and drain 525, which function as a pMOS transistor. A bias higher than the ground potential VSS on the nMOS side and lower than the power supply potential VDD on the pMOS side is set as the forward potential.

[0068] In the comparative example, if the body bias is set to the forward side, the operating speed is improved due to the substrate bias effect, but the diode component in the substrate turns on and the leakage current increases. For this reason, in the bulk structure, it is practically difficult to control the body bias to the forward side.

[0069] However, there are cases where it is desirable to improve operating speed even if it increases leakage current, and cases where the body bias is controlled to the forward side only in some circuits. Specifically, analog circuits such as differential pair circuits that require high-speed operation are assumed. On the other hand, logic circuits have a simpler logic cell structure than analog circuits, and there is no need to control the threshold voltage of transistors, so the body bias of logic circuits is rarely controlled to the forward side.

[0070] [Example of SOI substrate configuration] 6 is a cross-sectional view showing an example of the structure of an SOI substrate 500 according to the first embodiment of the present technology. In this SOI substrate 500, a circuit in the solid-state imaging device 200 is formed.

[0071] The SOI substrate 500 further includes a predetermined number of insulating layers 503 and insulating films 504 and 505. + Layers 512 and N + The structure differs from the bulk structure of the comparative example in that the position of layer 522 is different.

[0072] P + Layer and N +Between the layers, an insulating layer 503 is formed. Furthermore, with the gate side facing up, an insulating film 504 is formed immediately below the channel of the nMOS transistor, and an insulating film 505 is formed immediately below the channel of the pMOS transistor.

[0073] Also, P + Layer 512 is P - layer 521, and N + Layer 522 is N - formed in layer 511. + The layer 522 includes the body bias V NW1 This body bias V NW1 is set, for example, in the range of 0 to +2 volts (V). + Layer 512 includes body-bias V from body-bias generation block 330. PW1 This body bias V PW1 is set, for example, in the range of 0 to −2 volts (V).

[0074] In addition, N - Layer 511 is an example of an N-well as described in the claims. - Layer 521 is an example of a P-well as defined in the claims.

[0075] The SOI structure shown in the figure is called a FD (Fully Depleted)-SOI structure. In this FD-SOI structure, a layer to which a body bias is applied (i.e., P + Layers 512 and N + Since the polarity of the layer 522 is inverted, even if the body bias is on the forward side, the diode component in the substrate does not turn on, and leakage current is suppressed.

[0076] Therefore, the body bias control unit 300 can control the body bias in a direction to lower the threshold voltage of the transistor, in other words, to the forward side. A control signal CNT1 or the like is set for each SOI substrate 500, and the body bias control unit 300 controls the body bias according to the control signal, thereby suppressing fluctuations in the threshold voltage due to process variations.

[0077] For example, for slow-speed SOI substrates, setting the body bias on the forward side reduces the speed variation for each substrate and improves characteristics. It also reduces the difficulty of timing design. For fast-speed SOI substrates, the body bias is not set to the forward side, so the maximum leakage current of the entire product does not change.

[0078] [Example of operation of solid-state imaging device] 7 is a timing chart showing an example of the operation of the solid-state imaging device 200 according to the first embodiment of the present technology. During an exposure period from timing T0 to T1, a vertical scanning circuit (not shown) simultaneously exposes all pixels in the analog circuit 210. During a readout period from timing T1 to T2, the vertical scanning circuit sequentially selects rows in the analog circuit 210.

[0079] The row selection period includes a CDS period during which AD conversion and CDS processing are performed. The CDS period for a certain row is set to be from timing T11 to T15. During the period from timing T12 to T13 in this CDS period, the ramp signal Rmp gradually falls and sampling of the reset level is performed. This period is called a sampling period dT smp1 Let us assume that.

[0080] Then, the ramp signal Rmp gradually drops over the period from timing T14 to T15, and the signal level is sampled. This period is called a sampling period dT smp2 Let us assume that.

[0081] The control circuit 370 sets the control signals EN_PW1 and EN_NW1 to high level outside the CDS period to control the corresponding connection switches to the on state. For example, the period from the end of the CDS period of a row to the start of the CDS period of the next row and the exposure period correspond to the period outside the CDS period.

[0082] Furthermore, the control circuit 370 sets the control signals EN_PW1 and EN_NW1 to a low level during the CDS period to control the corresponding connection switches to an off state. During the period in which the switches are off, the body bias is sampled and held in the parasitic capacitance in the SOI substrate.

[0083] If the P-side connection switch 331 and the N-side connection switch 332 are always on, the body bias generation unit 400 that operates in synchronization with the clock signal CK becomes a noise source, and the noise may propagate to the analog circuit 210 during readout.

[0084] Therefore, as illustrated in the figure, the control circuit 370 controls the P-side connection switch 331 and the N-side connection switch 332 to be in the OFF state during the CDS period. This separates the body bias generation unit 400 from the well, suppressing the propagation of noise to the analog circuit 210 and reducing noise in the pixel signal. As a result, the image quality of the image data is improved.

[0085] It is also possible to use a rolling shutter method in which exposure is started by selecting rows in sequence. In this case, part of the exposure period overlaps with the CDS period, but the switch is similarly controlled to be in the off state during the CDS period.

[0086] 8A, the control circuit 370 can turn on and off only one of the switches when improving the speed of only one of the pMOS and nMOS. In this case, the control circuit 370 turns on one of the P-side connection switch 331 and the N-side connection switch 332 (for example, the N-side connection switch 332) outside the CDS period and turns off the other. During the CDS period, both the P-side connection switch 331 and the N-side connection switch 332 are controlled to be in the off state.

[0087] As shown in FIG. 1B, the control circuit 370 controls the sampling period T smp1 and T smp2 It is also possible to turn the P-side connection switch 331 and the N-side connection switch 332 off only during these periods and turn them on outside of these periods.

[0088] 9 is an example of a state transition diagram of the solid-state imaging device 200 in the first embodiment of the present technology. The initial state of the solid-state imaging device 200 is a power-off state 601. When the power is turned on in the power-off state 601, the solid-state imaging device 200 transitions to a hardware standby state 602.

[0089] When the viewing mode is set in the hardware standby state 602, the solid-state imaging device 200 transitions to a switch standby state 604. Here, the viewing mode is a mode for capturing still images or moving images.

[0090] When the still image mode is set in the switch standby state 604, the solid-state imaging device 200 transitions to a still image mode 605. This still image mode 605 is a mode for capturing a still image.

[0091] When imaging is completed in the still image mode 605, the solid-state imaging device 200 can transition to the sensing mode 603 or the moving image mode 606, for example, in accordance with a user operation.

[0092] When the moving image mode is set in the switch standby state 604, the solid-state imaging device 200 transitions to a moving image mode 606. This moving image mode 606 is a mode for capturing moving images.

[0093] When imaging is completed in the moving image mode 606, the solid-state imaging device 200 can transition to the sensing mode 603 or the still image mode 605, for example, in accordance with a user operation.

[0094] When the sensing mode is set in the hardware standby state 602, the solid-state imaging device 200 transitions to a sensing mode 603. The sensing mode 603 is a mode for detecting a moving object.

[0095] When a moving object is detected in the sensing mode 603, the solid-state imaging device 200 transitions to, for example, a still image mode 605 or a moving image mode 606.

[0096] 10 is a diagram showing an example of the control contents for each mode in the first embodiment of the present technology. In the sensing mode, high image quality is not required compared to the viewing mode. Therefore, the control circuit 370 always controls the P-side connection switch 331 and the N-side connection switch 332 to the off state and stops the application of the body bias.

[0097] On the other hand, in the still image mode and the video mode, higher image quality is required compared to the sensing mode. Therefore, the control circuit 370 controls the P-side connection switch 331 and the N-side connection switch 332 to the OFF state during the CDS period. Outside the CDS period, these connection switches are controlled to the ON state.

[0098] 11 is a flowchart showing an example of the operation of the solid-state imaging device 200 according to the first embodiment of the present technology. This operation is started, for example, when a predetermined application for capturing image data is executed.

[0099] The solid-state imaging element 200 selects one of the rows to be read out (step S901). The control circuit 370 turns off the P-side connection switch 331 and the N-side connection switch 332 during the CDS period of the selected row, and the ADC 220 performs AD conversion and CDS processing (step S902). At the end of the CDS processing, the control circuit 370 turns on the P-side connection switch 331 and the N-side connection switch 332 (step S903).

[0100] The solid-state imaging element 200 determines whether or not the readout of all rows is complete (step S904). If the readout of all rows is not complete (step S904: No), the solid-state imaging element 200 repeats steps S901 and onward. On the other hand, if the readout of all rows is complete (step S904: Yes), the solid-state imaging element 200 ends the operation for imaging.

[0101] As described above, according to the first embodiment of the present technology, the control circuit 370 turns off the P-side connection switch 331 and the N-side connection switch 332 during the CDS period, thereby making it possible to reduce noise in the pixel signal.

[0102] [Variations] In the above-described first embodiment, the control circuit 370 turns off the P-side connection switch 331 and the N-side connection switch 332 during the CDS period. However, during the CDS period, the potentials of the signal lines 408 and 409 between the P-side connection switch 331 and the N-side connection switch 332 and the well may become floating and fluctuate. The solid-state imaging device 200 in this modification of the first embodiment differs from the first embodiment in that the signal lines 408 and 409 are set to high impedance during the CDS period.

[0103] 12 is a block diagram showing a configuration example of a body bias generation block 330 in a modification of the first embodiment of the present technology. The body bias generation block 330 in the modification of the first embodiment differs from the first embodiment in that it further includes a P-side pull-down switch 333 and an N-side pull-down switch 334. For example, nMOS transistors are used as these switches.

[0104] The P-side pull-down switch 333 opens and closes a path between the P-side connection switch 331, the signal line 408 between the well, and a predetermined reference potential in accordance with a control signal PD_PW1 from the control circuit 370. As the reference potential, for example, the ground potential VSS is used.

[0105] The N-side pull-down switch 334 opens and closes a path between the signal line 409 between the N-side connection switch 332 and the well, and a predetermined reference potential (such as the ground potential VSS), in accordance with a control signal PD_NW1 from the control circuit 370.

[0106] The pull-down switches and the connect switches are exclusively controlled.

[0107] 13 is a timing chart showing an example of an operation of the solid-state imaging device 200 in the modification of the first embodiment of the present technology. In the modification of the first embodiment, the method of controlling the control signals EN_PW1 and EN_NW1 is similar to that of the first embodiment.

[0108] The control circuit 370 sets the control signals PD_PW1 and PD_NW1 to a high level during the CDS period to control the corresponding pull-down switches to an on state, and sets the control signals PD_PW1 and PD_NW1 to a low level outside the CDS period to control the corresponding pull-down switches to an off state.

[0109] As shown in the figure, the control circuit 370 turns on the pull-down switch during the CDS period, thereby fixing the signal lines 408 and 409 to the reference potential. These signal lines become high impedance, so that potential fluctuations during the CDS period can be suppressed.

[0110] As shown in FIG. 14, the control circuit 370 can turn on and off only one of the P-side pull-down switch 333 and the N-side pull-down switch 334.

[0111] In this case, the control circuit 370 turns on one of the P-side connection switch 331 and the N-side connection switch 332 (for example, the N-side connection switch 332) outside the CDS period and turns off the other. During the CDS period, both the P-side connection switch 331 and the N-side connection switch 332 are controlled to be in the off state.

[0112] When only the N-side connection switch 332 is turned on and off, the control circuit 370 turns off the N-side pull-down switch 334 outside the CDS period and turns on the P-side pull-down switch 333. During the CDS period, both the P-side pull-down switch 333 and the N-side pull-down switch 334 are controlled to be on.

[0113] Also, the control circuit 370 can turn the connection switch off only during the sampling period of the CDS period and turn the connection switch on outside of those periods. In this case, the pull-down switch is controlled to be on during the sampling period and the pull-down switch is controlled to be off outside the sampling period.

[0114] In this manner, according to the modification of the first embodiment of the present technology, the control circuit 370 turns on the P-side pull-down switch 333 and the N-side pull-down switch 334 during the CDS period, thereby suppressing the potential fluctuation of the signal line during that period.

[0115] <2. Second embodiment> In the above-described first embodiment, the clock generating unit 233 generates a clock signal CK having a frequency set in the register circuit 232, but there is a risk that an unintended resonant circuit may occur in the circuit of the solid-state imaging element 200, causing an increase in noise at the resonant frequency of the circuit. The solid-state imaging element 200 in this second embodiment differs from the first embodiment in that it generates a clock signal CK having a frequency that does not correspond to the resonant frequency.

[0116] 15 is a block diagram showing a configuration example of the body bias generation block 330 according to the second embodiment of the present technology. In the second embodiment, the control circuit 370 always sets the control signals EP_PW1 and EP_NW1 to a high level during imaging. Therefore, the P-side connection switch 331 and the N-side connection switch 332 are controlled to be in an on state even during the CDS period.

[0117] Moreover, the clock generating unit 233 of the second embodiment generates a clock signal CK having a frequency that does not correspond to the predetermined resonant frequency, and supplies the clock signal CK to the body bias generating unit 400.

[0118] 16 is a graph showing an example of noise characteristics in the second embodiment of the present technology, in which the vertical axis indicates the maximum voltage gain of the propagating noise, and the horizontal axis indicates the frequency of the clock signal CK.

[0119] When an unintended resonant circuit occurs in the noise propagation path, the noise may increase at the resonant frequency of the circuit. In the figure, the gain peaks at resonant frequencies f1, f2, and f3. Therefore, the clock generating unit 233 generates a clock signal CK with a frequency that does not fall within these resonant frequencies.

[0120] For example, the test circuit measures noise for each frequency and obtains the resonant frequency in advance. Then, the test circuit sets a frequency that does not correspond to the resonant frequency in the OTP memory 231. Alternatively, the test circuit sets a resonant frequency in the OTP memory 231, and the control circuit 370 controls the clock generation unit 233 to generate a frequency that does not correspond to the resonant frequency. When the resonant frequency is 20 megahertz (MHz), the frequency is controlled to 18 megahertz (MHz) or the like to avoid that frequency.

[0121] 17 is a timing chart showing an example of the operation of the solid-state imaging device 200 according to the second embodiment of the present technology. In the second embodiment, the clock generating unit 233 generates a clock signal CK having a frequency that does not correspond to the resonant frequency. In addition, the control signals EP_PW1 and EP_NW1 are controlled to a high level even during the CDS period.

[0122] As described above, according to the second embodiment of the present technology, the clock generating unit 233 generates the clock signal CK having a frequency that does not correspond to the resonant frequency, so that it is possible to reduce noise.

[0123] [Variations] In the second embodiment described above, the clock generating unit 233 generates a clock signal CK having a frequency that does not correspond to the resonant frequency, but the frequency can be lowered within the CDS period. The solid-state imaging device 200 in the modified example of the second embodiment differs from the second embodiment in that the frequency of the clock signal CK is lowered within the CDS period.

[0124] 18 is a timing chart showing an example of the operation of the solid-state imaging device 200 in the modified example of the second embodiment of the present technology. In this modified example of the second embodiment, the control circuit 370 controls the clock generating unit 233 to generate a clock signal CK having a frequency higher than a predetermined value outside the CDS period, and to generate a clock signal CK having a frequency lower than the predetermined value within the CDS period.

[0125] For example, the control circuit 370 controls the frequency of the clock signal CK to 20 megahertz (MHz) outside the CDS period, and reduces the frequency to 2 megahertz (MHz) during the CDS period. This control can reduce noise.

[0126] Furthermore, the control signals EP_PW1 and EP_NW1 are controlled to a high level during the CDS period as well.

[0127] The control circuit 370 can also control the frequency during the sampling period of the CDS interval to be lower than the frequency outside the sampling period.

[0128] In this way, according to the modification of the second embodiment of the present technology, the control circuit 370 reduces the frequency of the clock signal CK within the CDS period, so that the noise propagating to the analog circuit 210 can be reduced.

[0129] <3. Application examples for mobile objects> The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of moving body such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility device, an airplane, a drone, a ship, a robot, etc.

[0130] FIG. 19 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a moving object control system to which the technology according to the present disclosure can be applied.

[0131] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 19, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also, as functional configurations of the integrated control unit 12050, a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (interface) 12053 are illustrated.

[0132] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0133] The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as head lamps, back lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves or signals of various switches transmitted from a portable device that replaces a key may be input to the body system control unit 12020. The body system control unit 12020 receives the input of these radio waves or signals and controls the door lock device, power window device, lamps, and the like of the vehicle.

[0134] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture an image outside the vehicle and receives the captured image. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for a person, a car, an obstacle, a sign, or characters on a road surface, based on the received image.

[0135] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of light received. The imaging unit 12031 can output the electrical signal as an image, or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0136] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing.

[0137] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, the steering mechanism, or the braking device based on the information inside and outside the vehicle acquired by the outside-of-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output a control command to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, vehicle lane departure warning, etc.

[0138] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on the driver's operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle acquired by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0139] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside-vehicle information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside-vehicle information detection unit 12030, and perform cooperative control for the purpose of preventing glare, such as switching from high beams to low beams.

[0140] The audio / image output unit 12052 transmits at least one output signal of audio and image to an output device capable of visually or audibly notifying information to passengers in the vehicle or the outside of the vehicle. In the example of Fig. 19, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are exemplified as the output device. The display unit 12062 may include at least one of an on-board display and a head-up display, for example.

[0141] FIG. 20 is a diagram showing an example of the installation position of the imaging unit 12031.

[0142] In FIG. 20, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0143] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided at positions such as the front nose, side mirrors, rear bumper, back door, and the upper part of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided at the front nose and the imaging unit 12105 provided at the upper part of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided at the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided at the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided at the upper part of the windshield inside the vehicle cabin is mainly used to detect a preceding vehicle, a pedestrian, an obstacle, a traffic light, a traffic sign, a lane, or the like.

[0144] 20 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, an overhead image of the vehicle 12100 viewed from above is obtained by superimposing the image data captured by the imaging units 12101 to 12104.

[0145] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera made up of a plurality of imaging elements, or may be an imaging element having pixels for detecting a phase difference.

[0146] For example, the microcomputer 12051 can extract, as a preceding vehicle, a three-dimensional object that is the closest three-dimensional object on the travel path of the vehicle 12100 and travels at a predetermined speed (for example, 0 km / h or more) in approximately the same direction as the vehicle 12100, by calculating the distance to each three-dimensional object in the imaging ranges 12111 to 12114 and the change over time of this distance (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104. Furthermore, the microcomputer 12051 can set a vehicle distance to be secured in advance in front of the preceding vehicle, and perform automatic brake control (including follow-up stop control) and automatic acceleration control (including follow-up start control). In this way, cooperative control can be performed for the purpose of automatic driving that travels autonomously without relying on the driver's operation.

[0147] For example, the microcomputer 12051 classifies and extracts three-dimensional object data on three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. Then, the microcomputer 12051 determines a collision risk indicating the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0148] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether or not a pedestrian is present in the captured images of the imaging units 12101 to 12104. The recognition of such a pedestrian is performed, for example, by a procedure of extracting feature points in the captured images of the imaging units 12101 to 12104 as infrared cameras, and a procedure of performing pattern matching processing on a series of feature points that indicate the contour of an object to determine whether or not the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the captured images of the imaging units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating a pedestrian at a desired position.

[0149] An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to the imaging unit 12031, etc., among the configurations described above. Specifically, the imaging device 100 in FIG. 1 can be applied to the imaging unit 12031. By applying the technology according to the present disclosure to the imaging unit 12031, noise is reduced and a captured image that is easier to see can be obtained, thereby reducing driver fatigue.

[0150] The above-mentioned embodiment shows an example for realizing the present technology, and the matters in the embodiment and the matters specified in the claims correspond to each other. Similarly, the matters specified in the claims and the matters in the embodiment of the present technology having the same name correspond to each other. However, the present technology is not limited to the embodiment, and can be realized by applying various modifications to the embodiment within the scope of the gist of the technology.

[0151] It should be noted that the effects described in this specification are merely examples and are not limiting, and other effects may also be obtained.

[0152] The present technology can also be configured as follows. (1) A transistor formed in a predetermined well in an SOI (Silicon On Insulator) substrate; a body bias generating circuit for generating a body bias to be applied to the well; a connection switch that opens and closes a path between the well and the body bias generation circuit; A control circuit for controlling the connection switch; A semiconductor device comprising: (2) The control circuit controls the connection switch to an off state during a CDS period in which a CDS (Correlated Double Sampling) process is performed on an analog signal, and controls the connection switch to an on state outside the CDS period. The semiconductor device according to (1) above. (3) the level of the analog signal includes a reset level and a signal level; the CDS period includes a sampling period of the reset level and a sampling period of the signal level, The control circuit controls the connection switch to an OFF state during the sampling period of the CDS period, and controls the connection switch to an ON state outside the sampling period. The semiconductor device according to (1) above. (4) The transistor includes an nMOS transistor formed in an N well and a pMOS transistor formed in a P well; The connection switch includes an N-side connection switch that opens and closes a path between the N-well and the body bias generation circuit, and a P-side connection switch that opens and closes a path between the P-well and the body bias generation circuit. The semiconductor device according to any one of (1) to (3). (5) The semiconductor device according to any one of (1) to (4), further comprising a pull-down switch that opens and closes a path between the connection switch and the well and a predetermined reference potential. (6) The transistor includes an nMOS transistor formed in an N well and a pMOS transistor formed in a P well; the connection switch includes an N-side connection switch that opens and closes a path between the N-well and the body bias generation circuit, and a P-side connection switch that opens and closes a path between the P-well and the body bias generation circuit, The pull-down switch is an N-side pull-down switch that opens and closes a path between the N-side connection switch and the N-well and the reference potential; a P-side pull-down switch that opens and closes a path between the P-side connection switch and the P-well and a path between the reference potential; The semiconductor device according to (5) above, (7) The semiconductor device according to (1) above, further comprising a clock generating section which generates a predetermined clock signal and supplies the clock signal to the body bias generating section. (8) The clock generating unit generates the clock signal having a frequency that does not correspond to a predetermined shared frequency. The semiconductor device according to (7) above. (9) The control circuit controls the clock generating unit to generate the clock signal having a frequency higher than a predetermined value during a CDS period in which a CDS process is performed on an analog signal, and to generate the clock signal having a frequency lower than the predetermined value outside the CDS period. The semiconductor device according to (7) above. (10) a body bias generation step for generating a body bias to be applied to a well in an SOI (Silicon On Insulator) substrate in which a transistor is formed; a control procedure for controlling a connection switch that opens and closes a path between the well and the body bias generation circuit; A method for controlling a semiconductor device comprising the steps of: [Explanation of symbols]

[0153] 100 Imaging device 110 Optics Department 120 DSP circuits 130 Display section 140 Operation section 150 Bus 160 Frame Memory 170 Storage section 180 Power supply section 200 Solid-state image sensor 210 Analog Circuits 211 pixels 220 ADC 221 Comparator 222 Counter 230, 240, 250 Logic circuits 231 OTP Memory 232 Register Circuit 233 Clock Generation Unit 234 pMOS transistor 235 nMOS transistor 300 Body bias control unit 310 regulator circuit 321~324 Power switch 330, 340, 350, 360 Body bias generation block 331 P side connection switch 332 N-side connection switch 333 P side pull-down switch 334 N-side pull-down switch 370 Control circuit 400 Body bias generator 410 P-side charge pump 420 N-side charge pump 430 Control Blocks 440 P side voltage adjustment unit 450 N side voltage adjustment unit 500 SOI substrate 501P board 502 Deep N-well 503 Insulation Layer 504, 505 Insulating film 511 N - layer 512 P + layer 513, 523 Source Gates 514 and 524 515, 525 Drain 521 P - layer 522 N + layer 12031 Imaging unit

Claims

1. A transistor formed in a predetermined well in an SOI (Silicon On Insulator) substrate; a body bias generating circuit for generating a body bias to be applied to the well; a connection switch that opens and closes a path between the well and the body bias generation circuit; A control circuit for controlling the connection switch; A semiconductor device comprising:

2. The control circuit controls the connection switch to an OFF state during a CDS (Correlated Double Sampling) period in which a CDS process is performed on an analog signal, and controls the connection switch to an ON state outside the CDS period. The semiconductor device according to claim 1.

3. the level of the analog signal includes a reset level and a signal level; the CDS period includes a sampling period of the reset level and a sampling period of the signal level, The control circuit controls the connection switch to an OFF state during the sampling period of the CDS period, and controls the connection switch to an ON state outside the sampling period. The semiconductor device according to claim 1.

4. The transistors include an nMOS transistor formed in an N-well and a pMOS transistor formed in a P-well; The connection switch includes an N-side connection switch that opens and closes a path between the N-well and the body bias generation circuit, and a P-side connection switch that opens and closes a path between the P-well and the body bias generation circuit. The semiconductor device according to claim 1.

5. 2. The semiconductor device according to claim 1, further comprising a pull-down switch for opening and closing a path between the path between said connection switch and said well and a predetermined reference potential.

6. The transistors include an nMOS transistor formed in an N-well and a pMOS transistor formed in a P-well; the connection switch includes an N-side connection switch that opens and closes a path between the N-well and the body bias generation circuit, and a P-side connection switch that opens and closes a path between the P-well and the body bias generation circuit, The pull-down switch is an N-side pull-down switch that opens and closes a path between the N-side connection switch and the N-well and the reference potential; a P-side pull-down switch that opens and closes a path between the P-side connection switch and the P-well and a path between the reference potential; 6. The semiconductor device according to claim 5, comprising:

7. 2. The semiconductor device according to claim 1, further comprising a clock generating section which generates a predetermined clock signal and supplies the clock signal to said body bias generating section.

8. The clock generating unit generates the clock signal having a frequency that does not correspond to a predetermined shared frequency.

8. The semiconductor device according to claim 7.

9. The control circuit controls the clock generating unit to generate the clock signal having a frequency higher than a predetermined value during a CDS period in which a CDS process is performed on an analog signal, and to generate the clock signal having a frequency lower than the predetermined value outside the CDS period.

8. The semiconductor device according to claim 7.

10. a body bias generation procedure for generating a body bias to be applied to a well in which a transistor is formed in an SOI (Silicon On Insulator) substrate; a control procedure for controlling a connection switch that opens and closes a path between the well and the body bias generation circuit; A method for controlling a semiconductor device comprising the steps of:

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