Semiconductor memory device

Abstract

To provide a semiconductor memory device that can be suitably manufactured.SOLUTION: A semiconductor memory device includes a plurality of finger structures (FS) arranged in a first direction (Y). The plurality of finger structures (FS) include a first structure (ML1) and a second structure (ML2) that are different in position in a stacking direction (Z). The first structure and the second structure include a plurality of insulating member rows (HRR) including a plurality of insulating members (HR). From among the plurality of insulating member rows in the first structure and the second structure of a first finger structure, the one (HRR1) closest to a second finger structure includes a first insulating member (HR3) and a second insulating member (HR4). From among the plurality of insulating member rows in the first structure and the second structure of the second finger structure, the one (HRR3) closest to the first finger structure includes a third insulating member (HR3) and a fourth insulating member (HR4). A distance (D6) in the first direction between the first insulating member and the third insulating member is smaller than a distance (D5) in the first direction between the second insulating member and the fourth insulating member.SELECTED DRAWING: Figure 12

Description

[Technical field]

[0001] The present embodiment relates to a semiconductor memory device. [Background technology]

[0002] A semiconductor memory device is known that includes a plurality of conductive layers stacked in a stacking direction, a semiconductor layer facing the plurality of conductive layers, and a gate insulating film provided between the plurality of conductive layers and the semiconductor layer. The gate insulating film includes a memory section capable of storing data, such as an insulating charge storage film made of silicon nitride (SiN) or a conductive charge storage film made of a floating gate. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Pat. No. 1,091,0391 Summary of the Invention [Problem to be solved by the invention]

[0004] A semiconductor memory device that can be suitably manufactured is provided. [Means for solving the problem]

[0005] A semiconductor memory device according to one embodiment includes a plurality of finger structures aligned in a first direction and extending in a second direction intersecting the first direction, a first inter-finger insulating member provided between a first finger structure and a second finger structure adjacent to each other in the first direction among the plurality of finger structures, the first inter-finger insulating member extending in a stacking direction intersecting the first and second directions, and a plurality of bit lines provided on one side of the stacking direction relative to the plurality of finger structures and the first inter-finger insulating member, aligned in the second direction, and extending in the first direction.

[0006] Each of the multiple finger structures includes a first structure and a second structure provided on the multiple bit line side of the first structure in the stacking direction. The first structure and the second structure include: multiple conductive layers stacked in the stacking direction, extending in the second direction across a first region and a second region aligned in the second direction, and including multiple terrace portions provided in the second region; a first semiconductor pillar provided in the first region, extending in the stacking direction, facing the multiple conductive layers, and electrically connected to any of the multiple bit lines; a first charge storage film provided between the multiple conductive layers and the first semiconductor pillar; and multiple insulating member rows provided in the second region and aligned in the first direction, each row including multiple insulating members at different positions in the second direction, each of the multiple insulating members having an outer periphery surrounded by at least a portion of the multiple conductive layers as viewed from the stacking direction.

[0007] The first inter-finger insulating member has a portion that widens in the first direction from the side opposite the multiple bit lines in the stacking direction to the multiple bit lines in the stacking direction, across a position in the stacking direction corresponding to the first structure of the multiple finger structures and a position in the stacking direction corresponding to the second structure of the multiple finger structures, in the second region. Of the multiple insulating member rows in the first finger structure, the insulating member row provided at a position closest to the second finger structure includes a first insulating member provided at a first position in the second direction at a position in the stacking direction corresponding to the first structure of the first finger structure, and a second insulating member provided at a first position in the second direction at a position in the stacking direction corresponding to the second structure of the first finger structure. Of the multiple insulating member rows in the second finger structure, the insulating member row provided at a position closest to the first finger structure includes a third insulating member provided at a first position in the second direction at a position in the stacking direction corresponding to the first structure of the second finger structure, and a fourth insulating member provided at a first position in the second direction at a position in the stacking direction corresponding to the second structure of the second finger structure. The distance in the first direction between the first insulating member and the third insulating member is smaller than the distance in the first direction between the second insulating member and the fourth insulating member. [Brief description of the drawings]

[0008] [Figure 1]1 is a schematic circuit diagram showing a configuration of a semiconductor memory device according to a first embodiment. [Diagram 2] FIG. 2 is a schematic plan view showing a configuration of a portion of the semiconductor memory device. [Diagram 3] FIG. 2 is a schematic plan view showing a configuration of a portion of the semiconductor memory device. [Figure 4] FIG. 2 is a schematic plan view showing a configuration of a portion of the semiconductor memory device. [Diagram 5] FIG. 2 is a schematic plan view showing a configuration of a portion of the semiconductor memory device. [Figure 6] FIG. 2 is a schematic cross-sectional view showing a configuration of a portion of the semiconductor memory device. [Figure 7] FIG. 2 is a schematic cross-sectional view showing a configuration of a portion of the semiconductor memory device. [Figure 8] FIG. 2 is a schematic cross-sectional view showing a configuration of a portion of the semiconductor memory device. [Figure 9] FIG. 2 is a schematic plan view showing a configuration of a portion of the semiconductor memory device. [Figure 10] FIG. 2 is a schematic cross-sectional view showing a configuration of a portion of the semiconductor memory device. [Figure 11] FIG. 2 is a schematic cross-sectional view showing a configuration of a portion of the semiconductor memory device. [Figure 12] FIG. 2 is a schematic cross-sectional view showing a configuration of a portion of the semiconductor memory device. [Figure 13] FIG. 2 is a schematic cross-sectional view showing a configuration of a portion of the semiconductor memory device. [Figure 14] 5A to 5C are schematic cross-sectional views for illustrating a method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 15] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 16] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 17] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 18] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 19]5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 20] 1A to 1C are schematic plan views for explaining the manufacturing method. [Figure 21] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 22] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Diagram 23] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 24] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Diagram 25] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 26] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 27] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 28] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 29] 1A to 1C are schematic plan views for explaining the manufacturing method. [Diagram 30] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Diagram 31] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Diagram 32] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Diagram 33] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Diagram 34] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Diagram 35] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Diagram 36] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 37] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 38] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 39] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Diagram 40] 1A to 1C are schematic plan views for explaining the manufacturing method. [Diagram 41] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Diagram 42] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Diagram 43] 1A to 1C are schematic plan views for explaining the manufacturing method. [Diagram 44] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Diagram 45] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 46] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 47] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 48] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 49] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 50] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 51] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 52] FIG. 11 is a schematic plan view showing a configuration of a portion of a semiconductor memory device according to a second embodiment. [Figure 53] FIG. 2 is a schematic plan view showing a configuration of a portion of the semiconductor memory device. [Figure 54] FIG. 2 is a schematic cross-sectional view showing a configuration of a portion of the semiconductor memory device. [Figure 55] FIG. 2 is a schematic cross-sectional view showing a configuration of a portion of the semiconductor memory device. [Figure 56]FIG. 2 is a schematic cross-sectional view showing a configuration of a portion of the semiconductor memory device. [Figure 57] 10A to 10C are schematic cross-sectional views for illustrating a method for manufacturing a semiconductor memory device according to a second embodiment. [Figure 58] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 59] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 60] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 61] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 62] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 63] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 64] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 65] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 66] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 67] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 68] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 69] FIG. 11 is a schematic cross-sectional view showing a configuration of a portion of a semiconductor memory device according to a third embodiment. [Figure 70] FIG. 2 is a schematic cross-sectional view showing a configuration of a portion of the semiconductor memory device. [Figure 71] FIG. 11 is a schematic cross-sectional view showing a configuration of a portion of a semiconductor memory device according to a fourth embodiment. [Figure 72] FIG. 13 is a schematic plan view showing a configuration of a portion of a semiconductor memory device according to another embodiment. [Figure 73] FIG. 11 is a schematic cross-sectional view showing a configuration of a portion of a semiconductor memory device according to another embodiment. [Figure 74] FIG. 11 is a schematic cross-sectional view showing a configuration of a portion of a semiconductor memory device according to another embodiment. [Figure 75] FIG. 11 is a schematic cross-sectional view showing a configuration of a portion of a semiconductor memory device according to another embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Next, a semiconductor memory device according to an embodiment will be described in detail with reference to the drawings. Note that the following embodiment is merely an example, and is not intended to limit the present invention. Also, the following drawings are schematic, and for the sake of explanation, some configurations may be omitted. Also, parts common to multiple embodiments may be given the same reference numerals, and explanations may be omitted.

[0010] In addition, in this specification, the term "semiconductor memory device" may refer to a memory die, or may refer to a memory system including a controller die, such as a memory chip, a memory card, or an SSD (Solid State Drive). Furthermore, it may refer to a configuration including a host computer, such as a smartphone, a tablet terminal, or a personal computer.

[0011] In addition, in this specification, when it is said that a first configuration is "electrically connected" to a second configuration, the first configuration may be directly connected to the second configuration, or the first configuration may be connected to the second configuration via wiring, a semiconductor member, a transistor, etc. For example, when three transistors are connected in series, the first transistor is "electrically connected" to the third transistor even if the second transistor is in an OFF state.

[0012] In this specification, a predetermined direction parallel to the surface of the substrate is called the X direction, a direction parallel to the surface of the substrate and perpendicular to the X direction is called the Y direction, and a direction perpendicular to the surface of the substrate is called the Z direction.

[0013] In this specification, the direction intersecting with the surface of the substrate may be referred to as the stacking direction. Also, the direction along a specific plane intersecting with the stacking direction may be referred to as the first direction, and the direction intersecting with the first direction along this plane may be referred to as the second direction. The stacking direction may or may not match the Z direction. Also, the first and second directions may or may not correspond to either the X direction or the Y direction.

[0014] In this specification, expressions such as "upper" and "lower" refer to the bit line and the conductive layers. For example, the direction from the conductive layers toward the bit line along the Z direction is called "up," and the direction from the bit line toward the conductive layers along the Z direction is called "down."

[0015] [First embodiment] [Circuit configuration] Fig. 1 is a schematic circuit diagram showing the configuration of a semiconductor memory device according to the first embodiment. As shown in Fig. 1, the semiconductor memory device according to the present embodiment includes a memory cell array MCA and a peripheral circuit PC.

[0016] The memory cell array MCA includes a plurality of memory blocks BLK. Each of the memory blocks BLK includes a plurality of string units SU. Each of the string units SU includes a plurality of memory strings MS. One end of each of the memory strings MS is connected to a peripheral circuit PC via a bit line BL. The other ends of each of the memory strings MS are connected to the peripheral circuit PC via a common source line SL.

[0017] The memory string MS includes a drain side select transistor STD, a plurality of memory cells MC (memory transistors), and a source side select transistor STS. The drain side select transistor STD, the plurality of memory cells MC, and the source side select transistor STS are connected in series between a bit line BL and a source line SL. Hereinafter, the drain side select transistor STD and the source side select transistor STS may be simply referred to as select transistors (STD, STS).

[0018] The memory cells MC are field-effect transistors. The memory cells MC include a part of a semiconductor pillar, a gate insulating film, and a gate electrode. The part of the semiconductor pillar functions as a channel region. The gate insulating film includes a charge storage film. The threshold voltage of the memory cells MC changes depending on the amount of charge in the charge storage film. The memory cells MC store one bit or multiple bits of data. A word line WL is connected to each of the gate electrodes of the memory cells MC corresponding to one memory string MS. Each of these word lines WL is commonly connected to all the memory strings MS in one memory block BLK.

[0019] The selection transistors (STD, STS) are field-effect transistors. The selection transistors (STD, STS) include a portion of a semiconductor pillar, a gate insulating film, and a gate electrode. The portion of the semiconductor pillar functions as a channel region. The gate electrodes of the selection transistors (STD, STS) are connected to selection gate lines (SGD, SGS), respectively. One drain side selection gate line SGD is commonly connected to all memory strings MS in one string unit SU. One source side selection gate line SGS is commonly connected to all memory strings MS in one memory block BLK.

[0020] The peripheral circuit PC includes, for example, a voltage generation circuit that generates an operating voltage, a voltage transfer circuit that transfers the generated operating voltage to selected bit lines BL, word lines WL, source lines SL, select gate lines (SGD, SGS), etc., a sense amplifier module connected to the bit lines BL, and a sequencer that controls these.

[0021] [structure] Next, the structure of the semiconductor memory device according to the first embodiment will be described with reference to FIGS.

[0022] FIG. 2 is a schematic plan view showing a part of the configuration of the semiconductor memory device. FIG. 3 is a schematic plan view showing a part of the configuration of the semiconductor memory device, and shows an enlarged view of the part indicated by A in FIG. 2 with a part omitted. FIG. 4 is a schematic plan view showing a part of the configuration of the semiconductor memory device, and shows an enlarged view of the part indicated by B in FIG. 3. FIG. 5 is a schematic plan view showing a part of the configuration of the semiconductor memory device, and shows an enlarged view of the part indicated by C in FIG. 4. A part of FIG. 5 shows an XY cross section at a height position corresponding to a conductive layer 110 (WL) described later. A part of FIG. 5 shows a plane omitting a bit line BL and an insulating layer 102 described later. A part of FIG. 5 shows a bit line BL. FIG. 6 is a schematic cross-sectional view showing a part of the configuration of the semiconductor memory device, and shows a cross section of the structure shown in FIG. 4 cut along line DD' and viewed along the direction of the arrow. FIG. 7 is a schematic cross-sectional view showing a part of the configuration of the semiconductor memory device, and shows a cross section of the structure shown in FIG. 5 cut along line EE' and viewed along the direction of the arrow. Fig. 8 is a schematic cross-sectional view showing a configuration of a portion of the semiconductor memory device, and shows an enlarged view of the portion indicated by F in Fig. 7. Note that, although Fig. 8 shows a YZ cross section, a structure similar to that in Fig. 8 can be observed when a cross section other than the YZ cross section along the central axis of semiconductor pillar 120 (for example, an XZ cross section) is observed.

[0023] FIG. 9 is a schematic plan view showing a configuration of a part of the semiconductor memory device, and shows an enlarged view of the portion indicated by G in FIG. 3. FIG. 10 is a schematic cross-sectional view showing a configuration of a part of the semiconductor memory device, and shows a cross section of the structure shown in FIG. 9 cut along line HH' and viewed along the direction of the arrow. FIG. 11 is a schematic cross-sectional view showing a configuration of a part of the semiconductor memory device, and shows a cross section of the structure shown in FIG. 9 cut along line JJ' and viewed along the direction of the arrow. FIG. 12 is a schematic cross-sectional view showing a configuration of a part of the semiconductor memory device, and shows a cross section of the structure shown in FIG. 9 cut along line KK' and viewed along the direction of the arrow. FIG. 13 is a schematic cross-sectional view showing a configuration of a part of the semiconductor memory device, and shows an enlarged view of the portion indicated by L in FIG. 12.

[0024] 2 to 13 are schematic diagrams, and some components may be omitted.

[0025] 2, the semiconductor memory device according to this embodiment includes a memory die MD. In the illustrated example, the memory die MD includes four memory cell array regions R aligned in the X and Y directions. MCA In addition, the memory cell array region R MCA There are two memory hole regions R aligned in the X direction. MH and these two memory hole regions R MH Two hook-up regions R arranged in the X direction between HU1 And these two hookup areas R HU1 Hook-up area R between HU2 In addition, a peripheral circuit region R is provided at the end of the memory die MD in the Y direction. P is provided.

[0026] Memory cell array region R MCA The memory cell has a plurality of finger structures FS arranged in the Y direction. The finger structures FS are connected to two memory hole regions R arranged in the X direction. MH , and two hook-up regions R provided between them. HU1 , and a hook-up region R provided therebetween.HU2 The finger structure FS extends in the X direction over a length of the string unit SU. The finger structure FS includes a plurality of string units SU arranged in the Y direction, as shown in Fig. 4, for example. An inter-finger structure ST is provided between two finger structures FS adjacent to each other in the Y direction. In addition, an inter-string unit insulating member SHE made of silicon oxide (SiO2) or the like is provided between two string units SU adjacent to each other in the Y direction, as shown in Fig. 5, for example.

[0027] In this embodiment, one finger structure FS functions as one memory block BLK (FIG. 1). Each finger structure FS has five string units SU. However, multiple finger structures FS may function as one memory block BLK. Each finger structure FS may have two to four string units SU, or six or more string units SU.

[0028] [Memory hole area R MH Structure of 6, the finger structure FS includes a plurality of structures ML1, ML2, and ML3 (three in the illustrated example) arranged in the Z direction. A wiring layer 112 is provided below the plurality of structures ML1, ML2, and ML3. Moreover, a plurality of bit lines BL are provided above the plurality of structures ML1, ML2, and ML3.

[0029] The multiple structures ML1, ML2, and ML3 each include, for example, as shown in FIG. 7, multiple conductive layers 110 stacked in the Z direction, multiple semiconductor pillars 120 extending in the Z direction, and a gate insulating film 130 provided between the multiple conductive layers 110 and the multiple semiconductor pillars 120.

[0030] The conductive layer 110 has a substantially plate-like shape extending in the X direction. The conductive layer 110 may include a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). The conductive layer 110 may also include polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). An insulating layer 101 such as silicon oxide (SiO2) is provided between the multiple conductive layers 110 arranged in the Z direction. An insulating layer 102 such as silicon oxide (SiO2) is provided on the upper surface of the uppermost conductive layer 110 in the structures ML1, ML2, and ML3 (see FIG. 6).

[0031] Among the multiple conductive layers 110 included in the structure ML1, one or more conductive layers 110 provided at the bottom function as the gate electrodes of the source side selection gate line SGS and the multiple selection transistors STS (FIG. 1) connected thereto. In the following description, such a conductive layer 110 may be referred to as a conductive layer 110(SGS).

[0032] Among the multiple conductive layers 110 included in the structure ML3, one or more conductive layers 110 provided at the top function as the drain side selection gate line SGD and the gate electrodes of the multiple selection transistors STD (FIG. 1) connected thereto. In the following description, such a conductive layer 110 may be referred to as a conductive layer 110(SGD).

[0033] The remaining conductive layers 110 included in the structures ML1 and ML3 and the multiple conductive layers 110 included in the structure ML2 function as the word line WL and the gate electrodes of the multiple memory cells MC (FIG. 1) connected thereto. In the following description, such a conductive layer 110 may be referred to as a conductive layer 110(WL).

[0034] The conductive layers 110(WL) are electrically independent for each finger structure FS. When focusing on two finger structures FS adjacent to each other in the Y direction, the conductive layers 110(WL) arranged in the Z direction in these two finger structures FS and the insulating layers 101 provided on the upper and lower surfaces thereof are separated in the Y direction by the inter-finger structures ST.

[0035] The multiple conductive layers 110 (SGS) are electrically independent for each finger structure FS. When focusing on two finger structures FS adjacent to each other in the Y direction, one or more conductive layers 110 (SGS) in these two finger structures FS and the multiple insulating layers 101 provided on the upper and lower surfaces thereof are separated in the Y direction via an inter-finger structure ST.

[0036] As shown in FIG. 5, the conductive layer 110 (SGD) has a width Y SGD is the width Y in the Y direction of the conductive layer 110 (WL) WL Less than.

[0037] The multiple conductive layers 110 (SGD) are electrically independent for each string unit SU. In each finger structure FS, when focusing on two string units SU adjacent to each other in the Y direction, one or more conductive layers 110 (SGD) in these two string units SU and the multiple insulating layers 101 provided on the upper and lower surfaces thereof are divided in the Y direction by an inter-string unit insulating member SHE. When focusing on the string unit SU closest to the other string unit among the multiple string units SU included in one of the two finger structures FS adjacent to each other in the Y direction, and the string unit SU closest to the one string unit among the multiple string units SU included in the other finger structure, the conductive layers 110 (SGD) in these two string units SU and the multiple insulating layers 101 provided on the upper and lower surfaces thereof are divided in the Y direction by an inter-finger structure ST.

[0038] The semiconductor pillars 120 are aligned in a predetermined pattern in the X and Y directions, as shown in Fig. 5. For example, the finger structure FS includes 24 semiconductor pillar arrays SC arranged from one side in the Y direction to the other side in the Y direction. Each of the 24 semiconductor pillar arrays SC includes a plurality of semiconductor pillars 120 aligned in the X direction.

[0039] The semiconductor pillar 120 includes, for example, polycrystalline silicon (Si) or the like. As shown in Fig. 7, the semiconductor pillar 120 has a substantially cylindrical shape, and an insulating pillar 125 made of, for example, silicon oxide (SiO2) is provided in the center. The semiconductor pillar 120 functions as the channel region of the memory cell MC and the select transistors (STS, STD).

[0040] The lower end of semiconductor pillar 120 included in structure ML1 is provided with impurity region 121. The upper end of semiconductor pillar 120 included in structure ML1 is continuous with the lower end of semiconductor pillar 120 included in structure ML2. The upper end of semiconductor pillar 120 included in structure ML2 is continuous with the lower end of semiconductor pillar 120 included in structure ML3. The upper end of semiconductor pillar 120 included in structure ML3 is provided with impurity region 122.

[0041] The impurity region 121 includes an N-type impurity such as phosphorus (P). The impurity region 121 has a substantially cylindrical shape. The impurity region 121 is connected to the wiring layer 112.

[0042] The impurity region 122 includes an N-type impurity such as phosphorus (P). The impurity region 122 has a substantially cylindrical shape. The impurity region 122 is connected to a via contact electrode Ch. The semiconductor pillar 120 is electrically connected to a bit line BL through the via contact electrodes Ch and Vy.

[0043] The gate insulating film 130 has a substantially cylindrical shape covering the outer circumferential surface of the semiconductor pillar 120. The gate insulating film 130 includes a tunnel insulating film 131, a charge storage film 132, and a block insulating film 133 stacked between the semiconductor pillar 120 and the conductive layer 110, as shown in FIG. 8, for example. The tunnel insulating film 131 and the block insulating film 133 include, for example, silicon oxide (SiO2) or the like. The charge storage film 132 includes, for example, a film capable of storing charge, such as silicon nitride (SiN). The tunnel insulating film 131, the charge storage film 132, and the block insulating film 133 have a substantially cylindrical shape and extend in the Z direction along the outer circumferential surface of the semiconductor pillar 120 except for the contact portion between the semiconductor pillar 120 and the wiring layer 112, as shown in FIG. 7, for example.

[0044] 8 shows an example in which the gate insulating film 130 includes a charge storage film 132 such as silicon nitride. However, the charge storage film included in the gate insulating film 130 may be a floating gate such as polycrystalline silicon containing N-type or P-type impurities.

[0045] The wiring layer 112 (FIG. 7) may include, for example, polycrystalline silicon containing an N-type impurity such as phosphorus (P). A metal such as tungsten (W), a conductive material such as tungsten silicide, or other conductive material may be provided on the lower surface of the wiring layer 112. The wiring layer 112 functions as a part of the source line SL (FIG. 1).

[0046] The inter-string unit insulating member SHE extends in the X direction and the Z direction, for example, as shown in Figures 5 and 7. The inter-string unit insulating member SHE includes, for example, silicon oxide (SiO2) or the like. The lower end of the inter-string unit insulating member SHE is located above the lower surface of the conductive layer 110 (WL) located in the uppermost layer. In addition, the lower end of the inter-string unit insulating member SHE is located below the lower surface of the conductive layer 110 (SGD) located in the lowermost layer. In addition, the position in the Z direction of the upper end of the inter-string unit insulating member SHE is located above the upper surface of the conductive layer 110 (SGD) located in the uppermost layer.

[0047] The inter-finger structure ST extends in the X-direction and the Z-direction, as shown in, for example, FIG. 5 and FIG. 7. The inter-finger structure ST widens in the Y-direction from the bottom to the top. The inter-finger structure ST includes an inter-finger insulating member 140 extending in the X-direction and the Z-direction, and an inter-finger electrode 141 provided inside the inter-finger insulating member 140. The inter-finger insulating member 140 includes silicon oxide (SiO2) or the like. The inter-finger electrode 141 is separated in the Y-direction from the multiple conductive layers 110 arranged in the Z-direction, the multiple insulating layers 101 provided between them, and the insulating layer 102, via the inter-finger insulating member 140. The lower ends of the inter-finger insulating member 140 and the inter-finger electrode 141 are connected to the wiring layer 112. The inter-finger electrode 141 may be a conductive member including, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). The inter-finger electrodes 141 may also be semiconductor materials such as polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). The inter-finger electrodes 141 may include both conductive and semiconductor materials. The inter-finger electrodes 141 function as part of the source lines SL (FIG. 1).

[0048] The via contact electrodes Ch are arranged in a predetermined pattern in the X and Y directions in correspondence with the semiconductor pillars 120, as shown in Fig. 5. The via contact electrodes Ch extend in the Z direction, and are connected at their lower ends to the impurity regions 122 of the semiconductor pillars 120 and at their upper ends to the via contact electrodes Vy, as shown in Fig. 7.

[0049] 5, the bit lines BL extend in the Y direction and are aligned in the X direction. The pitch of the bit lines BL in the X direction is 1 / 4 times the pitch of the semiconductor pillars 120 aligned in the X direction in the X direction. The bit lines BL may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as copper (Cu). The above-mentioned via contact electrode Vy is provided at a position where the bit lines BL and the via contact electrode Ch overlap when viewed from the Z direction.

[0050] [Hookup Area RHU1 Structure of Hookup Area R HU1 As shown in FIG. 4, a plurality of terrace portions T corresponding to a plurality of conductive layers 110 (SGD) are provided in the conductive layer 110 (SGD). The terrace portion T is, for example, a portion of the upper surface of the conductive layer 110 that does not overlap with other conductive layers 110 when viewed from above. The terrace portion T of the conductive layer 110 (SGD) is provided at the end of the conductive layer 110 (SGD) in the X direction. In the example of FIG. 4, four terrace portions T corresponding to the first to fourth conductive layers 110 (SGD) counting from the top are lined up in the X direction from the negative side in the X direction to the positive side in the X direction. The plurality of terrace portions T are covered by the insulating layer 102 described above.

[0051] Also, hook-up area R HU1 A plurality of via contact electrodes CC are provided in the insulating layer 102 corresponding to the plurality of terrace portions T. The via contact electrodes CC may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). As shown in Fig. 10, the via contact electrodes CC extend in the Z direction through the insulating layer 102 and are connected at their lower ends to the terrace portions T of the conductive layer 110.

[0052] Also, hook-up area R HU1 A plurality of supporting and insulating members HR are provided on the terrace portion T. The supporting and insulating members HR include, for example, silicon oxide (SiO2). As shown in FIG. 10, the supporting and insulating members HR extend in the Z direction, penetrating the plurality of conductive layers 110 and the insulating layer 101. In this embodiment, the height position of the upper end of the supporting and insulating members HR substantially coincides with the height position of the corresponding terrace portion T. The outer peripheral surface of each of the supporting and insulating members HR is surrounded by a through hole provided in the conductive layer 110. In the example of FIG. 4, one supporting and insulating member HR is provided at each of the four corners of each terrace portion T.

[0053] [Hookup Area R HU2 Structure of Hookup Area R HU2As shown in FIG. 3, the memory cell includes a plurality of conductive layers 110 (WL), a plurality of terrace portions T corresponding to one or a plurality of conductive layers 110 (SGS), and two memory hole regions R aligned in the X direction. MH The connection portion 111 is provided between the hook-up region R in the X direction. HU2 The memory hole region R on one side in the X direction of the plurality of conductive layers 110(WL) and the one or more conductive layers 110(SGS) extends from one end to the other end. MH The portion provided in the memory hole region R on the other side in the X direction is connected to the memory hole region R MH The terrace portions T and the connection portions 111 are covered with the insulating layer 102. HU2 There is a hookup area R HU1 Similarly, a plurality of via contact electrodes CC are provided corresponding to a plurality of terrace portions T.

[0054] In the example of Figure 3, the hook-up region R HU2 A plurality of terrace portions T corresponding to the plurality of conductive layers 110(WL) and one or a plurality of conductive layers 110(SGS) are provided on the insulating layer 102. For example, the terrace portions T provided on the positive side of the X direction correspond to the upper conductive layer 110, and the terrace portions T provided on the negative side of the X direction correspond to the lower conductive layer 110. The length of the insulating layer 102 in the Z direction is generally smaller in a portion provided above the terrace portion T provided on the positive side of the X direction and larger in a portion provided above the terrace portion T provided on the negative side of the X direction.

[0055] In the illustrated example, in the conductive layers 110(WL) and one or more conductive layers 110(SGS) included in the even-numbered finger structures FS counting from one side in the Y direction, the terrace portions T are provided on the negative side in the Y direction with respect to the connection portion 111. In the conductive layers 110(WL) and one or more conductive layers 110(SGS) included in the odd-numbered finger structures FS counting from one side in the Y direction, the terrace portions T are provided on the positive side in the Y direction with respect to the connection portion 111.

[0056] Here, hookup area R HU2 In this example, an inter-finger structure ST1 (FIG. 9) provided between the (2n+2)th and (2n+3)th finger structures FS counting from one side in the Y direction has a widened portion. In the widened portion, the inter-finger structure ST1 widens in the Y direction from the positive side in the X direction to the negative side in the X direction, as shown in FIG.

[0057] That is, the width in the Y direction of the inter-finger structure ST1 basically increases as it approaches the terrace portion T of the conductive layer 110 provided below, in other words, as the length in the Z direction of the insulating layer 102 increases. For example, in the example of FIG. 9, the terrace portion T1 of the conductive layer 110a is provided at position X1 in the X direction. Furthermore, the terrace portion T2 of the conductive layer 110b below the conductive layer 110a is provided at position X2 in the X direction on the negative side of position X1. Here, the width Y1 in the Y direction of the inter-finger structure ST1 at position X1 is smaller than the width Y2 in the Y direction of the inter-finger structure ST1 at position X2.

[0058] Furthermore, the hook-up area R HU2 In the figure, the length in the Z direction of the portion of the insulating layer 102 provided above the connection portion 111 is substantially constant, and the inter-finger structures ST that divide the connection portion 111 other than the inter-finger structure ST1 do not include the widened portion as described above. The length in the Z direction of the portion of the insulating layer 102 provided above the connection portion 111 is smaller than the length in the Z direction of the portion provided above the terrace portion T. Therefore, for example, at a position X1 in the X direction, when the Y direction width Y1 of the inter-finger structure ST1 is compared with the Y direction width Y0 of the other inter-finger structures ST that divide the connection portion 111, the width Y1 is larger. Similarly, at a position X2 in the X direction, when the Y direction width Y2 of the inter-finger structure ST1 is compared with the Y direction width Y0 of the other inter-finger structures ST that divide the connection portion 111, the width Y2 is larger.

[0059] Also, hook-up area R HU211 and 12, each finger structure FS has a plurality of support insulating member rows HRR aligned in the Y direction at positions in the Z direction within structures ML1, ML2, and ML3 excluding the position of the insulating layer 102 provided above the terrace portion T.

[0060] 9, the supporting and insulating member row HRR basically includes a plurality of supporting and insulating members HR aligned in a row in the X direction. That is, the positions in the Y direction of the multiple supporting and insulating members HR included in the supporting and insulating member row HRR basically substantially coincide with each other.

[0061] However, the hook-up area R HU2 In the multiple support insulating member rows HRR corresponding to the 2n+2nd finger structure FS counting from one side in the Y direction, in the support insulating member row HRR1 closest to the inter-finger structure ST1 and the adjacent support insulating member row HRR2, the multiple support insulating members HR are arranged so as to gradually move away from the central position in the Y direction of the inter-finger structure ST1 from the positive side to the negative side in the X direction.

[0062] Similarly, the hookup area R HU2 Of the multiple support insulating member rows HRR corresponding to the 2n+3th finger structure FS counting from one side in the Y direction, in the support insulating member row HRR3 closest to the inter-finger structure ST1 and the adjacent support insulating member row HRR4, the multiple support insulating members HR are arranged so as to gradually move away from the central position in the Y direction of the inter-finger structure ST1 from the positive side to the negative side in the X direction.

[0063] In the support insulating member rows HRR1 to HRR4, the Y-direction positions of the multiple support insulating members HR are farther from the center position in the Y-direction of the inter-finger structure ST1 as they approach the terrace portion T of the conductive layer 110 provided below, i.e., as the length of the insulating layer 102 in the Z-direction increases. For example, in the example of Fig. 9, among the multiple support insulating members HR included in the support insulating member rows HRR1 and HRR3 adjacent in the Y-direction via the inter-finger structure ST1, the distance D1 in the Y-direction between the two support insulating members HR1 provided at the position X1 is smaller than the distance D2 in the Y-direction between the two support insulating members HR2 provided at the position X2. In addition, the distance D3 between the center positions in the Y-direction of the two support insulating members HR1 is smaller than the distance D4 between the center positions in the Y-direction of the two support insulating members HR2.

[0064] As described above, the supporting and insulating member row HRR basically includes a plurality of supporting and insulating members HR arranged in a line in the X direction. HU2 In the figure, of the multiple support insulating members HR included in two support insulating member rows HRR adjacent in the Y direction across an inter-finger structure ST that divides the connection portion 111 other than the inter-finger structure ST1, the distance D01 in the Y direction between the two support insulating members HR0 provided at position X1 is smaller than the above-mentioned distance D1. Similarly, the distance D01 in the Y direction between the two support insulating members HR0 provided at position X2 is smaller than the above-mentioned distance D2. Furthermore, the distance D03 between the centers in the Y direction of the two support insulating members HR0 provided at position X1 is smaller than the above-mentioned distance D3. Similarly, the distance D03 between the centers in the Y direction of the two support insulating members HR0 provided at position X2 is smaller than the above-mentioned distance D4.

[0065] 9 illustrates the configuration of the conductive layer 110 in the vicinity of the terrace portion T included in the structure ML2. However, the configurations of the conductive layer 110 in the vicinity of the terrace portion T included in the structures ML1 and ML3 are also substantially similar.

[0066] However, the inter-finger structure ST1 has a hook-up region R HU2The width of the inter-finger structure ST1 in the Y direction increases from the end on the positive side in the X direction to the end on the negative side in the X direction. Therefore, in the vicinity of the terrace portion T of the conductive layer 110 included in the structure ML1, the width of the inter-finger structure ST1 in the Y direction is larger than the widths Y1 and Y2. Conversely, in the vicinity of the terrace portion T of the conductive layer 110 included in the structure ML3, the width of the inter-finger structure ST1 in the Y direction is smaller than the widths Y1 and Y2.

[0067] Further, in the vicinity of the terrace portion T of the conductive layer 110 included in the structure ML3, among the multiple supporting insulating members HR included in two supporting insulating member rows HRR adjacent in the Y direction via the inter-finger structure ST1, the Y-direction distance between two supporting insulating members HR included in the structure ML2 that are provided at a predetermined X-direction position is smaller than the distances D1 and D2.

[0068] 11, the multiple supporting and insulating members HR included in structure ML2 are basically provided in positions that overlap the multiple supporting and insulating members HR included in structure ML1 when viewed from the Z direction. Similarly, the multiple supporting and insulating members HR included in structure ML3 are basically provided in positions that overlap the multiple supporting and insulating members HR included in structure ML2 when viewed from the Z direction.

[0069] However, as shown in Fig. 12, in the support insulating member row HRR arranged close to the inter-finger structure ST1 that widens in the Y direction from bottom to top, for example at or near position X2 (Fig. 9), the multiple support insulating members HR included in the structure ML2 and the multiple support insulating members HR included in the structure ML1 are provided at different positions in the Y direction so as to be along the Y direction side surface of the inter-finger structure ST1. That is, the support insulating member HR3 in the support insulating member row HRR1 included in the structure ML1 is provided at a position closer to the center position in the Y direction of the inter-finger structure ST1 than the support insulating member HR4 in the support insulating member row HRR1 included in the structure ML2. Similarly, the support insulating members HR3 in the support insulating member rows HRR2 to HRR4 included in the structure ML1 are each provided at a position closer to the center position in the Y direction of the inter-finger structure ST1 than the support insulating members HR4 in the support insulating member rows HRR2 to HRR4 included in the structure ML2.

[0070] In the example of Fig. 12, the distance D6 in the Y direction between two supporting insulating members HR3 adjacent in the Y direction with the inter-finger structure ST1 in the structure ML1 is smaller than the distance D5 in the Y direction between two supporting insulating members HR4 adjacent in the Y direction with the inter-finger structure ST1 in the structure ML2. Also, as shown in Fig. 13, the distance D7 between the centers of the two supporting insulating members HR3 in the Y direction is smaller than the distance D8 between the centers of the two supporting insulating members HR4 in the Y direction.

[0071] The length corresponding to the difference between the distance D6 and the distance D5 may be greater as the distance approaches the terrace portion T of the conductive layer 110 provided below, i.e., as the length in the Z direction of the insulating layer 102 increases. Similarly, the length corresponding to the difference between the distance D8 and the distance D7 may be greater as the distance approaches the terrace portion T of the conductive layer 110 provided below, i.e., as the length in the Z direction of the insulating layer 102 increases.

[0072] 13, the upper end of the supporting insulating member HR3 is spaced apart from the lower end of the supporting insulating member HR4 in the Y direction. However, the upper end of the supporting insulating member HR3 may be connected to the lower end of the supporting insulating member HR4.

[0073] As described above, the multiple supporting and insulating members HR included in the structure ML2 are basically provided at positions that overlap the multiple supporting and insulating members HR included in the structure ML1 when viewed from the Z direction.

[0074] For example, all of the support insulating members HR included in all of the support insulating member rows HRR other than the support insulating member rows HRR1 to HRR4 (Figure 9) in the structure ML2 are positioned so as to overlap, when viewed from the Z direction, with all of the support insulating members HR included in all of the support insulating member rows HRR other than the support insulating member rows HRR1 to HRR4 in the structure ML1.

[0075] 12 and 13 show the positional relationship between the multiple support insulating members HR included in the structure ML2 and the multiple support insulating members HR included in the structure ML1, but the multiple support insulating members HR included in the structure ML3 and the multiple support insulating members HR included in the structure ML2 may have the same positional relationship. That is, the multiple support insulating members HR included in the structure ML3 are basically provided at a position overlapping the multiple support insulating members HR included in the structure ML2 when viewed from the Z direction. However, for example, in an X direction position near the terrace portion T of the conductive layer 110 included in the structure ML3, the multiple support insulating members HR included in the structure ML3 and the multiple support insulating members HR included in the structure ML2 may be provided in the vicinity of the inter-finger structure ST1 at different Y direction positions so as to be along the Y direction side surface of the inter-finger structure ST1 that widens in the Y direction from the bottom to the top.

[0076] [Manufacturing method] Next, a method for manufacturing the semiconductor memory device according to the first embodiment will be described with reference to FIGS. 14 to 51. FIGS. 14, 17, 38, 46 to 48, 50, and 51 are schematic cross-sectional views for explaining the manufacturing method, and show a cross section corresponding to FIG. 7. FIGS. 15, 18, 23, 25, 27, 32, 34, 36, 37, and 44 are schematic cross-sectional views for explaining the manufacturing method, and show a cross section corresponding to FIG. 6. FIGS. 16, 19, 24, 26, 28, 30, 31, 33, 35, 39, 41, 42, and 45 are schematic cross-sectional views for explaining the manufacturing method, and show a cross section corresponding to FIG. 12. FIGS. 20, 29, and 40 are schematic plan views for explaining the manufacturing method, and show a plan corresponding to FIG. 3. Figures 21 and 22 are schematic cross-sectional views for explaining the same manufacturing method, and show a cross section corresponding to Figure 10. Figure 43 is a schematic plan view for explaining the same manufacturing method, and shows a plan view corresponding to Figure 9. Figure 49 is a schematic cross-sectional view for explaining the same manufacturing method, and shows a cross section corresponding to Figure 13.

[0077] In manufacturing the semiconductor memory device according to this embodiment, a semiconductor layer 112A of silicon or the like, a sacrificial layer 112B of silicon oxide or the like, a sacrificial layer 112C of silicon nitride (SiN) or the like, a sacrificial layer 112D of silicon oxide or the like, and a semiconductor layer 112E of silicon or the like are formed above a wafer (not shown), as shown in FIG. 14 for example. In addition, a plurality of insulating layers 101 and a plurality of sacrificial layers 110A are formed alternately. The sacrificial layer 110A includes, for example, silicon nitride (SiN) or the like. This process is performed by, for example, a method such as CVD (Chemical Vapor Deposition).

[0078] In this step, among the multiple insulating layers 101, those included in the structure ML1 (FIG. 6) and among the multiple sacrificial layers 110A, those corresponding to the conductive layer 110 in the structure ML1 are formed. Hereinafter, the configuration including these may be referred to as the structure MLA1.

[0079] Next, as shown in Figs. 15 to 17, for example, a plurality of memory holes MH are formed at positions corresponding to a plurality of semiconductor pillars 120 described with reference to Figs. 6, 7, etc. Also, a plurality of via holes HRA are formed at positions corresponding to a plurality of supporting insulating members HR described with reference to Fig. 12, etc. These memory holes MH and via holes HRA each extend in the Z direction, penetrating the insulating layer 101 and the sacrificial layer 110A, the semiconductor layer 112E, and the sacrificial layers 112D, 112C, and 112B, and exposing the upper surface of the semiconductor layer 112A. This step is performed by a method such as RIE.

[0080] 18, sacrificial pillars 120A of silicon (Si) or the like are formed inside the memory holes MH. This process is performed by, for example, CVD or the like.

[0081] Next, a supporting insulating member HR is formed inside the via holes HRA as shown in Fig. 19. This step is performed by, for example, CVD or the like.

[0082] Next, as shown in, for example, FIG. 20 and FIG. 21, the hook-up region R HU2In this process, a portion of the insulating layers 101 and the sacrificial layers 110A is removed to form a plurality of terrace portions TA. The terrace portions TA are, for example, portions of the upper surface of the sacrificial layers 110A that do not overlap with other sacrificial layers 110A when viewed from above. In this process, for example, a resist is formed on the upper surface of a structure as shown in Figs. 18 and 19. The removal of the sacrificial layers 110A, the removal of the insulating layers 101, and the removal of portions of the resist are repeated. The resist is removed by isotropic etching such as wet etching. In this process, a portion of the supporting insulating member HR is also removed, so that the height position of the upper end of the supporting insulating member HR approximately coincides with the height position of the corresponding terrace portion TA.

[0083] 22, an insulating layer 102 such as silicon oxide (SiO2) is formed to cover the terrace portions TA. This step is performed by a method such as CVD.

[0084] 23 and 24, for example, a plurality of insulating layers 101 and a plurality of sacrificial layers 110A are alternately formed on the upper surface of the insulating layer 102. In this process, among the plurality of insulating layers 101, those included in the structure ML2 (FIG. 6) and among the plurality of sacrificial layers 110A, those corresponding to the conductive layer 110 in the structure ML2 are formed. Hereinafter, a configuration including these may be referred to as the structure MLA2.

[0085] 25 and 26, a plurality of memory holes MH are formed at positions corresponding to a plurality of semiconductor pillars 120. A plurality of via holes HRA are also formed at positions corresponding to a plurality of supporting insulating members HR. These memory holes MH and via holes HRA each extend in the Z direction and penetrate the insulating layer 101 and the sacrificial layer 110A, exposing the upper surfaces of the sacrificial pillars 120A, the supporting insulating members HR, or the upper surface of the insulating layer 102. This step is performed by a method such as RIE.

[0086] 27, sacrificial pillars 120A of silicon (Si) or the like are formed inside the memory holes MH. This process is performed by, for example, CVD or the like.

[0087] Next, a supporting insulating member HR is formed inside the via holes HRA as shown in Fig. 28. This step is performed by, for example, CVD or the like.

[0088] Next, as shown in, for example, FIG. 29 and FIG. 30, the hook-up region R HU2 In this process, a portion of the insulating layers 101 and the sacrificial layers 110A is removed to form a plurality of terrace portions TA. In this process, a portion of the supporting insulating member HR is also removed, so that the height positions of the upper ends of the supporting insulating members HR substantially coincide with the height positions of the corresponding terrace portions TA.

[0089] Next, as shown in Fig. 31, an insulating layer 102 such as silicon oxide (SiO2) is formed to cover the terrace portions TA. This step is performed by a method such as CVD.

[0090] 32 and 33, a plurality of insulating layers 101 and a plurality of sacrificial layers 110A are alternately formed on the upper surface of the insulating layer 102. In this process, among the plurality of insulating layers 101, those included in the structure ML3 (FIG. 6) and among the plurality of sacrificial layers 110A, those corresponding to the conductive layer 110 in the structure ML3 are formed. Here, the configuration including these is referred to as the structure MLA3.

[0091] Next, as shown in Figures 34 and 35, for example, a plurality of memory holes MH are formed at positions corresponding to a plurality of semiconductor pillars 120. Also, a plurality of via holes HRA are formed at positions corresponding to a plurality of supporting insulating members HR. These memory holes MH and via holes HRA each extend in the Z direction and penetrate the insulating layer 101 and the sacrificial layer 110A, exposing the sacrificial pillars 120A, the top surfaces of the supporting insulating members HR, or the top surface of the insulating layer 102. This step is performed by a method such as RIE.

[0092] 36, the sacrificial columns 120A in the structures MLA1 and MLA2 are removed through the multiple memory holes MH. This step is performed by, for example, a method such as wet etching.

[0093] 37 and 38, the gate insulating film 130, the semiconductor pillar 120, and the insulating pillar 125 are formed inside the memory holes MH. This process is performed by, for example, CVD or the like.

[0094] Next, a supporting insulating member HR is formed inside the via holes HRA as shown in Fig. 39. This step is performed by, for example, CVD or the like.

[0095] Next, as shown in, for example, FIG. 40 and FIG. 41, the hook-up region R HU1 ,R HU2 In this process, a portion of the insulating layers 101 and the sacrificial layers 110A is removed to form a plurality of terrace portions TA. In this process, a portion of the supporting insulating member HR is also removed, so that the height positions of the upper ends of the supporting insulating members HR are approximately aligned with the height positions of the corresponding terrace portions TA.

[0096] 20 and 21, 29 and 30, and 40 and 41, a plurality of terrace portions TA are formed as shown in Fig. 40. For example, the terrace portions TA provided on the positive side in the X direction correspond to the upper sacrificial layer 110A, and the terrace portions TA provided on the negative side in the X direction correspond to the lower sacrificial layer 110A.

[0097] Next, as shown in Fig. 42, an insulating layer 102 such as silicon oxide (SiO2) is formed to cover the terrace portions TA. This step is performed by a method such as CVD.

[0098] Next, as shown in Figures 43 to 46, for example, a groove STA is formed at a position corresponding to an inter-finger structure ST. The groove STA extends in the Z direction and the X direction, divides the insulating layer 102, the insulating layer 101, the sacrificial layer 110A, the semiconductor layer 112E, and the sacrificial layer 112D in the Y direction, and exposes the upper surface of the sacrificial layer 112C. The groove STA is widened in the Y direction from the bottom to the top. This step is performed by a method such as RIE.

[0099] As described above, the insulating layers 101 and 102 contain silicon oxide. The sacrificial layer 110A and the like contain silicon nitride. When forming the groove STA, if conditions are adopted under which silicon oxide is more easily removed than silicon nitride, the length of the groove STA in the Y direction may become relatively large in a region of the insulating layer 102 that is long in the Z direction, for example, in a region corresponding to the terrace portion TA of the lower sacrificial layer 110A.

[0100] For example, hookup area R HU2 43, a widened portion of the groove STA is formed at a position corresponding to the inter-finger structure ST1 (FIG. 9). In the widened portion, the groove STA widens in the Y direction from the positive side in the X direction to the negative side in the X direction.

[0101] 42, the length of the insulating layer 102 in the Z direction is larger in the region corresponding to the terrace portion TA than in the region corresponding to the connection portion 111 (FIG. 9). Therefore, in such a region, the length of the groove STA in the Y direction may be relatively large, as shown in FIG.

[0102] Next, the wiring layer 112 is formed, for example, as shown in Fig. 47. In this step, the sacrificial layers 112B, 112C, and 112D are removed by a method such as wet etching. Also, a part of the gate insulating film 130 is removed by a method such as wet etching to expose a part of the outer circumferential surface of the semiconductor pillar 120. Also, the wiring layer 112 is formed by a method such as epitaxial growth.

[0103] Next, as shown in Fig. 48 and Fig. 49, the sacrificial layer 110A is removed through the groove STA. This forms a plurality of voids 110B aligned in the Z direction. In other words, a hollow structure including a plurality of insulating layers 101 aligned in the Z direction and a structure supporting the insulating layers 101 is formed. MH In the hook-up region R, the insulating layer 101 is supported by the structure in the memory hole MH (the semiconductor pillar 120, the gate insulating film 130, and the insulating pillar 125). HU1 ,R HU2 In this step, the insulating layer 101 is supported by the supporting insulating member HR. This step is performed by, for example, a method such as wet etching.

[0104] Next, a plurality of conductive layers 110 are formed in the plurality of gaps 110B aligned in the Z direction, as shown in Fig. 50. This step is performed by a method such as CVD.

[0105] Next, an inter-finger structure ST is formed inside the trench STA as shown in Fig. 51. This step is performed by, for example, CVD or the like.

[0106] Thereafter, the via contact electrodes CC, Ch, Vy, bit lines BL, etc. described with reference to Figures 4 and 5 are formed, and individual pieces are formed by dicing or the like to form the semiconductor memory device according to the first embodiment.

[0107] [effect] In the manufacture of the semiconductor memory device according to this embodiment, as described with reference to Figures 48 and 49, a hollow structure is formed that includes a plurality of insulating layers 101 arranged in the Z direction and a structure that supports the insulating layers 101. HU1 ,R HU2 In the embodiment, the insulating layer 101 is supported by the supporting insulating member HR.

[0108] As described above, the groove STA widens in the Y direction from bottom to top. Therefore, if the supporting insulating member HR is brought too close to the groove STA, a part of the supporting insulating member HR may be removed during processing of the groove STA, and the supporting insulating member HR may be exposed in the groove STA. For example, if a void is formed inside the supporting insulating member HR, a metal such as titanium nitride or tungsten may be formed inside the void in the process described with reference to FIG. 50, which may cause a leak current between the conductive layers 110.

[0109] On the other hand, if the supporting insulating member HR is placed too far away from the groove STA, the distance from the Y-direction side of the supporting insulating member HR to the Y-direction end of the insulating layer 101 will become too large in the process described with reference to Figures 48 and 49, which will cause the insulating layer 101 to warp.

[0110] Therefore, in this embodiment, the hook-up region R HU2 In this case, the supporting and insulating members HR in the supporting and insulating member rows HRR1 to HRR4 (Figure 9) corresponding to the structure MLA1 are each located closer to the center position in the Y direction of the inter-finger structure ST1 than the supporting and insulating members HR in the supporting and insulating member rows HRR1 to HRR4 included in the structure MLA2.

[0111] With this configuration, the distance from the Y-direction side of the supporting insulating member HR to the Y-direction end of the insulating layer 101 can be suitably adjusted, thereby suppressing the leakage current as described above and suppressing bending of the insulating layer 101.

[0112] As described with reference to FIG. HU2 In the groove STA, a widened portion is formed which widens in the Y direction from the positive side in the X direction to the negative side in the X direction.

[0113] Therefore, for example, if the multiple support insulating members HR included in the support insulating member rows HRR1, HRR3 closest to the inter-finger structure ST1 are arranged in a row in the X direction, there is a concern that some of the support insulating members HR will be exposed in the groove STA or that some of the support insulating members HR will be too far away from the groove STA.

[0114] Therefore, in this embodiment, as described with reference to Figure 9, the multiple support insulating members HR in the support insulating member rows HRR1, HRR3 are arranged so that they gradually move away from the central position in the Y direction of the inter-finger structure ST1 from the positive side to the negative side in the X direction.

[0115] With this configuration, the distance from the Y-direction side of the supporting insulating member HR to the Y-direction end of the insulating layer 101 can be suitably adjusted, thereby suppressing the leakage current as described above and suppressing bending of the insulating layer 101.

[0116] [Second embodiment] As described with reference to FIG. 2, in the first embodiment, the hook-up region R HU1 ,R HU2 are two memory hole regions R aligned in the X direction. MH As described with reference to FIG. HU2 In the hook-up region R, a plurality of terraces T corresponding to the plurality of conductive layers 110 (WL) and the plurality of conductive layers 110 (SGS) and a connection portion 111 are provided. However, this configuration is merely an example, and the specific configuration can be appropriately adjusted. For example, the hook-up region R HU1 ,R HU2 is the memory cell array region R MCA The hook-up region R may be provided at one end or both ends in the X direction. HU2 The connecting portion 111 may not be provided.

[0117] Such a configuration will be exemplified below as embodiment 2. In the following description, the same parts as those in embodiment 1 are given the same reference numerals, and the description thereof may be omitted.

[0118] [structure] 52 and 53 are schematic plan views showing a configuration of a portion of the semiconductor memory device. FIG. 54 is a schematic cross-sectional view showing a configuration of a portion of the semiconductor memory device, showing a cross section of the structure shown in FIG. 53 cut along line HH' and viewed in the direction of the arrows. FIG. 55 is a schematic cross-sectional view showing a configuration of a portion of the semiconductor memory device, showing a cross section of the structure shown in FIG. 53 cut along line JJ' and viewed in the direction of the arrows. FIG. 56 is a schematic cross-sectional view showing a configuration of a portion of the semiconductor memory device, showing a cross section of the structure shown in FIG. 53 cut along line KK' and viewed in the direction of the arrows.

[0119] 52, the semiconductor memory device according to the second embodiment includes a memory die MD2. In the illustrated example, the memory die MD2 includes four memory cell array regions R aligned in the X and Y directions. MCA2 The memory cell array region R MCA2 There are two hook-up areas R aligned in the X direction. HU3 And these two hookup areas R HU3 Two hook-up regions R arranged in the X direction between HU1 And these two hookup areas R HU1 The memory hole region R MH In addition, a peripheral circuit region R is provided at the end of the memory die MD2 in the Y direction. P is provided.

[0120] Memory cell array region R MCA2 The finger structure FS2 has a plurality of finger structures FS2 arranged in the Y direction. The finger structures FS2 have two hook-up regions R arranged in the X direction. HU3 , and two hook-up regions R provided between them. HU1 , and a memory hole region R MH The film extends in the X direction.

[0121] The finger structure FS2 is basically configured in the same manner as the finger structure FS. However, the finger structure FS2 has a plurality of (three in the illustrated example) structures ML arranged in the Z direction instead of the plurality of structures ML1, ML2, and ML3. 21 ,ML 22 ,ML 23 (Figures 55 and 56).

[0122] Multiple Structure ML 21 ,ML 22 ,ML 23 is basically configured in the same manner as the multiple structures ML2, ML2, and ML3. However, the multiple structures ML 21 ,ML 22 ,ML 23 Hookup area R HU3 The structure in is a hook-up region R of multiple structures ML2, ML2, and ML3. HU2 The structure differs from that in

[0123] Hookup Area R HU3 53, terrace portions T of the conductive layers 110 are provided on the hook-up region R. In this embodiment, the terrace portions T of the conductive layers 110(WL) and the one or more conductive layers 110(SGS) are provided on the ends in the X direction of the conductive layers 110(WL) and the one or more conductive layers 110(SGS), respectively. These terrace portions T are covered by the insulating layer 102 as shown in FIG. 54. In addition, the hook-up region R HU3 A plurality of via contact electrodes CC are provided in the insulating substrate 10 corresponding to the plurality of terrace portions T.

[0124] In the example of Fig. 53, a plurality of terrace portions T corresponding to the 3n+1th (n is an integer equal to or greater than 0) conductive layer 110(WL) counting from the top are aligned in the X direction as viewed from above. Similarly, a plurality of terrace portions T corresponding to the 3n+2th conductive layer 110(WL) counting from the top are aligned in the X direction as viewed from above. Similarly, a plurality of terrace portions T corresponding to the 3n+3th conductive layer 110(WL) counting from the top are aligned in the X direction as viewed from above. For example, the terrace portions T provided on the negative side of the X direction correspond to the upper conductive layer 110, and the terrace portions T provided on the positive side of the X direction correspond to the lower conductive layer 110.

[0125] In addition, in the illustrated example, the terrace portion T corresponding to the 3n+1th conductive layer 110(WL) counting from the top is aligned in the Y direction with two terrace portions T corresponding to the 3n+2nd and 3n+3rd conductive layers 110(WL) when viewed from above.

[0126] Here, hookup area R HU3 In the embodiment, the inter-finger structure ST has a widened portion. The inter-finger structure ST has a widened portion on one side in the X direction (the memory hole region R MH side) to the other side in the X direction (memory hole area R MH The width is increased in the Y direction from the opposite side to the Y direction.

[0127] Hookup Area R HU3 53, the Y-direction width of the inter-finger structure ST increases as it approaches the terrace portion T of the conductive layer 110 provided below, that is, as the length of the insulating layer 102 in the Z direction increases. For example, in the example of FIG. 53, a terrace portion T21 of the conductive layer 110c is provided at a position X21 in the X direction. Furthermore, a terrace portion T22 of the conductive layer 110d provided below the conductive layer 110c is provided at a position X22 in the X direction. Here, the Y-direction width Y21 of the inter-finger structure ST at the position X21 is smaller than the Y-direction width Y22 of the inter-finger structure ST at the position X22.

[0128] Also, hook-up area R HU354, in this embodiment, the height positions of the upper ends of the supporting and insulating members HR are provided above the height positions of the corresponding terrace portions T. That is, as shown in FIGS. 55 and 56, in each finger structure FS2, the plurality of supporting and insulating member rows HRR arranged in the Y direction are aligned with the structure ML including the positions in the Z direction corresponding to the insulating layer 102 provided to cover the terrace portions T. 21 ,ML 22 ,ML 23 It is located inside.

[0129] 53, the supporting and insulating member row HRR basically includes a plurality of supporting and insulating members HR aligned in a row in the X direction. That is, the positions in the Y direction of the multiple supporting and insulating members HR included in the supporting and insulating member row HRR basically substantially coincide with each other.

[0130] However, the hook-up area R HU3 In the first and second support insulating member rows HRR21 and HRR22 counting from one side in the Y direction, and the first and second support insulating member rows HRR23 and HRR24 counting from the other side in the Y direction, among the multiple support insulating member rows HRR included in each finger structure FS2, the multiple support insulating members HR are arranged on one side in the X direction (the memory hole region R MH side) to the other side in the X direction (memory hole area R MH and the opposite side) are arranged so as to gradually move away from the center position in the Y direction of the inter-finger structure ST.

[0131] In these support insulating member rows HRR21 to HRR24, the Y-direction positions of the multiple support insulating members HR are farther from the center position in the Y-direction of the inter-finger structure ST as they approach the terrace portion T of the conductive layer 110 provided below, i.e., as the length in the Z-direction of the insulating layer 102 increases. For example, in the example of FIG. 53, among the multiple support insulating members HR included in two support insulating member rows HRR21 and HRR23 adjacent in the Y-direction via the inter-finger structure ST, the Y-direction distance D21 between the two support insulating members HR21 provided at position X21 is smaller than the Y-direction distance D22 between the two support insulating members HR22 provided at position X22. In addition, the distance D23 between the center positions in the Y-direction of the two support insulating members HR21 is smaller than the distance D24 between the center positions in the Y-direction of the two support insulating members HR22.

[0132] Also, in Figure 53, the structure ML 22 1 illustrates a configuration of the conductive layer 110 in the vicinity of the terrace portion T. However, in the structure ML 21 ,ML 23 The configuration of the conductive layer 110 in the vicinity of the terrace portion T is also substantially the same.

[0133] However, the inter-finger structure ST has a hook-up region R HU3 One side of the X direction (memory hole area R MH side) to the other side in the X direction (memory hole area R MH The width of the structure increases in the Y direction toward the end of the structure (opposite the end of the ML structure). 21 In the vicinity of the terrace portion T of the conductive layer 110 included in the structure ML, the width in the Y direction of the inter-finger structure ST is larger than the widths Y21 and Y22. 23 In the vicinity of the terrace portion T of the conductive layer 110 included in the above, the width in the Y direction of the inter-finger structure ST is smaller than the widths Y21 and Y22.

[0134] In addition, the structure ML 23In the vicinity of the terrace portion T of the conductive layer 110 included in the above, among the plurality of supporting insulating members HR included in two supporting insulating member rows HRR adjacent to each other in the Y direction via the inter-finger structure ST, a structure ML 22 The distance in the Y direction between the two supporting insulating members HR included in is smaller than the distances D21 and D22.

[0135] Also, as shown in Figure 55, the structure ML 22 The plurality of supporting insulating members HR included in the structure ML 21 The structure ML is provided at a position overlapping with the multiple support insulating members HR included in the structure ML when viewed from the Z direction. 23 The plurality of supporting insulating members HR included in the structure ML 22 The support insulating members HR are provided at positions overlapping with the multiple support insulating members HR included in the support insulating members HR when viewed from the Z direction.

[0136] However, as shown in FIG. 56, for example, at position X22 (FIG. 53) or in its vicinity, the structure ML 21 The support insulating member HR in the support insulating member row HRR21 included in the structure ML 22 The structure ML is provided at a position closer to the center position in the Y direction of the inter-finger structure ST than the supporting insulating member HR in the supporting insulating member row HRR21 included in the structure ML. 21 The support insulating members HR in the support insulating member rows HRR22 to HRR24 included in 22 The structure ML is provided at a position closer to the center position in the Y direction of the inter-finger structure ST than the supporting and insulating members HR in the supporting and insulating member rows HRR22 to HRR24 included in the structure ML. 22 The support insulating members HR in the support insulating member rows HRR21 to HRR24 included in 23 The supporting and insulating members HR in the supporting and insulating member rows HRR21 to HRR24 included in the inter-finger structure ST are provided at positions closer to the center position in the Y direction of the inter-finger structure ST than the supporting and insulating members HR in the supporting and insulating member rows HRR21 to HRR24 included in the inter-finger structure ST.

[0137] In the example of Figure 56, the structure ML 21In the structure, the distance D25 in the Y direction between the supporting insulating members HR in the supporting insulating member rows HRR21 and HRR23 adjacent to each other in the Y direction with the inter-finger structure ST therebetween is equal to the distance D25 in the Y direction between the supporting insulating members HR in the supporting insulating member rows HRR21 and HRR23 adjacent to each other in the Y direction with the inter-finger structure ST therebetween, 22 In addition, the distance D26 is smaller than the distance D26 in the Y direction between the supporting insulating members HR in the supporting insulating member rows HRR21 and HRR23 adjacent to each other in the Y direction with the inter-finger structure ST therebetween. 23 This is smaller than the distance D27 in the Y direction between the supporting insulating members HR in the supporting insulating member rows HRR21, HRR23 adjacent in the Y direction with the inter-finger structures ST interposed therebetween.

[0138] The length corresponding to the difference between the distance D25 and the distance D26 may be greater as the distance approaches the terrace portion T of the conductive layer 110 provided below, i.e., as the length in the Z direction of the insulating layer 102 increases. Similarly, the length corresponding to the difference between the distance D26 and the distance D27 may be greater as the distance approaches the terrace portion T of the conductive layer 110 provided below, i.e., as the length in the Z direction of the insulating layer 102 increases.

[0139] [Manufacturing method] A method for manufacturing the semiconductor memory device according to the second embodiment will now be described with reference to Figures 57 to 68. Figures 57 to 68 are schematic cross-sectional views for explaining the manufacturing method, and show a cross section corresponding to Figure 56.

[0140] In manufacturing the semiconductor memory device according to this embodiment, the process described with reference to FIG. 14 is performed. In this process, the insulating layers 101 having the structure ML 21 (FIG. 56) and among the multiple sacrificial layers 110A, structure ML 21 In the following, a structure including these is referred to as the MLA structure. 21 It is sometimes called.

[0141] Next, hookup area R HU3In this process, a portion of the insulating layers 101 and a portion of the sacrificial layers 110A are removed to form a plurality of terrace portions TA. In this process, a resist is formed on the upper surface of the structure as shown in Fig. 14, similarly to the process described with reference to Fig. 20 and Fig. 21. In addition, the removal of the sacrificial layers 110A, the removal of the insulating layers 101, and the removal of a portion of the resist are repeatedly performed.

[0142] Next, an insulating layer 102 such as silicon oxide (SiO2) is formed to cover the terrace portions TA. This step is performed in the same manner as the step described with reference to FIG.

[0143] Next, as shown in Figures 15, 17 and 57, a plurality of memory holes MH are formed at positions corresponding to a plurality of semiconductor pillars 120. Also, a plurality of via holes HRA are formed at positions corresponding to a plurality of supporting insulating members HR. This process is performed in the same manner as the process described with reference to Figures 15 to 17, for example.

[0144] Next, for example, the steps described with reference to FIG. 18 are carried out.

[0145] Next, a supporting insulating member HR is formed inside the via holes HRA as shown in Fig. 58. This step is performed in the same manner as the step described with reference to Fig. 19, for example.

[0146] 23 and 59, a plurality of insulating layers 101 and a plurality of sacrificial layers 110A are alternately formed on the upper surface of the insulating layer 102. In this step, among the plurality of insulating layers 101, the structure ML 22 (FIG. 56) and among the multiple sacrificial layers 110A, structure ML 22 In the following, a structure including these is referred to as the MLA structure. 22 It is sometimes called.

[0147] Next, as shown in Figure 60, the hook-up area R HU3In step S20, a part of the insulating layers 101 and the sacrificial layers 110A is removed to form a plurality of terrace portions TA. This step is performed in the same manner as the step described with reference to FIGS.

[0148] Next, as shown in Fig. 61, an insulating layer 102 such as silicon oxide (SiO2) is formed to cover the plurality of terrace portions TA. This step is performed in the same manner as the step described with reference to Fig. 31, for example.

[0149] Next, as shown in Fig. 25 and Fig. 62, for example, a plurality of memory holes MH are formed at positions corresponding to a plurality of semiconductor pillars 120. Also, a plurality of via holes HRA are formed at positions corresponding to a plurality of supporting insulating members HR. This process is performed in the same manner as the process described with reference to Fig. 25 and Fig. 26.

[0150] Next, for example, the steps described with reference to FIG. 27 are carried out.

[0151] Next, a supporting insulating member HR is formed inside the via holes HRA as shown in Fig. 63. This step is performed in the same manner as the step described with reference to Fig. 28, for example.

[0152] Next, as shown in, for example, FIG. 32 and FIG. 64, a plurality of insulating layers 101 and a plurality of sacrificial layers 110A are alternately formed on the upper surface of the insulating layer 102. In this step, among the plurality of insulating layers 101, the structure ML 23 (FIG. 56) and among the multiple sacrificial layers 110A, structure ML 23 A structure including these is called the structure MLA. 23 It is called.

[0153] Next, hookup area R HU3 In step S20, a part of the insulating layers 101 and the sacrificial layers 110A is removed to form a plurality of terrace portions TA. This step is performed in the same manner as the step described with reference to FIGS.

[0154] Next, as shown in Fig. 65, for example, an insulating layer 102 such as silicon oxide (SiO2) is formed to cover the terrace portions TA. This step is performed in the same manner as the step described with reference to Fig. 42.

[0155] Next, as shown in Figures 34 and 66, for example, a plurality of memory holes MH are formed at positions corresponding to a plurality of semiconductor pillars 120. Also, a plurality of via holes HRA are formed at positions corresponding to a plurality of supporting insulating members HR. This process is performed in the same manner as the process described with reference to Figures 34 and 35, for example.

[0156] Next, the steps described with reference to, for example, FIGS. 36 to 38 are carried out.

[0157] Next, a supporting insulating member HR is formed inside the via holes HRA as shown in Fig. 67. This step is performed in the same manner as the step described with reference to Fig. 39, for example.

[0158] Next, grooves STA are formed at positions corresponding to the inter-finger structures ST, as shown in, for example, Figures 44 and 68. This step is performed in the same manner as the steps described with reference to, for example, Figures 43 to 46.

[0159] Thereafter, the steps subsequent to the step described with reference to FIG. 47 in the method for manufacturing the semiconductor memory device according to the first embodiment are performed to form the semiconductor memory device according to the second embodiment.

[0160] [effect] In the structure of the second embodiment, the structure MLA 21 The support insulating members HR in the support insulating member rows HRR21 to HRR24 corresponding to the structures MLA 22 By providing the insulating layer 101 at a position closer to the center in the Y direction of the inter-finger structure ST than the supporting insulating members HR in the supporting insulating member rows HRR21 to HRR24 included in the insulating layer 101, it is possible to suppress leakage current and to suppress bending of the insulating layer 101.

[0161] Also, hook-up area RHU3 Then, the plurality of supporting and insulating members HR in the supporting and insulating member rows HRR21 and HRR23 are arranged on one side in the X direction (the memory hole region R MH side) to the other side in the X direction (memory hole area R MH By arranging the insulating layer 101 so that the distance therebetween gradually increases from the center position in the Y direction of the inter-finger structure ST toward the opposite side (the opposite side to the Y direction), it is possible to suppress leakage current and to suppress bending of the insulating layer 101.

[0162] [Third embodiment] Next, a semiconductor memory device according to a third embodiment will be described with reference to Figures 69 and 70. In the following description, the same parts as those in the first embodiment are denoted by the same reference numerals, and description thereof may be omitted.

[0163] Fig. 69 is a schematic cross-sectional view showing a configuration of a portion of the semiconductor memory device, and Fig. 70 is a schematic cross-sectional view showing a configuration of a portion of the semiconductor memory device, and shows an enlarged view of the portion indicated by L in Fig. 69.

[0164] The semiconductor memory device according to the third embodiment is basically configured in the same manner as the semiconductor memory device according to the first embodiment, but has a structure ML 31 Equipped with structure ML 31 is basically configured similarly to structure ML1, but has support insulating member rows HRR31, HRR33 instead of support insulating member rows HRR1, HRR3. The support insulating member rows HRR31, HRR33 are basically configured similarly to the support insulating member rows HRR1, HRR3, but has support insulating member HR33 instead of support insulating member HR3.

[0165] The supporting insulating member HR33 is basically configured in the same manner as the supporting insulating member HR3, except that the lengths in the X and Y directions of the supporting insulating member HR3 are the same as those of the other supporting insulating members HR, whereas the lengths in the X and Y directions of the supporting insulating member HR33 are greater than those of the other supporting insulating members HR.

[0166] For example, at or near position X2 (FIG. 9), the structure ML 31 The supporting and insulating member HR33 in the supporting and insulating member row HRR31 included in the structure ML2 is provided closer to the center position in the Y direction of the inter-finger structure ST1 than the supporting and insulating member HR4 in the supporting and insulating member row HRR1 included in the structure ML2. 31 The supporting and insulating member HR33 in the supporting and insulating member row HRR33 included in the structure ML2 is provided closer to the center position in the Y direction of the inter-finger structure ST1 than the supporting and insulating member HR4 in the supporting and insulating member row HRR3 included in the structure ML2. 31 In the structure ML2, the Y-direction distance D6 between two supporting insulating members HR33 adjacent in the Y-direction with the inter-finger structure ST1 between them is smaller than the Y-direction distance D5 between two supporting insulating members HR4 adjacent in the Y-direction with the inter-finger structure ST1 between them in the structure ML2.

[0167] In addition, in the example of Figure 70, the structure ML 31 In the structure ML2, a distance D37 between the center positions in the Y direction of two supporting insulating members HR33 adjacent in the Y direction with the inter-finger structure ST1 interposed therebetween is smaller than a distance D8 between the center positions in the Y direction of two supporting insulating members HR4 adjacent in the Y direction with the inter-finger structure ST1 interposed therebetween in the structure ML2. However, the distance D37 may be approximately the same as the distance D8, or may be larger than the distance D8.

[0168] 70, the upper end of the supporting insulating member HR33 is connected to the lower end of the supporting insulating member HR4. However, the upper end of the supporting insulating member HR33 may be spaced apart from the lower end of the supporting insulating member HR4 in the Y direction.

[0169] The semiconductor memory device according to the third embodiment can be basically manufactured by the same method as the semiconductor memory device according to the first embodiment. However, in manufacturing the semiconductor memory device according to the third embodiment, a via hole HRA larger than the other via holes HRA is formed at a position corresponding to the supporting insulating member HR33 in the process described with reference to Figures 15 to 17.

[0170] In the structure of the third embodiment as well, it is possible to suppress the leakage current and the bending of the insulating layer 101.

[0171] In the semiconductor memory device according to the second embodiment, the structure ML 21 A part of the normal supporting and insulating members HR included in the supporting and insulating member rows HRR21, HRR23 may be replaced with the supporting and insulating members HR33 according to the third embodiment.

[0172] [Fourth embodiment] Next, a semiconductor memory device according to a fourth embodiment will be described with reference to Fig. 71. Fig. 71 is a schematic cross-sectional view showing a configuration of a portion of the semiconductor memory device. In the following description, the same reference numerals are used to designate the same parts as those in the first embodiment, and the description may be omitted.

[0173] The semiconductor memory device according to the fourth embodiment is basically configured similarly to the semiconductor memory device according to the first embodiment, but includes a supporting and insulating member HR' instead of the supporting and insulating member HR.

[0174] The support insulating member HR' includes a semiconductor pillar 420 extending in the Z direction, an insulating film 430 provided between the plurality of conductive layers 110 and the semiconductor pillar 420, and an insulating pillar 425 provided in the center of the semiconductor pillar 420. The semiconductor pillar 420, the insulating film 430, and the insulating pillar 425 are basically configured in the same manner as the semiconductor pillar 120, the gate insulating film 130, and the insulating pillar 125, respectively. However, the semiconductor pillar 420, the insulating film 430, and the insulating pillar 425 are not electrically connected to the bit line BL, and do not function as components of a memory cell MC or the like. In the illustrated example, a gap V is provided inside the insulating pillar 425.

[0175] As shown in Figure 71, the distance D47 between the center positions in the Y direction of two supporting insulating members HR' adjacent to each other in the Y direction with the inter-finger structure ST1 in structure ML1 is smaller than the distance D8 between the center positions in the Y direction of two supporting insulating members HR' adjacent to each other in the Y direction with the inter-finger structure ST1 in structure ML2.

[0176] As shown in FIG. 71, the upper ends of the semiconductor pillar 420, the insulating film 430 and the insulating pillar 425 included in the supporting insulating member HR' in the structure ML1 are connected to the lower ends of the semiconductor pillar 420, the insulating film 430 and the insulating pillar 425 included in the supporting insulating member HR' in the structure ML2, respectively.

[0177] The semiconductor memory device according to the fourth embodiment can be basically manufactured by the same method as the semiconductor memory device according to the first embodiment. However, in manufacturing the semiconductor memory device according to the fourth embodiment, in the process described with reference to Fig. 18 and the process described with reference to Fig. 27, sacrificial pillars 120A are formed not only in the memory holes MH but also inside the via holes HRA. In addition, in the process described with reference to Figs. 37 and 38, insulating film 430, semiconductor pillars 420, and insulating pillars 425 are formed inside the via holes HRA.

[0178] In addition, in manufacturing the semiconductor memory device according to the fourth embodiment, the process described with reference to FIG. 19, the process described with reference to FIG. 28, and the process described with reference to FIG. 39 are not performed.

[0179] In the structure of the fourth embodiment as well, it is possible to suppress the leakage current and the bending of the insulating layer 101.

[0180] In the semiconductor memory device according to the first embodiment, only a portion of the supporting and insulating members HR may be replaced with the supporting and insulating members HR' according to the fourth embodiment. In the semiconductor memory device according to the second or third embodiment, a portion or all of the supporting and insulating members HR may be replaced with the supporting and insulating members HR' according to the fourth embodiment.

[0181] [Other embodiments] The semiconductor memory devices according to the first to fourth embodiments have been described above. However, the configurations shown above are merely examples, and the specific configurations can be adjusted as appropriate.

[0182] For example, the arrangements of the supporting insulating members HR as shown in Figs. 4, 9 and 53 are merely examples, and the specific arrangements can be adjusted as appropriate.

[0183] Also, for example, in the semiconductor memory device according to the first embodiment, in each finger structure FS, in support and insulating member rows HRR1-HRR4 close to the inter-finger structure ST1, the support and insulating members HR in structure ML1 are provided at a position closer to the center of the inter-finger structure ST1 in the Y direction than the support and insulating members HR in structure ML2. Meanwhile, in each finger structure FS, in one or more support and insulating member rows HRR close to the other inter-finger structures ST, the support and insulating members HR in structure ML2 are provided at positions overlapping with the support and insulating members HR in structure ML1 when viewed from the Z direction.

[0184] However, for example, in the semiconductor memory device of the first embodiment, in one or more support insulating member rows HRR near inter-finger structures ST other than inter-finger structure ST1, the support insulating member HR in structure ML1 may be located closer to the center position of the inter-finger structure ST in the Y direction than the support insulating member HR in structure ML2.

[0185] In addition, for example, in the first to fourth embodiments, in all the supporting insulating member rows HRR in each finger structure FS (FS2), the structure ML2 (ML 22 The supporting insulating member HR (HR') in the structure ML1 (ML 21 , M.L. 31 In addition, in all the supporting insulating member rows HRR in each finger structure FS (FS2), the structure ML3 (ML 23 ) in the structure ML2 (ML 22 ) when viewed from the Z direction.

[0186] Also, for example, in the first to third embodiments, an example has been shown in which the outer circumferential surfaces of all the supporting insulating members HR are entirely surrounded by the conductive layer 110. However, this configuration is merely an example, and the specific configuration can be appropriately adjusted.

[0187] Figure 72 is a schematic plan view showing a partial configuration of a semiconductor memory device according to another embodiment, and Figure 73 is a schematic cross-sectional view showing a partial configuration of a semiconductor memory device according to another embodiment.

[0188] As described above, if the support insulating member HR is exposed to the trench STA during the manufacturing of the semiconductor memory device, metals such as titanium nitride and tungsten are formed in the voids inside the support insulating member HR in the process described with reference to FIG. 50, which causes leakage current between the conductive layers 110. However, since such voids tend to be formed in the vicinity of the central axis of the support insulating member HR, even if the support insulating member HR is exposed to the trench STA, the occurrence of leakage current can be suppressed as long as the voids inside the support insulating member HR are not exposed to the trench STA. Therefore, in the first to third embodiments, it is not necessary that the outer periphery of all the support insulating members HR is surrounded by the conductive layer 110 over the entire circumference. However, as shown in FIG. 72 and FIG. 73, at least a part of the outer periphery of the support insulating member HR is surrounded by the conductive layer 110.

[0189] In addition, for example, in the first to fourth embodiments, an example has been shown in which the inter-finger structure ST increases in width in the Y direction from the lower end to the upper end. However, such a configuration is merely an example, and the specific configuration can be appropriately adjusted.

[0190] 74 and 75 are schematic plan views showing the configuration of a portion of a semiconductor memory device according to another embodiment.

[0191] 74 and 75, the inter-finger structure ST has a widening portion that widens in the Y direction from the lower end to the height position corresponding to structure ML3. In the example of Figures 74 and 75, the inter-finger structure ST widens in the Y direction from the upper end to the height position corresponding to structure ML3. The inter-finger structure ST according to the first to fourth embodiments may have such a shape.

[0192] Furthermore, the manufacturing methods described above are merely examples, and the specific methods can be adjusted as appropriate.

[0193] For example, in manufacturing the semiconductor memory device according to the first embodiment, the memory hole MH, the via hole HRA, and their internal structures are formed as described with reference to Figures 15 to 19, and then the terrace portions TA and the insulating layer 102 thereover are formed as described with reference to Figures 20 to 22. This order is common to all of the steps of forming the structure corresponding to structure ML1, the step of forming the structure corresponding to structure ML2, and the step of forming the structure corresponding to structure ML3.

[0194] In the manufacturing process of the semiconductor memory device according to the second embodiment, a plurality of terrace portions TA are formed, and then the memory holes MH, the via holes HRA, and the internal structures thereof are formed. 21 forming a structure corresponding to structure ML 22 and forming a structure corresponding to structure ML 23 This is common to all of the steps of forming the structures corresponding to the above.

[0195] However, such a method is merely an example, and the specific method can be adjusted as appropriate.

[0196] For example, in the manufacture of the semiconductor memory device according to the first embodiment, in the process of forming the configuration corresponding to structure ML1, the process of forming the configuration corresponding to structure ML2, and in some or all of the configuration corresponding to structure ML3, the terrace portions TA may be formed prior to the memory holes MH, the via holes HRA, and the configurations therein. When the semiconductor memory device according to the first embodiment is formed by such a method, the height positions of the upper ends of the supporting insulating members HR are provided above the height positions of the corresponding terrace portions T in some or all of the structures ML1, ML2, and ML3.

[0197] In addition, for example, in the manufacture of the semiconductor memory device according to the second embodiment, the structure ML 21 forming a structure corresponding to structure ML 22 and forming a structure corresponding to structure ML 23 In a part or all of the configuration corresponding to the structure ML, the memory hole MH, the via hole HRA, and the internal configuration thereof may be formed before the terrace portions TA. 21 ,ML 22 ,ML 23 In some or all of these, the height position of the upper end of the supporting insulating member HR substantially coincides with the height position of the corresponding terrace portion T.

[0198] [others] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0199] 110...conductive layer, 120...semiconductor pillar, 130...gate insulating film, 131...tunnel insulating film, 132...charge storage film, 133...block insulating film, 140...inter-finger insulating member, 141...inter-finger electrode, BL...bit line, CC...via contact electrode, FS...finger structure, HR...support insulating member, HRR...support insulating member row, ML1, ML2, ML3...structure, R MH …Memory hole area, R HU1 ,R HU2 ...hook-up region, ST...inter-finger structure, T...terrace portion.

Claims

1. a plurality of finger structures aligned in a first direction and extending in a second direction intersecting the first direction; a first inter-finger insulating member provided between a first finger structure and a second finger structure adjacent to each other in the first direction among the plurality of finger structures, the first inter-finger insulating member extending in a stacking direction intersecting the first direction and the second direction and in the second direction; a plurality of bit lines provided on one side of the stacking direction with respect to the plurality of finger structures and the first inter-finger insulating member, aligned in the second direction, and extending in the first direction; Equipped with each of the plurality of finger structures includes a first structure and a second structure provided on a side of the first structure facing the plurality of bit lines in the stacking direction; The first structure and the second structure are a plurality of conductive layers stacked in the stacking direction, extending in the second direction across a first region and a second region aligned in the second direction, and including a plurality of terrace portions provided in the second region; a first semiconductor pillar provided in the first region, extending in the stacking direction, facing the plurality of conductive layers, and electrically connected to any one of the plurality of bit lines; a first charge storage film provided between the plurality of conductive layers and the first semiconductor pillar; a plurality of insulating member rows provided in the second region and aligned in the first direction, each row including a plurality of insulating members positioned at different positions in the second direction, each of the insulating members having an outer circumferential surface surrounded by at least a portion of the conductive layers as viewed from the stacking direction; Equipped with the first inter-finger insulating member has a portion that is expanded in width in the first direction from a side opposite to the bit lines in the stacking direction to a side of the bit lines in the stacking direction across a position in the stacking direction corresponding to the first structure of the plurality of finger structures and a position in the stacking direction corresponding to the second structure of the plurality of finger structures, Among the plurality of insulating member rows in the first finger structure, an insulating member row provided at a position closest to the second finger structure includes a first insulating member provided at a first position in the second direction at a position in the stacking direction corresponding to the first structure of the first finger structure, and a second insulating member provided at the first position in the second direction at a position in the stacking direction corresponding to the second structure of the first finger structure, Among the plurality of insulating member rows in the second finger structure, an insulating member row provided at a position closest to the first finger structure includes a third insulating member provided at the first position in the second direction at a position in the stacking direction corresponding to the first structure of the second finger structure, and a fourth insulating member provided at the first position in the second direction at a position in the stacking direction corresponding to the second structure of the second finger structure, A distance in the first direction between the first insulating member and the third insulating member is smaller than a distance in the first direction between the second insulating member and the fourth insulating member. Semiconductor memory device.

2. the plurality of finger structures further includes a third finger structure provided on an opposite side of the second finger structure from the first finger structure and adjacent to the second finger structure in the first direction; Among the plurality of insulating member rows in the second finger structure, an insulating member row provided at a position closest to the third finger structure includes a fifth insulating member provided at the first position in the second direction at a position in the stacking direction corresponding to the first structure of the second finger structure, and a sixth insulating member provided at the first position in the second direction at a position in the stacking direction corresponding to the second structure of the second finger structure, Among the plurality of insulating member rows in the third finger structure, an insulating member row provided at a position closest to the second finger structure includes a seventh insulating member provided at the first position in the second direction at a position in the stacking direction corresponding to the first structure of the third finger structure, and an eighth insulating member provided at the first position in the second direction at a position in the stacking direction corresponding to the second structure of the third finger structure, the sixth insulating member is provided at a position overlapping with the fifth insulating member when viewed from the stacking direction, The eighth insulating member is provided at a position overlapping the seventh insulating member when viewed from the stacking direction.

2. The semiconductor memory device according to claim 1.

3. the plurality of finger structures further includes a third finger structure provided on an opposite side of the second finger structure from the first finger structure and adjacent to the second finger structure in the first direction; Among the plurality of insulating member rows in the second finger structure, an insulating member row provided at a position closest to the third finger structure includes a fifth insulating member provided at the first position in the second direction at a position in the stacking direction corresponding to the first structure of the second finger structure, and a sixth insulating member provided at the first position in the second direction at a position in the stacking direction corresponding to the second structure of the second finger structure, Among the plurality of insulating member rows in the third finger structure, an insulating member row provided at a position closest to the second finger structure includes a seventh insulating member provided at the first position in the second direction at a position in the stacking direction corresponding to the first structure of the third finger structure, and an eighth insulating member provided at the first position in the second direction at a position in the stacking direction corresponding to the second structure of the third finger structure, A distance between the fifth insulating member and the seventh insulating member in the first direction is smaller than a distance between the sixth insulating member and the eighth insulating member in the first direction.

2. The semiconductor memory device according to claim 1.

4. a plurality of finger structures aligned in a first direction and extending in a second direction intersecting the first direction; a first inter-finger insulating member provided between a first finger structure and a second finger structure adjacent to each other in the first direction among the plurality of finger structures, the first inter-finger insulating member extending in a stacking direction intersecting the first direction and the second direction and in the second direction; Equipped with Each of the plurality of finger structures includes: a plurality of conductive layers stacked in the stacking direction, extending in the second direction across a first region and a second region aligned in the second direction, and including a plurality of terrace portions provided in the second region; a semiconductor pillar provided in the first region, extending in the stacking direction, and facing the plurality of conductive layers; a charge storage film provided between the plurality of conductive layers and the semiconductor pillar; a plurality of insulating member rows provided in the second region and aligned in the first direction, each row including a plurality of insulating members positioned at different positions in the second direction, each of the insulating members having an outer circumferential surface surrounded by at least a portion of the conductive layers as viewed from the stacking direction; Equipped with the first inter-finger insulating member expands in width in the first direction from a first position in the second direction to a second position in the second direction within the second region, a distance in the first direction between a first insulating member provided at the first position in a first insulating member row provided at a position closest to the second finger structure among the multiple insulating member rows in the first finger structure, and a second insulating member provided at the first position in a second insulating member row provided at a position closest to the first finger structure among the multiple insulating member rows in the second finger structure, is smaller than a distance in the first direction between a third insulating member provided at the second position in the first insulating member row, and a fourth insulating member provided at the second position in the second insulating member row. Semiconductor memory device.

5. a plurality of finger structures aligned in a first direction and extending in a second direction intersecting the first direction; a first inter-finger insulating member provided between a first finger structure and a second finger structure adjacent to each other in the first direction among the plurality of finger structures, the first inter-finger insulating member extending in a stacking direction intersecting the first direction and the second direction and in the second direction; a plurality of bit lines provided on one side of the stacking direction with respect to the plurality of finger structures and the first inter-finger insulating member, aligned in the second direction, and extending in the first direction; Equipped with each of the plurality of finger structures includes a first structure and a second structure provided on a side of the first structure facing the plurality of bit lines in the stacking direction; The first structure and the second structure are a plurality of conductive layers stacked in the stacking direction, extending in the second direction across a first region and a second region aligned in the second direction, and including a plurality of terrace portions provided in the second region; a semiconductor pillar provided in the first region, extending in the stacking direction, facing the plurality of conductive layers, and electrically connected to any one of the plurality of bit lines; a charge storage film provided between the plurality of conductive layers and the semiconductor pillar; a plurality of insulating member rows provided in the second region and aligned in the first direction, each row including a plurality of insulating members positioned at different positions in the second direction, each of the insulating members having an outer circumferential surface surrounded by at least a portion of the conductive layers as viewed from the stacking direction; Equipped with the first inter-finger insulating member has a portion that is expanded in width in the first direction from a side opposite to the bit lines in the stacking direction to a side of the bit lines in the stacking direction across a position in the stacking direction corresponding to the first structure of the plurality of finger structures and a position in the stacking direction corresponding to the second structure of the plurality of finger structures, Among the plurality of insulating member rows in the first finger structure, an insulating member row provided at a position closest to the second finger structure includes a first insulating member provided at a first position in the second direction at a position in the stacking direction corresponding to the first structure of the first finger structure, and a second insulating member provided at the first position in the second direction at a position in the stacking direction corresponding to the second structure of the first finger structure, The length of the first insulating member in the first direction is greater than the length of the second insulating member in the first direction. Semiconductor memory device.

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