Semiconductor device, electronic apparatus and vehicle

Abstract

To improve the characteristics of an output leakage current.SOLUTION: A semiconductor device 1 includes: a semiconductor substrate N-SUB; a well P / W formed in the semiconductor substrate N-SUB; an output terminal T4 electrically connected to the semiconductor substrate N-SUB; a ground terminal T7 to which a ground voltage GND is applied; a detection signal generating circuit 62a that generates a negative current detection signal DET when it is detected that an output voltage OUT at the output terminal T4 is less than the ground voltage GND; and a control circuit 62b that applies the ground voltage GND or the output voltage OUT to the well P / W in response to the negative current detection signal DET. The detection signal generating circuit 62a includes: a comparator CMP that generates the negative current detection signal DET by comparing an output detection voltage Vs with the ground voltage GND; a bias circuit BIAS that applies the output voltage OUT or a bias voltage VA-Vth as the output detection voltage Vs; and a clamp circuit CLP that operates when |Vs|>VCLP is satisfied.SELECTED DRAWING: Figure 19

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device, and an electronic device and a vehicle using the same. [Background technology]

[0002] The applicant of the present application has proposed many new technologies relating to semiconductor devices (for example, high-side switch LSIs [large scale integration] or low-side switch LSIs) such as in-vehicle intelligent power devices (IPDs) (for example, see Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2017 / 187785

[0004] [overview] However, in semiconductor devices such as in-vehicle IPDs, there is room for further study on preventing malfunctions of parasitic elements.

[0005] The semiconductor device according to the present disclosure comprises a semiconductor substrate of a first conductivity type, a well of a second conductivity type different from the first conductivity type formed in the semiconductor substrate, an output terminal configured to be electrically conductive with the semiconductor substrate, a ground terminal configured to apply a ground voltage, a detection signal generating circuit configured to detect that an output voltage appearing at the output terminal is lower than the ground voltage or a threshold voltage and generate a negative current detection signal, and a control circuit configured to switch between applying the ground voltage or the output voltage to the well in response to the negative current detection signal, wherein the detection signal generating circuit comprises a comparator configured to compare an output detection voltage with the ground voltage or the threshold voltage to generate the negative current detection signal, a bias circuit configured to switch between applying the output voltage or a bias voltage as the output detection voltage, and a clamp circuit configured to operate when the absolute value of the output detection voltage is higher than a clamp operating voltage. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is a diagram showing an overall configuration of a semiconductor device. [Diagram 2] FIG. 2 is a diagram showing a configuration example (first phase) of the electronic device. [Diagram 3] FIG. 3 is a diagram showing a configuration example (second phase) of the electronic device. [Figure 4] FIG. 4 is a diagram showing a configuration example (third phase) of the electronic device. [Diagram 5] FIG. 5 is a diagram showing a first embodiment of a negative current detection circuit. [Figure 6] FIG. 6 is a diagram illustrating a first operation state of the negative current detection circuit. [Figure 7] FIG. 7 is a diagram illustrating the second operation state of the negative current detection circuit. [Figure 8] FIG. 8 is a diagram illustrating the third operation state of the negative current detection circuit. [Figure 9] FIG. 9 is a diagram showing a fourth operation state of the negative current detection circuit. [Figure 10]FIG. 10 is a diagram showing the behavior when a negative current occurs (without a negative current detection circuit). [Figure 11] FIG. 11 is a vertical cross-sectional view of the semiconductor device (without a negative current detection circuit). [Figure 12] FIG. 12 is a diagram showing the behavior when a negative current occurs (with a negative current detection circuit). [Figure 13] FIG. 13 is a vertical cross-sectional view of the semiconductor device (with a negative current detection circuit). [Figure 14] FIG. 14 is a diagram showing the behavior (first leak condition) when the output is off in the first embodiment. [Figure 15] FIG. 15 is a diagram showing the relationship between the output voltage and the output leakage current (first leakage condition) in the first embodiment. [Figure 16] FIG. 16 is a diagram showing the behavior when the output is off (second leak condition) in the first embodiment. [Figure 17] FIG. 17 is a diagram showing the relationship between the output voltage and the output leakage current (second leakage condition) in the first embodiment. [Figure 18] FIG. 18 is a diagram showing output leakage current characteristics in the first embodiment. [Figure 19] FIG. 19 is a diagram showing a second embodiment of a negative current detection circuit. [Figure 20] FIG. 20 is a diagram showing the behavior (first leak condition) when the output is off in the second embodiment. [Figure 21] FIG. 21 is a diagram showing the relationship between the output voltage and the output leakage current (first leakage condition) in the second embodiment. [Figure 22] FIG. 22 is a diagram showing the behavior (second leak condition) when the output is off in the second embodiment. [Diagram 23] FIG. 23 is a diagram showing the relationship between the output voltage and the output leakage current (second leakage condition) in the second embodiment. [Figure 24] FIG. 24 is a diagram showing output leakage current characteristics in the second embodiment. [Diagram 25] FIG. 25 is a diagram showing the effect of improving the output leakage current characteristics. [Figure 26] FIG. 26 is a diagram showing the external appearance of the vehicle.

[0007] [Detailed Description] <Semiconductor device> 1 is a diagram showing the overall configuration of a semiconductor device. The semiconductor device 1 of this configuration example is an in-vehicle low-side switch LSI (= a type of in-vehicle IPD) that establishes / disconnects conduction between a load and a ground terminal in response to an external control signal IN and an external enable signal EN output from an ECU (electronic control unit) (not shown).

[0008] The semiconductor device 1 includes external terminals T1 to T7 as means for establishing electrical connection with the outside of the device. The external terminal T1 is a power supply terminal for receiving a supply of a power supply voltage VDD. The external terminals T2 and T3 are signal input terminals for receiving external inputs of an external enable signal EN and an external control signal IN, respectively. The external terminal T4 is a load connection terminal for externally connecting a load (such as a bulb lamp, a relay coil, a solenoid, a light-emitting diode, or a motor). The external terminal T4 can also be understood as an output terminal to which an output voltage OUT is applied. The external terminal T5 is a slew rate adjustment terminal for receiving an external input of a slew rate adjustment signal SR. The external terminal T6 is a signal output terminal for externally outputting a status signal ST. The external terminal T7 is a ground terminal.

[0009] Also, referring to this figure, the semiconductor device 1 is configured by integrating a power transistor 10 (e.g., an NMOSFET [N-channel type metal oxide semiconductor field effect transistor]), a sense transistor 20 (e.g., an NMOSFET), a gate control system 30, a logic 40, an input system 50, a reference system 60, a protection system 70, a status output unit 80, and current limiting resistors 91 and 92.

[0010] The drain of the power transistor 10 is connected to the external terminal T4. The source of the power transistor 10 is connected to the external terminal T7. The gate of the power transistor 10 is connected to the application terminal of the gate drive signal G1. The power transistor 10 connected in this manner functions as a lower switch element for conducting / cutting off the current path of the output current Io from the external terminal T4 to the external terminal T7. The power transistor 10 is turned on when the gate drive signal G1 is at a high level, and turned off when the gate drive signal G1 is at a low level. The power transistor 10 may be designed so that its on-resistance Ron is several tens of mΩ.

[0011] The sense transistor 20 is a current detection element with a gate and a drain commonly connected to the power transistor 10. The sense transistor 20 generates a sense current Is according to the output current Io flowing through the power transistor 10. The size ratio between the power transistor 10 and the sense transistor 20 is m:1 (where m>1). Therefore, the sense current Is has a magnitude obtained by subtracting the output current Io by 1 / m. Note that, like the power transistor 10, the sense transistor 20 is turned on when the gate drive signal G1 is at a high level, and turned off when the gate voltage G1 is at a low level.

[0012] The gate control system 30 performs on / off control of the power transistor 10 and the sense transistor 20 by generating a gate drive signal G1 in response to a gate control signal S1 from a logic 40. For example, the gate control system 30 includes a slew rate control circuit 31, an active clamp circuit 32, a gate resistor 33, and a transistor 34 (an NMOSFET in this figure).

[0013] The through-rate control circuit 31 operates by receiving the supply of the power supply voltage VDD through a path from the external terminal T1 via the current limiting resistor 91. The through-rate control circuit 31 includes, for example, a reference current source REF, a charging section CHG, and a discharging section DCHG. The reference current source REF generates a reference current Iref according to the through-rate adjustment signal SR externally input to the external terminal T5. The charging section CHG generates a charging current Ichg according to the reference current Iref. The discharging section DCHG generates a discharging current Idchg according to the reference current Iref. The through-rate control circuit 31 generates a gate drive signal G1 by charge-discharge control according to the gate control signal S1.

[0014] The active clamp circuit 32 is connected between the external terminal T4 and the gate of the power transistor 10. In an application where an inductive load is connected to the external terminal T4, when the power transistor 10 is switched from the on state to the off state, the output voltage OUT becomes a negative voltage (OUT < GND) due to the back electromotive force of the load. Therefore, the active clamp circuit 32 is provided for energy absorption. The active clamp circuit 32 restricts the drain-source voltage (= output voltage OUT) of the power transistor 10 to be equal to or lower than the active clamp voltage Vclp by not fully turning off the power transistor 10 during the off transition of the power transistor 10.

[0015] The gate resistor 33 is connected between the output terminal of the through-rate control circuit 31 and the gate of the power transistor 10 (= the applied terminal of the gate drive signal G1).

[0016] The transistor 34 is connected in parallel with the gate resistor 33. The transistor 34 may be controlled to be on / off, for example, according to the through-rate adjustment signal SR.

[0017] The logic 40 operates by receiving the supply of the power supply voltage VDD through a path from the external terminal T1 via the current limiting resistor 92. The logic 40 comprehensively controls the gate control system 30, the reference system 60, and the protection system 70 according to the external control signal IN and the external enable signal EN.

[0018] For example, the logic 40 sets the gate control signal S1 to a high level when the external enable signal EN is at a high level (=the logic level when enabled) and the external control signal IN is at a high level (=the logic level when turning on the power transistor 10). On the other hand, the logic 40 sets the gate control signal S1 to a low level when the external enable signal EN is at a low level (=the logic level when disabled) or when the external control signal IN is at a low level (=the logic level when turning off the power transistor 10).

[0019] The logic 40 also monitors various signals output from the gate control system 30, the input system 50, the reference system 60, and the protection system 70.

[0020] The input system 50 operates by receiving a supply of a power supply voltage VDD from an external terminal T1 through a path via a current limiting resistor 92. For example, the input system 50 includes an input control circuit 51, an enable control circuit 52, and a UVLO [under voltage lock out] circuit 53.

[0021] The input control circuit 51 receives an external input of an external control signal IN from an external terminal T3 and transmits it to the logic 40. The input control circuit 51 may be, for example, a Schmitt trigger.

[0022] The enable control circuit 52 receives an external input of an external enable signal EN from an external terminal T4 and transmits it to the logic 40. The enable control circuit 52 may be, for example, a Schmitt trigger.

[0023] The UVLO circuit 53 detects whether or not a low voltage abnormality occurs in the power supply voltage VDD, and outputs the detection result to the logic 40 and the reference system 60 (particularly a reference generation circuit 61 described later). The UVLO circuit 53 may be controlled by the enable control circuit 52 to be enabled or disabled.

[0024] The reference system 60 operates by receiving a supply of a power supply voltage VDD from an external terminal T1 through a path via a current limiting resistor 92. For example, the reference system 60 includes a reference generating circuit 61 and a negative current detecting circuit 62.

[0025] The reference generating circuit 61 generates a predetermined reference voltage VREF and a reference current IREF from a power supply voltage VDD. The reference voltage VREF and the reference current IREF may be supplied to the gate control system 30, for example.

[0026] The negative current detection circuit 62 monitors the output voltage OUT to detect whether the output current Io flows in the negative direction (= the direction from the source to the drain of the power transistor 10). The configuration and operation of the negative current detection circuit 62 will be described in detail later.

[0027] The protection system 70 operates by receiving a supply of a power supply voltage VDD from the external terminal T1 through a path via a current limiting resistor 92. The protection system 70 includes, for example, an overcurrent protection circuit 71, a temperature protection circuit 72, and an open load detection circuit 73.

[0028] The overcurrent protection circuit 71 monitors the sense current Is to detect whether or not an overcurrent abnormality has occurred in the output current Io, and outputs the detection result to the logic 40. The overcurrent protection circuit 71 may also have a function of limiting the output current Io by pulling down the gate drive signal G1 when an overcurrent is detected.

[0029] The temperature protection circuit 72 detects whether or not abnormal heat generation occurs in the semiconductor device 1, and outputs the detection result to the logic 40 and the status output unit 80. The temperature protection circuit 72 may also have a function of forcibly turning off the power transistor 10 by setting the gate drive signal G1 to a low level when abnormal heat generation is detected. The temperature protection circuit 72 may monitor the element temperature of the power transistor 10, or may monitor the temperature difference between the power transistor 10 and another circuit block (for example, the logic 40).

[0030] The load open detection circuit 73 detects whether or not a load open has occurred at the external terminal T4, and outputs the detection result to the logic 40 and the status output section 80.

[0031] The status output unit 80 operates by receiving a power supply voltage VDD from the external terminal T1 via a path via a current limiting resistor 92. The status output unit 80 generates a status signal ST in accordance with the detection results of the temperature protection circuit 72 and the load open detection circuit 73, and outputs this to the outside from an external terminal T6.

[0032] In addition to the ground voltage GND, a reference voltage GND_REF is applied to each of the above-mentioned functional blocks (details will be described later).

[0033] <Electronic equipment> 2 to 4 are diagrams showing an example of a configuration of an electronic device to which the semiconductor device 1 can be applied. The electronic device 100 of this example includes a voltage source E, transistors M1 to M4 (for example, NMOSFETs), and a load Z.

[0034] The voltage source E may be, for example, an in-vehicle battery that outputs a battery voltage VBAT.

[0035] The drains of the transistors M1 and M3 are both connected to the positive terminal of the voltage source E (=the terminal to which the battery voltage VBAT is applied). The source of the transistor M1 and the drain of the transistor M2 are both connected to a first terminal of the load Z. The source of the transistor M3 and the drain of the transistor M4 are both connected to a second terminal of the load Z. The sources of the transistors M2 and M4 are both connected to the negative terminal of the voltage source E (=the terminal to which the ground voltage GND is applied).

[0036] In this manner, the transistors M1 to M4 form a full-bridge type switch output stage that drives the load Z.

[0037] That is, the transistors M1 and M2 form a half-bridge type switch output stage (first phase) that drives a first terminal of the load Z. The transistors M3 and M4 form a half-bridge type switch output stage (second phase) that drives a second terminal of the load Z.

[0038] The above-mentioned semiconductor device 1 can be used as, for example, the transistor M2 or M4 (or its driving means) which is a lower-side switch element of the switch output stage. That is, the above-mentioned power transistor 10 can be understood as equivalent to the transistor M2 or M4.

[0039] The load Z may be an inductive load (for example a coil forming an on-board motor).

[0040] 2 to 4 respectively depict the first to third phases of the electronic device 100. The operating states in each figure will be described in detail below.

[0041] The first phase (Figure 2) corresponds to a state in which the motor, which is the load Z, is rotating. In accordance with this figure, in the first phase (Figure 2), both transistors M1 and M4 are on, and both transistors M2 and M3 are off. Therefore, the output current Io flows in the direction from the application terminal of the battery voltage VBAT to the application terminal of the ground voltage GND via the transistor M1, the load Z, and the transistor M4. At this time, there is no path through which the output current Io flows in the negative direction via the transistor M2. Therefore, the power consumption CP1 of the transistor M2 is zero.

[0042] The second phase (Fig. 3) corresponds to the dead time from the motor rotation state to the regeneration state. Such a dead time is provided for the purpose of preventing an excessive through current through the transistors M1 and M2. In accordance with this figure, by switching from the first phase (Fig. 2) to the second phase (Fig. 3), the transistor M1 switches from the on state to the off state. At this time, the inductive load Z tries to continue to flow the output current Io in the same direction as before. However, both the transistors M1 and M2 are in the off state. Therefore, the output current Io flows in the negative direction from the application terminal of the ground voltage GND to the load Z through the body diode BD associated with the transistor M2. As a result, the power consumption CP2 of the transistor M2 becomes relatively large (CP2=Io×Vf, where Vf is the forward drop voltage of the body diode BD).

[0043] The third phase (Fig. 4) corresponds to the regenerative state. In terms of this figure, by switching from the second phase (Fig. 3) to the third phase (Fig. 4), the transistor M2 switches from the off state to the on state. At this time, the inductive load Z tries to continue to flow the output current Io in the same direction as in the second phase (Fig. 3). In the third phase (Fig. 4), the transistor M2 is in the on state. Therefore, the output current Io flows in the negative direction from the application terminal of the ground voltage GND toward the load Z via the transistor M2. As a result, the power consumption CP3 of the transistor M2 becomes relatively small (CP3=Io×Io×Ron, where Ron is the on resistance of the transistor M2).

[0044] However, when the semiconductor device 1 is used as the transistor M2 or M4, malfunction of a parasitic element can become a problem.

[0045] For example, in the second phase (FIG. 3), consider a case where the transistor M2 is a VDMOSFET (vertical double diffused MOSFET) with an N-type semiconductor substrate as the drain. In this case, the drain voltage of the transistor M2 becomes a negative voltage (-Vf), which may cause a parasitic element (parasitic npn bipolar transistor or parasitic pn junction diode) associated with the semiconductor device 1 to malfunction.

[0046] In addition, malfunction of parasitic elements may cause the power supply voltage VDD to drop or latch-up to occur. In particular, if the transistor M2 does not switch to the on state correctly during the transition from the second phase (Figure 3) to the third phase (Figure 4), the result will be increased power consumption (heat generation).

[0047] In view of the above considerations, a negative current detection circuit 62 capable of preventing malfunction of a parasitic element associated with the semiconductor device 1 will be proposed below.

[0048] <Negative current detection circuit (first embodiment)> 5 is a diagram showing a first embodiment of the negative current detection circuit 62. The negative current detection circuit 62 of the present embodiment includes a comparator CMP, transistors N1 to N4 (e.g., NMOSFETs), transistors P1 and P2 (e.g., PMOSFETs), and resistors R1 to R4 (e.g., semiconductor diffused resistors).

[0049] The source and back gate of the transistor P1 are both connected to the application terminal of the power supply voltage VDD. The gate of the transistor P1 is connected to the application terminal of the inverted external enable signal ENB (=the logical inversion signal of the external enable signal EN). The drain of the transistor P1 is connected to the first terminal of the resistor R1. The second terminal of the resistor R1 is connected to the first terminal of the resistor R2. The second terminal of the resistor R2 and the first terminal of the resistor R3 are both connected to the non-inverting input terminal (+) of the comparator CMP (=the application terminal of the output detection voltage Vs). The second terminal of the resistor R3 and the inverting input terminal (-) of the comparator CMP are both connected to the application terminal of the ground voltage GND.

[0050] The drain of the transistor N1 is connected to the application terminal of the output voltage OUT (=N-type semiconductor substrate N-SUB). The gate of the transistor N1 is connected to the drain of the transistor P1 (=application terminal of the node voltage VA). The source and backgate of the transistor N1 are both connected to the non-inverting input terminal (+) of the comparator CMP.

[0051] The source and back gate of transistor P2 are all connected to the application terminal of the power supply voltage VDD. The drain of transistor P2 is connected to the drain of transistor N2. The source and back gate of transistor N2 and the drain and back gate of transistor N3 are all connected to the application terminal of the reference voltage GND_REF (=P-type well P / W). The gates of transistors P2, N2, and N3 are all connected to the output terminal of the comparator CMP (=application terminal of the negative current detection signal DET). The source of transistor N3 is connected to the application terminal of the ground voltage GND.

[0052] The drain of the transistor N4 is connected to the application terminal of the output voltage OUT (=N-type semiconductor substrate N-SUB). The gate of the transistor N4 is connected to the drains of the transistors P2 and N2 (=application terminal of the node voltage VB). The source and backgate of the transistor N4 and a first terminal of the resistor R4 are all connected to the application terminal of the reference voltage GND_REF (=P-type well P / W). The second terminal of the resistor R4 is connected to the application terminal of the ground voltage GND.

[0053] The transistors P1 and P2 and the resistors R1 to R4 are each formed in a P-type well P / W (= an application terminal of the reference voltage GND_REF) of the semiconductor device 1. That is, the reference voltage GND_REF is applied to the P-type well P / W and the back gates of the NMOSFETs of all the circuit blocks.

[0054] The comparator CMP operates by receiving the supply of a power supply voltage VDD. The comparator CMP generates a negative current detection signal DET by comparing the output detection voltage Vs input to the non-inverting input terminal (+) with the ground voltage GND applied to the inverting input terminal (-). Therefore, the negative current detection signal DET is at a high level when the output detection voltage Vs is higher than the ground voltage GND, and is at a low level when the output detection voltage Vs is lower than the ground voltage GND.

[0055] A predetermined threshold voltage VTH may be applied to the inverting input terminal (-) of the comparator CMP instead of the ground voltage GND. The comparator CMP may be controlled in operation according to an external enable signal EN (and an inverted external enable signal ENB). A reference voltage VREF may be applied to the comparator CMP.

[0056] Of the above components, the transistor N3 functions as a first transistor that establishes / cuts conduction between the application terminal of the reference voltage GND_REF (=P-type well P / W) and the application terminal of the ground voltage GND in response to the negative current detection signal DET.

[0057] The transistor N4 functions as a second transistor that establishes / cuts conduction between the application terminal of the reference voltage GND_REF (=P-type well P / W) and the application terminal of the output voltage OUT in response to the negative current detection signal DET.

[0058] The transistors P2 and N2 function as an inverter that drives the transistor N4 in response to the negative current detection signal DET.

[0059] The transistors P1 and P2 and the resistors R1 to R3 function as a bias section that switches between applying the output voltage OUT or a predetermined bias voltage (= a divided voltage of the power supply voltage VDD) to the non-inverting input terminal (+) of the comparator.

[0060] The negative current detection circuit 62 of this embodiment detects the output voltage OUT that appears at the external terminal T4 (=output terminal), and switches between applying the ground voltage GND or the output voltage OUT to the application terminal (=P-type well P / W) of the reference voltage GND_REF.

[0061] More specifically, when the negative current detection circuit 62 detects that the output voltage OUT is lower than the ground voltage GND, it applies the output voltage OUT to the application terminal of the reference voltage GND_REF (=P-type well P / W). On the other hand, when the negative current detection circuit 62 detects that the output voltage OUT is higher than the ground voltage GND, it applies the ground voltage GND to the application terminal of the reference voltage GND_REF (=P-type well P / W).

[0062] For example, when the output current Io flows in the negative direction and the output voltage OUT becomes a negative voltage (-Vf), the output voltage OUT is applied to the application terminal of the reference voltage GND_REF. That is, the N-type semiconductor substrate N-SUB and the P-type well P / W become the same voltage. Therefore, malfunction of parasitic elements associated with the semiconductor device 1 is prevented. As a result, a drop in the power supply voltage VDD and latch-up can be suppressed. In particular, since the transition from the second phase (FIG. 3) to the third phase (FIG. 4) is less likely to be hindered, power consumption (heat generation) can be kept low.

[0063] In the following, a number of operating states of the negative current detection circuit 62 will be listed and each will be specifically described.

[0064] 6 is a diagram showing a first operation state (ON sequence & positive current) of the negative current detection circuit 62. In the first operation state, the power transistor 10 is in an ON state, and the output current Io flows in a positive direction (=direction from the drain to the source of the power transistor 10). At this time, the output voltage OUT becomes a positive voltage (=Io×Ron) determined according to the output current Io and the on-resistance Ron of the power transistor 10. The first operation state in this figure corresponds to the transistor M4 in the first to third phases (FIGS. 2 to 4) described above.

[0065] When the external enable signal EN is at a high level (i.e., when the inverted external enable signal ENB is at a low level), the transistor P1 is turned on. Therefore, the node voltage VA is at a high level (≒ VDD), and the transistor N1 is turned on. As a result, the output voltage OUT is applied to the non-inverting input terminal (+) of the comparator CMP as the output detection voltage Vs.

[0066] As described above, in the first operating state, the output voltage OUT becomes a positive voltage (=Io×Ron) higher than the ground voltage GND, so the negative current detection signal DET becomes high level. At this time, the transistor P2 becomes off, and the transistors N2 and N3 are both on. Therefore, the node voltage VB becomes low level (≒GND), so the transistor N4 becomes off. As a result, the reference voltage GND_REF becomes the same voltage as the ground voltage GND.

[0067] In addition, the output detection voltage Vs in the first operating state is on the order of several tens to several hundreds of mV. Therefore, it is desirable for the comparator CMP to have a low offset.

[0068] Furthermore, it is preferable to appropriately set the resistance value of each of the resistors R1 to R3 so that the output detection voltage Vs is reliably higher than the ground voltage GND even if the output voltage OUT is close to the ground voltage GND.

[0069] 7 is a diagram showing the second operation state (ON sequence & negative current) of the negative current detection circuit 62. In the second operation state, the power transistor 10 is in the ON state, and the output current Io flows in the negative direction (=direction from the source to the drain of the power transistor 10). At this time, the output voltage OUT becomes a negative voltage (=-Io×Ron) determined according to the output current Io and the ON resistance Ron of the power transistor 10. The second operation state in this figure corresponds to the transistor M2 in the third phase (FIG. 4) described above.

[0070] In the second operating state, the output voltage OUT becomes a negative voltage (=-Io×Ron) lower than the ground voltage GND, so the negative current detection signal DET becomes low level. At this time, the transistor P2 becomes on, and the transistors N2 and N3 are both off. Therefore, the node voltage VB becomes high level (≒VDD), so the transistor N4 becomes on. As a result, the reference voltage GND_REF becomes the same voltage as the output voltage OUT.

[0071] In addition, the output detection voltage Vs in the second operating state is on the order of minus several tens to several hundreds of mV. Therefore, it is desirable for the comparator CMP to have a low offset.

[0072] 8 is a diagram showing the third operating state (OFF sequence) of the negative current detection circuit 62. In the third operating state, the power transistor 10 is in an OFF state, and the output current Io does not flow in either the positive or negative direction. At this time, the output voltage OUT rises to near the battery voltage VBAT via an upper switch (e.g., transistor M1 or M3) forming a half-bridge type switch output stage. The third operating state in this figure corresponds to the transistor M2 in the first phase (FIG. 2) described above.

[0073] In the third operating state, the output detection voltage Vs is clamped to a positive voltage (≒ VDD-Vgs) that is lower than the node voltage VA by the gate-source voltage Vgs of transistor N1, so the negative current detection signal DET goes to high level. At this time, transistor P2 goes to the off state, and transistors N2 and N3 both go to the on state. Therefore, the node voltage VB goes to a low level (≒ GND), so transistor N4 goes to the off state. As a result, the reference voltage GND_REF becomes the same voltage as the ground voltage GND.

[0074] 9 is a diagram showing the fourth operation state (OFF sequence & negative current) of the negative current detection circuit 62. In the fourth operation state, the power transistor 10 is in the off state, and the output current Io flows in the negative direction (=direction from the anode to the cathode of the body diode BD associated with the power transistor 10). At this time, the output voltage OUT becomes a negative voltage (=-Vf) determined according to the forward drop voltage Vf of the body diode BD. The fourth operation state in this figure corresponds to the transistor M2 in the second phase (FIG. 3) described above.

[0075] In the fourth operating state, the output voltage OUT becomes a negative voltage (=-Vf) lower than the ground voltage GND, so the negative current detection signal DET becomes low level. At this time, the transistor P2 becomes on, and the transistors N2 and N3 are both off. Therefore, the node voltage VB becomes high level (≒VDD), so the transistor N4 becomes on. As a result, the reference voltage GND_REF becomes the same voltage as the output voltage OUT.

[0076] <Behavior when negative current occurs> 10 is a diagram showing the behavior when a negative current occurs (particularly, the behavior when it is assumed that the negative current detection circuit 62 is not provided). In this diagram, from the top, the behaviors of the external enable signal EN, the inverted external enable signal ENB, the output voltage OUT, and the reference voltage GND_REF are depicted.

[0077] As shown in this figure, if it is assumed that the negative current detection circuit 62 is not provided, even if the output voltage OUT becomes a negative voltage (-Vf), the reference voltage GND_REF remains at the ground voltage GND. Therefore, as described above, malfunction of the parasitic elements associated with the semiconductor device 1 may occur.

[0078] 11 is a diagram showing a vertical cross section of the semiconductor device 1 (a diagram for explaining behavior on the assumption that the negative current detection circuit 62 is not provided). The semiconductor device 1 includes an N-type semiconductor substrate 201. An N-type epitaxial layer 202 is formed on the N-type semiconductor substrate 201. Various circuit elements are formed in the N-type epitaxial layer 202. With reference to this diagram, a power transistor 10 (e.g., a VDMOSFET) and a transistor Nx (e.g., an NMOSFET) are formed in the N-type epitaxial layer 202.

[0079] First, the description will focus on the element structure of the power transistor 10. In the formation region of the power transistor 10, a plurality of trench gates 203 are formed at predetermined intervals in an N-type epitaxial layer 202. In addition, an N-type drift region 204 is embedded in the N-type epitaxial layer 202 so as to surround each of the plurality of trench gates 203.

[0080] An N-type body region 205 is formed above the N-type drift region 204. A high-concentration P-type region 206 and a high-concentration N-type region 207 are formed in the N-type body region 205. The region in which the power transistor 10 is formed is surrounded by an element isolation region 208.

[0081] The high-concentration P-type region 206, the high-concentration N-type region 207, and the element isolation region 208 are each electrically connected to a metal wiring 210 through a via 209. The metal wiring 210 is connected to an application terminal of a ground voltage GND as the source (or backgate) of the power transistor 10. On the other hand, the N-type semiconductor substrate 201 is connected to an application terminal of an output voltage OUT as the drain of the power transistor 10.

[0082] Next, the element structure of the transistor Nx will be described. In the formation region of the transistor Nx, a high-voltage P-type well 211 is buried in the N-type epitaxial layer 202. A low-voltage P-type well 212 is formed above the high-voltage P-type well 211, and is wider in the lateral direction than the high-voltage P-type well 211 and extends to the surface of the N-type epitaxial layer 202.

[0083] High-concentration N-type regions 213a and 213b (corresponding to a drain region and a source region) are formed at a predetermined channel length apart in the low-withstand voltage P-type well 212. In addition, a high-concentration P-type region 214 (corresponding to a backgate contact) is formed along the outer edge of the low-withstand voltage P-type well 212.

[0084] A gate insulating layer 215 is formed on an upper layer of a channel region separating the high concentration N-type regions 213a and 213b. The formation region of the transistor Nx is surrounded by an element isolation region 216.

[0085] The high concentration P-type region 214 and the element isolation region 216 are each electrically connected to a metal wiring 218 through a via 217. The metal wiring 218 is connected to the application terminal of the ground voltage GND through a resistor R4 as the back gate (=the application terminal of the reference voltage GND_REF) of the transistor Nx.

[0086] The high-concentration N-type region 213a is electrically connected to a metal wiring 219 through a via 217. The metal wiring 219 corresponds to the drain of the transistor Nx. The gate insulating layer 215 is electrically connected to a metal wiring 220 through a via 217. The metal wiring 220 corresponds to the gate of the transistor Nx. The high-concentration N-type region 213b is electrically connected to a metal wiring 221 through a via 217. The metal wiring 221 corresponds to the source of the transistor Nx, and is connected to an application terminal of a ground voltage GND.

[0087] The surface of the N-type epitaxial layer 202 is covered with a protective layer 222 except for the region where the via 217 is formed.

[0088] Incidentally, the power transistor 10 having the above-described element structure is accompanied by a body diode BD with the high-concentration P-type region 206 as the anode and the N-type semiconductor substrate 201 and the N-type epitaxial layer 202 as the cathode. Also, the transistor Nx is accompanied by a parasitic transistor Q1 (= npn bipolar transistor) having the high-concentration N-type region 213a as the collector, the N-type semiconductor substrate 201 and the N-type epitaxial layer 202 as the emitter, and the high-concentration P-type region 214, the low-breakdown-voltage P-type well 212, and the high-breakdown-voltage P-type well 211 as the base.

[0089] Here, consider the case where the body diode BD of the power transistor 10 is in the forward bias state and an output current Io in the negative direction (the direction from the applied end of the ground voltage GND toward the N-type semiconductor substrate 201) flows through the body diode BD. In this case, the output voltage OUT applied to the emitter of the parasitic transistor Q1 becomes a negative voltage (-Vf < GND). On the other hand, the reference voltage GND_REF applied to the base of the parasitic transistor Q1 is maintained at the ground voltage GND. As a result, the parasitic transistor Q1 may be turned on.

[0090] FIG. 12 is a diagram showing the behavior when a negative current occurs (the behavior when the negative current detection circuit 62 is provided). In this figure, as in the above-described FIG. 10, the behaviors of the external enable signal EN, the inverted external enable signal ENB, the output voltage OUT, and the reference voltage GND_REF are depicted in order from the top.

[0091] As shown in this figure, when the negative current detection circuit 62 is provided, when the output voltage OUT becomes a negative voltage (-Vf), the reference voltage GND_REF becomes the same voltage as the output voltage OUT. Therefore, the parasitic elements associated with the semiconductor device 1 are less likely to malfunction.

[0092] FIG. 13 is a diagram showing a longitudinal cross-section of the semiconductor device 1 (a diagram for explaining the behavior when the negative current detection circuit 62 is provided). In this figure, while based on the above-described FIG. 11, a transistor N4 provided between the applied end of the output voltage OUT and the applied end of the reference voltage GND_REF is clearly shown.

[0093] When the output current Io flows in the negative direction and the output voltage OUT becomes a negative voltage (-Vf), the negative current detection circuit 62 turns on the transistor N4. As a result, the reference voltage GND_REF becomes the same voltage as the output voltage OUT. Therefore, the base-emitter voltage of the parasitic transistor Q1 (=GND_REF-OUT) becomes 0. As a result, the parasitic transistor Q1 can be prevented from being erroneously turned on.

[0094] <Considerations on Output Leakage Current Characteristics of Negative Current Detection Circuit (First Embodiment)> Incidentally, it is desirable for the negative current detection circuit 62 to suppress the output leakage current Io_leak (to make Io_leak ≈ 0 μA) when the output voltage OUT is 0 V or higher. The output leakage current Io_leak can be defined as a current flowing through the external terminal T4 when the output of the semiconductor device 1 is off, that is, when the power transistor 10 is in an off state (standby state).

[0095] However, in the negative current detection circuit 62 of the first embodiment, there is room for consideration regarding the output leakage current characteristics.

[0096] 14 is a diagram showing the behavior (first leak condition) when the output is off in the negative current detection circuit 62 of the first embodiment. Note that the first leak condition can be assumed to be a case in which the battery voltage VBAT (≈ output voltage OUT) is higher than a differential voltage VDD-Vth obtained by subtracting the on-threshold voltage Vth of the transistor N1 from the power supply voltage VDD (VBAT≈OUT>VDD-Vth).

[0097] When the first leakage condition is satisfied, as indicated by the arrow in the figure, a positive output leakage current Io_leak can flow from the application terminal of the output voltage OUT to the ground terminal via the transistor N1 and the resistor R3.

[0098] At this time, if the transistor N1 is in the OFF state, no output leakage current Io_leak flows. The transistor N1 enters the OFF state when the gate-source voltage Vgs is lower than the ON threshold voltage Vth.

[0099] Here, when the first leakage condition is satisfied, among the two main electrodes provided in the transistor N1, the one connected to the applied end of the output detection voltage Vs functions as the source. That is, the gate-source voltage Vgs of the transistor N1 is expressed by the following equation (1).

[0100] Vgs = VA - Vs … (1)

[0101] Note that VA ≒ VDD. Also, Vs = VA × R3 / (R1 + R2 + R3). Therefore, the above equation (1) can be rewritten as the following equation (2).

[0102] Vgs ≒ VDD × (R1 + R2) / (R1 + R2 + R3) … (2)

[0103] As can be seen from the above equation (2), in order to make the transistor N1 in the OFF state (Vgs < Vth), it is necessary to satisfy (R1 + R2) << R3. Therefore, in order to suppress the positive output leakage current Io_leak (Io_leak ≒ 0 μA), it is necessary to make R1 + R2 a relatively smaller value than R3. That is, the smaller R1 + R2 is, the better the positive output leakage current characteristics become.

[0104] FIG. 15 is a diagram showing the relationship between the output voltage OUT and the output leakage current Io_leak in the first embodiment (first leakage condition: VBAT ≒ OUT > VDD - Vth).

[0105] When R1 + R2 is small, the gate-source voltage Vgs of transistor N1 decreases, so transistor N1 is likely to turn off (the on-resistance value increases). Therefore, as shown by the solid line in this figure, the positive output leakage current Io_leak can be suppressed (Io_leak ≈ 0 μA). Thus, when R1 + R2 is small, the positive output leakage current characteristics are good.

[0106] On the other hand, when R1 + R2 is large, the gate-source voltage Vgs of transistor N1 increases, so transistor N1 is not likely to turn off (the on-resistance value decreases). Therefore, as shown by the dashed line in this figure, the positive output leakage current Io_leak can increase according to the output voltage OUT. Thus, when R1 + R2 is large, the positive output leakage current characteristics deteriorate.

[0107] FIG. 16 is a diagram showing the behavior at the time of output off (second leakage condition) in the negative current detection circuit 62 of the first embodiment. As the second leakage condition, a case where the battery voltage VBAT (≈ output voltage OUT) is lower than the differential voltage VDD - Vth obtained by subtracting the on-threshold voltage Vth of transistor N1 from the power supply voltage VDD (VBAT ≈ OUT < VDD - Vth) can be assumed.

[0108] When the second leakage condition is satisfied, among the two main electrodes provided in transistor N1, the one connected to the applied end of the output voltage OUT functions as the source. That is, the gate-source voltage Vgs of transistor N1 is expressed by the following equation (3).

[0109] Vgs = VA - OUT … (3)

[0110] Note that VA ≈ VDD. Therefore, when the second leakage condition is satisfied, transistor N1 can be in an on state (Vgs > Vth). Therefore, as indicated by the arrow in the figure, a negative output leakage current Io_leak can flow from the applied end of the power supply voltage VDD through transistor P1, resistors R1 and R2, and transistor N1 to the applied end of the output voltage OUT.

[0111] Here, the negative-direction output leakage current Io_leak is represented by the following equation (4).

[0112] Io_leak ≒ (VDD - Vs) / (R1 + R2) … (4)

[0113] Also, since the transistor N1 is in the on state, Vs ≒ OUT. Therefore, the above equation (4) can be rewritten as the following equation (5).

[0114] Io_leak ≒ (VDD - OUT) / (R1 + R2) … (5)

[0115] As can be seen from the above equation (5), the larger R1 + R2 is, the more the negative-direction output leakage current Io_leak is suppressed (Io_leak ≒ 0 μA). That is, the larger R1 + R2 is, the better the output leakage current characteristics become.

[0116] FIG. 17 is a diagram showing the relationship between the output voltage OUT and the output leakage current Io_leak in the first embodiment (second leakage condition: VBAT ≒ OUT < VDD - Vth).

[0117] When R1 + R2 is large, as shown by the solid line in this figure, the negative-direction output leakage current Io_leak is suppressed (Io_leak ≒ 0 μA). Thus, when R1 + R2 is large, the negative-direction output leakage current characteristics become good.

[0118] On the other hand, when R1 + R2 is small, as shown by the broken line in this figure, the negative-direction output leakage current Io_leak can increase according to the output voltage OUT (deviate from 0 μA). That is, when R1 + R2 is small, the negative-direction output leakage current characteristics deteriorate.

[0119] FIG. 18 is a diagram showing the output leakage current characteristics in the negative current detection circuit 62 of the first embodiment. This figure can be understood as a superposition of the above-mentioned FIGS. 15 and 17.

[0120] When R1+R2 is small, the positive output leakage current characteristics are good but the negative output leakage current characteristics are poor, as shown by the solid line in this figure. On the other hand, when R1+R2 is large, the negative output leakage current characteristics are good but the positive output leakage current characteristics are poor, as shown by the dashed line in this figure. In other words, there is a trade-off between the positive output leakage current characteristics and the negative output leakage current characteristics.

[0121] As described above, in the negative current detection circuit 62 of the first embodiment, the quality of the output leakage current characteristic changes with OUT=VDD-Vth as the boundary no matter what value R1+R2 is set to. Therefore, it is difficult to achieve the goal of suppressing the output leakage current Io_leak (Io_leak≈0 μA) when the output voltage OUT is 0 V or higher.

[0122] In view of the above considerations, a second embodiment capable of achieving good output leakage current characteristics in both positive and negative directions will be proposed below.

[0123] <Negative current detection circuit (second embodiment)> 19 is a diagram showing a second embodiment of a negative current detection circuit 62. The negative current detection circuit 62 of this embodiment is based on the first embodiment (FIG. 5) described above, with some modifications to the circuit configuration. In the following description, the same reference numerals as in FIG. 5 are used for the components already described. Duplicate descriptions of the components already described may be omitted.

[0124] The negative current detection circuit 62 of this embodiment includes a detection signal generation circuit 62a, a reference voltage control circuit 62b, a transistor N4 (for example, an NMOSFET), and a resistor R4. The transistor N4 may be a VDMOSFET.

[0125] The detection signal generating circuit 62a detects that the output voltage OUT appearing at the external terminal T4 is lower than the ground voltage GND (or a predetermined threshold voltage) applied to the external terminal T7, and generates a negative current detection signal DET. Referring to this figure, the detection signal generating circuit 62a includes a bias circuit BIAS and a clamp circuit CLP in addition to the comparator CMP already described.

[0126] As explained above, the comparator CMP compares the output detection voltage Vs input to the non-inverting input terminal (+) with the ground voltage GND (or a predetermined threshold voltage VTH) input to the inverting input terminal (-) to generate the negative current detection signal DET. In accordance with this figure, the negative current detection signal DET is at a high level when Vs>GND, and <GNDであるときにローレベルとなる。なお、コンパレータCMPは、ヒステリシスコンパレータであってもよい。

[0127] The bias circuit BIAS switches between applying the output voltage OUT or a bias voltage (≈VA-Vth≈VDD-Vth) as the output detection voltage Vs. Referring to the figure, the bias circuit BIAS includes a transistor N5 (e.g., an NMOSFET) and resistors R5 and R6. The transistor N5 may be a VDMOSFET.

[0128] The drain of the transistor N5 is connected to the external terminal T4 (=output terminal). The source of the transistor N5 is connected to the first terminal of the resistor R5. The second terminal of the resistor R5 is connected to the application terminal of the output detection voltage Vs. The first terminal of the resistor R6 is connected to the external terminal T1 (=application terminal of the power supply voltage VDD). The second terminal of the resistor R6 is connected to the gate of the transistor N5.

[0129] The resistor R5 corresponds to a first resistor connected between the source of the transistor N5 and the application terminal of the output detection voltage Vs. The resistor R6 corresponds to a second resistor connected between the gate of the transistor N5 and the external terminal T1 (=the application terminal of the power supply voltage VDD). The resistors R5 and R6 function as ESD [electro-static discharge] protection elements for protecting the non-inverting input terminal (+) of the comparator CMP and the gate of the transistor N5, respectively.

[0130] The clamp circuit CLP operates when the absolute value of the output detection voltage Vs is higher than the clamp operation voltage VCLP. Therefore, the output detection voltage Vs has an upper limit in the positive direction limited to +VCLP and an upper limit in the negative direction limited to -VCLP. In other words, the clamp operation voltage VCLP can be understood as the upper limit of the positive and negative values ​​of the output detection voltage Vs. Referring to this figure, the clamp circuit CLP includes diodes D1 and D2.

[0131] The cathode of the diode D1 is connected to the application terminal of the output detection voltage Vs. The anode of the diode D1 is connected to the anode of the diode D2. The cathode of the diode D2 is connected to the external terminal T7 (=ground terminal). A plurality of diodes D1 and D2 may be provided in a vertical row.

[0132] The diode D1 corresponds to at least one first diode connected with a first polarity between the application terminal of the output detection voltage Vs and the external terminal T7 (=ground terminal). The diode D2 corresponds to at least one second diode connected with a second polarity opposite to the first polarity between the application terminal of the output detection voltage Vs and the external terminal T7 (=ground terminal).

[0133] The clamp operation voltage VCLP is desirably higher than a differential voltage VA-Vth (≈VDD-Vth) obtained by subtracting the on-threshold voltage Vth of the transistor N5 from the node voltage VA applied to the gate of the transistor N5 (details will be described later).

[0134] The reference voltage control circuit 62b switches the node voltage VB applied to the gate of the transistor N4 between high and low levels in response to the negative current detection signal DET. In this way, the reference voltage control circuit 62b switches between applying the ground voltage GND or the output voltage OUT to the application terminal (=P-type well P / W) of the reference voltage GND_REF. Although not explicitly shown in this figure, the reference voltage control circuit 62b may include, for example, the aforementioned transistors P2, N2, and N3 (FIG. 5).

[0135] The negative current detection circuit 62 of this embodiment, like the first embodiment (FIG. 5), applies the output voltage OUT to the application terminal of the reference voltage GND_REF (=P-type well P / W) when it detects that the output voltage OUT is lower than the ground voltage GND. On the other hand, the negative current detection circuit 62 applies the ground voltage GND to the application terminal of the reference voltage GND_REF (=P-type well P / W) when it detects that the output voltage OUT is higher than the ground voltage GND.

[0136] For example, when the output current Io flows in the negative direction and the output voltage OUT becomes a negative voltage (=-Io×Ron or -Vf), the output detection voltage Vs (≒OUT) becomes lower than the ground voltage GND. Therefore, the negative current detection signal DET becomes low level. At this time, the reference voltage control circuit 62b turns on the transistor N4. As a result, the output voltage OUT is applied to the application terminal of the reference voltage GND_REF.

[0137] That is, the N-type semiconductor substrate N-SUB and the P-type well P / W are at the same voltage. Therefore, malfunction of parasitic elements associated with the semiconductor device 1 is prevented. As a result, a drop in the power supply voltage VDD and latch-up can be suppressed. In particular, since there is less likely to be a disruption in the transition from the second phase (FIG. 3) to the third phase (FIG. 4), power consumption (heat generation) can be kept low.

[0138] Also, when the output current Io flows in the positive direction and the output voltage OUT becomes a positive voltage (=Io×Ron), the output detection voltage Vs (≒OUT) becomes higher than the ground voltage GND. Therefore, the negative current detection signal DET becomes high level. At this time, the reference voltage control circuit 62b turns off the transistor N4. As a result, the application terminal of the reference voltage GND_REF is pulled down to the external terminal T7 via the resistor R4. That is, the reference voltage GND_REF becomes the same voltage as the ground voltage GND.

[0139] <Considerations on Output Leakage Current Characteristics of Negative Current Detection Circuit (Second Embodiment)> FIG. 20 is a diagram showing the behavior of the negative current detection circuit 62 of the second embodiment when the output is off (first leakage condition: VBAT≈OUT>VDD-Vth).

[0140] When the first leakage condition is satisfied, as shown by the arrow in the figure, a positive output leakage current Io_leak can flow from external terminal T4 (= the application terminal of output voltage OUT) through transistor N5, resistor R5, diodes D1 and D2 toward external terminal T7 (= the application terminal of ground voltage GND).

[0141] When the first leak condition is satisfied, the transistor N5 has two main electrodes, and the one connected to the first end of the resistor R5 functions as the source. At this time, the bias circuit BIAS operates so that the upper limit of the output detection voltage Vs is VA-Vth (≈VDD-Vth).

[0142] Therefore, when VCLP>VDD-Vth, the clamp circuit CLP does not operate. In other words, the clamp circuit CLP does not become a path for conducting the positive output leakage current Io_leak. Therefore, the positive output leakage current Io_leak is suppressed (Io_leak≈0μA). In other words, the positive output leakage current characteristics are improved.

[0143] FIG. 21 is a diagram showing the relationship between the output voltage OUT and the output leakage current Io_leak in the negative current detection circuit 62 of the second embodiment (first leakage condition: VBAT ≒ OUT > VDD - Vth).

[0144] When VCLP > VDD - Vth, as described above, the clamp circuit CLP does not operate. Therefore, as shown by the solid line in this figure, the positive output leakage current Io_leak is suppressed (Io_leak ≒ 0 μA). Thus, when VCLP > VDD - Vth, the positive output leakage current characteristics are good.

[0145] On the other hand, when VCLP < VDD - Vth, the clamp circuit CLP operates. In other words, the clamp circuit CLP becomes a path for conducting the positive output leakage current Io_leak. Therefore, as shown by the broken line in this figure, the positive output leakage current Io_leak can increase according to the output voltage OUT. Thus, when VCLP < VDD - Vth, the positive output leakage current characteristics deteriorate.

[0146] FIG. 22 is a diagram showing the behavior at the time of output off in the negative current detection circuit 62 of the second embodiment (second leakage condition: VBAT ≒ OUT < VDD - Vth).

[0147] When the second leakage condition is satisfied, of the two main electrodes provided in the transistor N5, the one connected to the external terminal T4 (= the applied end of the output voltage OUT) functions as the source. Therefore, the transistor N5 can be in an on state (Vgs > Vth). As shown by the arrow in the figure, a negative output leakage current Io_leak can flow from the external terminal T7 (= the applied end of the ground voltage GND) through the diodes D2 and D1, the resistor R5, and the transistor N5 to the external terminal T4 (= the applied end of the output voltage OUT).

[0148] However, the clamp circuit CLP does not operate unless the output detection voltage Vs (≒OUT≒VBAT) drops to a negative voltage (-VCLP) that is lower than the ground voltage GND by the clamp operation voltage VCLP. Here, the minimum value of the battery voltage VBAT is 0V. Therefore, the clamp circuit CLP never operates. In other words, the clamp circuit CLP does not provide a path for the negative output leakage current Io_leak to conduct. Therefore, the negative output leakage current Io_leak does not flow.

[0149] FIG. 23 is a diagram showing the relationship between the output voltage OUT and the output leakage current Io_leak in the negative current detection circuit 62 of the second embodiment (second leakage condition: VBAT≒OUT<VDD-Vth).

[0150] As described above, under the second leakage condition, the clamp circuit CLP does not operate even when the battery voltage VBAT is at its minimum value (0V). Therefore, as shown by the solid line and the broken line in this figure, regardless of the relationship between the clamp operation voltage VCLP and the differential voltage VDD-Vth, the negative output leakage current Io_leak does not flow. That is, the negative output leakage current characteristics are always good.

[0151] FIG. 24 is a diagram showing the output leakage current characteristics of the negative current detection circuit 62 of the second embodiment. This figure can be understood as a superposition of the previously shown FIGS. 21 and 23. As shown by the solid line in this figure, when VCLP>VDD-Vth, the output leakage current characteristics in both positive and negative directions are good.

[0152] FIG. 25 is a diagram showing the improvement effect of the output leakage current characteristics. In this figure, as the output leakage current characteristics of the second embodiment, the solid line (VCP>VDD-Vth) in FIG. 24 is depicted as the solid line. Also, in this figure, as the output leakage current characteristics of the first embodiment, the solid line (R1+R2: small) in FIG. 18 is depicted as the broken line.

[0153] As is clear from a comparison between the solid line and the dashed line, the negative current detection circuit 62 of this embodiment, unlike the first embodiment (FIG. 18), does not change the quality of the output leakage current characteristics at the boundary of OUT=VDD-Vth. Therefore, as long as the clamp operation voltage VCLP is appropriately set, the goal of suppressing the output leakage current Io_leak (Io_leak≈0 μA) when the output voltage OUT is 0 V or higher can be achieved.

[0154] <Application to vehicles> 26 is a diagram showing the external appearance of a vehicle X. The vehicle X of this configuration example is equipped with various electronic devices that operate by receiving power supply from a battery.

[0155] The vehicle X includes not only engine vehicles but also electric vehicles (xEVs such as BEVs (battery electric vehicles), HEVs (hybrid electric vehicles), PHEVs / PHVs (plug-in hybrid electric vehicles / plug-in hybrid vehicles), or FCEVs / FCVs (fuel cell electric vehicles / fuel cell vehicles)).

[0156] The semiconductor device 1 described above can be incorporated into any of the electronic devices mounted on the vehicle X.

[0157] <Additional Notes> The following is a supplementary note regarding the above disclosure: According to the present disclosure, it is possible to prevent malfunction of a parasitic element.

[0158] (Appendix 1) A semiconductor substrate of a first conductivity type (N-SUB); A well (P / W) of a second conductivity type different from the first conductivity type formed in the semiconductor substrate (N-SUB); an output terminal (T4) configured to be electrically connected to the semiconductor substrate (N-SUB); A ground terminal (T7) configured to apply a ground voltage (GND); a detection signal generating circuit (62a) configured to detect that the output voltage (OUT) appearing at the output terminal (T4) is lower than the ground voltage (GND) or a threshold voltage and generate a negative current detection signal (DET); a control circuit (62b) configured to switch between applying the ground voltage (GND) or the output voltage (OUT) to the well (P / W) in response to the negative current detection signal (DET); Equipped with The detection signal generating circuit (62a) a comparator (CMP) configured to compare an output detection voltage (Vs) with the ground voltage (GND) or the threshold voltage to generate the negative current detection signal (DET); a bias circuit (BIAS) configured to switch between applying the output voltage (OUT) or a bias voltage (VA-Vth) as the output detection voltage (Vs); a clamp circuit (CLP) configured to operate when the absolute value of the output detection voltage (Vs) is higher than a clamp operation voltage (VCLP); A semiconductor device (1).

[0159] (Appendix 2) The semiconductor device (1) described in Appendix 1, wherein the clamp circuit (CLP) includes at least one first diode (D1) connected with a first polarity between the application terminal of the output detection voltage (Vs) and the ground terminal (T7), and at least one second diode (D2) connected with a second polarity opposite to the first polarity between the application terminal of the output detection voltage (Vs) and the ground terminal (T7).

[0160] (Appendix 3) The bias circuit (BIAS) includes a first transistor (N5) connected between the output terminal (T4) and an application terminal of the output detection voltage (Vs); The semiconductor device (1) described in Appendix 1 or 2, wherein the clamp operating voltage (VCLP) is higher than a differential voltage (VA-Vth) obtained by subtracting an on-threshold voltage (Vth) of the first transistor from a voltage (VA) applied to a control terminal of the first transistor (N5).

[0161] (Appendix 4) The semiconductor device (1) described in Appendix 3, wherein the bias circuit (BIAS) further includes a first resistor (R5) connected between the main electrode of the first transistor (N5) and the application terminal of the output detection voltage (Vs).

[0162] (Appendix 5) The semiconductor device (1) described in Appendix 4, wherein the bias circuit (BIAS) further includes a second resistor (R6) connected between a control terminal of the first transistor (N5) and an application terminal of a power supply voltage (VDD).

[0163] (Appendix 6) The control circuit (62b) a second transistor (N3) configured to connect / disconnect the well (P / W) and the ground terminal (T7) in response to the negative current detection signal (DET); a third resistor (R4) connected between the well (P / W) and the ground terminal (T7); The semiconductor device (1) according to any one of claims 1 to 5, further comprising:

[0164] (Appendix 7) The semiconductor device (1) according to any one of claims 1 to 6, further comprising a power transistor (10) configured to be connected between the output terminal (T4) and the ground terminal (T7).

[0165] (Appendix 8) An inductive load (Z), a half-bridge or full-bridge switch output stage (M1 to M4) configured to drive the load (Z); A semiconductor device (1) according to any one of appendices 1 to 7 configured to be a lower switch element (M2, M4) of the switch output stage (M1 to M4) or a drive means thereof; An electronic device (100) comprising:

[0166] (Appendix 9) 9. The electronic device (100) of claim 8, wherein the load (Z) includes a motor.

[0167] (Appendix 10) A vehicle (X) equipped with the electronic device (100) according to appendix 8 or 9.

[0168] <Other> In addition, various technical features disclosed in this specification can be modified in various ways without departing from the spirit of the technical creation, in addition to the above-mentioned embodiment. In other words, the above-mentioned embodiment should be considered to be illustrative and not restrictive in all respects. In addition, the technical scope of the present disclosure is defined by the claims, and should be understood to include all modifications that fall within the meaning and scope equivalent to the claims. [Explanation of symbols]

[0169] 1. Semiconductor device (Low-side switch LSI) 10 Power transistor (NMOSFET) 20 Sense transistor (NMOSFET) 30 Gate control system 31 Slew rate control circuit 32 Active clamp circuit 33 Gate resistor 34 Transistor (NMOSFET) 40 Logic 50 inputs 51 Input control circuit 52 Enable control circuit 53 UVLO circuit 60 reference system 61 Reference generation circuit 62 Negative current detection circuit 62a Detection signal generating circuit 62b Reference voltage control circuit 70 Protection system 71 Overcurrent protection circuit 72 Temperature protection circuit 73 Load open detection circuit 80 Status output section 91, 92 Current limiting resistor 100 Electronic equipment 201 N-type semiconductor substrate 202 N-type epitaxial layer 203 Trench Gate 204 N-type drift region 205 N-type body region 206 High concentration P type region 207 Highly concentrated N-type region 208 Element isolation region 209 Beer 210 Metal Wiring 211 High voltage P-well 212 Low voltage P-well 213a, 213b High concentration N type region 214 Highly concentrated P-type region 215 Gate Insulation Layer 216 Element isolation region 217 Beer 218, 219, 220, 221 Metal wiring 222 Protective layer BD Body diode CHG live part CMP Comparator D1, D2 Diodes DCHG discharge section E voltage source M1~M4 Transistors (NMOSFET) N1~N5, Nx transistors (NMOSFET) P1, P2 transistors (PMOSFET) Q1 Parasitic transistor (npn bipolar transistor) R1~R6 resistance REF Reference current source T1~T7 External terminals X Vehicle Z load

Claims

1. a semiconductor substrate of a first conductivity type; a well of a second conductivity type different from the first conductivity type formed in the semiconductor substrate; an output terminal configured to be in electrical conduction with the semiconductor substrate; A ground terminal configured to receive a ground voltage; a detection signal generating circuit configured to detect that an output voltage appearing at the output terminal is lower than the ground voltage or a threshold voltage and generate a negative current detection signal; a control circuit configured to switch between applying the ground voltage or the output voltage to the well in response to the negative current detection signal; Equipped with The detection signal generating circuit includes: a comparator configured to compare an output sense voltage with the ground voltage or the threshold voltage to generate the negative current sense signal; a bias circuit configured to switch between applying the output voltage or a bias voltage as the output detection voltage; a clamp circuit configured to operate when the absolute value of the output detection voltage is higher than a clamp operation voltage; A semiconductor device comprising:

2. 2. The semiconductor device according to claim 1, wherein the clamp circuit includes at least one first diode connected with a first polarity between the application terminal of the output detection voltage and the ground terminal, and at least one second diode connected with a second polarity opposite to the first polarity between the application terminal of the output detection voltage and the ground terminal.

3. the bias circuit includes a first transistor connected between the output terminal and an application terminal of the output detection voltage, 2 . The semiconductor device according to claim 1 , wherein the clamp operating voltage is higher than a difference voltage obtained by subtracting an on-threshold voltage of the first transistor from a voltage applied to a control end of the first transistor.

4. 4. The semiconductor device according to claim 3, wherein said bias circuit further includes a first resistor connected between a main electrode of said first transistor and an application terminal of said output detection voltage.

5. 5. The semiconductor device according to claim 4, wherein said bias circuit further includes a second resistor connected between a control terminal of said first transistor and a terminal to which a power supply voltage is applied.

6. a second transistor configured to establish / shut off conduction between the well and the ground terminal in response to the negative current detection signal; a third resistor connected between the well and the ground terminal; The semiconductor device according to claim 1 , further comprising:

7. The semiconductor device according to claim 1 , further comprising a power transistor configured to be connected between said output terminal and said ground terminal.

8. Inductive load, a half-bridge or full-bridge switched output stage configured to drive the load; The semiconductor device according to any one of claims 1 to 7, configured to be a lower switch element of the switch output stage or a driving means thereof; An electronic device comprising:

9. The electronic device of claim 8 , wherein the load includes a motor.

10. A vehicle comprising the electronic device according to claim 8.

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