Semiconductor device

Abstract

To improve the performance of a semiconductor device.SOLUTION: A semiconductor device of an embodiment includes a first electrode, a first oxide semiconductor, a first insulator, a first conductor, a first conducive oxide, a second conductive oxide, and a second conductor. The first oxide semiconductor has one end in contact with the first electrode and extends in a first direction that intersects with a surface of the first electrode. The first insulator surrounds a side surface of the first oxide semiconductor. The first conductor surrounds at least a part of a side surface of the first insulator in a top view. The first conducive oxide is in contact with the other end of the first oxide semiconductor. The second conductive oxide is located on the first conducive oxide. The second conductor is located on the second conductive oxide. The second conductive oxide and the second conductor include a first metallic element. The first conductive oxide and the second conductive oxide include oxygen.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The embodiments relate to a semiconductor device. [Background technology]

[0002] Semiconductor devices are used in a variety of electronic devices. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2011 / 0108834 Summary of the Invention [Problem to be solved by the invention]

[0004] The performance of the semiconductor device is improved. [Means for solving the problem]

[0005] A semiconductor device according to an embodiment includes a first electrode, a first oxide semiconductor, a first insulator, a first conductor, a first conductive oxide, a second conductive oxide, and a second conductor. One end of the first oxide semiconductor is in contact with the first electrode and extends in a first direction intersecting with a surface of the first electrode. The first insulator surrounds a side surface of the first oxide semiconductor. The first conductor surrounds at least a portion of the side surface of the first insulator in a top view. The first conductive oxide is in contact with the other end of the first oxide semiconductor. The second conductive oxide is located on the first conductive oxide. The second conductor is located on the second conductive oxide. The second conductive oxide and the second conductor contain a first metal element. The first conductive oxide and the second conductive oxide contain oxygen. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 shows a cross-sectional view of a configuration example of a semiconductor device 100 according to the first embodiment. [Diagram 2]FIG. 2 is a plan view showing an example of a planar layout of the semiconductor device 100 according to the first embodiment. [Diagram 3] FIG. 3 shows a cross-sectional view taken along line III-III in FIG. 2, which is an example of the cross-sectional structure of the semiconductor device 100 according to the first embodiment. [Figure 4] FIG. 4 shows a cross-sectional view taken along line IV-IV in FIG. 2, which is an example of the cross-sectional structure of the semiconductor device 100 according to the first embodiment. [Diagram 5] FIG. 5 shows a cross-sectional view taken along line VV in FIG. 3, which is an example of the cross-sectional structure of the semiconductor device 100 according to the first embodiment. [Figure 6] FIG. 6 shows a flowchart of an example of a manufacturing process for the semiconductor device 100 according to the first embodiment. [Figure 7] FIG. 7 shows an example of a cross-sectional structure of the semiconductor device 100 according to the first embodiment during its manufacture. [Figure 8] FIG. 8 shows an example of a cross-sectional structure of the semiconductor device 100 according to the first embodiment during its manufacture. [Figure 9] FIG. 9 shows an example of a cross-sectional structure of the semiconductor device 100 according to the first embodiment during its manufacture. [Figure 10] FIG. 10 shows an example of a cross-sectional structure of the semiconductor device 100 according to the first embodiment during its manufacture. [Figure 11] FIG. 11 shows an example of a cross-sectional structure of the semiconductor device 100 according to the first embodiment during its manufacture. [Figure 12] FIG. 12 shows an example of a cross-sectional structure of the semiconductor device 100 according to the first embodiment during its manufacture. [Figure 13] FIG. 13 shows an example of a cross-sectional structure of the semiconductor device 100 according to the first embodiment during its manufacture. [Figure 14] FIG. 14 shows an example of a cross-sectional structure of the semiconductor device 100 according to the first embodiment during its manufacture. [Figure 15] FIG. 15 shows an example of a cross-sectional structure of the semiconductor device 100 according to the first embodiment during its manufacture. [Figure 16] FIG. 16 shows an example of a cross-sectional structure of a semiconductor device 100 according to a first modification of the first embodiment. [Figure 17] FIG. 17 shows an example of a cross-sectional structure of a semiconductor device 100b according to the second embodiment. [Figure 18] FIG. 18 is a flowchart showing an example of a manufacturing process for the semiconductor device 100b according to the second embodiment. [Figure 19] FIG. 19 shows an example of a cross-sectional structure of a semiconductor device 100b according to the second embodiment during its manufacture. [Figure 20] FIG. 20 shows an example of a cross-sectional structure of a semiconductor device 100b according to a first modification of the second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, embodiments will be described with reference to the drawings. In the following description, components having substantially the same functions and configurations are given the same reference numerals, and repeated explanations may be omitted. In order to distinguish a plurality of components having substantially the same functions and configurations from one another, additional numbers or letters may be added to the end of the reference numerals.

[0008] The drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, etc. may differ from the actual ones. Therefore, the specific thickness and dimensions should be determined by taking into consideration the following explanation. In addition, the drawings may include parts in which the dimensional relationships and ratios differ from each other. In addition, all descriptions of one embodiment also apply to descriptions of another embodiment, unless explicitly or obviously excluded. Each embodiment is an example of an apparatus or method for embodying the technical idea of ​​this embodiment, and the technical idea of ​​the embodiment does not specify the material, shape, structure, arrangement, etc. of the components as described below.

[0009] In this specification, the terms "substantially the same," "approximately the same," "approximately uniform," and "approximately consistent" refer to something that is intended to be the same, but is not completely identical due to limitations in manufacturing technology and / or measurement technology, and allows for some error.

[0010] [1] First embodiment The semiconductor device 100 according to the first embodiment will be described below.

[0011] [1-1] Configuration (structure) An example of the structure of the semiconductor device 100 according to the first embodiment will be described below. In the following description, an orthogonal coordinate system consisting of an X-axis, a Y-axis, and a Z-axis is used. In the following description, the term "lower" and its derivatives and related terms refer to a position of a smaller coordinate on the Z-axis, and the term "upper" and its derivatives and related terms refer to a position of a larger coordinate on the Z-axis. Hatching is appropriately added to the plan view to make the diagram easier to see. The hatching added to the plan view does not necessarily relate to the material or characteristics of the component to which the hatching is added. In the cross-sectional view, components such as an insulating layer (interlayer insulating film), a substrate SU, wiring, and contacts are appropriately omitted to make the diagram easier to see.

[0012] 1 is a cross-sectional view showing an example of the configuration of a semiconductor device 100 according to a first embodiment. As shown in FIG 1, the semiconductor device 100 includes a substrate SU, a capacitor CC, a lower electrode BE, a pillar PI, an upper electrode TE, a gate electrode GE, and a bit line BL.

[0013] The semiconductor substrate SUB is, for example, a silicon substrate.

[0014] The capacitor CC is, for example, a capacitive element. The capacitor CC is, for example, provided above the substrate SU. The capacitor CC is, for example, columnar extending along the Z-axis. The capacitor CC is, for example, cylindrical. The capacitor CC includes, for example, a conductive material.

[0015] The bottom electrode BE is provided on the capacitor CC. The bottom electrode BE has, for example, a columnar shape.

[0016] The pillar PI is provided on the bottom electrode BE. The pillar PI has a columnar shape extending along the Z axis, for example.

[0017] The upper electrode TE is provided on the pillar PI. The upper electrode TE has, for example, a columnar shape.

[0018] The gate electrode GE is provided between the lower electrode BE and the upper electrode TE. The gate electrode GE is in contact with a side surface of the pillar PI. The gate electrode GE will be described in detail later.

[0019] The bit line BL is provided on the top electrode TE. The bit line BL extends along the Y-axis. The lower end of the pillar PI is electrically connected to the bottom electrode BE, and the upper end of the pillar PI is electrically connected to the top electrode TE. The upper end of the top electrode TE and the lower end of the bit line BL are electrically connected.

[0020] The combination of the lower electrode BE, gate electrode GE, pillar PI, and upper electrode TE functions as a transistor. The lower electrode BE and upper electrode TE each function as a source electrode or drain electrode of the transistor. The gate electrode GE functions as a gate electrode of the transistor. The pillar PI functions as a current path (channel) of the transistor. In this way, the combination of the lower electrode BE, gate electrode GE, pillar PI, and upper electrode TE may be referred to as a vertical transistor CT below, since a current flows between the lower electrode BE and the upper electrode TE via the pillar PI extending along the Z-axis.

[0021] The bottom electrode BE includes a first bottom electrode layer 11 and a second bottom electrode layer 12. The second bottom electrode layer 12 is, for example, cylindrical and is provided in the center of the bottom electrode BE. The top surface of the second bottom electrode layer 12 contacts the pillar PI as the top surface of the bottom electrode BE.

[0022] The second lower electrode layer 12 includes a material having electrical conductivity. The second lower electrode layer 12 includes, for example, a conductive oxide. The second lower electrode layer 12 is, for example, a conductive oxide layer.

[0023] The second lower electrode layer 12 includes, for example, indium (In), tin (Sn), and oxygen (O). The second lower electrode layer 12 includes, for example, indium tin oxide. The second lower electrode layer 12 is, for example, an indium tin oxide layer.

[0024] The second lower electrode layer 12 includes, for example, tin (Sn) and oxygen (O). The second lower electrode layer 12 includes, for example, tin oxide. The second lower electrode layer 12 is, for example, a tin oxide layer.

[0025] The first lower electrode layer 11 contacts the surface of the second lower electrode layer 12 except for the upper surface. That is, the first lower electrode layer 11 contacts the side and lower surface of the second lower electrode layer 12. The lower surface of the first lower electrode layer 11 contacts the upper surface of the capacitor CC. The first lower electrode layer 11 includes, for example, a third metal element. The first lower electrode layer 11 includes, for example, the third metal element and N. The first lower electrode layer 11 includes, for example, a nitride of the third metal element. The third metal element is, for example, Ti, Sn, Zn, Ru, or Nb. The first lower electrode layer 11 is, for example, titanium nitride (TiN).

[0026] By providing the second lower electrode layer 12 between an oxide semiconductor 30 described below and the first lower electrode layer 11, the contact resistance between the oxide semiconductor 30 and the first lower electrode layer 11 can be reduced.

[0027] The pillar PI includes an oxide semiconductor 30 and a first gate insulating film 31. The oxide semiconductor 30 is provided on the second lower electrode layer 12. The oxide semiconductor 30 extends along the Z axis and is provided in the center of the pillar PI. The oxide semiconductor 30 is provided, for example, in a cylindrical shape. The second lower electrode layer 12 is provided wider than the oxide semiconductor 30 in an XY plan view (top view) seen from the +Z side.

[0028] The oxide semiconductor 30 includes, for example, at least one element selected from the group consisting of indium (In), gallium (Ga), silicon (Si), aluminum (Al), and tin (Sn), zinc (Zn), and oxygen (O). The oxide semiconductor 30 includes, for example, indium (In), gallium (Ga), zinc (Zn), and oxygen (O). The oxide semiconductor 30 includes, for example, indium gallium zinc oxide. The oxide semiconductor 30 is, for example, an indium gallium zinc oxide layer.

[0029] The first gate insulating film 31 covers, for example, the periphery of the oxide semiconductor 30. The first gate insulating film 31 is provided, for example, in a cylindrical shape in the pillar PI. The first gate insulating film 31 includes, for example, an insulator such as silicon oxide.

[0030] The second gate insulating film 32 covers, for example, the periphery of the first gate insulating film 31. The second gate insulating film 32 is provided, for example, in a cylindrical shape in the pillar PI. The second gate insulating film 32 includes, for example, an insulator such as silicon nitride.

[0031] Either the first gate insulating film 31 or the second gate insulating film 32 may be omitted.

[0032] The upper electrode TE includes a first upper electrode layer 14 , a second upper electrode layer 15 , a third upper electrode layer 16 , and a fourth upper electrode layer 17 .

[0033] The first upper electrode layer 14 is provided on the oxide semiconductor 30. In other words, the first upper electrode layer 14 contacts the upper end of the oxide semiconductor 30. The first upper electrode layer 14 is provided wider than the oxide semiconductor 30 in the XY plan view (top view) seen from the +Z side. The first upper electrode layer 14 includes, for example, a conductive oxide. The first upper electrode layer 14 includes, for example, indium (In), tin (Sn), and oxygen (O). The first upper electrode layer 14 includes, for example, indium tin oxide. The first upper electrode layer 14 is, for example, an indium tin oxide layer.

[0034] The first upper electrode layer 14 includes, for example, tin (Sn) and oxygen (O). The first upper electrode layer 14 includes, for example, tin oxide. The first upper electrode layer 14 is, for example, a tin oxide layer.

[0035] The second upper electrode layer 15 is provided on the first upper electrode layer 14. The second upper electrode layer 15 includes, for example, a first metal element and O. The second upper electrode layer 15 includes, for example, an oxide of the first metal element. The second upper electrode layer 15 includes, for example, the first metal element, O, and the first element. The second upper electrode layer 15 includes, for example, a conductive oxide including the first metal element. The first metal element is, for example, Ti, Sn, Zn, Ru, or Nb. The first element is, for example, N, Ti, Sn, Zn, Ru, Ta, W, Mo, Al, Ga, Mn, or Mg. The second upper electrode layer 15 is, for example, titanium oxide (TiO).

[0036] The third upper electrode layer 16 is provided on the second upper electrode layer 15. The third upper electrode layer 16 includes, for example, a first metal element. The third upper electrode layer 16 includes, for example, the first metal element and N. The third upper electrode layer 16 includes, for example, a nitride of the first metal element. The third upper electrode layer 16 is, for example, titanium nitride (TiN).

[0037] The fourth upper electrode layer 17 is provided on the third upper electrode layer 16. The fourth upper electrode layer 17 includes, for example, tungsten (W). The third upper electrode layer 16 can prevent, for example, W included in the fourth upper electrode layer 17 from diffusing into the second upper electrode layer 15. That is, the third upper electrode layer 16 functions as, for example, a barrier metal. The fourth upper electrode layer 17 has, for example, a thickness three times or more that of the second upper electrode layer 15 along the Z axis. Note that the fourth upper electrode layer 17 may be omitted.

[0038] By providing the first upper electrode layer 14 between the oxide semiconductor 30 and the second upper electrode layer 15, the contact resistance between the oxide semiconductor 30 and the second upper electrode layer 15 can be reduced.

[0039] By providing the second upper electrode layer 15 between the first upper electrode layer 14 and the third upper electrode layer 16, it is possible to improve the adhesion between the first upper electrode layer 14 and the third upper electrode layer 16. Details will be described later in the section on effects.

[0040] The bit line BL includes conductors 18 to 20. The conductor 18 is provided on the fourth upper electrode layer 17. The conductor 18 includes, for example, TiN.

[0041] The conductor 19 is provided on the conductor 18. The conductor 19 includes W, for example.

[0042] The conductor 20 is provided on the conductor 19. The conductor 20 includes, for example, TiN.

[0043] The conductors 18 and 20 function as, for example, a barrier metal. The conductors 18 and 20 can prevent, for example, W contained in the conductor 19 from diffusing into an adjacent insulator layer or the like. The conductors 18 and 20 may be omitted. The fourth upper electrode layer 17 and the third upper electrode layer 16 may be integrated, and the third upper electrode layer 16, the fourth upper electrode layer 17, and the conductor 18 may be integrated.

[0044] Fig. 2 is a plan view showing an example of a planar layout of the semiconductor device 100 according to the first embodiment. As shown in Fig. 2, the semiconductor device 100 shows a plurality of bit lines BL and a plurality of word lines WL (gate electrodes GE), and a plurality of pillars PI and a plurality of upper electrodes TE associated with these wirings.

[0045] The plurality of pillars PI include, for example, five rows of pillars PI in the XY plane. In each row, the pillars PI are aligned along the X axis. In two adjacent rows of pillars PI, the positions of the pillars PI in one row in the X direction are offset from the positions of the pillars PI in the other row in the X direction. In other words, the memory pillars MP in the two adjacent rows are arranged in a zigzag pattern in the XY plane. FIG. 2 illustrates an example in which there are five rows of pillars PI, but the number and arrangement of the pillars PI are not limited to this and may be changed as appropriate. Each of the pillars PI functions, for example, as one vertical transistor CT.

[0046] As shown in FIG. 1, each pillar PI and an associated bit line BL are connected via a top electrode TE. The multiple bit lines BL each extend along the Y axis and are aligned along the X axis. Each bit line BL is arranged so as to overlap one pillar PI for each row of the multiple pillars PI. In this case, for example, each bit line BL overlaps with the -X side of each pillar PI in the odd-numbered rows and overlaps with the +X side of each pillar PI in the even-numbered rows.

[0047] The bit lines BL overlapping the pillars PI are electrically connected to the pillars PI. The number of pillars PI overlapping each bit line BL can be designed to be any number.

[0048] The gate electrode GE surrounds the pillar PI in the XY plan view (top view) seen from the +Z side. That is, the gate electrode GE is provided around the oxide semiconductor 30 and surrounds the oxide semiconductor 30. This allows the semiconductor device 100 to have a high gate electrostatic control force. Furthermore, the gate electrode GE has a portion extending along the X-axis. In this example, the gate electrode GE functions as a word line WL.

[0049] Fig. 3 shows an example of a cross-sectional structure of the semiconductor device 100 according to the first embodiment, and is a cross-sectional view taken along line III-III in Fig. 2. Fig. 4 shows an example of a cross-sectional structure of the semiconductor device 100 according to the first embodiment, and is a cross-sectional view taken along line IV-IV in Fig. 2. As shown in Figs. 3 and 4, the semiconductor device 100 includes a capacitor CC, insulators 21-25, lower electrodes BE, pillars PI, an upper electrode TE, a gate electrode GE, a bit line BL, and a member SLT.

[0050] The insulator 21 is provided, for example, above a substrate SU (not shown). An insulator 22 is provided on the insulator 21. A conductor 13 is provided on the insulator 22. An insulator 23 is provided on the conductor 13. An insulator 24 is provided on the insulator 23. A bit line BL is provided on the insulator 24. An insulator 25 is provided on the bit line BL.

[0051] The capacitor CC and the lower electrode BE are provided in the insulator 21. For example, the upper surface of the insulator 21 and the upper surface of the lower electrode BE are substantially flush with each other, and the lower surface of the insulator 21 and the lower surface of the capacitor CC are substantially flush with each other. The lower end of the lower electrode BE is located in the insulator 21 and contacts the upper end of the capacitor CC.

[0052] The upper electrode TE is provided in the insulator 24. For example, the upper surface of the insulator 24 and the upper surface of the upper electrode TE are substantially flush with each other, and the lower surface of the insulator 24 and the lower surface of the upper electrode TE are substantially flush with each other.

[0053] A pillar PI is provided between the insulator 21 and the insulator 24. The side surface of the pillar PI is in contact with the insulator 22, the conductor 13, and the insulator 23.

[0054] The conductors 18 to 20 extend along the Y axis.

[0055] Each of the insulators 21 to 25 includes, for example, SiO2.

[0056] 1 and 2, a member SLT is provided between adjacent bit lines BL along the X-axis. Each of the multiple members SLT extends along the Y-axis and is aligned along the X-axis. The bit lines BL adjacent along the X-axis are insulated from each other by the members SLT.

[0057] Each member SLT is arranged so as to overlap one pillar PI for each row of the pillars PI. In this case, for example, each member SLT overlaps with the +X side of the pillar PI in an odd-numbered row and overlaps with the -X side of the pillar PI in an even-numbered row.

[0058] The member SLT divides the insulator 25 and the conductors 18 to 20. The bottom surface of the member SLT may reach, for example, the insulator 24. A part of the upper end of the fourth upper electrode layer 17 contacts the member SLT. The upper end of the fourth upper electrode layer 17 has a portion in contact with the member SLT and a portion in contact with the conductor 18.

[0059] Each of the members SLT includes, for example, SiO2.

[0060] FIG. 5 shows an example of a cross-sectional structure of the semiconductor device 100 according to the first embodiment, and is a cross-sectional view taken along line VV in FIG. 3. More specifically, FIG. 5 shows a cross-sectional structure of the semiconductor device 100 in a layer parallel to the surface of the substrate SU and including the gate electrode GE. As shown in FIG. 5, in the cross section including the gate electrode GE, the oxide semiconductor 30 is provided in the center of the pillar PI. The first gate insulating film 31 surrounds the side surface of the oxide semiconductor 30. In other words, the oxide semiconductor 30 is embedded inside the first gate insulating film 31, which is provided in a cylindrical shape, for example. The second gate insulating film 32 surrounds the side surface of the first gate insulating film 31.

[0061] The conductor 13 has a portion surrounding the side surface of the second gate insulating film 32 and a portion extending along the X-axis.

[0062] In this manner, the first gate insulating film 31 and the second gate insulating film 32 are provided between the oxide semiconductor 30 and the conductor 13 functioning as the gate electrode.

[0063] In each pillar PI described above, the oxide semiconductor 30 is used as a channel of the semiconductor device 100.

[0064] [1-2] Manufacturing method of semiconductor device 100 FIG. 6 is a flowchart showing an example of a manufacturing process of the semiconductor device 100 according to the first embodiment. Each of FIGS. 7 to 15 shows an example of a cross-sectional structure during the manufacturing process of the semiconductor device 100 according to the first embodiment. Each of FIGS. 7 to 15 shows a cross-section of the same region as FIG. 3. An example of a manufacturing process relating to the formation of the semiconductor device 100 according to the first embodiment will be described below with reference to FIG. 6 as appropriate. As shown in FIG. 6, the manufacturing method of the semiconductor device 100 according to the first embodiment sequentially performs the processes of steps S11 to S19, for example.

[0065] In the process of step S11, as shown in FIG. 7, a hole HL1 is formed. Specifically, first, an insulator 21 is formed above a substrate SU (not shown). Next, an area where a capacitor CC and a lower electrode BE are to be formed is etched to form a hole HL1. The hole HL1 is formed by, for example, photolithography and anisotropic etching. For example, RIE (Reactive ion etching) is used as the anisotropic etching. After that, the capacitor CC is formed below the hole HL1, and the area where the lower electrode BE is to be formed remains as the hole HL1.

[0066] In the process of step S12, a lower electrode BE is formed as shown in Fig. 8. First, a first lower electrode layer 11 is formed on the bottom and side surfaces of the hole HL1. That is, in the hole HL1, the first lower electrode layer 11 is formed on the upper surface of the capacitor CC and the side surface of the insulator 21. Next, a second lower electrode layer 12 is embedded in the hole HL1. That is, the second lower electrode layer 12 is formed on the surface of the first lower electrode layer 11 and the entire inside of the hole HL1.

[0067] In the process of step S13, a hole HL2 is formed as shown in Fig. 9. Specifically, first, the insulator 22, the conductor 131, and the insulator 231 are formed in this order on the upper surface of the insulator 21 and the lower electrode BE. The conductor 131 is formed by, for example, sputtering. By performing the subsequent process, the conductor 13 is formed from a part of the conductor 131. That is, the conductor 131 is etched to form the conductor 13. The insulator 231 is formed in, for example, a region including a region where the insulator 23 is to be formed.

[0068] Next, the region where the pillar PI is to be formed is etched to form a hole HL2. The hole HL2 is formed by, for example, photolithography and anisotropic etching so as to reach the upper surface of the insulator 231 to the upper surface of the lower electrode BE. For example, RIE is used as the anisotropic etching.

[0069] In the process of step S14, a pillar PI is formed as shown in Fig. 10. First, a second gate insulating film 32 is formed on the surface of the hole HL2. Then, a first gate insulating film 31 is formed on the surface of the second gate insulating film 32. The first gate insulating film 31 and the second gate insulating film 32 are formed by, for example, CVD or the like.

[0070] Next, for example, a portion of the first gate insulating film 31 and the second gate insulating film 32 formed at the bottom of the hole HL2 is removed by anisotropic etching such as RIE, thereby exposing the surface of the second lower electrode layer 12 in the hole HL2.

[0071] Thereafter, the oxide semiconductor 30 is formed. The oxide semiconductor 30 is filled into the entire inside of the hole HL2 by, for example, ALD or the like. The oxide semiconductor 30 contacts the second lower electrode layer 12 at the bottom surface of the hole HL2. The oxide semiconductor 30 contacts the first gate insulating film 31.

[0072] Next, the conductor 131 is removed except for the region where the conductor 13 is to be formed. An insulator 232 (not shown) is formed in the portion where the conductor 131 has been removed. The upper surface of the insulator 232 and the upper surface of the insulator 231 formed in step S13 are approximately flush with each other. Hereinafter, the insulator consisting of the insulator 232 and the insulator 231 will be referred to as the insulator 23. In this way, the conductor 13 and the insulator 23 are formed.

[0073] Thereafter, the oxide semiconductor 30 formed on the insulator 23 is removed. The upper surfaces of the insulator 23, the first gate insulating film 31, the second gate insulating film 32, and the oxide semiconductor 30 may be planarized by CMP.

[0074] In the process of step S15, as shown in FIG. 11, a material that functions as an upper electrode TE is formed. Specifically, first, a first upper electrode layer 141 is formed on the upper surface of the insulator 23 and the pillar PI. Next, a second upper electrode layer 151 is formed on the upper surface of the first upper electrode layer 141. Next, a third upper electrode layer 161 is formed on the upper surface of the second upper electrode layer 151. Next, a fourth upper electrode layer 171 is formed on the upper surface of the third upper electrode layer 161. The first upper electrode layer 141, the second upper electrode layer 151, the third upper electrode layer 161, and the fourth upper electrode layer 171 are formed by, for example, sputtering.

[0075] In the process of step S16, as shown in Fig. 12, holes HL3 are formed. First, holes HL3 are formed in the region where the insulator 24 is to be formed. Specifically, a mask having an opening in the region where the hole HL3 is to be formed is formed by photolithography or the like, and the hole HL3 is formed by anisotropic etching using the mask. The first upper electrode layer 141, the second upper electrode layer 151, the third upper electrode layer 161, and the fourth upper electrode layer 171 are divided by the formed hole HL3, and the insulator 23 is exposed.

[0076] That is, the first upper electrode layer 141, the second upper electrode layer 151, the third upper electrode layer 161, and the fourth upper electrode layer 171 are removed except for the region where the upper electrode TE is to be formed. In this manner, the first upper electrode layer 14 is formed from a part of the first upper electrode layer 141. That is, a part of the first upper electrode layer 141 is etched to form the first upper electrode layer 14. Similarly, the second upper electrode layer 15, the third upper electrode layer 16, and the fourth upper electrode layer 17 are formed from a part of the second upper electrode layer 151, a part of the third upper electrode layer 161, and a part of the fourth upper electrode layer 171, respectively.

[0077] In the process of step S17, the insulator 24 is formed as shown in Fig. 13. The insulator 24 is formed so as to fill the hole HL3, thereby forming an upper electrode TE that extends in a columnar shape along the Z axis. That is, the insulator 24 is buried between the adjacent upper electrodes TE.

[0078] Thereafter, the insulator 24 formed on the upper electrode layer 17 is removed. The upper surfaces of the insulator 24 and the fourth upper electrode layer 17 may be planarized by CMP.

[0079] In the process of step S18, a material that functions as the bit line BL is formed, as shown in Fig. 14. Specifically, first, a conductor 18 is formed on the upper surface of the insulator 24 and the upper electrode TE. Next, a conductor 19 is formed on the upper surface of the conductor 18. Next, a conductor 20 is formed on the upper surface of the conductor 19. Next, an insulator 25 is formed on the upper surface of the conductor 20. The conductors 18 to 20 are formed by, for example, sputtering.

[0080] In the process of step S19, the bit line BL is processed as shown in Fig. 15. First, a slit SH is formed in the region where the member SLT is to be formed. Specifically, a mask having an opening in the region where the slit SH is to be formed is formed by photolithography or the like, and the slit SH is formed by anisotropic etching using the mask.

[0081] The slits SH, for example, divide the insulator 25 and the conductors 18 to 20, and reach the insulator 24. Part of the insulator 24 and the upper electrode layer 17 are exposed by the slits SH. The upper end of the upper electrode layer 17 has a portion in contact with the conductor 18 and a portion exposed by the slits SH.

[0082] Next, the members SLT are formed so as to fill the slits SH. The members SLT are disposed so as to overlap one pillar PI for each row of the plurality of pillars PI in the XY plan view.

[0083] By forming the member SLT, the bit lines BL extending along the Y-axis and aligned along the X-axis are formed as shown in Figures 3 and 4. In other words, the member SLT is embedded between adjacent bit lines BL.

[0084] The semiconductor device 100 is formed by the manufacturing process of the semiconductor device 100 according to the first embodiment described above. Note that the manufacturing process described above is merely an example, and is not limited to this. For example, other processing may be inserted between each manufacturing process, or some processes may be omitted or integrated. Also, the order of each manufacturing process may be changed as long as no problems arise.

[0085] [1-3] Advantages (effects) of the first embodiment The semiconductor device 100 according to the first embodiment described above can improve the performance of the semiconductor device 100. The following describes detailed effects of the semiconductor device 100 according to the first embodiment.

[0086] As described above, the semiconductor device 100 according to the first embodiment has the second upper electrode layer 15 between the first upper electrode layer 14 and the third upper electrode layer 16 in the upper electrode TE. Hereinafter, a semiconductor device that does not have the second upper electrode layer 15 between the first upper electrode layer 14 and the third upper electrode layer 16 may be referred to as a semiconductor device 100r according to a comparative example of the first embodiment.

[0087] Since the semiconductor device 100r does not have the second upper electrode layer 15, for example, the first upper electrode layer 14 and the third upper electrode layer 16 come into contact with each other. When the first upper electrode layer 14 and the third upper electrode layer 16 come into contact with each other, the adhesion between the two layers may decrease. When the adhesion between the first upper electrode layer 14 and the third upper electrode layer 16 decreases, peeling may occur between the two layers. When peeling occurs between the first upper electrode layer 14 and the third upper electrode layer 16, for example, the migration resistance of the upper electrode TE may decrease, and the resistance of the upper electrode TE may increase.

[0088] In addition, a structure in which each layer is stacked, such as the upper electrode TE of this embodiment, is more susceptible to a decrease in adhesion than a structure such as the lower electrode BE. In the lower electrode BE, the first lower electrode layer 11 contacts the lower surface and side surface of the second lower electrode layer 12. In contrast, in the upper electrode TE, the first upper electrode layer 14 contacts only the lower surface of the second upper electrode layer 15, and the second upper electrode layer 15 contacts only the lower surface of the third upper electrode layer 16. In other words, this is because the contact area of ​​each layer of the upper electrode TE is smaller than the contact area of ​​each layer of the lower electrode BE.

[0089] In contrast, the semiconductor device 100 has a second upper electrode layer 15 between the first upper electrode layer 14 and the third upper electrode layer 16. By having the second upper electrode layer 15, the semiconductor device 100 improves adhesion between the second upper electrode layer 15 and the third upper electrode layer 16 and between the first upper electrode layer 14 and the second upper electrode layer 15.

[0090] This is because the first upper electrode layer 14 and the second upper electrode layer 15 contain O, and the second upper electrode layer 15 and the third upper electrode layer 16 contain the above-mentioned first metal element. That is, O in the first upper electrode layer 14 and the first metal element in the second upper electrode layer 15 can be bonded at the interface. Furthermore, In in the first upper electrode layer 14 and O in the second upper electrode layer 15 can be bonded at the interface. This improves the adhesion between the first upper electrode layer 14 and the second upper electrode layer 15.

[0091] Next, O in the second upper electrode layer 15 and the first metal element in the third upper electrode layer 16 can be bonded at the interface. Furthermore, the first metal element in the second upper electrode layer 15 and N in the third upper electrode layer 16 can be bonded at the interface. The first element in the second upper electrode layer 15 and the first metal element or N in the third upper electrode layer 16 can be bonded at the interface. This improves the adhesion between the second upper electrode layer 15 and the third upper electrode layer 16.

[0092] In this manner, in the semiconductor device 100, by inserting the second upper electrode layer 15 containing O and the first metal element between the first upper electrode layer 14 containing O and the third upper electrode layer 16 containing the first metal element, the adhesion between the first upper electrode layer 14 and the third upper electrode layer 16 is improved. Due to the improved adhesion, the semiconductor device 100 has improved migration resistance and can have improved reliability compared to the semiconductor device 100r.

[0093] [2] Modification of the first embodiment (First Modification) In the upper electrode TE of the semiconductor device 100 according to the first embodiment described above, an example is shown in which the second upper electrode layer 15 is provided between the first upper electrode layer 14 and the third upper electrode layer 16. However, in the upper electrode TE according to the first modification of the first embodiment, the second upper electrode layer 15 and the third upper electrode layer 16 may be integrated into one layer as shown in FIG. 16. In other words, the interface between the second upper electrode layer 15 and the third upper electrode layer 16 may be unclear. The layer in which the second upper electrode layer 15 and the third upper electrode layer 16 are integrated is hereinafter referred to as the fifth upper electrode layer 40a. That is, the upper electrode TE according to the first modification of the first embodiment includes the first upper electrode layer 14, the fifth upper electrode layer 40a, and the fourth upper electrode layer 17.

[0094] The fifth upper electrode layer 40a includes, for example, a first metal element, O, and N. The fifth upper electrode layer 40a includes, for example, an oxide of the first metal element. The fifth upper electrode layer 40a includes, for example, a nitride of the first metal element. The fifth upper electrode layer 40a includes, for example, the first metal element, the first element, O, and N. The fifth upper electrode layer 40a includes, for example, a conductive oxide including the first metal element. The first metal element is, for example, Ti, Sn, Zn, Ru, or Nb, as in the first embodiment. The first element is, for example, N, Ti, Sn, Zn, Ru, Ta, W, Mo, Al, Ga, Mn, or Mg, as in the first embodiment.

[0095] For example, in the fifth upper electrode layer 40a, the concentration of O contained in a region located closer to the first upper electrode layer 14 may be greater than the concentration of O contained in a region located closer to the fourth upper electrode layer 17 (farther from the first upper electrode layer 14).

[0096] For example, in the fifth upper electrode layer 40a, the concentration of the first metal element contained in a region located closer to the first upper electrode layer 14 may be lower than the concentration of the first metal element contained in a region located closer to the fourth upper electrode layer 17 (farther from the first upper electrode layer 14).

[0097] For example, in the fifth upper electrode layer 40a, the concentration of N contained in a region located closer to the first upper electrode layer 14 may be lower than the concentration of N contained in a region located closer to the fourth upper electrode layer 17 (farther from the first upper electrode layer 14).

[0098] For example, the fifth upper electrode layer 40a contains a large amount of titanium oxide (TiO) in a region located closer to the first upper electrode layer 14. For example, the fifth upper electrode layer 40a has a composition close to TiO2 in a region located closer to the first upper electrode layer 14, that is, contains about 33% Ti.

[0099] For example, the fifth upper electrode layer 40a contains a large amount of titanium nitride (TiN) in a region located closer to the fourth upper electrode layer 17. For example, the fifth upper electrode layer 40a has a composition close to TiN in a region located closer to the fourth upper electrode layer 17, that is, contains about 50% Ti.

[0100] For example, the fifth upper electrode layer 40a contains a large amount of titanium oxynitride (TiON) in a region close to the middle between the first upper electrode layer 14 and the fourth upper electrode layer 17.

[0101] Even if the fifth upper electrode layer 40a is such an integrated single layer, it can improve the adhesion between the first upper electrode layer 14 and the fifth upper electrode layer 40a, similar to the second upper electrode layer 15. That is, even if the fifth upper electrode layer 40a is a single layer and has a structure in which the concentrations of the first metal element, the first element, O, and N change along the Z axis in the layer, it can improve the adhesion between the first upper electrode layer 14 and the fifth upper electrode layer 40a. That is, the upper electrode TE according to the first modification of the first embodiment can improve the migration resistance. This is because the fifth upper electrode layer 40a contains O, N, and the first metal element, and thus the adhesion at the interface and the bond inside the fifth upper electrode layer 40a can be strengthened.

[0102] [3] Second embodiment Hereinafter, the semiconductor device 100b according to the second embodiment will be described. Hereinafter, the semiconductor device 100 according to the second embodiment may be referred to as the semiconductor device 100b in order to distinguish it from the semiconductor device 100 according to the first embodiment.

[0103] [3-1] Configuration (structure) The semiconductor device 100b according to the second embodiment differs from the semiconductor device 100 according to the first embodiment mainly in the structure of the lower electrode BE. Hereinafter, the lower electrode BE of the second embodiment may be referred to as the lower electrode BEb to distinguish it from the lower electrode BE of the first embodiment. The other structures of the second embodiment are almost the same as those of the first embodiment. Below, the semiconductor device 100b according to the second embodiment will be mainly described with respect to the differences from the first embodiment.

[0104] The structure of the lower electrode BEb will be described in detail with reference to Fig. 17. Fig. 17 shows an example of a cross-sectional structure of a semiconductor device 100b according to the second embodiment. Fig. 17 shows a cross section of the same region as Fig. 3 in the first embodiment.

[0105] 17, the lower electrode BEb in the second embodiment differs from the lower electrode BE in the first embodiment in that it further includes a third lower electrode layer 50b between the first lower electrode layer 11 and the second lower electrode layer 12. The structure of the lower electrode BEb will be described below.

[0106] The lower electrode BEb has, for example, a cylindrical shape extending along the Z-axis. The lower electrode BEb is located in the insulator 21. For example, the upper surface of the insulator 21 and the upper surface of the lower electrode BEb are substantially flush with each other, and the lower surface of the insulator 21 and the lower surface of the capacitor CC are substantially flush with each other. The lower end of the lower electrode BEb is located in the insulator 21 and contacts the upper end of the capacitor CC.

[0107] The bottom electrode BEb includes a first bottom electrode layer 11, a second bottom electrode layer 12, and a third bottom electrode layer 50b. The second bottom electrode layer 12 is, for example, cylindrical, and is provided in the center of the bottom electrode BEb. The top surface of the second bottom electrode layer 12 is substantially flush with the top surface of the insulator 21. The top end of the second bottom electrode layer 12 contacts the bottom end of the pillar PI.

[0108] The second lower electrode layer 12 includes a material having electrical conductivity. The second lower electrode layer 12 includes, for example, a conductive oxide. The second lower electrode layer 12 is, for example, a conductive oxide layer.

[0109] The second lower electrode layer 12 includes, for example, indium (In), tin (Sn), and oxygen (O). The second lower electrode layer 12 includes, for example, indium tin oxide. The second lower electrode layer 12 is, for example, an indium tin oxide layer.

[0110] The second lower electrode layer 12 includes, for example, tin (Sn) and oxygen (O). The second lower electrode layer 12 includes, for example, tin oxide. The second lower electrode layer 12 is, for example, a tin oxide layer.

[0111] The second lower electrode layer 12 is provided between the oxide semiconductor 30 and a third lower electrode layer 50b described later, thereby making it possible to reduce the contact resistance between the oxide semiconductor 30 and the third lower electrode layer 50b.

[0112] The third lower electrode layer 50b contacts the surface of the second lower electrode layer 12 except for the upper surface. That is, the third lower electrode layer 50b contacts the side surface and the lower surface of the second lower electrode layer 12. The third lower electrode layer 50b includes, for example, a fourth metal element and O. The third lower electrode layer 50b includes, for example, an oxide of the fourth metal element. The third lower electrode layer 50b includes, for example, a fourth metal element, O, and the second element. The third lower electrode layer 50b includes, for example, a conductive oxide including the fourth metal element. The fourth metal element is, for example, Ti, Sn, Zn, Ru, or Nb, similar to the first metal element. The second element is, for example, N, Ti, Sn, Zn, Ru, Ta, W, Mo, Al, Ga, Mn, or Mg, similar to the first element. The third lower electrode layer 50b is, for example, titanium oxide (TiO).

[0113] The fourth metal element contained in the bottom electrode BEb may be the same element as the first metal element contained in the top electrode TE. The second element contained in the bottom electrode BEb may be the same element as the first element contained in the top electrode TE.

[0114] The first lower electrode layer 11 contacts the surface of the third lower electrode layer 50b except for the upper surface. That is, the first lower electrode layer 11 contacts the side surface and the lower surface of the third lower electrode layer 50b. The lower surface of the first lower electrode layer 11 contacts the upper surface of the capacitor CC. The first lower electrode layer 11 includes, for example, a fourth metal element. The first lower electrode layer 11 includes, for example, the fourth metal element and N. The first lower electrode layer 11 includes, for example, a nitride of the fourth metal element. The first lower electrode layer 11 is, for example, titanium nitride (TiN).

[0115] [3-2] Manufacturing method of semiconductor device 100b Fig. 18 is a flow chart showing an example of a manufacturing process of the semiconductor device 100b according to the second embodiment. Fig. 19 is an example of a cross-sectional structure during the manufacturing process of the semiconductor device 100b according to the second embodiment. Fig. 19 shows a cross section of the same region as Fig. 8. Hereinafter, an example of a manufacturing process for forming the semiconductor device 100b according to the second embodiment will be described with reference to Fig. 18.

[0116] As shown in FIG. 18, the method for manufacturing the semiconductor device 100b according to the second embodiment includes, for example, sequentially executing the processes of steps S11, S22, and S13 to S19.

[0117] First, like the first embodiment, the process of step S11 is executed.

[0118] Next, in the process of step S22, a lower electrode BEb is formed as shown in FIG. 19. First, a first lower electrode layer 11 is formed on the bottom and side surfaces of the hole HL1. That is, in the hole HL1, the first lower electrode layer 11 is formed on the upper surface of the capacitor CC and the side surface of the insulator 21. Next, a third lower electrode layer 50b is formed on the surface of the first lower electrode layer 11. Next, a second lower electrode layer 12 is embedded in the hole HL1. That is, the second lower electrode layer 12 is formed on the surface of the third lower electrode layer 50b and the entire inside of the hole HL1.

[0119] Next, similarly to the first embodiment, the processes of steps S13 to S19 are executed in order.

[0120] The semiconductor device 100b is formed by the manufacturing process of the semiconductor device 100b according to the second embodiment described above. Note that the manufacturing process described above is merely an example, and is not limited to this. For example, other processes may be inserted between the manufacturing processes, or some processes may be omitted or integrated. Also, the order of the manufacturing processes may be changed as long as no problems arise.

[0121] [3-3] Advantages (effects) of the second embodiment According to the semiconductor device 100b according to the second embodiment described above, the performance of the semiconductor device 100b can be improved, similarly to the first embodiment.

[0122] As described above, the semiconductor device 100b according to the second embodiment has the third lower electrode layer 50b in the lower electrode BEb between the first lower electrode layer 11 and the second lower electrode layer 12. By having the third lower electrode layer 50b, the semiconductor device 100b improves adhesion between the first lower electrode layer 11 and the third lower electrode layer 50b and between the third lower electrode layer 50b and the second lower electrode layer 12.

[0123] This is because, as in the first embodiment, the second lower electrode layer 12 and the third lower electrode layer 50b contain O, and the third lower electrode layer 50b and the first lower electrode layer 11 contain a fourth metal element. That is, O in the second lower electrode layer 12 and the fourth metal element in the third lower electrode layer 50b can be bonded at the interface. Furthermore, In in the second lower electrode layer 12 and O in the third lower electrode layer 50b can be bonded at the interface. This improves the adhesion between the second lower electrode layer 12 and the third lower electrode layer 50b.

[0124] Next, O in the third lower electrode layer 50b and the fourth metal element in the first lower electrode layer 11 can be bonded at the interface. Furthermore, the fourth metal element in the third lower electrode layer 50b and N in the first lower electrode layer 11 can be bonded at the interface. The second element in the third lower electrode layer 50b and the fourth metal element or N in the first lower electrode layer 11 can be bonded at the interface. This improves the adhesion between the third lower electrode layer 50b and the first lower electrode layer 11.

[0125] In this manner, the lower electrode BEb has the third lower electrode layer 50b containing O and the fourth metal element inserted between the second lower electrode layer 12 containing O and the first lower electrode layer 11 containing the fourth metal element, thereby improving adhesion between the second lower electrode layer 12 and the first lower electrode layer 11. The improved adhesion improves the migration resistance of the lower electrode BEb, and the reliability can be improved.

[0126] [4] Modification of the second embodiment (First Modification) In the lower electrode BEb of the semiconductor device 100b according to the second embodiment described above, an example is shown in which the third lower electrode layer 50b is provided between the first lower electrode layer 11 and the second lower electrode layer 12. However, in the lower electrode BEb according to the first modification of the second embodiment, as shown in FIG. 20, the third lower electrode layer 50b and the first lower electrode layer 11 may be integrated into one layer. In other words, the interface between the third lower electrode layer 50b and the first lower electrode layer 11 may be unclear. The layer in which the third lower electrode layer 50b and the first lower electrode layer 11 are integrated is hereinafter referred to as the fourth lower electrode layer 51b. That is, the lower electrode BEb according to the first modification of the second embodiment includes the second lower electrode layer 12 and the fourth lower electrode layer 51b.

[0127] The fourth lower electrode layer 51b includes, for example, a fourth metal element, O, and N. The fourth lower electrode layer 51b includes, for example, an oxide of the fourth metal element. The fourth lower electrode layer 51b includes, for example, a nitride of the fourth metal element. The fourth lower electrode layer 51b includes, for example, a fourth metal element, a second element, O, and N. The fourth lower electrode layer 51b includes, for example, a conductive oxide including the fourth metal element. The fourth metal element is, for example, Ti, Sn, Zn, Ru, or Nb, as in the first embodiment. The second element is, for example, N, Ti, Sn, Zn, Ru, Ta, W, Mo, Al, Ga, Mn, or Mg, as in the first embodiment.

[0128] For example, in the fourth lower electrode layer 51b, the concentration of O contained in a region located closer to the second lower electrode layer 12 may be higher than the concentration of O contained in a region located farther from the second lower electrode layer 12.

[0129] For example, in the fourth lower electrode layer 51b, the concentration of the fourth metal element contained in a region located closer to the second lower electrode layer 12 may be smaller than the concentration of the fourth metal element contained in a region located farther from the second lower electrode layer 12.

[0130] For example, in the fourth lower electrode layer 51b, the concentration of N contained in a region located closer to the second lower electrode layer 12 may be lower than the concentration of N contained in a region located farther from the second lower electrode layer 12.

[0131] For example, the fourth lower electrode layer 51b contains a large amount of titanium oxide (TiO) in a region located closer to the second lower electrode layer 12. For example, the fourth lower electrode layer 51b has a composition close to TiO2 in a region located closer to the second lower electrode layer 12, that is, contains about 33% Ti.

[0132] For example, the fourth lower electrode layer 51b contains a large amount of titanium nitride (TiN) in a region located farther from the second lower electrode layer 12. For example, the fourth lower electrode layer 51b has a composition close to TiN in a region located farther from the second lower electrode layer 12, that is, contains about 50% Ti.

[0133] For example, the fourth lower electrode layer 51b contains a large amount of titanium oxynitride (TiON) in a region located between a region close to the second lower electrode layer 12 and a region far from the second lower electrode layer 12.

[0134] Even if the fourth lower electrode layer 51b is one integrated layer, it can improve the adhesion between the second lower electrode layer 12 and the fourth lower electrode layer 51b, similar to the third lower electrode layer 50b. That is, even if the fourth lower electrode layer 51b is a single layer and has a structure in which the concentrations of the fourth metal element, the second element, O, and N change within the layer, it can improve the adhesion between the second lower electrode layer 12 and the fourth lower electrode layer 51b. That is, the lower electrode BEb according to the first modification of the second embodiment can improve the migration resistance. This is because the fourth lower electrode layer 51b contains O, N, and the fourth metal element, thereby strengthening the adhesion at the interface and the bond inside the fourth lower electrode layer 51b.

[0135] [4] Other modifications, etc. In the first and second embodiments, the semiconductor devices 100 and 100b may have other structures. The structure in the first embodiment may also be applied to the second embodiment. The structures shown in the modified examples of the first and second embodiments may be applied to the first and second embodiments, even if only a part of the structures or a combination of multiple structures is used.

[0136] The pillar PI may have a tapered or inversely tapered shape, or may have a shape with a bulging middle portion.

[0137] In this specification, the term "connect" refers to being electrically connected, and does not exclude, for example, the presence of another element between them. "Electrically connected" may be connected through an insulator as long as it is possible for the device to function in the same manner as an electrically connected device.

[0138] The first and second embodiments of the present invention are presented as examples and are not intended to limit the scope of the invention. The first and second embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the gist of the invention. The first and second embodiments and their modifications are included in the scope and gist of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0139] 100, 100b... semiconductor device, 11, 12, 50b, 51b... lower electrode layer, 13, 18 to 20... conductor, 14, 15, 16, 17, 40a... upper electrode layer, 21 to 25... insulator, 31, 32... gate insulating film, 30... oxide semiconductor, PI... pillar, SLT... member, CC... capacitor, BL... bit line

Claims

1. A first electrode; a first oxide semiconductor having one end in contact with the first electrode and extending in a first direction intersecting a surface of the first electrode; a first insulator surrounding a side surface of the first oxide semiconductor; a first conductor surrounding at least a portion of a side surface of the first insulator in a top view; a first conductive oxide in contact with the other end of the first oxide semiconductor; a second conductive oxide on the first conductive oxide; a second conductor on the second conductive oxide; and Equipped with the second conductive oxide and the second conductor contain a first metal element; The first conductive oxide and the second conductive oxide contain oxygen. Semiconductor device.

2. The first metal element is Ti, Sn, Zn, Ru, or Nb; The semiconductor device according to claim 1 .

3. The second conductive oxide further includes a first element, The first element is N, Ti, Sn, Zn, Ru, Ta, W, Mo, Al, Ga, Mn, or Mg; The semiconductor device according to claim 2 .

4. The first oxide semiconductor and the first conductive oxide contain a second metal element. The semiconductor device according to claim 1 .

5. The second metal element is In. The semiconductor device according to claim 4.

6. The second conductor further includes nitrogen. The semiconductor device according to claim 1 .

7. The first electrode is a third conductive oxide having an upper surface in contact with the one end of the first oxide semiconductor; a fourth conductor in contact with a lower surface of the third conductive oxide; Including, the fourth conductor includes a third metal element; the first oxide semiconductor, the first conductive oxide, and the third conductive oxide each contain a second metal element; The semiconductor device according to claim 1 .

8. The first electrode is a third conductive oxide having an upper surface in contact with the one end of the first oxide semiconductor; a fourth conductive oxide in contact with a lower surface of the third conductive oxide; a fourth conductor in contact with a lower surface of the fourth conductive oxide; Including, the fourth conductive oxide and the fourth conductor contain a third metal element; the third conductive oxide and the fourth conductive oxide contain oxygen; The semiconductor device according to claim 1 .

9. the fourth conductive oxide is in contact with a lower surface and a side surface of the third conductive oxide, The fourth conductor contacts a lower surface and a side surface of the fourth conductive oxide. The semiconductor device according to claim 8.

10. The first metal element and the third metal element are the same element. The semiconductor device according to claim 8.

11. The third metal element is Ti, Sn, Zn, Ru, or Nb; The semiconductor device according to claim 8.

12. The fourth conductive oxide further includes a first element, The first element is N, Ti, Sn, Zn, Ru, Ta, W, Mo, Al, Ga, Mn, or Mg; The semiconductor device according to claim 11.

13. the first oxide semiconductor, the first conductive oxide, and the third conductive oxide each contain a second metal element; The semiconductor device according to claim 8.

14. The second metal element is In. The semiconductor device according to claim 13.

15. A first electrode; a first oxide semiconductor having one end in contact with the first electrode and extending in a first direction intersecting a surface of the first electrode; a first insulator surrounding a side surface of the first oxide semiconductor; a first conductor surrounding at least a portion of a side surface of the first insulator in a top view; a first conductive oxide in contact with the other end of the first oxide semiconductor; a fifth conductive oxide on the first conductive oxide; Equipped with the fifth conductive oxide contains a first metal element and nitrogen; the first conductive oxide and the fifth conductive oxide contain oxygen, the first oxide semiconductor and the first conductive oxide contain a second metal element; the first metal element is Ti, Sn, Zn, Ru, or Nb; The second metal element is In. Semiconductor device.

16. In the fifth conductive oxide, a concentration of oxygen contained in a region located closer to the first conductive oxide is greater than a concentration of oxygen contained in a region located farther from the first conductive oxide, and a concentration of nitrogen contained in a region located closer to the first conductive oxide is less than a concentration of nitrogen contained in a region located farther from the first conductive oxide. The semiconductor device according to claim 15.

17. The first electrode is a third conductive oxide having an upper surface in contact with the one end of the first oxide semiconductor; a sixth conductive oxide in contact with a lower surface of the third conductive oxide; Including, the sixth conductive oxide contains a third metal element and nitrogen; the third conductive oxide and the sixth conductive oxide contain oxygen, the first oxide semiconductor, the first conductive oxide, and the third conductive oxide each contain a second metal element; the first metal element and the third metal element are Ti, Sn, Zn, Ru, or Nb; The second metal element is In. The semiconductor device according to claim 1 .

18. In the sixth conductive oxide, a concentration of oxygen contained in a region located closer to the third conductive oxide is greater than a concentration of oxygen contained in a region located farther from the third conductive oxide, and a concentration of nitrogen contained in a region located closer to the third conductive oxide is less than a concentration of nitrogen contained in a region located farther from the third conductive oxide. The semiconductor device according to claim 17.

19. The first metal element and the third metal element are the same element. The semiconductor device according to claim 17.

20. The first oxide semiconductor contains at least one element selected from the group consisting of In, Ga, Si, Al, and Sn, Zn, and O; The semiconductor device according to claim 1 .

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