Isolator

Abstract

To provide an isolator capable of suppressing the occurrence of a defect.SOLUTION: An isolator according to an embodiment includes a substrate and a plurality of leads. The substrate includes a plurality of coils and a plurality of conductive parts. A lower surface of the substrate has a square shape having first to fourth corner parts in a plan view seen along a first direction. The coils include a first coil and a second coil facing the first coil. The conductive parts include first to fourth conductive parts. The first to fourth conductive parts include first to fourth terminal parts existing at first to fourth opening parts provided in the first to fourth corner parts. The leads include first to fourth leads connected to the first to fourth terminal parts by solder. The leads include metal.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] SUMMARY OF THE DISCLOSURE The present invention relates to an isolator. [Background technology]

[0002] A circuit that transmits a signal from a transmitting circuit to a receiving circuit while isolating the transmitting circuit from the receiving circuit. Transmissive isolators are known. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 09-023099 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide an isolator capable of suppressing the occurrence of defects. [Means for solving the problem]

[0005] The isolator according to the embodiment includes a substrate and a plurality of leads. The substrate has an upper surface extending along a plane perpendicular to a first direction and a lower surface opposite to the upper surface. The substrate includes a plurality of coils and a plurality of conductive parts. The lower surface is a quadrangle having a first corner portion, a second corner portion, a third corner portion, and a fourth corner portion in a plan view along the first direction. The plurality of coils are provided inside the substrate. The plurality of coils include a first coil and a second coil facing the first coil. The plurality of conductive parts include a first conductive part, a second conductive part, a third conductive part, and a fourth conductive part. The first conductive part has a first terminal portion located at a first opening portion provided in the first corner portion. The second conductive part has a second terminal portion located at a second opening portion provided in the second corner portion. The third conductive part has a third terminal portion located at a third opening portion provided in the third corner portion. The fourth conductive portion has a fourth terminal portion located in a fourth opening provided in the fourth corner portion. The plurality of leads include a first lead connected to the first terminal portion by solder, a second lead connected to the second terminal portion by solder, a third lead connected to the third terminal portion by solder, and a fourth lead connected to the fourth terminal portion by solder. The plurality of leads include a metal. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is a schematic plan view illustrating an isolator according to an embodiment. [Diagram 2] FIG. 2 is a schematic plan view illustrating the isolator according to the embodiment. [Diagram 3] 3(a) to 3(d) are cross-sectional views illustrating a portion of the isolator according to the embodiment. [Figure 4] 4A and 4B are schematic cross-sectional views illustrating the isolator according to the embodiment. [Diagram 5] 5A and 5B are schematic cross-sectional views illustrating the isolator according to the embodiment. [Figure 6]6A and 6B are schematic cross-sectional views illustrating the isolator according to the embodiment. [Figure 7] FIG. 7 is a schematic diagram illustrating the circuit configuration of the isolator according to the embodiment. [Figure 8] 8A and 8B are schematic cross-sectional views illustrating a portion of the isolator according to the embodiment. [Figure 9] 9A and 9B are schematic plan views illustrating a part of an isolator according to a modification of the embodiment. [Figure 10] FIG. 10 is a schematic plan view illustrating a part of an isolator according to a modified example of the embodiment. [Figure 11] 11A and 11B are schematic plan views illustrating the periphery of the leads of the isolator according to the embodiment. [Figure 12] 12A and 12B are schematic plan views illustrating a part of the isolator according to the embodiment. [Figure 13] 13A and 13B are a schematic cross-sectional view and a schematic plan view illustrating a part of the isolator according to the embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as those in reality. Even when the same part is shown, the dimensions and ratios of each part may be different depending on the drawing. In this specification and each drawing, elements similar to those already explained are given the same reference numerals and detailed explanations are omitted as appropriate.

[0008] FIG. 1 is a schematic plan view illustrating an isolator according to an embodiment. The isolator 100 according to the embodiment includes a substrate 10, a plurality of leads 20, a first semiconductor chip 61, a second semiconductor chip 62, a die pad 31, a die pad 32, a plurality of external terminals 33, and a plurality of external terminals 34. These components are covered with an insulating section 36 (sealing resin) (see FIG. 4(a)). FIG. 1 shows a schematic view of the inside of the insulating section 36. The isolator 100 is, for example, a semiconductor package.

[0009] The substrate 10 has an upper surface 10t and a lower surface 10s (see FIG. 4(a)) opposite to the upper surface 10t. In the description of the embodiment, an XYZ Cartesian coordinate system is used. The direction perpendicular to the upper surface 10t is defined as the Z direction (first direction). Two directions perpendicular to the Z direction and perpendicular to each other are defined as the X direction (second direction) and the Y direction (third direction). The upper surface 10t and the lower surface 10s are each a surface extending along the XY plane. For the sake of description, the direction from the lower surface 10s to the upper surface 10t is referred to as "up" and the opposite direction is referred to as "down". These directions are based on the relative positional relationship between the upper surface 10t and the lower surface 10s and are unrelated to the direction of gravity.

[0010] A plurality of coils C including a first coil C1 and a second coil C2 are provided inside the substrate 10. Each of the plurality of coils C is a spiral coil in a plan view. The second coil C2 is disposed so as to face the first coil C1. The second coil C2 overlaps with the first coil C1 in the up-down direction. The second coil C2 is disposed above the first coil C1 and is spaced apart from the first coil C1. The first coil C1 and the second coil C2 are disposed so as to be magnetically coupled. In this example, two each of the first coil C1 and the second coil C2 are provided.

[0011] The multiple leads 20 are connected to the underside of the substrate 10. The multiple leads 20 include a signal lead 28 electrically connected to the first semiconductor chip 61. The signal lead 28 is electrically connected to the first semiconductor chip 61 by a wire W1. The first coil C1 is electrically connected to the first semiconductor chip 61 via the signal lead 28 and the wire W1.

[0012] The first semiconductor chip 61 is fixed onto the die pad 31 by, for example, an insulating adhesive. The first semiconductor chip 61 is also electrically connected to an external terminal 33 by a wire W2. The external terminal 33 is located on the outer edge of the isolator 100 (the outer edge of the insulating portion 36). An electrical signal is input from the outside to the first semiconductor chip 61 via the external terminal 33 and the wire W2.

[0013] The second semiconductor chip 62 is electrically connected to the second coil C2 via a wire W3. The second semiconductor chip 62 is fixed onto the die pad 32 by, for example, an insulating adhesive. The second semiconductor chip 62 is also electrically connected to an external terminal 34 via a wire W4. The external terminal 34 is located on the outer edge of the isolator 100 (the outer edge of the insulating portion 36). An electrical signal is output from the second semiconductor chip 62 to the outside via the wire W4 and the external terminal 34.

[0014] The substrate 10 may be provided with an element E other than the multiple coils C. The element E may be any circuit element, and may include, for example, at least one of a resistor, a capacitor, and an inductor. One end of the element E is electrically connected to the first semiconductor chip 61 in the same manner as the first coil C1. The other end of the element E is electrically connected to the second semiconductor chip 62 in the same manner as the second coil C2.

[0015] FIG. 2 is a schematic plan view illustrating the isolator according to the embodiment. Fig. 2 shows an enlarged view of a portion of the periphery of the substrate 10 shown in Fig. 1. The substrate 10 (upper surface 10t and lower surface 10s) has a quadrangular shape (e.g., rectangular) in a plan view seen along the Z direction. That is, the outer edge of the substrate 10 in a plan view includes a first side s1, a second side s2, a third side s3, and a fourth side s4.

[0016] The second side s2 is spaced from the first side s1 in the X direction. The first side s1 and the second side s2 extend in the Y direction. The third side s3 connects one end of the first side s1 to one end of the second side s2. The fourth side s4 is spaced from the third side s3 in the Y direction and connects the other end of the first side s1 to the other end of the second side s2. The third side s3 and the fourth side s4 extend in the X direction.

[0017] The lower surface 10s of the substrate 10 includes a first corner portion cr1, a second corner portion cr2, a third corner portion cr3, and a fourth corner portion cr4. The first corner portion cr1 is a portion including the intersection p23 (vertex) of the second side s2 and the third side s3. For example, the first corner portion cr1 is a portion closer to the intersection p23 than the coils C. In other words, the distance from the intersection p23 to any point on the first corner portion cr1 is shorter than the shortest distance from the intersection p23 to any of the coils C. As an example, the first corner portion cr1 is within 1 mm (millimeter) of the second side s2 and within 1 mm of the third side s3.

[0018] Similarly, the second corner portion cr2 is a portion including an intersection p13 (vertex) between the first side s1 and the third side s3. For example, the second corner portion cr2 is a portion closer to the intersection p13 than the multiple coils C. As an example, the second corner portion cr2 is within 1 mm from the first side s1 and within 1 mm from the third side s3. The third corner portion cr3 is a portion including an intersection p24 (vertex) between the second side s2 and the fourth side s4. For example, the third corner portion cr3 is a portion closer to the intersection p24 than the multiple coils C. As an example, the third corner portion cr3 is within 1 mm from the second side s2 and within 1 mm from the fourth side s4. The fourth corner portion cr4 is a portion including an intersection p14 (vertex) between the first side s1 and the fourth side s4. For example, the fourth corner portion cr4 is a portion closer to the intersection p14 than the multiple coils C. As an example, the fourth corner portion cr4 is within 1 mm from the first side s1 and within 1 mm from the fourth side s4.

[0019] Furthermore, the multiple leads 20 include a first lead 21, a second lead 22, a third lead 23, and a fourth lead 24. These four leads 20 (21 to 24) are disposed, for example, at each of the four corners of the substrate 10 in a plan view.

[0020] 3(a) to 3(d) are cross-sectional views illustrating a portion of the isolator according to the embodiment. Fig. 3(a) corresponds to the cross section taken along the line A1-A2 shown in Fig. 2. Fig. 3(b) corresponds to the cross section taken along the line A3-A4 shown in Fig. 2. Fig. 3(c) corresponds to the cross section taken along the line A5-A6 shown in Fig. 2. Fig. 3(d) corresponds to the cross section taken along the line A7-A8 shown in Fig. 2.

[0021] The substrate 10 includes an insulating layer 11. As shown in FIGS. 3(a) to 3(d), the substrate 10 includes a plurality of conductive portions 12. At least a portion of each of the conductive portions 12 is provided in the substrate 10 (in the insulating layer 11). The above-mentioned plurality of coils C are also provided in the insulating layer 11.

[0022] An opening 13 is provided in the lower surface 10s of the substrate 10. The opening 13 is an opening provided in the insulating layer 11. The conductive portion 12 has a terminal portion 14 located in the opening 13. The terminal portion 14 is exposed from the substrate 10 at the opening 13. The terminal portion 14 may protrude downward from the lower surface 10s.

[0023] 3(a), an opening 13a is provided in the lower surface 10s. The conductive portions 12 include a first conductive portion 12a. The first conductive portion 12a has a first terminal portion 14a located in the opening 13a. 3B, an opening 13b is provided in the lower surface 10s. The conductive portions 12 include a second conductive portion 12b. The second conductive portion 12b has a second terminal portion 14b located in the opening 13b. 3(c), an opening 13c is provided in the lower surface 10s. The conductive portions 12 include a third conductive portion 12c. The third conductive portion 12c has a third terminal portion 14c located in the opening 13c. 3(d), an opening 13d is provided in the lower surface 10s. The conductive portions 12 include a fourth conductive portion 12d. The fourth conductive portion 12d has a fourth terminal portion 14d located in the opening 13d.

[0024] 2, in a plan view, the second terminal portion 14b and the fourth terminal portion 14d are on the opposite side to the first terminal portion 14a and the third terminal portion 14c when viewed from the center CX in the X direction of the substrate 10. In addition, in a plan view, the third terminal portion 14c and the fourth terminal portion 14d are on the opposite side to the first terminal portion 14a and the second terminal portion 14b when viewed from the center CY in the Y direction of the substrate 10.

[0025] More specifically, the first terminal 14a is located at the first corner cr1, the second terminal 14b is located at the second corner cr2, the third terminal 14c is located at the third corner cr3, and the fourth terminal 14d is located at the fourth corner cr4.

[0026] As shown in FIG. 2, in this example, in a planar view, the first lead 21 extends from the first terminal portion 14a and the third side s3 in the +Y direction (the direction from the fourth side s4 to the third side s3), the second lead 22 extends from the second terminal portion 14b and the third side s3 in the +Y direction, the third lead 23 extends from the third terminal portion 14c and the fourth side s4 in the -Y direction (the opposite direction to the +Y direction), and the fourth lead 24 extends from the fourth terminal portion 14d and the fourth side s4 in the -Y direction.

[0027] In the example shown in FIG. 3(a) to FIG. 3(d), the first to fourth conductive parts 12a to 12d are covered with the insulating layer 11 except for the terminal part 14. For example, the entire surfaces of the first to fourth conductive parts 12a to 12d except for the terminal part 14 are in contact with the insulating layer 11. The first to fourth conductive parts 12a to 12d may be electrically insulated from other conductive parts and elements provided in the substrate 10. For example, the first to fourth conductive parts 12a to 12d may be electrically insulated from a plurality of coils C. In other words, the first to fourth conductive parts 12a to 12d may be conductive parts 12 that are not used for conduction (where no electrical signal flows). The first to fourth conductive parts 12a to 12d may not be in contact with anything in the substrate 10 except for the insulating layer 11.

[0028] The lead 20 is connected to the terminal portion 14 of the conductive portion 12 by the solder 40. That is, the upper surface of the solder 40 contacts the lower surface of the terminal portion 14. Also, the lower surface of the solder 40 contacts the upper surface of the lead 20. The lead 20 and the conductive portion 12 are electrically connected via the solder 40.

[0029] For example, in Figures 3(a) to 3(d), the first lead 21 is connected to the first terminal portion 14a by solder 40a, the second lead 22 is connected to the second terminal portion 14b by solder 40b, the third lead 23 is connected to the third terminal portion 14c by solder 40c, and the fourth lead 24 is connected to the fourth terminal portion 14d by solder 40d.

[0030] The first to fourth leads 21 to 24 may be electrically insulated from the first semiconductor chip 61 and the second semiconductor chip 62. The first to fourth leads 21 to 24 may be electrically insulated from elements (such as a plurality of coils C) provided in the substrate 10. In other words, the first to fourth leads 21 to 24 may be leads 20 that are not used for conduction (through which no electrical signal flows). For example, the first to fourth leads 21 to 24 may not be in contact with any conductive member other than the solder 40. The potentials of the first to fourth leads 21 to 24 and the first to fourth conductive portions 12a to 12d may be electrically floating.

[0031] 4A and 4B are schematic cross-sectional views illustrating the isolator according to the embodiment. Fig. 4(a) corresponds to a cross section taken along line A9-A10 shown in Fig. 1. Fig. 4(b) corresponds to an enlarged view of the vicinity of region R1 shown in Fig. 4(a).

[0032] 4B, the conductive portions 12 include a signal conductive portion 12sa. The signal conductive portion 12sa has a terminal portion 14 (signal terminal portion 14sa) located in an opening 13 (signal opening 13sa) provided in the lower surface 10s of the substrate 10.

[0033] The signal conductive portion 12sa is electrically connected to one end C1a of the first coil C1. The signal lead 28 (signal lead 28a) is connected to the signal terminal portion 14sa by solder 40 (solder 41a). Thus, the signal lead 28a is electrically connected to the first coil C1.

[0034] 4A, the upper surface of the signal lead 28a is connected to the upper surface (pad) of the first semiconductor chip 61 by the wire W1. As a result, the first coil C1 is electrically connected to the first semiconductor chip 61.

[0035] In addition, in a plan view, the signal lead 28a extends from the signal terminal portion 14sa and the first side s1 of the substrate 10 (see FIG. 2) toward the first semiconductor chip 61 along the X direction.

[0036] For example, as shown in FIG. 4(b), the substrate 10 is further provided with an upper conductive portion 52a. At least a portion of the upper conductive portion 52a is disposed in the substrate 10 (in the insulating layer 11). The upper conductive portion 52a has a terminal portion 54a located in an opening portion 53a provided in the upper surface 10t of the substrate 10. The upper conductive portion 52a is electrically connected to one end portion C2a of the second coil C2. The terminal portion 54a of the upper conductive portion 52a is connected to the upper surface (pad) of the second semiconductor chip 62 by a wire W3. As a result, the second coil C2 is electrically connected to the second semiconductor chip 62.

[0037] 5A and 5B are schematic cross-sectional views illustrating the isolator according to the embodiment. Fig. 5(a) corresponds to a cross section taken along line A11-A12 shown in Fig. 1. Fig. 5(b) corresponds to an enlarged view of the vicinity of region R2 shown in Fig. 5(a).

[0038] 5B, the conductive portions 12 include a signal conductive portion 12sb. The signal conductive portion 12sb has a terminal portion 14 (signal terminal portion 14sb) located in an opening 13 (signal opening 13sb) provided in the lower surface 10s of the substrate 10.

[0039] The signal conductive portion 12sb is electrically connected to the other end C1b of the first coil C1. The signal lead 28 (signal lead 28b) is connected to the signal terminal portion 14sb by solder 40 (solder 41b). Thus, the signal lead 28b is electrically connected to the first coil C1.

[0040] 5(a), the upper surface of the signal lead 28b is connected to the upper surface (pad) of the first semiconductor chip 61 by the wire W1. As a result, the first coil C1 is electrically connected to the first semiconductor chip 61.

[0041] In addition, in a plan view, the signal lead 28b extends from the signal terminal portion 14sb and the first side s1 of the substrate 10 (see FIG. 2) toward the first semiconductor chip 61 along the X direction.

[0042] 6A and 6B are schematic cross-sectional views illustrating the isolator according to the embodiment. Fig. 6(a) corresponds to a cross section taken along line A13-A14 shown in Fig. 1. Fig. 6(b) corresponds to an enlarged view of the vicinity of region R3 shown in Fig. 6(a).

[0043] As shown in FIG. 6(b), the substrate 10 is further provided with an upper conductive portion 52b. At least a portion of the upper conductive portion 52b is disposed in the substrate 10 (in the insulating layer 11). The upper conductive portion 52b has a terminal portion 54b located in an opening portion 53b provided in the upper surface 10t of the substrate 10. The upper conductive portion 52b is electrically connected to the other end portion C2b of the second coil C2. The terminal portion 54b of the upper conductive portion 52b is connected to the upper surface (pad) of the second semiconductor chip 62 by a wire W3. As a result, the second coil C2 is electrically connected to the second semiconductor chip 62.

[0044] 6(a), a support lead 29 may be provided below the substrate 10. The support lead 29 is located below the upper conductive portion 52b. The support lead 29 can support the substrate 10 from below when connecting the wire W3 to the upper conductive portion 52b. The support lead 29 does not need to be connected to the conductive portion by solder.

[0045] FIG. 7 is a schematic diagram illustrating the circuit configuration of the isolator according to the embodiment. In the isolator 100, for example, a transmitting circuit (primary circuit) and a receiving circuit (secondary circuit) are insulated from each other. A coil connected to the transmitting circuit and a coil connected to the receiving circuit are magnetically coupled. This allows a signal to be transmitted from the transmitting circuit to the receiving circuit.

[0046] In this example, the isolator 100 is an isolator with two channels. The isolator 100 transmits a signal from a transmitting circuit to a receiving circuit for each channel while isolating the transmitting circuit from the receiving circuit. Note that the isolator 100 may be an isolator with one channel or an isolator with three or more channels.

[0047] The isolator 100 includes a transmission circuit TC. One transmission circuit TC corresponds to one channel. In this example, two transmission circuits TC (a first transmission circuit TCa and a second transmission circuit TCb) are provided. The first transmission circuit TCa is a circuit that transmits a signal corresponding to the first channel. The second transmission circuit TCb is a circuit that transmits a signal corresponding to the second channel.

[0048] Each transmission circuit TC includes an external terminal 33, an electronic circuit 61a, a transmission circuit 61b, a first coil C1, a second coil C2, a reception circuit 62a, an electronic circuit 62b, and an external terminal .

[0049] The electronic circuit 61a and the transmission circuit 61b are formed on a first semiconductor chip 61. The first semiconductor chip 61 is, for example, an IC (Integrated Circuit) chip. The first semiconductor chip 61 corresponds to a transmission side circuit. For example, a power supply voltage and a ground voltage are supplied to the first semiconductor chip 61. As described above in FIG. 4(b) and FIG. 5(b), the transmission circuit 61b is electrically connected to one end C1a and the other end C1b of the first coil C1 via the wire W1 and the signal lead 28.

[0050] The receiving circuit 62a and the electronic circuit 62b are formed on a second semiconductor chip 62. The second semiconductor chip 62 is, for example, an IC chip. The second semiconductor chip 62 corresponds to a receiving circuit. For example, a power supply voltage and a ground voltage are supplied to the second semiconductor chip 62. As described above in FIG. 4(b) and FIG. 6(b), the receiving circuit 62a is electrically connected to one end C2a and the other end C2b of the second coil C2 via the wire W3.

[0051] An input signal IN is input from the outside to the external terminal 33. The electronic circuit 61a includes, for example, a modulation circuit. The electronic circuit 61a modulates (for example, amplitude shift keying) the input signal IN received from the outside via the external terminal 33, and transmits the modulated signal Sig1 to the transmission circuit 61b.

[0052] The transmission circuit 61b includes, for example, an oscillator OSC and a power amplifier PA. The oscillator OSC generates an inverted signal of the signal Sig1 based on the signal Sig1 received from the electronic circuit 61a, and transmits the generated inverted signal to the power amplifier PA. The oscillator OSC transmits the received signal Sig1 to the power amplifier PA as a non-inverted signal.

[0053] The power amplifier PA amplifies the non-inverted signal received from the oscillator OSC and transmits the amplified non-inverted signal to one end of the first coil C1. The power amplifier PA amplifies the inverted signal received from the oscillator OSC and transmits the amplified inverted signal to the other end of the first coil C1.

[0054] When the first coil C1 receives an inverted signal and a non-inverted signal from the power amplifier PA, a current corresponding to the received inverted signal and non-inverted signal flows through the first coil C1. This generates a magnetic field in the first coil C1. Then, the magnetic flux passing through the second coil C2 changes. This causes a current (induced current) to flow through the second coil C2.

[0055] Based on the current flowing through the second coil C2, a non-inverted signal is input from one end of the second coil C2 to the receiving circuit 62a, and an inverted signal is input from the other end of the second coil C2 to the receiving circuit 62a.

[0056] The receiving circuit 62a includes, for example, an amplifier AMP and a detection circuit DEC. The amplifier AMP amplifies the inverted signal received from the second coil C2 and transmits the amplified inverted signal to the detection circuit DEC. The amplifier AMP amplifies the non-inverted signal received from the second coil C2 and transmits the amplified non-inverted signal to the detection circuit DEC.

[0057] The detector circuit DEC detects the non-inverted signal from the non-inverted signal and the inverted signal received from the amplifier AMP. The detector circuit DEC transmits the detected non-inverted signal as a signal Sig6 to the electronic circuit 62b.

[0058] The electronic circuit 62b includes, for example, a demodulation circuit. The electronic circuit 62b demodulates the signal Sig6 received from the detection circuit DEC, and outputs the demodulated signal as an output signal OUT via the external terminal 34 to the outside.

[0059] In this way, the isolator 100 (transmission circuit TC) converts the signal transmitted to the first coil C1 by the first semiconductor chip 61 (transmission circuit) into magnetic energy via the first coil C1. Then, the isolator 100 converts the magnetic energy again into a signal (electrical signal) via the second coil C2, and transmits the converted signal to the second semiconductor chip 62 (reception circuit). The second semiconductor chip 62 outputs an output signal corresponding to the signal received from the second coil C2. In this way, the isolator 100 transmits a signal from the first semiconductor chip 61 to the second semiconductor chip 62 via multiple coils while isolating the first semiconductor chip 61 from the second semiconductor chip 62.

[0060] For example, a low-voltage circuit driven by a low voltage may be connected to the first semiconductor chip 61, and a high-voltage circuit driven by a voltage higher than that of the low-voltage circuit may be connected to the second semiconductor chip 62. Note that the circuit configuration illustrated in Fig. 7 is merely an example, and the embodiment is not limited thereto. The embodiment may be one in which signals can be transmitted between the first semiconductor chip 61 and the second semiconductor chip 62 via a plurality of coils while the first semiconductor chip 61 and the second semiconductor chip 62 are insulated from each other.

[0061] In this example, the first semiconductor chip 61 on the transmitting side is electrically connected to the first coil C1 via the lead 20 (signal lead 28). On the other hand, the second semiconductor chip 62 on the receiving side is electrically connected to the second coil C2 without the lead 20.

[0062] The materials of each element of the embodiment will be described. The leads 20 (first to fourth leads 21 to 24, signal lead 28), the support lead 29, the die pad 31, the die pad 32, the external terminal 33 and the external terminal 34 are thin plates containing a metal such as copper. The wires W1 to W4 are metal wires containing gold (Au), silver (Ag) or copper (Cu), for example. The first coil C1 and the second coil C2 contain a metal such as copper. The insulating layer 11 of the substrate 10 contains, for example, a resin. More specifically, the insulating layer 11 contains polyimide or epoxy resin. The substrate 10 is, for example, an FPC (Flexible printed circuits) substrate or a glass epoxy substrate. The substrate 10 may be flexible. The insulating section 36 (sealing resin) contains, for example, an epoxy resin.

[0063] The structure and operation of the isolator 100 according to the embodiment have been described above. However, in an isolator, defects such as rotation or misalignment (rotation or translation in the XY plane) may occur in the substrate that includes the coil. When such defects occur, they may cause defects in the electrical connections of the wires or solder, for example. For example, short circuits or open circuits may occur. In contrast, in the isolator 100 according to the embodiment, the first to fourth leads 21 to 24 are connected to the terminal portion 14 of the substrate 10 by soldering. By connecting the leads at a plurality of positions in this manner, it is possible to suppress at least one of rotation and positional deviation of the substrate 10. This makes it possible to suppress electrical defects from occurring between the first to fourth leads 21 to 24 and the terminal portion 14 of the substrate 10, thereby making it possible to obtain an isolator 100 with high reliability.

[0064] 8A and 8B are schematic cross-sectional views illustrating a portion of the isolator according to the embodiment. In the manufacture of the isolator 100, the solder 40 connects the leads 20 and the terminals 14, for example, by a reflow process. That is, for example, the multiple terminals 14 are mounted on the multiple leads 20, respectively, via the solder 40. Then, the multiple leads 20 on which the terminals 14 are mounted are heated, for example, in a reflow furnace. The solder is heated to melt, and then cooled to solidify, thereby solder-joining the leads 20 and the terminals 14. FIG. 8(a) shows the state of the solder 40 before heating in the manufacture of the isolator 100. FIG. 8(b) shows an example of the state of the solder 40 after heating.

[0065] When the solder 40 is heated, the insulating layer 11 of the substrate 10 repels the solder 40. On the other hand, since the solder 40 is easily wetted by metal, when the solder 40 is heated, the solder 40 may flow on the leads 20 and spread as shown in FIG. 8(b). When the solder 40 flows, a force is applied to the substrate 10. Therefore, the substrate 10 may rotate or shift in position. In response to this, the isolator 100 according to the embodiment is provided with first to fourth terminals 14a to 14d to which the first to fourth leads 21 to 24 are connected by solder. This makes it possible to further suppress at least one of the rotation and the shift in position of the substrate 10. For example, a force due to the surface tension of the molten solder acts on the substrate 10. For example, the forces from the solder 40 pull the substrate 10 to balance each other. For example, at least a part of the force applied to the substrate 10 by the solder 40 on the multiple leads 20 is balanced.

[0066] It is desirable to provide each of the first terminal portion 14a to the fourth terminal portion 14d near a corner (within the range of each of the first to fourth corner portions cr1 to cr4) of the substrate 10. This makes it possible to further suppress the Θ rotation of the substrate 10 during solder reflow. As shown in FIG. 8(b), the distance d1 from the outer edge of the substrate 10 to the terminal portion 14 may be longer than the diameter r14 (the maximum length in the XY plane) of the terminal portion 14. This makes it easier to arrange the terminal portion 14 within the lower surface 10s of the substrate 10. Alternatively, the distance d1 may be shorter than the diameter r14. For example, this can prevent the terminal portion 14 from interfering with other wiring or the like provided on the substrate 10. The distance d1 is, for example, 50 μm (micrometers) or more. In a plan view, the first terminal portion 14a to the fourth terminal portion 14d (and the first to fourth corner portions cr1 to cr4) may be located on diagonals of the substrate 10, respectively.

[0067] For example, at least some of the first terminal portion 14a to the fourth terminal portion 14d may be terminal portions that are not used for electrical continuity. This makes it easier to design the arrangement of the first terminal portion 14a to the fourth terminal portion 14d, for example. By providing terminal portions that are not used for electrical continuity, it is possible to make up for the lack of terminals when suppressing the Θ rotation of the substrate 10. At least some of the four terminal portions (14a, 14b, 14c, 14d) do not necessarily have to be terminals not used for electrical continuity. At least some of the four terminal portions (14a, 14b, 14c, 14d) may be electrically connected to the first semiconductor chip 61 or the second semiconductor chip 62 and transmit electrical signals flowing to the first semiconductor chip 61 or the second semiconductor chip 62.

[0068] 9A and 9B are schematic plan views illustrating a part of an isolator according to a modification of the embodiment. Fig. 9(b) corresponds to the cross section taken along line A15-A16 in Fig. 9(a). The isolator 101 according to the embodiment shown in Fig. 9(a) and Fig. 9(b) differs from the above-described isolator 100 in that a fifth lead 25 and a fifth conductive portion 12e are provided. The isolator 101 is otherwise similar to the isolator 100.

[0069] 9B, the conductive portions 12 further include a fifth conductive portion 12e. The fifth conductive portion 12e has a fifth terminal portion 14e located in an opening 13e provided in the lower surface 10s of the substrate 10.

[0070] 9A, in this example, the fifth lead 25 extends in the +Y direction from the fifth terminal portion 14e and the third side s3 in a plan view. In this example, the fifth lead 25 overlaps with the center of the third side s3 in the X direction.

[0071] In the example shown in FIG. 9(b), the fifth conductive portion 12e is covered with the insulating layer 11 except for the fifth terminal portion 14e. For example, the entire surface of the fifth conductive portion 12e except for the fifth terminal portion 14e is in contact with the insulating layer 11. The fifth conductive portion 12e may be electrically insulated from other conductive portions and elements provided in the substrate 10. For example, the fifth conductive portion 12e may be electrically insulated from a plurality of coils C. In other words, the fifth conductive portion 12e may be a conductive portion 12 that is not used for conduction. The fifth conductive portion 12e may not be in contact with anything in the substrate 10 except for the insulating layer 11.

[0072] The multiple leads 20 further include a fifth lead 25. The fifth lead 25 is connected to the fifth terminal portion 14e by the solder 40e. The fifth lead 25 may be electrically insulated from the first semiconductor chip 61 and the second semiconductor chip 62. The fifth lead 25 may be electrically insulated from elements (such as the multiple coils C) provided in the substrate 10. In other words, the fifth lead 25 may be a lead 20 that is not used for conduction. For example, the fifth lead 25 may not be in contact with any conductive member other than the solder 40. The potential of the fifth lead 25 and the fifth conductive portion 12e may be electrically floating.

[0073] In this manner, the fifth terminal portion 14e to which the fifth lead 25 is connected by solder may be provided. This cancels out at least a part of the force acting on the terminal portions (signal terminal portion 14sa, signal terminal portion 14sb) used for electrical continuity, which moves the substrate 10 when the solder spreads. This makes it possible to further suppress at least one of the rotation and the positional deviation of the substrate 10.

[0074] In the embodiment, the number of leads 20 and conductive portions 12 not used for conduction is not limited to four or five, but is at least one or more, and may be six or more.

[0075] FIG. 10 is a schematic plan view illustrating a part of an isolator according to a modified example of the embodiment. 10 differs from the previously described isolator 101 in the width of the leads 20. Otherwise, the isolator 102 is similar to the isolator 101.

[0076] In the embodiment, the width of the lead 20 can be adjusted as appropriate. The width of the lead 20 is the length of the lead 20 in the short direction in a plan view. In the isolator 102, the width W25 (length in the X direction) of the fifth lead 25 is different from the width W21 (length in the X direction) of the first lead 21.

[0077] 11A and 11B are schematic plan views illustrating the periphery of the leads of the isolator according to the embodiment. Fig. 11(a) shows a case where the width W20 of the lead 20 is narrow. Fig. 11(b) shows a case where the width W20 of the lead 20 is wider than that in Fig. 11(a). As shown in Fig. 11(a) and Fig. 11(b), for example, when the width W20 is wide, the width over which the solder 40 wets and spreads is wide, and when the width W20 is narrow, the width over which the solder 40 wets and spreads is narrow.

[0078] For example, when the width W20 is wide, the force that moves the substrate 10 when the solder 40 wets and spreads is large, and when the width W20 is narrow, the force that moves the substrate 10 when the solder 40 wets and spreads is small. By adjusting the width W20, at least a part of the force that moves the substrate 10 when the solder 40 wets and spreads, which is applied to the terminal portion used for conduction, is offset. At least one of the rotation and positional deviation of the substrate 10 can be further suppressed.

[0079] 10, the width W25 of the fifth lead 25 is wider than the width W21 of the first lead 21. However, the width W25 may be narrower than the width W21. Also, the width W25 may be the same as the width W21.

[0080] 10, the width W21 of the first lead 21, the width W22 (length in the X direction) of the second lead 22, the width W23 (length in the X direction) of the third lead 23, and the width W24 (length in the X direction) of the fourth lead 24 are the same. Without being limited to this, the widths W21, W22, W23, and W24 may be different from each other. For example, the width W20 of the lead 20 can be adjusted depending on the arrangement of the lead 20.

[0081] For example, the multiple leads 20 include, in a planar view, a lead 20 (referred to as a "first-side lead") arranged on the first side s1 of the substrate 10 and a lead 20 (referred to as a "second-side lead") arranged on the second side s2 of the substrate 10.

[0082] The first-side leads are leads 20 that extend from the outer edge of the substrate 10 on the first side s1 side of the center CX in the X direction of the substrate 10 in a plan view. More specifically, in the example of Fig. 10, the second lead 22, the fourth lead 24, and the signal lead 28 are the first-side leads. The second-side lead is a lead 20 that extends from the outer edge of the substrate 10 on the second side s2 side of the center CX in the X direction of the substrate 10 in a plan view. More specifically, in the example of Fig. 10, the first lead 21 and the third lead 23 are second-side leads.

[0083] The number of the first side leads and the number of the second side leads may be different from each other. In the example of FIG. 10, the number of the second side leads is less than the number of the first side leads. In such a case, for example, the width of at least one of the second side leads may be wider than the width of at least one of the first side leads. For example, the width W21 may be wider than each of the width W22 and the width W24. Also, for example, the width W23 may be wider than each of the width W22 and the width W24. However, this is not limited thereto, and the width W21 may be narrower than each of the width W22 and the width W24, and the width W23 may be narrower than each of the width W22 and the width W24.

[0084] Furthermore, for example, the width W28 (length in the Y direction) of the signal lead 28 may be narrower than at least one of the width W21, the width W22, the width W23, and the width W24.

[0085] The fifth lead 25 overlaps with the center of the third side s3 in the Z direction and extends from the third side s3 in the Y direction. This is not limiting, and for example, the fifth lead 25 may be disposed on the second side s2 side. In other words, the fifth lead 25 may be a second side lead. For example, as shown by the two-dot chain line in FIG. 10, the fifth lead 25 may be disposed so as to overlap with the second side s2 in the Z direction and extend from the second side s2 in the X direction. In this case, the fifth terminal portion 14e is disposed close to the second side s2.

[0086] 12A and 12B are schematic plan views illustrating a part of the isolator according to the embodiment. 12(a) and 12(b) differs from the above-described isolator 100 in that an insulating member 43 (e.g., insulating tape) is provided. In other respects, the isolator 103 is similar to the isolator 100.

[0087] FIG. 12(b) corresponds to the cross section taken along line A17-A18 in FIG. 12(a). As shown in FIG. 12(b), the top surface 20t of the lead 20 includes a connection region 20ta and an adjacent region 20tb. The connection region 20ta is a region that contacts the solder 40. The connection region 20ta is located below the substrate 10. The connection region 20ta overlaps with the terminal portion 14 and the substrate 10 in the Z direction. The adjacent region 20tb is a region that is adjacent to the connection region 20ta and does not contact the solder 40. The adjacent region 20tb may or may not include a portion that overlaps with the substrate 10 in the Z direction.

[0088] The insulating member 43 is provided on the adjacent region 20tb. For example, an insulating tape is attached onto the adjacent region 20tb. The insulating member 43 includes a resin such as polyimide. By providing the insulating member 43, it is possible to suppress the spreading of the solder 40. At least one of the rotation and the positional deviation of the substrate 10 can be further suppressed.

[0089] 12(b), the end of the insulating member 43 may overlap with the substrate 10 in the Z direction. The end of the insulating member 43 is in contact with the solder 40, for example.

[0090] For example, the insulating member 43 is provided on at least one of the first to fourth leads 21 to 24. When the first to fourth leads 21 to 24 are leads that are not used for conduction, there are few design constraints and the insulating member 43 can be arranged relatively easily. For example, as shown in FIG. 12(a), one insulating member 43 may be continuous from above the first lead 21 to above the second lead 22. For example, another insulating member 43 may be continuous from above the third lead 23 to above the fourth lead 24. The insulating member 43 covers each lead 20, to which the insulating member 43 is attached, from one end p1 to the other end p2 in the width direction.

[0091] 13A and 13B are a schematic cross-sectional view and a schematic plan view illustrating a part of the isolator according to the embodiment. An isolator 104 shown in Figures 13(a) and 13(b) differs from the above-described isolator 100 in the shape of the lead 20. Otherwise, the isolator 104 is similar to the isolator 100. Figure 13(a) corresponds to a cross section similar to Figure 3(a). Figure 13(b) is a plan view of the lead 20 shown in Figure 13(a) as viewed along the Z direction.

[0092] As shown in FIG. 13(a), the upper surface 20t of the lead 20 (for example, the first lead 21) includes a connection region 20ta in contact with the solder 40, an adjacent region 20tb not in contact with the solder 40, and a step 20tc between the connection region 20ta and the adjacent region 20tb. The step 20tc extends along the Z direction and is a connection surface that connects the connection region 20ta and the adjacent region 20tb. The lower surface 20s of the lead 20 may be flat. The lead 20 is thinner in a portion having the adjacent region 20tb than in a portion including the connection region 20ta. As shown in FIG. 13(b), the step 20tc continues from one end p1 to the other end p2 in the width direction of the lead 20.

[0093] By providing the step portion 20tc, surface tension acts during reflow, making it difficult for the solder 40 to flow out. This makes it possible to further suppress at least one of rotation and displacement of the substrate 10.

[0094] Such a step portion 20tc is provided, for example, in at least one of the first to fourth leads 21 to 24. On the other hand, the upper surface 20t of the signal lead 28 may be flat without including the step portion 20tc. The thickness of the signal lead 28 may be constant.

[0095] The embodiment may include the following configurations (e.g., technical solutions). (Configuration 1) A substrate having an upper surface extending along a plane perpendicular to a first direction and a lower surface opposite to the upper surface, the substrate including a plurality of coils and a plurality of conductive portions, the lower surface has a quadrangular shape having a first corner portion, a second corner portion, a third corner portion, and a fourth corner portion in a plan view along the first direction, the plurality of coils are provided inside the substrate and include a first coil and a second coil facing the first coil; the plurality of conductive portions include a first conductive portion, a second conductive portion, a third conductive portion, and a fourth conductive portion, the first conductive portion has a first terminal portion located in a first opening portion provided in the first corner portion, the second conductive portion has a second terminal portion located in a second opening portion provided in the second corner portion, the third conductive portion has a third terminal portion located in a third opening portion provided in the third corner portion, the fourth conductive portion has a fourth terminal portion located in a fourth opening provided in the fourth corner portion; and a first lead connected to the first terminal portion by solder, a second lead connected to the second terminal portion by solder, a third lead connected to the third terminal portion by solder, and a fourth lead connected to the fourth terminal portion by solder, the leads including a metal; An isolator comprising: (Configuration 2) the first coil is electrically connected to a first semiconductor chip; the second coil is electrically connected to a second semiconductor chip; each of the first conductive portion, the second conductive portion, the third conductive portion, and the fourth conductive portion is electrically insulated from the plurality of coils; 2. The isolator of configuration 1, wherein the first lead, the second lead, the third lead, and the fourth lead are electrically insulated from the first semiconductor chip and the second semiconductor chip, respectively. (Configuration 3) A substrate having an upper surface extending along a plane perpendicular to a first direction and a lower surface opposite to the upper surface, the substrate including a plurality of coils and a plurality of conductive portions, the plurality of coils include a first coil provided in the substrate and electrically connected to a first semiconductor chip, and a second coil facing the first coil and electrically connected to a second semiconductor chip, the plurality of conductive portions include a first conductive portion, a second conductive portion, a third conductive portion, and a fourth conductive portion, the first conductive portion has a first terminal portion located in a first opening provided on the lower surface, the second conductive portion has a second terminal portion located in a second opening provided on the lower surface, the third conductive portion has a third terminal portion located in a third opening provided on the lower surface, the fourth conductive portion has a fourth terminal portion located in a fourth opening provided on the lower surface, each of the first conductive portion, the second conductive portion, the third conductive portion, and the fourth conductive portion is electrically insulated from the plurality of coils; In a plan view along the first direction, the second terminal portion and the fourth terminal portion are located on an opposite side to the first terminal portion and the third terminal portion when viewed from a center of the substrate in a second direction perpendicular to the first direction, a substrate, in a plan view along the first direction, the third conductive portion and the fourth conductive portion are located on an opposite side to the first conductive portion and the second conductive portion when viewed from a center of the substrate in a third direction perpendicular to the first direction and the second direction; a first lead connected to the first terminal portion by solder, a second lead connected to the second terminal portion by solder, a third lead connected to the third terminal portion by solder, and a fourth lead connected to the fourth terminal portion by solder, wherein each of the first lead, the second lead, the third lead, and the fourth lead is a plurality of leads including a metal and electrically insulated from the first semiconductor chip and the second semiconductor chip; An isolator comprising: (Configuration 4) the plurality of conductive portions includes a fifth conductive portion electrically insulated from the plurality of coils, the fifth conductive portion has a fifth terminal portion located in a fifth opening provided on the lower surface, the plurality of leads includes a fifth lead connected to the fifth terminal portion by soldering, The isolator of configuration 2 or 3, wherein the fifth lead is electrically insulated from the first semiconductor chip and the second semiconductor chip. (Configuration 5) 5. The isolator of configuration 4, wherein the width of the fifth lead is different from the width of the first lead. (Configuration 6) the plurality of conductive portions include a signal conductive portion, the signal conductive portion has a signal terminal portion located in an opening provided on the lower surface, the plurality of leads include a signal lead electrically connected to the signal terminal portion, the first coil is electrically connected to the first semiconductor chip via the signal conductive portion and the signal lead; 6. The isolator according to any one of configurations 2 to 5, wherein the first lead has a width greater than a width of the signal lead. (Configuration 7) 7. The isolator according to any one of configurations 1 to 6, wherein a width of the first lead is different from a width of the second lead. (Configuration 8) Further comprising an insulating member; an upper surface of the first lead includes a connection region in contact with the solder and an adjacent region adjacent to the connection region and not in contact with the solder; The isolator according to any one of configurations 1 to 7, wherein the insulating member is provided on the adjacent region. (Configuration 9) The isolator of any one of configurations 1 to 7, wherein the upper surface of the first lead includes a connection region in contact with solder, an adjacent region not in contact with solder, and a step portion between the connection region and the adjacent region.

[0096] According to the embodiment, an isolator capable of suppressing the occurrence of defects can be provided.

[0097] In this specification, "electrically connected" includes connection through direct contact as well as connection via other conductive members.

[0098] Although some embodiments of the present invention have been illustrated above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, modifications, etc. can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are included in the scope of the invention and its equivalents described in the claims. In addition, the above-mentioned embodiments can be implemented in combination with each other. [Explanation of symbols]

[0099] 10: Substrate 10s: Bottom side 10t:Top surface 11: Insulating layer 12: Conductive part 12a~12e: 1st~5th conductive part 12sa, 12sb: Signal conductive part 13, 13a~13e: Opening 13sa, 13sb: Signal opening 14:Terminal part 14a~14e: 1st~5th terminal section 14sa, 14sb: Signal terminal section 20: Lead 20s: Bottom side 20t:Top surface 20ta: Connection area 20tb: adjacent area 20tc: Step 21-25: 1st to 5th leads 28, 28a, 28b: signal leads 29: Supporting Lead 31, 32: Die pad 33, 34: External terminals 36: Insulation section 40, 40a to 40e, 41a, 41b: solder 43: Insulating material 52a, 52b: Upper conductive part 53a, 53b: Opening 54a, 54b: Terminal section 61: First semiconductor chip 61a:Electronic circuit 61b: Transmitting circuit 62: Second semiconductor chip 62a: Receiving circuit 62b:Electronic circuit 100~104: Isolator AMP: Amplifier C: Coil C1: First coil C1a: One end C1b: Other end C2: Second coil C2a: One end C2b: Other end CX: Central CY:Central DEC: Detection circuit E: Element IN: Input signal OSC: Oscillator OUT: Output signal PA: Power amplifier R1~R3: Area Sig1, Sig6: Signal TC: Transmission circuit TCa: First transmission circuit TCb: Second transmission circuit W1~W4: Wires W20~W25, W28: Width cr1~cr4: 4th corner d1: distance p1: one end p2: other end p13, p14, p23, p24: Intersection r14: diameter s1~s4: Sides 1~4

Claims

1. A substrate having an upper surface extending along a plane perpendicular to a first direction and a lower surface opposite to the upper surface, the substrate including a plurality of coils and a plurality of conductive portions, the lower surface has a quadrangular shape having a first corner portion, a second corner portion, a third corner portion, and a fourth corner portion in a plan view along the first direction, the plurality of coils are provided inside the substrate and include a first coil and a second coil facing the first coil, the plurality of conductive portions include a first conductive portion, a second conductive portion, a third conductive portion, and a fourth conductive portion, the first conductive portion has a first terminal portion located in a first opening portion provided in the first corner portion, the second conductive portion has a second terminal portion located in a second opening portion provided in the second corner portion, the third conductive portion has a third terminal portion located in a third opening portion provided in the third corner portion, a substrate, the fourth conductive portion having a fourth terminal portion located in a fourth opening portion provided in the fourth corner portion; a first lead connected to the first terminal portion by solder, a second lead connected to the second terminal portion by solder, a third lead connected to the third terminal portion by solder, and a fourth lead connected to the fourth terminal portion by solder, the leads including a metal; An isolator comprising:

2. the first coil is electrically connected to a first semiconductor chip; the second coil is electrically connected to a second semiconductor chip; each of the first conductive portion, the second conductive portion, the third conductive portion, and the fourth conductive portion is electrically insulated from the plurality of coils; The isolator according to claim 1 , wherein the first lead, the second lead, the third lead, and the fourth lead are electrically insulated from the first semiconductor chip and the second semiconductor chip, respectively.

3. A substrate having an upper surface extending along a plane perpendicular to a first direction and a lower surface opposite to the upper surface, the substrate including a plurality of coils and a plurality of conductive portions, the plurality of coils include a first coil provided in the substrate and electrically connected to a first semiconductor chip, and a second coil facing the first coil and electrically connected to a second semiconductor chip, the plurality of conductive portions include a first conductive portion, a second conductive portion, a third conductive portion, and a fourth conductive portion, the first conductive portion has a first terminal portion located in a first opening provided on the lower surface, the second conductive portion has a second terminal portion located in a second opening portion provided on the lower surface, the third conductive portion has a third terminal portion located in a third opening provided on the lower surface, the fourth conductive portion has a fourth terminal portion located in a fourth opening provided on the lower surface, each of the first conductive portion, the second conductive portion, the third conductive portion, and the fourth conductive portion is electrically insulated from the plurality of coils; In a plan view along the first direction, the second terminal portion and the fourth terminal portion are located on an opposite side to the first terminal portion and the third terminal portion when viewed from a center of the substrate in a second direction perpendicular to the first direction, a substrate, in a plan view along the first direction, the third conductive portion and the fourth conductive portion are located on an opposite side to the first conductive portion and the second conductive portion when viewed from a center of the substrate in a third direction perpendicular to the first direction and the second direction; a first lead connected to the first terminal portion by solder, a second lead connected to the second terminal portion by solder, a third lead connected to the third terminal portion by solder, and a fourth lead connected to the fourth terminal portion by solder, wherein each of the first lead, the second lead, the third lead, and the fourth lead is a plurality of leads including a metal and electrically insulated from the first semiconductor chip and the second semiconductor chip; An isolator comprising:

4. the plurality of conductive portions includes a fifth conductive portion electrically insulated from the plurality of coils, The fifth conductive portion has a fifth terminal portion located in a fifth opening provided on the lower surface, the plurality of leads includes a fifth lead connected to the fifth terminal portion by soldering, The isolator according to claim 2 , wherein the fifth lead is electrically insulated from the first semiconductor chip and the second semiconductor chip.

5. The isolator of claim 4 , wherein a width of the fifth lead is different than a width of the first lead.

6. the plurality of conductive portions include a signal conductive portion, the signal conductive portion has a signal terminal portion located in an opening provided on the lower surface, the plurality of leads include a signal lead electrically connected to the signal terminal portion, the first coil is electrically connected to the first semiconductor chip via the signal conductive portion and the signal lead; 4. The isolator of claim 2, wherein the first lead has a width greater than a width of the signal lead.

7. 4. The isolator of claim 1, wherein a width of the first lead is different from a width of the second lead.

8. Further comprising an insulating member; an upper surface of the first lead includes a connection region in contact with the solder and an adjacent region adjacent to the connection region and not in contact with the solder; 4. The isolator according to claim 1, wherein the insulating member is provided on the adjacent region.

9. 4. The isolator according to claim 1, wherein an upper surface of the first lead includes a connection region in contact with solder, an adjacent region not in contact with solder, and a step portion between the connection region and the adjacent region.

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