Semiconductor device and manufacturing method for the same

Abstract

To relax electric field concentration at an edge of a control electrode disposed inside a groove.SOLUTION: A semiconductor device 100 includes: a drift region 7, a drain region 10, and a source region 9 of a first conductivity type; a well region 3 of a second conductivity type; a control electrode 15 disposed via an insulating film 14 inside a groove 13 formed in a major surface 1a of a substrate 1; and an electric field relaxation region 12 of the second conductivity type disposed below a bottom 13b of the groove 13. The source region 9, the well region 3, and the drift region 7 are in contact with a lateral surface 13a of the groove 13. A part of the electric field relaxation region 12 extends from the lateral surface 13a of the groove 13 to a side of the drift region 7. The electric field relaxation region 12 includes: a first region 12A where a second conductivity type impurity concentration is higher than a second conductivity type impurity concentration in the well region 3; and a second region 12B that is located at an edge 12Ba of the electric field relaxation region 12 extended to a side of the drift region 7, and has a second conductivity type impurity concentration higher than that in the first region 12A.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] Patent Document 1 discloses a trench-gate MOSFET in which a trench is formed in a semiconductor substrate and a control electrode is provided inside the formed trench. An N-type drift region and a P-type drift region are arranged in the drift region through which the main current flows. The thicknesses of the N-type and P-type drift regions are selected so that the N-type drift region and the P-type drift region become substantially complete depletion layers when a voltage lower than the rated voltage is applied between the main electrodes of the MOSFET, thereby increasing the breakdown voltage. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2006-303543 A Summary of the Invention [Problem to be solved by the invention]

[0004] However, because the N-type drift region and the P-type drift region are essentially completely depleted layers, the electric field due to the drain voltage is concentrated at the edge of the trench gate, reducing the breakdown voltage.

[0005] The present invention has been made in consideration of the above-mentioned problems, and its purpose is to provide a semiconductor device and a manufacturing method thereof that can reduce electric field concentration at the end of a control electrode arranged inside a groove. [Means for solving the problem]

[0006] A semiconductor device according to one aspect of the present invention includes a drift region, a drain region, and a source region of a first conductivity type, a well region of a second conductivity type, a control electrode disposed via an insulating film inside a groove formed from a main surface of a substrate, and an electric field relaxation region of a second conductivity type disposed below a bottom of the groove. The source region, the well region, and the drift region are in contact with a side surface of the groove. A part of the electric field relaxation region extends toward the drift region beyond the side surface of the groove. The electric field relaxation region includes a first region having a second conductivity type impurity concentration higher than the second conductivity type impurity concentration of the well region, and a second region located at an end of the electric field relaxation region extended toward the drift region and having a second conductivity type impurity concentration lower than the first region. Effect of the Invention

[0007] According to one aspect of the present invention, it is possible to reduce electric field concentration at the end of the control electrode disposed inside the groove. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a cross-sectional perspective view showing the structure of a semiconductor device 100 according to the first embodiment. [Diagram 2] FIG. 2 is a cross-sectional view showing the structure of the semiconductor device 100 of FIG. 1 along the XY cross section. [Figure 3A] FIG. 3A is a cross-sectional perspective view (part 1) showing a manufacturing process of the semiconductor device 100 of FIG. [Figure 3B] FIG. 3B is a cross-sectional perspective view (part 2) showing a manufacturing process of the semiconductor device 100 of FIG. [Figure 3C] FIG. 3C is a cross-sectional perspective view (part 3) showing a manufacturing process of the semiconductor device 100 in FIG. [Figure 3D] FIG. 3D is a cross-sectional perspective view (part 4) showing a manufacturing process of the semiconductor device 100 in FIG. [Figure 3E] FIG. 3E is a cross-sectional perspective view (part 5) showing a manufacturing process of the semiconductor device 100 in FIG. [Figure 3F] FIG. 3F is a cross-sectional perspective view (part 6) showing a manufacturing process of the semiconductor device 100 in FIG. [Figure 3G]FIG. 3G is a cross-sectional perspective view (part 7) showing a manufacturing process of the semiconductor device 100 in FIG. [Figure 3H] FIG. 4H is a cross-sectional perspective view (part 8) showing a manufacturing process of the semiconductor device 100 in FIG. [Figure 4] FIG. 4 is a cross-sectional perspective view showing the structure of a semiconductor device 101 according to the second embodiment. [Diagram 5] FIG. 5 is a cross-sectional perspective view showing a manufacturing process of the semiconductor device 101 of FIG. [Figure 6] FIG. 6 is a cross-sectional view showing the structure of the semiconductor device 200 according to the reference example along the XY cross section. [Figure 7A] FIG. 7A is a diagram showing the calculation results of the electric field distribution in the semiconductor device 200 according to the reference example. [Figure 7B] FIG. 7B is a diagram showing the calculation results of the electric field distribution in the semiconductor device 100 according to the first embodiment. [Figure 7C] FIG. 7C is a diagram showing the calculation results of the electric field distribution in the semiconductor device 101 according to the second embodiment. [Figure 8A] FIG. 8A is a cross-sectional view showing the position of line segment L1 in semiconductor device 100 of FIG. 7B. [Figure 8B] FIG. 8B is a graph showing the electric field intensity on the line segment L1 of the semiconductor devices 100, 101, and 200. In FIG. [Figure 8C] FIG. 8C is an enlarged graph of a portion GA including the maximum values ​​of the electric field intensity of symbols C to D in FIG. 8B. [Figure 9] FIG. 9 is a cross-sectional perspective view showing the structure of a semiconductor device 102 according to the third embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] The embodiments will be described with reference to the drawings. In the description of the drawings, the same or equivalent parts are given the same reference numerals, and the description will be omitted. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each part, etc. are different from the actual ones. In addition, the drawings include parts with mutually different dimensional relationships or ratios.

[0010] In addition, the embodiments described below are merely examples of devices or methods for embodying the technical ideas, and are not intended to specify the shapes, structures, arrangements, etc. of the components described below. Various modifications can be made to the embodiments within the scope of the claims.

[0011] (First embodiment) [Structure of semiconductor device] The semiconductor device 100 according to the embodiment is a MOS type field effect transistor (MOSFET: Metal-Oxide-Semiconductor Field Effect Transistor) having a trench gate structure and a lateral structure. FIG. 1 is a cross-sectional perspective view showing the structure of the semiconductor device according to the first embodiment. FIG. 1 shows a unit cell structure of a MOSFET. In an actual device, the unit cell structure is repeated in the Z direction, and in the Y direction, a structure that is plane-symmetric with respect to the Y direction side surface of the unit cell structure is repeated.

[0012] 1, the semiconductor device 100 has a substrate 1, a first conductivity type drift region 7, a first conductivity type drain region 10, a second conductivity type well region 3, a first conductivity type source region 9, a second conductivity type column region 5, and a second conductivity type electric field relaxation region 12. The semiconductor device 100 also has a drain electrode 17 joined to the drain region 10, a control electrode 15, and a source electrode 16 joined to the source region 9.

[0013] The first and second conductive types are different from each other. That is, if the first conductive type is P type, the second conductive type is N type, and if the first conductive type is N type, the second conductive type is P type. In this embodiment, the case where the first conductive type is N type and the second conductive type is P type will be described.

[0014] The substrate 1 is an insulating semiconductor substrate. This can simplify the element isolation process when integrating multiple semiconductor devices on the same substrate 1. Here, an insulating substrate refers to a substrate having a resistivity of several kΩ·cm or more. However, the substrate 1 may also be a semi-insulating semiconductor substrate.

[0015] For example, a silicon carbide substrate (SiC substrate) having insulating properties can be used for the substrate 1. Since SiC is a wide band gap semiconductor with a small number of intrinsic carriers, it is easy to obtain high insulating properties, and a semiconductor device 100 with high withstand voltage can be realized. There are several polytypes (crystal polymorphism) of SiC, and a typical 4H SiC substrate of the hexagonal crystal system can be used for the substrate 1. By using a SiC substrate for the substrate 1, the insulating properties of the substrate 1 can be increased.

[0016] Furthermore, the substrate 1 is not limited to a SiC substrate, and may be a semiconductor substrate made of a semiconductor material having a wide band gap. Examples of semiconductor materials having a wide band gap include III-V compound semiconductors using nitrogen as a V group element, such as GaN (gallium nitride), AlN (aluminum nitride), AlGaN (aluminum gallium nitride), and InN (indium nitride), diamond, and ZnO (zinc oxide).

[0017] The N-type drift region 7 is formed in the substrate 1 in contact with the main surface 1a of the substrate 1, and is a region through which the main current of the semiconductor device 100 flows when the transistor (semiconductor device 100) is in the on state. The drift region 7 is in contact with the P-type well region 3, and also in contact with the N+ type drain region 10. The well region 3 and the drain region 10 are not in direct contact with each other, but are electrically connected via the drift region 7. The N-type impurity concentration of the drift region 7 is, for example, 1×1015 / cm 3 More than 1×10 19 / cm 3 The drift region 7 is preferably formed of a wide band gap semiconductor. This allows a low on-resistance and a high dielectric breakdown field to be compatible. The substrate 1, well region 3, and drift region 7 may be formed of the same material. This makes it possible to prevent performance degradation due to lattice mismatch and the like that occurs when different materials are used.

[0018] An N+ type drain region 10 is formed in the substrate 1 in contact with the drift region 7. The N type impurity concentration of the drain region 10 is higher than that of the drift region 7, and is, for example, 1×10 18 / cm 3 More than 1×10 21 / cm 3 The following is an example. In this specification, "N+ type" indicates that the N-type impurity concentration is high. Similarly, "P+ type" indicates that the P-type impurity concentration is high. The drain region 10 is joined to the drain electrode 17 on the main surface 1a of the substrate 1. The junction between the drain region 10 and the drain electrode 17 forms a metal-semiconductor junction that does not have a rectifying effect, a so-called ohmic contact.

[0019] The P-type well region 3 is formed in the substrate 1 in contact with the drift region 7. The contact surface between the well region 3 and the drift region 7 forms a PN junction. The P-type impurity concentration of the well region 3 is, for example, 1×10 15 / cm 3 More than 1×10 19 / cm 3 Like the drift region 7, the well region 3 is preferably formed of a wide band gap semiconductor, which can achieve both a low on-resistance and a high dielectric breakdown field.

[0020] An N+ type source region 9 is formed in the substrate 1 in contact with the well region 3. The contact surface between the source region 9 and the well region 3 forms a PN junction. The N type impurity concentration of the source region 9 is higher than that of the drift region 7, and is, for example, 1×10 18 / cm 3 More than 1×10 21 / cm 3 The source region 9 is joined to the source electrode 16 on the main surface 1a of the substrate 1. The junction between the source region 9 and the source electrode 16 forms an ohmic contact.

[0021] The control electrode 15 is disposed inside a groove 13 formed in the substrate 1 from the main surface 1a of the substrate 1 via an insulating film 14. For example, polycrystalline silicon to which N-type or P-type impurities are highly doped can be used as the material of the control electrode 15. The insulating film 14 contacts the side surface 13a and the bottom 13b of the groove 13. The control electrode 15 contacts the insulating film 14 and backfills the entire groove 13. The control electrode 15 does not directly contact the side surface 13a and the bottom 13b of the groove 13. The bottom 13b may be a flat bottom surface or may be a curved surface. In the semiconductor device 100, the bottom 13b forms a flat bottom surface. The depth of the groove 13 and the depth of the drift region 7 may be the same or different. In the semiconductor device 100, the bottom 13b of the groove 13 is located in the same depth direction as the bottom of the drift region 7.

[0022] The source region 9, well region 3, and drift region 7 are in contact with the side surface 13a of the trench 13. In other words, at the side surface 13a of the trench 13, the source region 9, well region 3, and drift region 7 are in contact with the control electrode 15 via the insulating film 14. From the main surface 1a of the substrate 1 toward the depth direction of the trench 13 (the opposite direction to the X direction), the source region 9, well region 3, and drift region 7 are in contact with the side surface 13a of the trench 13 in this order. The MOS structure of the semiconductor device 100 corresponds to a structure in which the control electrode 15 and the well region 3 sandwich the insulating film 14.

[0023] The P+ type electric field relief region 12 is disposed in the substrate 1 and below the bottom 13b of the groove 13. "Disposed below the bottom 13b of the groove 13" includes both being disposed in contact with the bottom of the bottom 13b of the groove 13 and being disposed below and spaced apart from the bottom 13b of the groove 13. In the semiconductor device 100 shown in FIG. 1, the electric field relief region 12 is disposed in contact with the bottom of the bottom 13b of the groove 13. In other words, the electric field relief region 12 is disposed in contact with the bottom of the insulating film 14 that is in contact with the bottom 13b of the groove 13.

[0024] The electric field relaxation region 12 extends beyond the side surface 13a of the groove 13 toward the drift region 7, that is, in the Y direction. Although not shown in the drawing, the electric field relaxation region 12 extends in the Z direction while maintaining the cross-sectional portion of the cross-sectional perspective view of FIG. 1, that is, the shape shown in FIG. 2. That is, when viewed from the X direction, the electric field relaxation region 12 in FIG. 1 has a rectangular shape overlapping with the groove 13 and a part of the source region 9. In addition, the extension portion 12L of the electric field relaxation region 12 contacts the bottom of the drift region 7 to form a PN junction. This is because the bottom 13b of the groove 13 is located in the same depth direction as the bottom of the drift region 7.

[0025] The electric field relaxation region 12 has a first region 12A and a second region 12B. The P-type impurity concentration of the first region 12A is higher than the P-type impurity concentration of the well region 3. The second region 12B is located at an end 12Ba of the electric field relaxation region 12 that extends toward the drift region 7. The P-type impurity concentration of the second region 12B is lower than that of the first region 12A. The P-type impurity concentration of the first region 12A is, for example, 1×10 18 / cm 3 More than 1×10 21 / cm 3 The P-type impurity concentration of the second region 12B is, for example, 70% or more and 130% or less of the P-type impurity concentration of the well region 3.

[0026] 1 and 2, in the semiconductor device 100, the electric field relaxation region 12 is extended to the end 3a of the well region 3 on the drift region 7 side. The effect of relaxing the electric field concentration at the end EF of the control electrode 15 can be obtained as long as the end 12Ba of the electric field relaxation region 12 is located in the range from the side surface 13a of the groove 13 to the center of the P-type column region 51. The condition for the effect of relaxing the electric field concentration at the end EF of the control electrode 15 to be the highest is that the electric field relaxation region 12 is extended to the end 3a of the well region 3 on the drift region 7 side. In other words, when the position of the end 12Ba of the electric field relaxation region 12 coincides with the position of the end 3a of the well region 3 on the drift region 7 side as viewed from the X direction, the effect of relaxing the electric field concentration at the end EF of the control electrode 15 is the highest.

[0027] 1, the P-type column region 5 is formed in the drift region 7. The P-type column region 5 is in contact with the well region 3 and extends along the direction in which the main current of the semiconductor device 100 flows (the opposite direction to the Y direction). The P-type impurity concentration of the P-type column region 5 is, for example, 1×10 15 / cm 3 More than 1×10 19 / cm 3 The P-type column region 5 has a plurality of P-type column regions 51, 52. The number of the P-type column regions 51, 52 is not limited to two, and may be three or more. An N-type drift region 7 is disposed between the P-type column regions 51, 52. The P-type column regions 51, 52 and the N-type drift region 7 between the P-type column regions 51, 52 form a superjunction (SJ) structure in which the P-type column regions 51, 52 and the N-type drift region 7 between the P-type column regions 51, 52 are alternately disposed in a direction (Z direction) perpendicular to the direction in which the main current of the semiconductor device 100 flows. The shape and impurity concentration conditions of each region for forming the superjunction (SJ) structure by the P-type column regions 51, 52 and the drift region 7 therebetween will be described later.

[0028] The P-type column region 5 is not connected to the drain region 10, and an end of the P-type column region 5 faces the drain region 10 via the drift region 7. As shown in FIG. 2, the P-type column region 51 contacts the main surface 1a of the substrate 1 and also extends in the depth direction of the substrate 1 (the opposite direction to the X direction). The length of the P-type column region 5 in the depth direction can be set arbitrarily as long as the P-type column region 5 does not contact the electric field relaxation region 12. For example, the length of the P-type column region 5 in the depth direction may be about half that of the well region 3 as shown in FIG. 2. Alternatively, as shown in FIG. 1 and FIG. 2, when the end 12Ba of the electric field relaxation region 12 is located closer to the control electrode 15 than the end 3a of the well region 3 on the drift region 7 side, the P-type column region 51 may extend to the interface between the substrate 1 and the drift region 7. Although only the P-type column region 51 is shown and described in FIG. 2, the other P-type column regions 52 and the like included in the P-type column region 5 are the same as the P-type column region 51.

[0029] The source electrode 16 is formed on the main surface 1a of the substrate 1 and is electrically connected to the source region 9. The drain electrode 17 is formed on the main surface 1a of the substrate 1 and is electrically connected to the drain region .

[0030] The operation of the semiconductor device 100 shown in FIGS. 1 and 2 will be described below.

[0031] When a positive potential is applied to the drain electrode 17 with the source electrode 16 as a reference potential, a depletion layer spreads from the interface between the drift region 7 and the P-type column region 5, and when the voltage increases to a certain level, the drift region 7 and the P-type column region 5 enter a completely depleted state (pinch-off state). In the pinch-off state, the electric field distribution in the drift region 7 and the P-type column region 5 becomes a uniform rectangular distribution, and the maximum electric field applied to the semiconductor device 100 is greatly reduced. This improves the breakdown voltage of the semiconductor device 100.

[0032] In order to completely deplete the SJ structure, it is necessary to set the ratio of the total amount of N-type impurities in the N-type semiconductor region to the total amount of P-type impurities in the P-type semiconductor region to close to 1. In order to achieve this charge balance, the concentration (donor concentration) Nd of the N-type impurities in the drift region 7, the concentration (acceptor concentration) Na of the P-type impurities in the P-type column region 5, the width Wn of the drift region 7 sandwiched between the P-type column regions 5, and the width Wp of the P-type column regions 5 are set to satisfy the following formula (1). The widths Wn and Wp are the widths in the direction in which the drift regions 7 and the P-type column regions 5 are alternately arranged (Z direction).

[0033] Na × Wp = Nd × Wn (1) By setting the impurity concentrations of the drift region 7 and the P-type column region 5 to satisfy formula (1), it is possible to achieve a charge balance between the P-type impurities and the N-type impurities at the interface between the drift region 7 and the P-type column region 5. As a result, the drift region 7 and the P-type column region 5 are depleted by a depletion layer extending from the interface between the drift region 7 and the P-type column region 5, and a high breakdown voltage is obtained. Furthermore, by increasing the impurity concentration Nd of the drift region 7 while satisfying the relationship of formula (1), it is possible to reduce the resistance value of the drift region 7, thereby reducing the on-resistance.

[0034] The semiconductor device 100 functions as a transistor by controlling the potential of the control electrode 15 while applying a positive potential to the drain electrode 17 with the source electrode 16 as a reference potential. That is, when the voltage between the control electrode 15 and the source electrode 16 is set to a predetermined threshold voltage or higher, electrons, which are minority carriers, are attracted to the well region 3 that contacts the control electrode 15 through the insulating film 14, and an N-type inversion layer is formed. The source region 9 and the drift region 7 are connected by the N-type inversion layer, so that the semiconductor device 100 is turned on and a current flows from the drain electrode 17 to the source electrode 16. When the voltage between the control electrode 15 and the source electrode 16 is set to a value lower than the predetermined threshold voltage, the N-type inversion layer disappears, the semiconductor device 100 is turned off, and the current from the drain electrode 17 to the source electrode 16 is cut off.

[0035] In the off state, an electric field is generated inside the substrate 1 by applying a positive potential to the drain electrode 17 with the source electrode 16 as a reference potential. This electric field does not concentrate in the portion where the SJ structure is present, but concentrates on the end of the control electrode 15, which is prone to dielectric breakdown. In order to suppress the electric field concentration on the end of the control electrode 15, a P-type electric field relaxation region 12 is disposed near the end of the control electrode 15, and the electric potential of the electric field relaxation region 12 is set to the same potential as that of the source region 9. Then, the electric field relaxation region 12 is extended toward the drift region 7 beyond the side surface 13a of the groove 13 in which the control electrode 15 is embedded. As a result, an electric field is formed between the electric field relaxation region 12 extended toward the drift region 7 and the drain electrode 17, and the electric field concentration on the end of the control electrode 15 is relaxed.

[0036] Furthermore, a second region 12B having a lower P-type impurity concentration than first region 12A is disposed at end 12Ba of electric field relaxation region 12 extended toward drift region 7. By disposing a low-concentration P region (second region 12B) at end 12Ba of electric field relaxation region 12 extended toward drift region 7, electric field concentration at end 12Ba of electric field relaxation region 12 can be alleviated.

[0037] The effect of the second region 12B will be described with reference to Figs. 6, 7A, 7B, 8A and 8B. Fig. 6 is a cross-sectional view showing the configuration of a semiconductor device 200 according to a reference example. The difference from the semiconductor device 100 shown in Fig. 2 is that the electric field relaxation region 12 is composed of only the first region 12A, and the other configurations are the same. Fig. 7A is a diagram showing the calculation results (map) of the electric field distribution in the semiconductor device 200 according to the reference example. In the calculation of the electric field distribution, the impurity concentrations of the first region 12A, the second region 12B and the well region 3 are each 2 x 10 18 / cm 3 , 4×10 17 / cm 3 , 4×10 17 / cm 3 In the semiconductor device 200, a high-concentration first region 12A is disposed at a corner 12Ab of the electric field relaxation region 12. Therefore, a depletion layer does not spread into the first region 12A, and an electric field is concentrated at the corner 12Ab of the electric field relaxation region 12.

[0038] 7B is a diagram showing a calculation result (map) of the electric field distribution in the semiconductor device 100 according to the first embodiment. In the semiconductor device 100, a low-concentration second region 12B is disposed at the end of the electric field relaxation region 12. Therefore, a depletion layer spreads in the second region 12B, and the electric field concentration at the corner 12Bb of the electric field relaxation region 12 is relaxed.

[0039] By setting the P-type impurity concentration of second region 12B to be 70% or more and 130% or less of the P-type impurity concentration of well region 3, it is possible to make the P-type impurity concentrations approximately the same between second region 12B and well region 3. This makes it possible to achieve charge balance in the substrate depth direction between second region 12B and well region 3 and suppress electric field concentration in second region 12B or well region 3.

[0040] FIG. 8A is a cross-sectional view showing the position of the line segment L1 in the semiconductor device 100 in FIG. 7B. FIG. 8B is a graph showing the electric field intensity on the line segment L1 of the semiconductor devices 100 and 200. The horizontal axis of FIG. 8B corresponds to the vertical axis (X-axis) of FIG. 8A, and the vertical axis of FIG. 8B shows the electric field intensity (relative value). The line segment L1 is a line segment parallel to the X-axis passing through the end 3a of the well region 3 on the drift region 7 side and the end 12Ba of the electric field relaxation region 12 shown in FIG. 2. Reference character B indicates the position of the corner 12Bb in FIG. 7B, and reference character C indicates the position of the corner 3b-1 in FIG. 7B. Reference characters A to D in FIG. 8A correspond to reference characters A to D in FIG. 8B. FIG. 8A shows the position of the line segment L1 and the positions of the reference characters A to D in the semiconductor device 100 as an example, but the positions of the line segment L1 and the reference characters A to D in the semiconductor device 200 according to the reference example and the semiconductor device 101 according to the second embodiment are also the same.

[0041] 8B, the maximum value of the electric field strength between symbols A and B in the semiconductor device 100 according to the first embodiment is significantly reduced compared to the semiconductor device 200 according to the reference example. It can be seen that by arranging a low-concentration P region (second region 12B) at end 12Ba of electric field relaxation region 12, the electric field concentration at end 12Ba of electric field relaxation region 12 can be relaxed.

[0042] [Method of manufacturing semiconductor device] Next, an example of a method for manufacturing the semiconductor device 100 according to this embodiment will be described with reference to FIGS. 3A to 3H.

[0043] First, a substrate 1 to which no impurities are added is prepared. Next, as shown in FIG. 3A, a mask material 2 formed on the main surface 1a of the substrate 1 is patterned to expose a region in which a well region 3 is to be formed. Then, ion implantation is performed to selectively add P-type impurities to the substrate 1 using the mask material 2 as a mask, and the well region 3 is formed. Thereafter, ion implantation is performed to selectively add N-type impurities to the substrate 1 using the mask material 2 as is, and a part 7a of the drift region that is in contact with the bottom of the well region 3 is formed. By adjusting the acceleration energy of the impurity ions during ion implantation, the position in the depth direction where the impurities are added into the substrate 1 can be controlled. The acceleration energy of the N-type impurity ions when forming the part 7a of the drift region is made higher than the acceleration energy of the P-type impurity ions when forming the well region 3.

[0044] A silicon oxide film can be used as a general mask material 2, and a thermal CVD method or a plasma CVD method can be used as a deposition method. A photolithography method can be used as a patterning method. That is, the mask material 2 is etched using a patterned photoresist film as a mask. A wet etching method using hydrofluoric acid or a dry etching method such as reactive ion etching can be used as an etching method. After etching the mask material 2, the photoresist film is removed with oxygen plasma or sulfuric acid. In this way, the mask material 2 is patterned. Note that only the outer edge of the mask material 2 is illustrated in order to make the structure easier to understand. The same applies not only to the mask material 2 but also to other mask materials.

[0045] After forming the well region 3 and a portion 7a of the drift region, a P-type impurity is selectively added from the main surface 1a of the substrate 1 by ion implantation using the patterned new mask material 4 as a mask, as shown in FIG. 3B, to form a P-type column region 5 in contact with the well region 3.

[0046] 3C, P-type impurities are selectively added from the main surface 1a of the substrate 1 by ion implantation using the new patterned mask material 6 as a mask to form the remaining portion 7b of the drift region. The N-type impurity concentration of the drift regions 7a and 7b may be the same as the P-type impurity concentration of the P-type column region 5. The P-type impurity concentration of the P-type column region 5 may also be lower than the P-type impurity concentration of the well region 3.

[0047] 3D, N-type impurity ions are selectively implanted from the main surface 1a of the substrate 1 using the patterned new mask material 8 as a mask to simultaneously form a source region 9 and a drain region 10 doped with a high concentration of N-type impurity. By implanting N-type impurity ions into a part of the well region 3, a source region 9 in contact with the main surface 1a of the substrate 1 is formed in the well region 3. By implanting N-type impurity ions into a part of the drift region 7, a drain region 10 in contact with the main surface 1a of the substrate 1 is formed in the drift region 7.

[0048] Next, as shown in Fig. 3E, using the patterned new mask material 11 as a mask, P-type impurities are selectively and highly concentratedly added from the main surface 1a of the substrate 1 by ion implantation to form a first region 12A. By sufficiently increasing the acceleration energy of the P-type impurity ions, it is possible to implant the P-type impurity ions into the bottom of a groove to be formed later and below the drift region 7. In the example shown in Fig. 3E, the first region 12A is formed using the mask material 11 in which the region where the groove 13 (the control electrode 15 and the insulating film 14) will be formed and the source region 9 are exposed.

[0049] 3F, using the patterned new mask material 22 as a mask, P-type impurities are selectively added at a low concentration from the main surface 1a of the substrate 1 by ion implantation to form the second region 12B. As with the first region 12A, the P-type impurity ions can be implanted below the drift region 7 by sufficiently increasing the acceleration energy of the P-type impurity ions.

[0050] In the ion implantation in the steps up to this point, for example, group V elements nitrogen (N) and phosphorus (P) can be used as N-type impurities, and group III elements boron (B), gallium (Ga), and aluminum (Al) can be used as P-type impurities. By implanting ions while the temperature of the substrate 1 is heated to about 600°C, it is possible to suppress the occurrence of crystal defects in the ion-implanted region. The implanted impurities are then activated by heat treatment (annealing). For example, heat treatment is performed at about 1700°C in an argon or nitrogen atmosphere.

[0051] 3G, a part of the substrate 1 is selectively etched from the main surface 1a of the substrate 1 by anisotropic dry etching or wet etching using the patterned new mask material 18 as a mask to form a groove 13. The source region 9, the well region 3, and the drift region 7 are exposed on the side surface 13a of the groove 13. The electric field relaxation region 12 is exposed on the bottom portion 13b of the groove 13.

[0052] 3H, an insulating film 14 and a control electrode 15 are formed inside the groove 13. The control electrode 15 is formed so as to be in contact with each of the source region 9, the well region 3, the drift region 7, and the electric field relaxation region 12 via the insulating film 14.

[0053] The insulating film 14 is formed on the inner wall surface of the groove 13 including the side surface 13a and the bottom portion 13b of the groove 13. The insulating film 14 can be formed by, for example, a thermal oxidation method or a deposition method. As an example, in the case of the thermal oxidation method, the substrate 1 is heated to about 1100°C in an oxygen atmosphere, and a silicon oxide film is formed as the insulating film 14 in all parts of the substrate 1 that are in contact with oxygen. However, the insulating film 14 may not be a silicon oxide film, but may be a silicon nitride film or a laminated film of a silicon oxide film and a silicon nitride film. In the case of a silicon nitride film, isotropic etching can be performed by cleaning with hot phosphoric acid at 160°C.

[0054] After forming the insulating film 14, in order to reduce the interface state at the interface between the well region 3 and the insulating film 14, a heat treatment (annealing) may be performed at about 1000°C in an atmosphere of nitrogen, argon, nitrous oxide (N2O), or the like. Alternatively, thermal oxidation may be performed directly in an atmosphere of nitric oxide (NO) or N2O. In this case, the temperature is preferably 1100°C to 1400°C. The thickness of the insulating film 14 is about several tens of nm.

[0055] The control electrode 15 is formed so as to be deposited inside the groove 13 with the insulating film 14 formed therein. The material of the control electrode 15 may be, for example, a polysilicon film.

[0056] The polysilicon film can be deposited by a low pressure CVD method or the like. For example, the thickness of the polysilicon film to be deposited is set to a value greater than half the width of the groove 13, and the groove 13 is filled with the polysilicon film. Since the polysilicon film is formed from the inner wall surface of the groove 13, the groove 13 can be filled with the polysilicon film by setting the thickness of the polysilicon film as described above. For example, when the width of the groove 13 is 2 μm, the polysilicon film is formed so that the film thickness is greater than 1 μm. In addition, after the polysilicon film is deposited, an annealing process is performed in phosphorus oxychloride (POCl3) at 950° C., thereby forming an N-type polysilicon film and imparting conductivity to the control electrode 15.

[0057] The polysilicon film is planarized by etching or the like. The etching method may be isotropic etching or anisotropic selective etching. The amount of etching is set so that the polysilicon film remains inside the groove 13. For example, when the polysilicon film is deposited to a thickness of 1.5 μm for the groove 13 having a width of 2 μm, the amount of etching of the polysilicon film is set to 1.5 μm. However, in controlling the etching, there is no problem even if the etching amount of 1.5 μm is overetched by a few percent. Note that although N-type polysilicon is used here for the explanation, P-type polysilicon may be used. Also, other semiconductor materials or conductive materials such as metal materials may be used. For example, P-type polysilicon carbide, SiGe, Al, etc. may be used.

[0058] Thereafter, although not shown, an interlayer insulating film made of a silicon oxide film is formed on the main surface 1a of the substrate 1 by, for example, thermal CVD or plasma CVD. A silicon nitride film may be used for the interlayer insulating film. Then, contact holes are formed in the interlayer insulating film by photolithography, through which the source region 9 and the drain region 10 are exposed. The electrode film formed so as to fill the contact holes is patterned to form the source electrode 16 and the drain electrode 17. This completes the semiconductor device 100 shown in FIGS. 1 and 2. The interlayer insulating film is not shown.

[0059] The source electrode 16 and the drain electrode 17 can be preferably made of a metal material used for metal wiring, such as titanium (Ti), nickel (Ni), or molybdenum (Mo). Alternatively, a laminated film in which titanium (Ti), nickel (Ni), and silver (Ag) are laminated in this order from the main surface 1a of the substrate 1 may be used for the source electrode 16 and the drain electrode 17. The source electrode 16 and the drain electrode 17 are formed by depositing a metal material on the entire surface by a sputtering method or an electron beam (EB) deposition method, and then etching the metal material. Alternatively, the source electrode 16 and the drain electrode 17 may be formed by filling contact holes with a metal material by a plating process.

[0060] Next, the effects of the semiconductor device 100 according to this embodiment and the manufacturing method thereof will be described. A part of the electric field relaxation region 12 extends beyond the side surface 13a of the trench 13 toward the drift region 7. This allows the electric field relaxation region 12 to mitigate the concentration of the electric field formed in the substrate 1 at the end EF of the trench 13 when a voltage is applied between the source region 9 and the drain region 10. That is, the electric field concentration at the end of the control electrode 15 disposed inside the trench 13 can be alleviated. Also, in a transistor with a horizontal structure, an inversion layer is formed along the side surface 13a of the trench 13 perpendicular to the main surface 1a of the substrate 1, so that the channel density can be improved.

[0061] When a voltage is applied between the source region 9 and the drain region 10, the electric field relaxation region 12 blocks the electric field applied from the drain region 10 to the end EF of the trench 13, thereby reducing the electric field concentration at the end of the control electrode 15 arranged inside the trench 13.

[0062] Electric field relaxation region 12 contacts bottom 13b of groove 13. As a result, electric field relaxation region 12 is closer to drift region 7 than when electric field relaxation region 12 is disposed away from bottom 13b of groove 13, so that electric field concentration on side surface 13a of groove 13 with which drift region 7 contacts can be alleviated.

[0063] The electric field relaxation region 12 has the same potential as the source region 9. As a result, when a voltage is applied between the source region 9 and the drain region 10, by extending the electric field relaxation region 12, which has the same potential as the source region 9, toward the drift region 7 beyond the side surface 13a of the groove 13, an electric field is formed between the electric field relaxation region 12 and the drift region 7, and therefore the electric field concentration at the end of the control electrode 15 can be alleviated.

[0064] The well region 3 and the drift region 7 are made of a wide band gap semiconductor, which makes it possible to achieve both a low on-resistance and a high dielectric breakdown field.

[0065] The substrate 1 is a semi-insulating substrate or an insulating substrate. It is possible to simplify the element isolation process when integrating a plurality of semiconductor devices on the same substrate 1. In addition, when mounting the semiconductor device 100 on a cooler, it is possible to omit the insulating substrate placed between the substrate 1 and the cooler.

[0066] The substrate 1, well region 3, and drift region 7 are made of the same material, which makes it possible to prevent performance degradation due to lattice mismatch or the like that occurs when different materials are used.

[0067] The substrate 1 is made of silicon carbide. This makes it possible to obtain characteristics such as high heat dissipation, low on-resistance, and high dielectric breakdown field. Since SiC is a wide band gap semiconductor with a small number of intrinsic carriers, it is easy to obtain high insulation, and a semiconductor device with high withstand voltage can be realized. By using a SiC substrate for the substrate 1, the insulation property and thermal conductivity of the substrate 1 can be increased. Therefore, the back surface of the substrate 1 can be directly attached to a cooling mechanism to efficiently cool the semiconductor device 100. With this structure, since the thermal conductivity of the SiC substrate is high, heat generated by the main current when the semiconductor device 100 is in the on state can be efficiently dissipated.

[0068] The drift region 7, the drain region 10, the well region 3, the source region 9, and the electric field relaxation region 12 are formed by ion implantation. By using the ion implantation method, the degree of freedom in designing each of the semiconductor regions 7, 10, 3, 9, and 12 can be improved.

[0069] Second embodiment The structure of a semiconductor device 101 according to the second embodiment will be described with reference to Fig. 4. The semiconductor device 101 is different from the semiconductor device 100 of Fig. 1 in that it further includes a third region 20 that is placed between the well region 3 and the second region 12B and is doped with a high concentration of N-type impurities. The other configurations are the same.

[0070] The third region 20 is formed in the drift region 7 and is a region doped with an N-type impurity at a higher concentration than the drift region 7. For example, when the N-type impurity concentration of the drift region 7 is 1×10 17 / cm 3 In this case, the N-type impurity concentration in the third region 20 is 1.5×10 17 / cm 3 One end of the third region 20 contacts the second region 12B, and the third region 20 extends from the second region 12B toward the well region 3. The third region 20 has a function of balancing the charges in the substrate depth direction (X direction) between the second region 12B and the well region 3, and suppressing the concentration of an electric field in the second region 12B or the well region 3.

[0071] 4, the other end of the third region 20 extended toward the well region 3 may be in contact with the well region 3. This further improves the charge balance in the substrate depth direction between the second region 12B and the well region 3, as compared to the case where the drift region 7 is disposed between the other end of the third region 20 and the well region 3.

[0072] 5, the third region 20 can be formed by selectively adding N-type impurities to the main surface 1a of the substrate 1 using the mask material 22 used in the step of forming the second region 12B (FIG. 3F). By controlling the acceleration energy of the N-type impurity ions, the N-type impurity ions can be selectively implanted into the drift region 7 between the second region 12B and the well region 3.

[0073] The effect of the third region 20 will be described with reference to Figures 7B, 7C, 8B, and 8C. Figure 7C is a diagram showing a calculation result (map) of the electric field distribution in the semiconductor device 101 according to the second embodiment. In the calculation of the electric field distribution, the impurity concentrations of the second region 12B, the third region 20, the well region 3, and the drift region 7 are each 4 x 10 17 / cm 3 , 1.5×10 17 / cm 3 , 4×10 17 / cm 3 , 1×10 17 / cm 3 As shown in FIG. 7B, when the third region 20 was not provided, the electric field was concentrated at the corner 3b-1 of the well region 3. On the other hand, by providing the third region 20, the electric field at the corner 3b-2 of the well region 3 was diffused toward the control electrode 15 side (the opposite direction of the Y direction) as shown in FIG. 7C, and the electric field concentration at the corner 3b-2 of the well region 3 was suppressed. Similarly, the electric field at the corner 12Bb of the electric field relaxation region 12 was diffused toward the control electrode 15 side (the opposite direction of the Y direction), and the electric field concentration at the corner 12Bb of the electric field relaxation region 12 was suppressed.

[0074] Fig. 8C is a graph showing an enlarged view of a portion GA including the maximum values ​​of the electric field strength between symbols C and D in Fig. 8B. As shown in Fig. 8C, the maximum value of the electric field strength between symbols C and D is reduced in the semiconductor device 101 according to the second embodiment compared to the semiconductor device 100 according to the first embodiment.

[0075] By disposing the third region 20 between the well region 3 and the second region 12B, it is possible to achieve charge balance in the substrate depth direction (X direction) between the second region 12B and the well region 3. This makes it possible to suppress electric field concentration at the corner portion 3b-2 of the well region 3.

[0076] By arranging third region 20 having a higher impurity concentration than drift region 7, the on-resistance of the transistor (semiconductor device 100) can be reduced.

[0077] Third embodiment The structure of a semiconductor device 102 according to the third embodiment will be described with reference to Fig. 9. In the semiconductor device 100 of Fig. 1, the electric field relief region 12 is disposed below and in contact with the bottom 13b of the groove 13. In contrast, the semiconductor device 102 according to the third embodiment differs from the semiconductor device 100 of Fig. 1 in that the electric field relief region 12 is disposed below and spaced apart from the bottom 13b of the groove 13. Apart from this difference, the semiconductor device 102 has the same configuration as the semiconductor device 100 of Fig. 1, and therefore will not be described again.

[0078] The electric field relaxation region 12 is separated from the bottom 13b of the groove 13 and the bottom of the drift region 7. The substrate 1 is disposed between the bottom 13b of the groove 13 and the bottom of the drift region 7 and the electric field relaxation region 12, respectively.

[0079] The position of the electric field relaxation region 12 in the depth direction (X direction) can be controlled by adjusting the acceleration energy of the P-type impurity ions in the manufacturing process shown in FIGS. 3E and 3F.

[0080] When electric field relaxation region 12 (first region 12A) doped with a high concentration of P-type impurity comes into contact with drift region 7, a depletion layer spreads in drift region 7, narrowing the path through which the main current of the semiconductor device flows. By arranging electric field relaxation region 12 below and spaced apart from bottom 13b of groove 13, it is possible to prevent the path of the main current flowing through drift region 7 from being narrowed. In other words, according to the third embodiment, it is possible to alleviate electric field concentration on control electrode 15 and simultaneously prevent the narrowing of drift region 7 due to the depletion layer in electric field relaxation region 12. [Explanation of symbols]

[0081] 1 Board 1a Main surface 3 Well Area 3a end 3b-1, 3b-2 corner 7. Drift Region 9 Source Area 10 Drain Region 12 Electric field relaxation region 12A 1st area 12B 2nd area 12Ba end 12Bb Corner 13 Groove 13a side 13b bottom 14 Insulating film 15 Control electrode 16 Source electrode 17 Drain electrode 20 Third area 51, 52 P-type column region 100, 101, 102 Semiconductor device

Claims

1. A substrate; a drift region of a first conductivity type formed in the substrate in contact with a major surface of the substrate; a drain region of a first conductivity type formed in the substrate in contact with the drift region; a well region of a second conductivity type formed in the substrate in contact with the drift region; a source region of a first conductivity type formed in the substrate in contact with the well region; a control electrode disposed within a groove formed in the substrate from the main surface via an insulating film; a field relief region of a second conductivity type disposed below a bottom of the trench; A semiconductor device comprising: the source region, the well region, and the drift region contact side surfaces of the trench; a portion of the electric field relaxation region extends beyond a side surface of the groove toward the drift region; The electric field relaxation region is a first region having a second conductive type impurity concentration higher than a second conductive type impurity concentration of the well region; a second region located at an end of the electric field buffer region extended toward the drift region and having a second conductivity type impurity concentration lower than that of the first region; Semiconductor device.

2. 2. The semiconductor device according to claim 1, wherein the second region has a second conductivity type impurity concentration that is 70% to 130% of the second conductivity type impurity concentration of the well region.

3. 2. The semiconductor device according to claim 1, further comprising a third region in contact with said second region, extended from said second region toward said well region, and having a first conductivity type impurity concentration higher than that of said drift region.

4. 4. The semiconductor device according to claim 3, wherein said third region is in contact with said well region.

5. 2. The semiconductor device according to claim 1, wherein said electric field relaxation region extends to an end of said well region on the drift region side.

6. 2. The semiconductor device according to claim 1, wherein said well region and said drift region are formed from a wide band gap semiconductor.

7. 2. The semiconductor device according to claim 1, wherein said substrate is a semi-insulating substrate or an insulating substrate.

8. 2. The semiconductor device according to claim 1, wherein said substrate, said well region and said drift region are made of the same material.

9. The semiconductor device according to claim 1 , wherein said substrate is made of silicon carbide.

10. A method for manufacturing a semiconductor device according to any one of claims 1 to 9, comprising the steps of: The drift region, the drain region, the well region, the source region and the electric field relaxation region are formed by ion implantation. A method for manufacturing a semiconductor device.

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