Regulator circuit

Abstract

To provide a regulator circuit capable of implementing an over-current protection by suppressing an increase in consumption power and a circuit scale.SOLUTION: A regulator circuit comprises: a power supply circuit that generates a second power supply voltage; an operational amplifier that generates a differential voltage; a first current mirror circuit that outputs a current, which is a copy of a first current, to an output terminal as an output current; an over-current protection circuit that limits a current value of the output current to less than or equal to a predetermined value; a latch circuit that holds a voltage of a first logic signal and outputs the held voltage as a second logic signal in the case where the output voltage drops when one or a plurality of first logic signals are being input; and a current changing circuit that changes an upper limit current value based on the second logic signal by defining the current which corresponds to the predetermined value as an upper limit current.SELECTED DRAWING: Figure 10

Description

[Technical field]

[0001] The present invention relates to a regulator circuit, and more particularly to a regulator circuit having an overcurrent protection function. [Background technology]

[0002] As a regulator that generates a constant power supply voltage and supplies it to a load such as an electronic device, a regulator circuit equipped with a protection function for protecting the internal circuit from element damage caused by an overcurrent has been proposed (see, for example, FIG. 10 of Patent Document 1).

[0003] FIG. 1 is a circuit diagram showing an example of a regulator circuit 800 described in Patent Document 1.

[0004] 1 receives a power supply voltage VDD1, generates an output voltage VOUT by stepping down the power supply voltage VDD1, and supplies this to a load 14. The regulator circuit 800 includes a stabilized power supply circuit 1, a reference voltage generating circuit 2, an operational amplifier 3, P-channel transistors 6 and 16, N-channel transistors 15 and 830, and resistors 17 and 18. The regulator circuit 800 further includes an overcurrent protection circuit consisting of N-channel transistors 19 and 20, a current source 21, and a NOT gate 22.

[0005] The stabilized power supply circuit 1 is provided to realize the reference voltage generation circuit 2, the operational amplifier 3, and the above-mentioned overcurrent protection circuit using elements with a low withstand voltage lower than the power supply voltage VDD1. The stabilized power supply circuit 1 generates a power supply voltage VDD2 by stepping down the power supply voltage VDD1, and supplies this to the reference voltage generation circuit 2, the operational amplifier 3, the current source 21, the NOT gate 22, and the transistor 830.

[0006] The reference voltage generating circuit 2 generates a reference voltage VREF based on the power supply voltage VDD2 and supplies it to the operational amplifier 3. The operational amplifier 3 supplies a differential voltage corresponding to the difference between the reference voltage VREF and a feedback voltage Vfb obtained by dividing the output voltage VOUT to the gates of the transistors 15 and 19.

[0007] The transistor 15 passes a current corresponding to the differential voltage through the voltage protection transistor 830 to the primary side (transistor 16) of the current mirror circuit composed of the transistors 16 and 6. As a result, a current corresponding to the differential voltage is output as an output current from the secondary side (transistor 6) of the current mirror circuit. At this time, the resistors 17 and 18 connected in series receive the output current through the output terminal, and an output voltage VOUT corresponding to the output current is applied to the phase compensation capacitor 13 and one end of the load 14 through the output terminal. Furthermore, a voltage obtained by dividing the output voltage VOUT by the resistors 17 and 18 is supplied to the operational amplifier 3 as the feedback voltage Vfb.

[0008] Based on the power supply voltage VDD2, the current source 21 generates an upper limit current having a current value corresponding to the upper limit value that can be tolerated as an output current, that is, a threshold value for determining whether or not an overcurrent occurs, and sends this to a node N5. The input capacitance of the NOT gate 22 is charged by this upper limit current. The transistor 19 discharges the input capacitance of the NOT gate 22 by drawing from the node N5 a current corresponding to the differential voltage output from the operational amplifier 3.

[0009] Here, while a relatively small output current is being output from the secondary side of the current mirror circuit, the differential voltage is also relatively small, and so the current that transistor 19 draws from node N5 is also small. Therefore, at this time, if the current that transistor 19 draws from node N5 is small relative to the constant current that current source 21 outputs to node N5, the voltage at node N5 rises.

[0010] On the other hand, while a large output current is being output from the secondary side of the current mirror circuit, the differential voltage is also large, and so the current that transistor 19 draws from node N5 is also large. Therefore, at this time, if the current that transistor 19 draws from node N5 is large compared to the constant current that current source 21 outputs to node N5, the voltage at node N5 drops.

[0011] The NOT gate 22 receives the power supply voltage VDD2 and operates as follows: That is, the NOT gate 22 supplies a low-level signal to the gate of the transistor 20 when the voltage of the node N5 is equal to or higher than the threshold voltage, and supplies a high-level signal to the gate of the transistor 20 when the voltage of the node N5 is lower than the threshold voltage.

[0012] When a high-level signal is received, the transistor 20 is turned off. On the other hand, when a low-level signal is received, the transistor 20 is turned on and forcibly grounds the gate of the transistor 15. Then, the current flowing through the primary side of the current mirror circuit (16, 6) decreases, and following this, the current flowing through the secondary side of the current mirror circuit, i.e., the output current, also decreases.

[0013] In this way, when the output current becomes excessively large, the overcurrent protection circuit (19 to 21) forcibly reduces the gate voltage of the transistor 15, thereby reducing the output current and protecting the transistor 6 from the excessive current. [Prior art documents] [Patent documents]

[0014] [Patent Document 1] JP 2017-62688 A Summary of the Invention [Problem to be solved by the invention]

[0015] In the configuration described in Patent Document 1, if a stabilized power supply circuit 1 with low load regulation characteristics is adopted, the power supply voltage VDD2 fluctuates due to the current flowing through the transistor 19. This causes the threshold voltage of the transistor constituting the NOT gate 22 to fluctuate, causing the output of the NOT gate 22 to fluctuate. This causes the output current to fluctuate because the above-mentioned reduction process for the output current is intermittently and repeatedly performed.

[0016] Therefore, in the regulator circuit described in Patent Document 1, it is necessary to adopt a stabilized power supply circuit 1 having high load regulation characteristics, for example, as shown in FIG. 2, which is composed of a reference voltage generating circuit 102, an operational amplifier 103, a P-channel transistor 104, a capacitor 130, and resistors 170 and 180.

[0017] However, a stabilized power supply circuit with good load regulation characteristics generally consumes high power and has a large circuit area. Therefore, the regulator circuit described in Patent Document 1, which requires a stabilized power supply circuit as shown in Figure 2, has the problem of large power consumption and circuit size.

[0018] SUMMARY OF THE PRESENT EMBODIMENTS An object of the present invention is to provide a regulator circuit capable of providing overcurrent protection while suppressing increases in power consumption and circuit size. [Means for solving the problem]

[0019] A regulator circuit according to the present invention is a regulator circuit that generates an output voltage having a value corresponding to a reference voltage based on a first power supply voltage and outputs the output voltage from an output terminal, and includes a power supply circuit that generates a second power supply voltage having a value lower than the first power supply voltage based on the first power supply voltage, an operational amplifier that operates based on the second power supply voltage and generates a differential voltage representing the difference between a voltage obtained by dividing the output voltage and the reference voltage, a first current path that flows a first current corresponding to the differential voltage, a first current mirror circuit that outputs a current obtained by copying the first current as an output current to the output terminal, and a current mirror circuit that mirrors the current of the output current. an overcurrent protection circuit that limits a value of the output voltage to a predetermined value or lower; a latch circuit that holds the voltage of the first logic signal and outputs the held voltage as a second logic signal when the output voltage drops while one or more first logic signals are being input; and a current change circuit that changes a value of the upper limit current based on the second logic signal, with a current corresponding to the predetermined value as an upper limit current, wherein the overcurrent protection circuit is connected to the first current path and includes a first transistor that receives the upper limit current at a gate of the overcurrent protection circuit and flows the first current between a source and a drain of the overcurrent protection circuit. Effect of the Invention

[0020] In the present invention, when generating an output current that is a copy of a first current corresponding to the differential voltage between a voltage obtained by dividing the output voltage and a reference voltage, a transistor controlled to pass a current below a predetermined value is connected to a first current path through which the first current passes, and the first current is passed through the transistor, thereby limiting the upper limit of the current value of the output current to a predetermined value.

[0021] With this configuration, even if a power supply circuit with poor load regulation characteristics is used to reduce the withstand voltage of each element, it is possible to prevent the overcurrent protection circuit from malfunctioning and causing the output current to flutter. Therefore, since a power supply circuit with a simple configuration can be used to reduce the withstand voltage of the elements, it is possible to reduce the area and current consumption of the regulator circuit itself. [Brief description of the drawings]

[0022] [Figure 1] FIG. 1 is a circuit diagram showing a configuration of a conventional regulator circuit. [Diagram 2] 1 is a circuit diagram showing an example of the configuration of a stabilized power supply circuit having good load regulation characteristics; [Diagram 3] 1 is a circuit diagram showing a configuration of a regulator circuit 200 according to a first embodiment of the present invention. [Figure 4] 1 is a circuit diagram showing a configuration of a regulator circuit 200A as an example of a modified example of the regulator circuit 200. FIG. [Diagram 5] 11 is a circuit diagram showing a configuration of a regulator circuit 200B as another example of a modification of the regulator circuit 200. FIG. [Figure 6] FIG. 11 is a circuit diagram showing a configuration of a regulator circuit 200C according to a second embodiment of the present invention. [Figure 7] 1 is a diagram showing the correspondence relationship between the load current and the output current Iout, currents I1 and I3. FIG. [Figure 8] 1 is a diagram comparing the current consumption of the overcurrent protection circuit with respect to the load current in regulator circuits 200, 200A, and 200B, and a regulator circuit 200C. [Figure 9] 2 is a circuit diagram showing another example of the configuration of the power supply circuit 201. FIG. [Figure 10] FIG. 11 is a circuit diagram showing a configuration of a regulator circuit 200D according to a third embodiment of the present invention. [Figure 11] FIG. 2 is a diagram illustrating an example of the configuration of a latch circuit 32a. [Figure 12] 1 is a circuit diagram showing a configuration of a regulator circuit 200E according to a first comparative example. [Figure 13] 11 is a circuit diagram showing a configuration of a regulator circuit 200F according to a second comparative example. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0023] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. EXAMPLES

[0024] FIG. 3 is a circuit diagram showing a configuration of a regulator circuit 200 according to a first embodiment of the present invention.

[0025] The regulator circuit 200 receives a high power supply voltage HV_VDD and a ground potential VSS at a power supply terminal t1 and a ground terminal t2, and generates an output voltage VOUT having a constant voltage value by stepping down the high power supply voltage HV_VDD. The regulator circuit 200 supplies the generated output voltage VOUT to a load LD connected to output terminals t3 and t4. A phase compensation capacitor C0 is connected between the output terminals t3 and t4 in parallel with the load LD.

[0026] 3, the regulator circuit 200 includes the following various circuits and circuit elements that operate by receiving a high power supply voltage HV_VDD and a ground potential VSS via a power supply line L1 connected to a power supply terminal t1 and a ground line Lg connected to a ground terminal t2: That is, the regulator circuit 200 includes a power supply circuit 201, an overcurrent protection circuit 202, a reference voltage generating circuit RV1, an operational amplifier OP1, P-channel transistors HV_MP0 and HV_MP1, N-channel transistors HV_MN0 and HV_MN3, and resistors R1 and R2.

[0027] The power supply circuit 201 is provided to realize the reference voltage generation circuit RV1, the operational amplifier OP1, and the overcurrent protection circuit 202 using low-voltage elements lower than the high power supply voltage HV_VDD, and includes a current source CD0, an N-channel transistor HV_MN1, and a Zener diode DLZ1.

[0028] The current source CD0 receives the high power supply voltage HV_VDD via the power supply line L1, generates a current having a predetermined constant current value based on the high power supply voltage HV_VDD, and sends this as a bias current Ibias to a node n1. The cathode of a Zener diode DLZ1 is connected to the node n1. The anode of the Zener diode DLZ1 is connected to the ground line Lg.

[0029] The drain of the transistor HV_MN1 is connected to the power supply line L1, and the gate of the transistor HV_MN1 is connected to the node n1. The source of the transistor HV_MN1 and its own backgate are connected to the power supply line L2. The transistor HV_MN1 sends a current corresponding to the voltage of the node n1 from its own source to the power supply line L2 based on the high power supply voltage HV_VDD.

[0030] With this configuration, the power supply circuit 201 generates a voltage obtained by stepping down the high power supply voltage HV_VDD as the low power supply voltage VDD on the power supply line L2.

[0031] The reference voltage generating circuit RV1 receives a low power supply voltage VDD, generates a reference voltage VREF that determines the voltage value of the output voltage VOUT based on the low power supply voltage VDD, and supplies this to the inverting input terminal of the operational amplifier OP1.

[0032] One end of the resistor R1 is connected to the output terminal t3, and the other end is connected to one end of the resistor R2. The other end of the resistor R2 is connected to the ground line Lg. The resistors R1 and R2 supply a voltage obtained by dividing the output voltage VOUT as a feedback voltage VF to the non-inverting input terminal of the operational amplifier OP1.

[0033] The operational amplifier OP1 receives the low power supply voltage VDD and performs the following operation: That is, the operational amplifier OP1 generates a differential voltage VQ representing the difference between the above-mentioned reference voltage VREF and the feedback voltage VF, and supplies this to the gate of the transistor MN3.

[0034] The transistors HV_MP0 and HV_MP1 have their gates connected to each other and their sources and back gates connected to the power supply line L1, and the gate and drain of the transistor HV_MP0 are connected to each other to form a current mirror circuit. The gate and drain of the transistor HV_MP0 on the primary side of the current mirror circuit are connected to the drain of the transistor HV_MN0 for voltage protection, and the drain of the transistor HV_MP1 on the secondary side is connected to one end of the resistor R1 and the output terminal t3 via the node n2.

[0035] The source and back gate of the transistor HV_MN0 are connected to the drain of the transistor MN3, and the low power supply voltage VDD is applied to the gate of the transistor HV_MN0 via the power supply line L2.

[0036] The back gate of the transistor MN3 is connected to the ground line Lg, and the differential voltage VQ is supplied to the gate.

[0037] The overcurrent protection circuit 202 includes a current source CD1 and N-channel transistors MN0 and MN1.

[0038] The current source CD1 generates a current that specifies a predetermined upper limit value that can be tolerated as an output current output by the regulator circuit 200, that is, a threshold value that is a boundary between whether or not an overcurrent occurs, based on the low power supply voltage VDD received via the power supply line L2. The current source CD1 supplies this generated current as the upper limit current Ilimit to the drain and gate of the transistor MN0.

[0039] The gates of the transistors MN0 and MN1 are connected to each other via the node n3, and the sources and back gates of the transistors MN0 and MN1 are both connected to the ground line Lg, forming a current mirror circuit in which the gate and drain of the transistor MN0 are connected. The drain of the transistor MN1 on the secondary side of the current mirror circuit is connected to the source of the transistor MN3.

[0040] The operation of the regulator circuit 200 shown in FIG. 3 will now be described.

[0041] First, the operational amplifier OP1 supplies a differential voltage VQ representing the difference between a feedback voltage VF having a voltage value corresponding to the output voltage VOUT and a reference voltage VREF to the gate of the transistor MN3. The transistor MN3 sends a current I1 corresponding to the differential voltage VQ from the transistor HV_MP0 on the primary side of the current mirror circuit to the transistor MN1 of the overcurrent protection circuit 202 via the transistor HV_MN0. As a result, an output current Iout having a voltage value corresponding to the current I1 is sent from the transistor HV_MP1 on the secondary side of the current mirror circuit to the resistor R1 and the output terminal t3 via the node n2. At this time, an output voltage VOUT corresponding to the output current Iout is applied to the load LD, and a feedback voltage VF having a voltage value corresponding to the output voltage VOUT is supplied to the non-inverting terminal of the operational amplifier OP1.

[0042] Therefore, through a series of processes by the operational amplifier OP1, transistor MN3, current mirror circuit (HV_MP0, HV_MP1), and resistors R1 and R2, an output voltage VOUT having a voltage value corresponding to the reference voltage VREF is applied to the load LD.

[0043] Furthermore, the regulator circuit 200 is provided with an overcurrent protection circuit 202 that prevents the output current Iout from exceeding an upper limit value represented by the upper limit current Ilimit, ie, from becoming an excessive current, and protects the transistor HV_MP1 from the excessive current.

[0044] The overcurrent protection operation by the overcurrent protection circuit 202 will be described in detail below.

[0045] First, the maximum current value I1max of the current I1 that the transistor MN3 can pass is I1max = [(W N1 / L N1 ) / (W N0 / L N0 )]·Ilimit WN1 : Gate width of transistor MN1 W N0 : Gate width of transistor MN0 L N1 : Gate length of transistor MN1 L N0 : Gate length of transistor MN0 It becomes.

[0046] Here, L N0 =L N1 , L HV_P0 =L HV_P1 L HV_P0 : Gate length of transistor HV_MP0 L HV_P1 : Gate length of transistor HV_MP1 Then, I1max=(W N1 / W N0 )·Ilimit It becomes.

[0047] Next, the maximum current value IOmax of the output current Iout output by the transistor HV_MP1 is IOmax=[(W HV_P1 / L HV_P1 ) / (W HV_P0 / L HV_P0 )]·I1max W HV_P0 : Gate width of transistor HV_MP0 W HV_P1 : Gate width of transistor HV_MP1 It becomes.

[0048] Here, L HV_P0 =L HV_P1 Then, IOmax=(W HV_P1 / W HV_P0 )·I1 max =[(W N1 ·W HV_P1 ) / (W N0 ·W HV_P0 )]·Ilimit It becomes.

[0049] That is, the maximum current value IOmax of the output current Iout output by the regulator circuit 200 can be set by the size ratio of the transistors HV_MP0, HV_MP10, MN0 and MN1 and the upper limit current Ilimit.

[0050] In this case, in the overcurrent protection circuit 202, a transistor MN1 that receives a current corresponding to a predetermined value at its gate as an upper limit current Ilimit and flows the current I1 between its source and drain is connected to a current path through which a current I1 corresponding to the differential voltage VQ output by the operational amplifier OP1 flows, thereby preventing the output current Iout from becoming excessive.

[0051] As a result, even if fluctuations occur in the low power supply voltage VDD supplied to the overcurrent protection circuit 202, it is possible to perform overcurrent protection without malfunctioning, without causing the output current Iout to flutter. Therefore, as the power supply circuit 201 provided in the regulator circuit 200, a power supply circuit (CD0, HV_MN1, DLZ1) having a simple configuration as shown in Fig. 3, although having poor load regulation characteristics, can be used, making it possible to reduce the circuit area and current consumption.

[0052] In the regulator circuit 200 shown in FIG. 3, the load LD is driven by the unipolar transistor HV_MP1, but the load LD may be driven by an external bipolar transistor.

[0053] FIG. 4 is a circuit diagram showing the configuration of a regulator circuit 200A as an example of a modified regulator circuit that has been made in consideration of the above points.

[0054] The regulator circuit 200A shown in FIG. 4 is identical in configuration to that shown in FIG. 3 except that a power supply relay terminal t5 connected to the power supply line L1 and a base connection terminal t6 are newly provided, and the drain of the transistor HV_MP1 is connected only to the base connection terminal t6 rather than to the resistor R1 and the output terminal t3, thereby forming an open-drain configuration.

[0055] In the regulator circuit 200A, as shown in FIG. 4, for example, a high-voltage bipolar transistor TR has its collector externally connected to a power relay terminal t5, its base externally connected to a base connection terminal t6, and its emitter connected to a load LD.

[0056] The configuration shown in FIG. 4 makes it possible to drive a heavy load LD while limiting the current value of the output current Iout flowing into the base of the externally connected bipolar transistor TR so that the current value does not become an overcurrent.

[0057] In addition, in the example shown in Figures 3 and 4, a pair of N-channel transistors MN0 and MN1 is used as the current mirror circuit included in the overcurrent protection circuit 202, but a pair of P-channel transistors may also be used.

[0058] FIG. 5 is a circuit diagram showing the configuration of a regulator circuit 200B as another example of a modified regulator circuit made in consideration of the above points.

[0059] The configuration shown in FIG. 5 is the same as that shown in FIG. 3 except that an overcurrent protection circuit 202a is employed instead of the overcurrent protection circuit 202 shown in FIG.

[0060] The overcurrent protection circuit 202a shown in FIG. 5 includes a current source CD2, and P-channel transistors HV_MP2 and HV_MP3.

[0061] The transistors HV_MP2 and HV_MP3 have their respective gates connected to each other via node n4, and their respective sources and backgates both connected to the power supply line L1. The drain and gate of the transistor HV_MP2 are connected to each other to form a current mirror circuit.

[0062] The current source CD2 is connected between the node n4 and the ground line Lg, and draws from the node n4 an upper limit current Ilimit that represents an allowable upper limit value for the output current Iout output by the regulator circuit 200B, that is, a threshold value for whether or not an overcurrent occurs. The drain of the transistor HV_MP0 on the secondary side of the current mirror circuit (HV_MP2, HV_MP3) is connected to the back gate and source of each of the transistors HV_MP0 and HV_MP1.

[0063] In the regulator circuit 200B, an overcurrent protection circuit 202a including a transistor HV_MP3 that limits the current value of the current I1 corresponding to the differential voltage VQ to a current value corresponding to an upper limit current Ilimit is provided in a current path (HV_MP3, HV_MN0, MN3) through which the current I1 corresponding to the differential voltage VQ flows, thereby preventing the output current Iout from becoming excessive.

[0064] As described above in detail, the regulator circuit (200, 200A to 200C) according to the present invention includes the following power supply circuit, operational amplifier, first current path, current mirror circuit, and overcurrent protection circuit.

[0065] The power supply circuit (201) generates a low power supply voltage (VDD) having a voltage value lower than a power supply voltage (HV_VDD) based on the power supply voltage. The operational amplifier (OP1) operates by receiving the low power supply voltage (VDD) and generates a differential voltage (VQ) representing the difference between a voltage (VF) obtained by dividing the output voltage (VOUT) and a reference voltage (VREF). A first current (I1, I2 or I3) corresponding to the differential voltage (VQ) flows through the first current path (HV_MN0, MN3). The current mirror circuit (HV_MP0, HV_MP1) sends a current obtained by copying the first current as an output current (Iout) to the output terminal (t3). The overcurrent protection circuit (202, 202a, 202b) is connected to a first current path, and receives a current corresponding to a predetermined value at its gate as an upper limit current (Ilimit), and limits the current value of the output current (Iout) to a predetermined value or less by a first transistor that flows a first current between its source and drain.

[0066] As a result, even if fluctuations occur in the low power supply voltage (VDD) supplied to the overcurrent protection circuit, it is possible to perform overcurrent protection without malfunctioning, without causing the output current to flutter. Therefore, according to the regulator circuit of the present invention, a power supply circuit having a simple configuration can be used as the power supply circuit (201) that generates the power supply voltage (VDD) to be supplied to the low-voltage circuit or low-voltage element, making it possible to reduce the circuit area and current consumption. EXAMPLES

[0067] FIG. 6 is a circuit diagram showing a configuration of a regulator circuit 200C according to a second embodiment of the present invention.

[0068] The regulator circuit 200C has the same configuration as that shown in Fig. 3, except that an overcurrent protection circuit 202b is used instead of the overcurrent protection circuit 202 shown in Fig. 3. Therefore, only the configuration and operation of the overcurrent protection circuit 202b will be described below.

[0069] The overcurrent protection circuit 202b includes P-channel transistors MP0 to MP3, N-channel transistors MN0, MN1, MN3, and MN4, and current sources CD3 and CD4.

[0070] The gates of transistors MN0 and MN1 are connected to each other via node n3, and the sources and back gates of transistors MN0 and MN1 are both connected to the ground line Lg. The gate and drain of transistor MN0 are connected to each other to form a current mirror circuit.

[0071] The current source CD3 receives a low power supply voltage VDD via the power supply line L2, and generates a current to be added based on the low power supply voltage VDD to stabilize operation during small current output, and sends this to node n3 as a bias current Ibias2.

[0072] The transistors MP2 and MP3 have their gates connected to each other, their sources and back gates connected to the power supply line L2, and the drain and gate of the transistor MP3 are connected to each other to form a current mirror circuit. This current mirror circuit (MP2, MP3) supplies a current that is a copy of the current I3 corresponding to the differential voltage VQ that indicates the difference between the reference voltage VREF and the feedback voltage VF, as the feedback output current IFB, to the sources of the transistors MP0 and MP1.

[0073] The transistors MP0 and MP1 have their gates connected to each other and their sources connected to the drain of the transistor MP2, and the drain and gate of the transistor MP0 are connected to form a current mirror circuit. The back gates of the transistors MP0 and MP1 are connected to the power supply line L2.

[0074] A current source CD4 is connected to the drain of the transistor MP0 on the primary side of the current mirror circuit (MP0, MP1), and the drain of the transistor MP1 on the secondary side is connected to the drain of the transistor MN0.

[0075] The current source CD4 supplies an upper limit current Ilimit, which indicates a predetermined upper limit value that is permissible as the output current Iout output by the regulator circuit 200C, to the gates of the transistors MP0 and MP1.

[0076] The drain of the transistor MP3 on the primary side of the current mirror circuit (MP2, MP3) is connected to the drain of the transistor MN4.

[0077] The gate of the transistor MN4 is supplied with the differential voltage VQ output by the operational amplifier OP1, and the source and back gate are connected to the drain of the transistor MN1 on the secondary side of the current mirror circuit (MN0, MN1).

[0078] The operation of the overcurrent protection circuit 202b will be described in detail below.

[0079] First, the current flowing through transistor MN1 is defined as I1, the current output by transistor MN3 in response to differential voltage VQ output from operational amplifier OP1 is defined as I2, and the current output by transistor MN4 in response to said differential voltage VQ is defined as I3.

[0080] At this time, the current I1 is I1=I2+I3 =I2+[(W N4 / L N4 ) / (W N3 / L N3 )]·I2 W N4 : Gate width of transistor MN4 W N3 : Gate width of transistor MN3 L N4 : Gate length of transistor MN4 L N3 : Gate length of transistor MN3 It becomes.

[0081] Here, L N4 =L N3 Then, I1 = [1 + (W N4 / W N3 )]·I2 It becomes.

[0082] In addition, the maximum current value I1max of the current I1 that the transistor MN1 can pass is I1max = [(W P1 / L P1 )·(W N1 / L N1 ) / (W P0 / L P0 )·(W N0 / L N0 )]·Ilimit+Ibias2 W P0 : Gate width of transistor MP0 W P1 : Gate width of transistor MP1 W N0 : Gate width of transistor MN0 W N1 : Gate width L of transistor MN1 P0 : Gate length of transistor MP0 L P1 : Gate length of transistor MP1 L N0 : Gate length of transistor MN0 L N1 : Gate length of transistor MN1 It becomes.

[0083] Here, L N0 =L N1 , L P0 =L P1 So, I1max = [(W P1 ·W N1 ) / (W P0 ·W N0 )]·Ilimit+Ibias2 It becomes.

[0084] Next, the maximum current value IOmax of the output current Iout that the transistor HV_MP1 can flow is IOmax=[(W HV_P1 / L HV_P1 ) / (W HV_P0 / L HV_P0 )]·I2 W HV_P0 : Gate width of transistor HV_MP0 W HV_P1 : Gate width of transistor HV_MP1 It becomes.

[0085] Here, L HV_P0 =L HV_P1 L HV_P0 : Gate length of transistor HV_MP0 L HV_P1 : Gate length of transistor HV_MP1 Then, IOmax=(W HV_P1 / W HV_P0 )·I2 It becomes.

[0086] Here, the maximum current value I2max of the current I2 that can flow through the transistor MN3 is I2max = [(W P1 ·W N1 ·Ilimit / W P0 ·W N0 )+Ibias2] / [1+(W N4 / W N3 )] It is.

[0087] Therefore, the maximum current value IOmax of the output current Iout that the transistor HV_MP1 can actually flow is IOmax=[(W P1 ·W N1 ·Ilimit / W P0 ·W N0 ) + Ibias2] × (W HV_P1 / W HV_P0 ) / [1+(W N4 / W N3 )] It becomes.

[0088] Therefore, the maximum current value IOmax of the output current Iout output by the regulator circuit 200C can be set by the bias currents Ilimit and Ibais2 and the size ratios of the transistors HV_MP0, HV_MP10, MN0, MN1, MN3 and MN4.

[0089] In this way, in the regulator circuit 200C, an overcurrent protection circuit 202b including a transistor MN1 that limits the current value of the current I2 (I3) corresponding to the differential voltage VQ, which represents the difference between the feedback voltage VF corresponding to the output voltage and the reference voltage VREF, is provided in the current path through which the current I2 (I3) flows, to a current value corresponding to the upper limit current Ilimit, thereby preventing the output current Iout from becoming excessive.

[0090] In the overcurrent protection circuit 202b, a current source CD4 generates an upper limit current Ilimit based on a current corresponding to the current I3 (=I2) by a current mirror circuit (MP2, MP3), that is, a current copied from a current that follows the current value of the output current Iout. Furthermore, a maximum current value I1max of the current I1 that the transistor MN1 can pass is set according to the upper limit current Ilimit.

[0091] In short, the overcurrent protection circuit 202b is connected to a first current path (HV_MN0, MN3) and has a first transistor (MN1) that receives a current corresponding to a predetermined value as an upper limit current (Ilimit) at its gate and flows a first current (I2, I3) between its source and drain, as well as the following second transistor, first current source path, and upper limit control circuit.

[0092] The second transistor (MN0) has its gate and drain connected to the gate of the first transistor (MN1) via the first node, and its source connected to the source of the first transistor. The first current source (CD4) generates an upper limit current (Ilimit) corresponding to a predetermined value (upper limit value).

[0093] The upper limit control circuits (MP0 to MP3) pass a current corresponding to the first current (I2, I3) through the gate and drain of the second transistor when the first current (I2, I3) is equal to or less than the upper limit current, and pass a current corresponding to the upper limit current through the gate and drain of the second transistor when the first current is greater than the upper limit current.

[0094] The upper limit control circuit includes the following first and second current mirror circuits.

[0095] The first current mirror circuit (MP2, MP3) outputs a current obtained by copying the first current (I2, I3) flowing through the first current path (HV_MN0, MN3) according to a differential voltage (VQ) indicating the difference between the reference voltage (VREF) and the feedback voltage (VF) as a feedback output current (IFB). The second current mirror circuit has a primary side transistor (MP0) and a secondary side transistor (MP1) whose gates are connected to each other and whose sources receive the feedback output current. A first current source is connected to the gate and drain of the primary side transistor (MP0), and the gate and drain of the second transistor are connected to the drain of the secondary side transistor (MP1).

[0096] With this configuration, in the overcurrent protection circuit 202b, when the output current Iout is equal to or less than the upper limit current value IOmax, the current I1 flowing through transistor MN1, the current I3 flowing through transistor MN4, and the output current Iout change in accordance with the load current Iload sent to the load LD, as shown in FIG. 7.

[0097] Thus, in the overcurrent protection circuits 202 and 202a shown in Figures 3 to 5, the current consumption is constant regardless of the magnitude of the load current Iload, as shown by the dashed line in Figure 8, whereas in the overcurrent protection circuit 202b, when the load current Iload is equal to or less than the upper limit current value IOmax, the current consumption decreases as the load current Iload becomes smaller.

[0098] In the regulator circuit 200C shown in FIG. 6, the transistor HV_MP1 can also be modified to have an open-drain configuration so that the load LD can be driven by the external bipolar transistor TR as shown in FIG.

[0099] 6, the current I3 generated by the transistor MN4 may be reflected in the bias current that determines the current output capacity of the operational amplifier OP1. This allows the current output capacity of the operational amplifier OP1 to be adjusted according to the load current, and makes it possible to reduce the current consumption of the operational amplifier OP1 when there is no load.

[0100] As the power supply circuit 201 included in the regulator circuits 200, 200A to 200C, a switching regulator including capacitors C2, C3, a coil LC, a transistor QT, and a control circuit CNT as shown in FIG. 9 may be used.

[0101] As shown in FIG. 9, a high power supply voltage HV_VDD is applied to one end of a capacitor C2, and the other end is grounded at a ground potential VSS. A high power supply voltage HV_VDD is applied to the drain of an N-channel transistor QT, and its source and back gate are connected to one end of a coil LC. One end of a capacitor C3 and a control circuit CNT are connected to the other end of the coil LC. The control circuit CNT generates a control signal that alternately switches the transistor QT between on and off so that the voltage at the other end of the coil LC becomes a predetermined voltage value lower than the high power supply voltage HV_VDD, and supplies this to the gate of the transistor QT. As a result, a low power supply voltage VDD having the predetermined voltage value is generated at the other end of the coil LC. EXAMPLES

[0102] FIG. 10 is a circuit diagram showing a configuration of a regulator circuit 200D according to a third embodiment of the present invention.

[0103] The regulator circuit 200D may include a first current mirror circuit 30, a logic circuit 31, a trimming circuit 32, and an overcurrent protection circuit 202d.

[0104] (First current mirror circuit 30) The first current mirror circuit 30 may include a transistor HV_MP0 and a transistor HV_MP1.

[0105] (Logic Circuit 31) The logic circuit 31 may be interpreted as a circuit that outputs a logic signal. The logic signal may be interpreted as a trimming signal. The trimming signal may be interpreted as a signal for changing the value of an upper limit current Ilimit that defines the upper limit of the output current Iout. The trimming signal may include a first trimming signal (TRM0) and a second trimming signal (TRM1).

[0106] (Trimming circuit 32) The trimming circuit 32 may include a latch circuit 32a and a current modifying circuit 32b.

[0107] (Latch circuit 32a) The latch circuit 32a may be interpreted as a circuit that, when the output voltage VOUT drops while one or more first logic signals are being input, holds the voltage of the first logic signal and outputs the held voltage as a second logic signal.

[0108] When the output voltage VOUT drops, it may be interpreted as the latch circuit 32a receiving the UVLO signal output from the drop detection circuit 31a. The drop detection circuit 31a may compare the output voltage VOUT with a specific value, and when the output voltage VOUT is equal to or lower than the specific value, it may output a signal indicating that the output voltage VOUT has dropped. This signal may be interpreted as a UVLO signal.

[0109] When the UVLO signal is input, the latch circuit 32a may hold the voltage of the trimming signal, which is the first logic signal.

[0110] Specifically, if the value of the trimming signal is H level when the UVLO signal is input, even if the value of the trimming signal changes to L level, the H level trimming signal may be held, and the held H level trimming signal may be output as the second logic signal.

[0111] If the value of the trimming signal is at L level when the UVLO signal is input, even if the value of the trimming signal changes to H level, the trimming signal at L level may be held, and the held L-level trimming signal may be output as the second logic signal.

[0112] The latch circuit 32a may generate a second logic signal using a low power supply voltage VDD. The second logic signal may be interpreted as at least one of a trimming signal (TRM0_LCH) that holds the first trimming signal (TRM0) and a trimming signal (TRM1_LCH) that holds the second trimming signal (TRM1). A detailed configuration example of the latch circuit 32a will be described later.

[0113] The trimming signal (TRM0_LCH) may be input to the gate of an N-channel transistor MN8, and the trimming signal (TRM1_LCH) may be input to the gate of an N-channel transistor MN9.

[0114] (Current changing circuit 32b) The current change circuit 32b may be interpreted as a circuit that changes the value of the upper limit current Ilimit based on the second logic signal, with a current corresponding to a predetermined value being the upper limit current Ilimit.

[0115] The current changing circuit 32b may include N-channel transistors MN4, MN5, MN6, MN7, MN8, and MN9.

[0116] (Transistor MN4) The drain of transistor MN4 may be connected to bias current Ibias2 and the gate of transistor MN4. The drain of transistor MN4 may be connected to the gates of transistor MN5, transistor MN6, and transistor MN7. The source of transistor MN4 may be grounded to ground potential VSS. The gate of transistor MN4 may be connected to the gates of transistor MN5, transistor MN6, and transistor MN7.

[0117] (Transistor MN5) The drain of the transistor MN5 may be connected to the second current mirror circuit 40, which is a current source of the bias current Ibias6. The drain of the transistor MN5 may receive a bias current Ibias3, which is a part of the bias current Ibias6. The source of the transistor MN5 may be grounded to the ground potential VSS. The gate of the transistor MN5 may be connected to the gates of the transistor MN4, the transistor MN6, and the transistor MN7.

[0118] (Transistor MN6) The drain of the transistor MN6 may be connected to the source of the transistor MN8. A bias current Ibias4, which is a part of the bias current Ibias6, may be input to the drain of the transistor MN6. The source of the transistor MN6 may be grounded to the ground potential VSS. The gate of the transistor MN6 may be connected to the gates of the transistor MN4, the transistor MN5, and the transistor MN7.

[0119] (Transistor MN7) The drain of transistor MN7 may be connected to the source of transistor MN9. A bias current Ibias5, which is a part of the bias current Ibias6, may be input to the drain of transistor MN7. The source of transistor MN7 may be grounded to the ground potential VSS. The gate of transistor MN7 may be connected to the gates of transistor MN4, transistor MN5, and transistor MN6.

[0120] (Transistor MN8) The drain of the transistor MN8 may be connected to the second current mirror circuit 40, which is a current source of the bias current Ibias6. The source of the transistor MN8 may be connected to the drain of the transistor MN6. The gate of the transistor MN8 may be connected to the latch circuit 32a.

[0121] (Transistor MN9) The drain of the transistor MN9 may be connected to the second current mirror circuit 40, which is a current source of the bias current Ibias6. The source of the transistor MN9 may be connected to the drain of the transistor MN7. The gate of the transistor MN9 may be connected to the latch circuit 32a.

[0122] When the second logic signal is input only to the transistor MN8, the transistor MN8 is turned on and a bias current Ibias4 flows.

[0123] When the second logic signal is input only to the transistor MN9, the transistor MN9 is turned on and a bias current Ibias5 flows.

[0124] When a second logic signal is input to the transistors MN8 and MN9, the transistors MN8 and MN9 are turned on, causing the bias currents Ibias4 and Ibias5 to flow.

[0125] In this way, the value of the bias current Ibias6 can be changed to a specific value by changing the input state of the second logic signal to the current change circuit 32b. Changing the value of the bias current Ibias6 to a specific value may be interpreted as trimming (adjusting) the value of the bias current Ibias6.

[0126] Since the second current mirror circuit 40 outputs a current obtained by copying the bias current Ibias6 as the upper limit current Ilimit, the current change circuit 32b may be interpreted as a circuit for trimming (adjusting) the value of the upper limit current Ilimit.

[0127] (Overcurrent protection circuit 202d) The overcurrent protection circuit 202d may be interpreted as a circuit for protecting a specific circuit from an overcurrent by limiting the current value of the output current Iout to a predetermined value or less. The overcurrent protection circuit 202d may be interpreted as a circuit for generating an upper limit current Ilimit that defines the upper limit of the output current Iout based on a second power supply voltage. The second power supply voltage may be interpreted as a low power supply voltage VDD.

[0128] The overcurrent protection circuit 202d may include a second current mirror circuit 40, an N-channel transistor MN0, and an N-channel transistor MN1.

[0129] (Second current mirror circuit 40) The second current mirror circuit 40 may be interpreted as a circuit that inputs a current obtained by copying the current output by the current change circuit 32b as an upper limit current Ilimit to the first current path 33. The second current mirror circuit 40 may be interpreted as the current source CD1 shown in Fig. 3. The second current mirror circuit 40 may include a P-channel transistor MP0 and a P-channel transistor MP1.

[0130] The transistors MP0 and MP1 may have their respective sources and back gates connected together, and a low power supply voltage VDD may be applied to the sources and back gates.

[0131] The gates of the transistors MP0 and MP1 may be connected to the current modifying circuit 32b.

[0132] The drain of the transistor MP0 may be connected to the gate of the transistor MP0 and the current modifying circuit 32b.

[0133] The drain of transistor MP1 may be connected to transistor MN0.

[0134] The second current mirror circuit 40 thus configured may generate a current that specifies (or sets) an upper limit, that is, a threshold value that is a boundary between whether or not an overcurrent occurs, based on the low power supply voltage VDD. The second current mirror circuit 40 may supply the generated current as an upper limit current Ilimit to the drain and gate of the transistor MN0.

[0135] (Transistor MN0) The source of the transistor MN0 may be grounded to the ground potential VSS. The drain of the transistor MN0 may be connected to the second current mirror circuit 40 and the gate of the transistor MN0. The gate of the transistor MN0 may be connected to the gate of the transistor MN1.

[0136] (Transistor MN1) The transistor MN1 may be interpreted as a first transistor connected to the first current path 33. The transistor MN1 may receive the upper limit current Ilimit at the gate of the transistor MN1 and may cause a first current to flow between the source and drain of the transistor MN1. The first current may be interpreted as a first current (current I1) flowing in the first current path 33.

[0137] Fig. 11 is a diagram showing an example of the configuration of the latch circuit 32a. Fig. 11 shows the latch circuit 32a that outputs a trimming signal (TRM0_LCH) that holds the first trimming signal (TRM0) when a UVLO signal is input.

[0138] The latch circuit 32a may include an N-channel transistor MN10, a logical NOT circuit 41, and a P-channel transistor MP4.

[0139] (Transistor MN10) The transistor MN10 may be interpreted as a transistor that outputs, from its source, a first logic signal input to its drain when a voltage drop signal indicating that the output voltage VOUT has dropped is input to its gate.

[0140] The drain of transistor MN10 may be connected to the logic circuit 31 shown in Fig. 10. The gate of transistor MN10 may be connected to a drop detection circuit 31a shown in Fig. 10. The source of transistor MN10 may be connected to the input terminal of a logical NOT circuit 41. The back gate of transistor MN10 may be grounded to the ground potential VSS.

[0141] (Logical NOT circuit 41) The logical NOT circuit 41 may be considered as an inverter circuit that outputs an inverted signal S1 obtained by inverting the level of the first logic signal output from the N-channel transistor.

[0142] (Transistor MP4) The transistor MP4 may be interpreted as a transistor that outputs, from its drain, a second logic signal that is generated based on the second power supply voltage applied to its source when the inverted signal S1 is input to its gate.

[0143] 10. The gate of the transistor MP4 may be connected to the output terminal of the logical NOT circuit 41. A low power supply voltage VDD may be applied to the source and back gate of the transistor MP4.

[0144] The latch circuit 32a shown in FIG. 11 may have a function of receiving the second trimming signal (TRM1) and outputting a trimming signal (TRM1_LCH) that holds the second trimming signal (TRM1).

[0145] (operation) The output current Iout of the regulator circuit 200D can be adjusted by the upper limit current Ilimit. Specifically, when the W / L aspect ratios of MP0 and MP1 are the same, the upper limit current Ilimit is equal to Ibias6 (Ilimit=Ibias6).

[0146] Since the bias current Ibias6 varies depending on the trimming signals TRM0 / TRM1, the value of the bias current Ibias6 can be defined as follows: In other words, the output current Iout of the regulator circuit 200D can be adjusted by the trimming signals TRM0 / TRM1. (When TRM0=1, TRM1=1, Ibias6=Ibias3+Ibias4+Ibias5) (When TRM0=1, TRM1=0, Ibias6=Ibias3+Ibias4) (When TRM0=0 and TRM1=1, Ibias6=Ibias3+Ibias5) (When TRM0=0, TRM1=0, Ibias6=Ibias3)

[0147] (Comparative Example) 12 is a circuit diagram showing a configuration of a regulator circuit 200E according to a first comparative example. The regulator circuit 200E does not include a latch circuit 32a. The power source of the logic circuit 31 of the regulator circuit 200E is the regulator output voltage (output voltage VOUT). Therefore, when the regulator output voltage is short-circuited, that is, when the regulator output voltage=0V, the power supply voltage of the logic circuit 31 becomes 0V. Therefore, the value of the trimming signal output from the logic circuit 31 becomes an L level, and the output current Iout does not become a trimmed value.

[0148] A comparative example having a configuration for solving such problems is shown in Fig. 13. Fig. 13 is a circuit diagram showing the configuration of a regulator circuit 200F according to a second comparative example. The regulator circuit 200F includes a regulator circuit 42 for logic.

[0149] The regulator circuit for logic 42 may be considered as a power supply circuit that supplies power to the logic circuit 31. By providing the regulator circuit for logic 42, the logic circuit 31 operates even when the regulator output voltage is 0 V, and the output current Iout becomes a trimmed value. However, the current consumption generated inside the regulator circuit for logic 42 increases, and adding the regulator circuit for logic 42 may increase the circuit area of ​​the regulator circuit 200F.

[0150] (Action and effect) According to the regulator circuit 200D of the present disclosure, by providing the latch circuit 32a, even if the output voltage VOUT drops, the voltage of the first logic signal can be held and the held voltage can be output as the second logic signal. Therefore, the second logic signal having the same voltage level as the first logic signal can be continuously output without using the regulator circuit for logic 42. Therefore, an increase in the circuit area of ​​the regulator circuit 200D as a whole can be suppressed. Also, an increase in the current consumption of the regulator circuit 200D as a whole can be suppressed. Also, since it is not necessary to provide the regulator circuit for logic 42 outside the trimming circuit 32, the circuit configuration of the regulator circuit 200D can be simplified and the reliability of the regulator circuit 200D can be improved.

[0151] In addition, the following supplementary notes are provided in relation to the above description.

[0152] (Appendix 1) A regulator circuit that generates an output voltage having a value corresponding to a reference voltage based on a first power supply voltage, and outputs the output voltage from an output terminal, a power supply circuit that generates a second power supply voltage, the second power supply voltage being lower than the first power supply voltage, based on the first power supply voltage; an operational amplifier that operates based on the second power supply voltage and generates a differential voltage that represents a difference between a voltage obtained by dividing the output voltage and the reference voltage; a first current path for passing a first current corresponding to the differential voltage; a first current mirror circuit that outputs a current obtained by copying the first current as an output current to the output terminal; an overcurrent protection circuit that limits a current value of the output current to a predetermined value or less; a latch circuit that, when the output voltage drops while one or more first logic signals are being input, holds a voltage of the first logic signal and outputs the held voltage as a second logic signal; a current change circuit that changes a value of the upper limit current based on the second logic signal and sets a current corresponding to the predetermined value as an upper limit current; Equipped with the overcurrent protection circuit includes a first transistor connected to the first current path, receiving the upper limit current at a gate of the overcurrent protection circuit and causing the first current to flow between a source and a drain of the overcurrent protection circuit.

[0153] (Appendix 2) The latch circuit includes: an N-channel transistor that outputs, from a source, the first logic signal input to its drain when a voltage drop signal indicating that the output voltage has dropped is input to its gate; a logical NOT circuit that outputs an inverted signal obtained by inverting the level of the first logic signal output from the N-channel transistor; a P-channel transistor that outputs, from a drain, the second logic signal that is generated based on the second power supply voltage applied to a source when the inverted signal is input to a gate of the P-channel transistor; 2. The regulator circuit of claim 1, comprising:

[0154] (Appendix 3) 2. The regulator circuit of claim 1, wherein the overcurrent protection circuit includes a second current mirror circuit that inputs a current that is a copy of the current output by the current change circuit as the upper limit current to the first current path. [Explanation of symbols]

[0155] 1 Stabilized power supply circuit 2 Reference voltage generation circuit 3. Operational Amplifiers 21 Current source 30 First current mirror circuit 31 Logic Circuits 31a Decrease detection circuit 32 Trimming circuit 32a Latch circuit 32b Current change circuit 33 First current path 40 Second current mirror circuit 41 Logical Negation Circuit 42 Regulator circuit for logic 102 Reference voltage generation circuit 200 Regulator circuit 200A regulator circuit 200B regulator circuit 200C regulator circuit 200D Regulator circuit 200E regulator circuit 200F regulator circuit 201 Power supply circuit 202 Overcurrent protection circuit 202a Overcurrent protection circuit 202b Overcurrent protection circuit 202d overcurrent protection circuit

Claims

1. A regulator circuit that generates an output voltage having a value corresponding to a reference voltage based on a first power supply voltage, and outputs the output voltage from an output terminal, a power supply circuit that generates a second power supply voltage, the second power supply voltage being lower than the first power supply voltage, based on the first power supply voltage; an operational amplifier that operates based on the second power supply voltage and generates a differential voltage that represents a difference between a voltage obtained by dividing the output voltage and the reference voltage; a first current path for passing a first current corresponding to the differential voltage; a first current mirror circuit that outputs a current obtained by copying the first current as an output current to the output terminal; an overcurrent protection circuit that limits a current value of the output current to a predetermined value or less; a latch circuit that holds a voltage of the first logic signal when the output voltage drops while one or more first logic signals are being input, and outputs the held voltage as a second logic signal; a current change circuit that changes a value of the upper limit current based on the second logic signal and sets a current corresponding to the predetermined value as an upper limit current; Equipped with the overcurrent protection circuit includes a first transistor connected to the first current path, receiving the upper limit current at a gate of the overcurrent protection circuit and causing the first current to flow between a source and a drain of the overcurrent protection circuit.

2. The latch circuit includes: an N-channel transistor that outputs, from a source, the first logic signal input to its drain when a voltage drop signal indicating that the output voltage has dropped is input to its gate; a logical NOT circuit that outputs an inverted signal obtained by inverting a level of the first logic signal output from the N-channel transistor; a P-channel transistor that outputs, from a drain, the second logic signal that is generated based on the second power supply voltage applied to a source when the inverted signal is input to a gate of the P-channel transistor; 2. The regulator circuit of claim 1 , comprising:

3. 2. The regulator circuit according to claim 1, wherein the overcurrent protection circuit includes a second current mirror circuit that inputs a current obtained by copying a current output by the current change circuit as the upper limit current to the first current path.

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