Semiconductor device and method for manufacturing semiconductor device

Abstract

To provide a semiconductor device and a method for manufacturing the same that can improve reliability.SOLUTION: A semiconductor device according to an embodiment comprises: a semiconductor section with a first main surface and a second main surface on the opposite side of the first main surface; a surface structure provided on the first main surface and including a first electrode; a second electrode provided on the second main surface; a first protective resin film covering a top surface of the surface structure; and a second protective resin film connected to the first protective resin film and covering the sides of the surface structure.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device and a method for manufacturing a semiconductor device. [Background technology]

[0002] 2. Description of the Related Art In semiconductor devices such as metal oxide semiconductor field effect transistors (MOSFETs), metal parts such as wiring layers and electrodes are covered with a protective resin film such as a polyimide resin in order to protect the metal parts.

[0003] In order to prevent chipping and dust from occurring during the dicing process of a semiconductor device, the protective resin film on the dicing line is usually removed in advance. However, due to misalignment of the exposure position, the protective resin film covering the side of the metal part may also be removed. In such a case, foreign matter such as moisture and ions that have entered the semiconductor device may easily reach the metal part, causing a decrease in the reliability of the semiconductor device. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2003-249465 A [Patent Document 2] JP 2000-269166 A [Patent Document 3] Japanese Patent Application Publication No. 4-305945 Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present invention is to provide a semiconductor device and a manufacturing method thereof that can improve reliability. [Means for solving the problem]

[0006] The semiconductor device of the embodiment comprises a semiconductor portion having a first main surface and a second main surface opposite the first main surface, a surface structure portion provided on the first main surface and including a first electrode, a second electrode provided on the second main surface, a first protective resin film covering an upper surface of the surface structure portion, and a second protective resin film connected to the first protective resin film and covering a side surface of the surface structure portion. [Brief description of the drawings]

[0007] [Figure 1] 2 is a schematic cross-sectional view of a peripheral portion of the semiconductor device according to the embodiment. FIG. [Diagram 2] 4 is a cross-sectional view showing details of a peripheral portion of the semiconductor device according to the embodiment. FIG. [Diagram 3] 4 is a flowchart showing an example of a manufacturing process of a semiconductor device according to the embodiment. [Figure 4A] 5A to 5C are cross-sectional views for explaining an example of a manufacturing process of the semiconductor device according to the embodiment. [Figure 4B] 4B is a cross-sectional view illustrating an example of a manufacturing process of the semiconductor device according to the embodiment, subsequent to FIG. 4A. [Figure 4C] 4C is a cross-sectional view illustrating an example of a manufacturing process of the semiconductor device according to the embodiment, subsequent to FIG. 4B. [Figure 4D] 4D is a cross-sectional view illustrating an example of a manufacturing process of the semiconductor device according to the embodiment, subsequent to FIG. 4C. [Figure 4E] 4D, followed by a cross-sectional view for explaining an example of a manufacturing process of the semiconductor device according to the embodiment. FIG. [Diagram 5] 13 is a cross-sectional view showing details of a peripheral portion of a semiconductor device according to a modified example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The embodiment does not limit the present invention. The drawings are schematic or conceptual, and the ratio of each part is not necessarily the same as the actual one. In the specification and drawings, elements similar to those described above with respect to the previous drawings are given the same reference numerals, and detailed descriptions are omitted as appropriate.

[0009] For convenience of explanation, the gate wiring layer and source electrode side in the stacking direction (thickness direction) of the semiconductor device is also referred to as the "upper" and the drain electrode side is also referred to as the "lower." However, these expressions are for convenience and have no relation to the direction of gravity.

[0010] In the following description, n + , n, n - , and p + , p, p - In some cases, the notation n + has a relatively higher n-type impurity concentration than n, - indicates that the n-type impurity concentration is relatively lower than that of n. + has a relatively higher p-type impurity concentration than p, - indicates that the p-type impurity concentration is relatively lower than p. When both p-type and n-type impurities are contained in each region, these notations indicate the relative high and low net impurity concentrations after the impurities compensate for each other. Note that in the following explanation, n-type and p-type may be reversed.

[0011] <Semiconductor device> A semiconductor device 1 according to an embodiment will be described with reference to Figures 1 and 2. Figure 1 is a schematic cross-sectional view of a peripheral portion of the semiconductor device 1 according to the embodiment. Figure 2 is a cross-sectional view showing details of the peripheral portion of the semiconductor device 1 according to the embodiment. Note that the sealing portion 7 is omitted in Figure 2.

[0012] The following describes the case where the semiconductor device 1 is a vertical MOSFET.

[0013] As shown in FIG. 1, the semiconductor device 1 includes a semiconductor portion 2, a surface structure portion 3, a drain electrode 4, a protective resin film 5, an additional protective resin film 6, a sealing portion 7, a die pad 8, and a bonding material 9.

[0014] The semiconductor portion 2 has an upper surface (first main surface) 2a, a lower surface (second main surface) 2b opposite to the upper surface 2a, and a side surface 2c. As will be described in detail later, the semiconductor portion 2 includes semiconductor regions such as a drift region, a base region, a source region, and a drain region. For convenience of explanation, the upper surface 2a, the lower surface 2b, and the side surface 2c of the semiconductor portion 2 are approximately planar, but this does not limit the shape of the semiconductor portion 2.

[0015] The semiconductor portion 2 may be an epitaxial layer, a semiconductor substrate, or a semiconductor substrate and an epitaxial layer disposed thereon. In this embodiment, the semiconductor portion 2 is silicon (Si). In this case, for example, arsenic (As), phosphorus (P), or antimony (Sb) is used as the n-type impurity, and for example, boron (B) is used as the p-type impurity. The semiconductor portion 2 may be made of a compound semiconductor such as silicon carbide (SiC) or gallium nitride (GaN).

[0016] A surface structure 3 is provided on an upper surface 2a of the semiconductor portion 2. In this embodiment, as shown in Fig. 2, the surface structure 3 includes a gate wiring layer 31 and an interlayer insulating film 32. Although not shown, the surface structure 3 may also include a source electrode, wiring, and the like.

[0017] The gate wiring layer 31 is a wiring layer provided on the upper surface 2a of the semiconductor portion 2 to electrically connect gate electrodes 26 described below to each other. The gate wiring layer 31 is made of a metal such as copper, titanium, tungsten, or aluminum. The gate wiring layer 31 is an example of a first electrode in the claims.

[0018] The interlayer insulating film 32 is provided between the semiconductor portion 2 and the gate wiring layer 31. The gate wiring layer 31 is electrically insulated from the semiconductor portion 2 by the interlayer insulating film 32. Meanwhile, the gate wiring layer 31 is electrically connected to a gate electrode 26 (described later) via a contact plug 41 that fills an opening provided in the interlayer insulating film 32 and a gate insulating film 24 (described later). The contact plug 41 is made of a metal such as copper, titanium, tungsten, or aluminum, or polysilicon containing p-type or n-type impurities.

[0019] 2, the upper surface 2a of the semiconductor portion 2 has an end portion 2ae where the surface structure portion 3 is not provided. More specifically, the upper surface 2a of the semiconductor portion 2 has an end portion 2ae that is not covered with the interlayer insulating film 32. This end portion 2ae is a margin region provided to prevent the dicing blade from coming into contact with the interlayer insulating film 32 due to misalignment of the dicing blade during the dicing process.

[0020] 2, in this embodiment, the end 32e of the interlayer insulating film 32 is not covered by the gate wiring layer 31, but is instead covered by an additional protective resin film 6 described below. However, this is not limited thereto, and the end 32e of the interlayer insulating film 32 may be covered by the gate wiring layer 31.

[0021] As shown in Fig. 1, a drain electrode 4 is provided on the lower surface 2b of the semiconductor portion 2. The drain electrode 4 is an electrode that functions as a drain electrode of a MOSFET. The drain electrode 4 is made of a metal such as copper, titanium, tungsten, or aluminum. The drain electrode 4 is an example of a second electrode in the claims.

[0022] The protective resin film 5 is provided so as to cover the upper surface of the surface structure portion 3. In this embodiment, as shown in Fig. 2, the protective resin film 5 is provided so as to cover the upper surface of the gate wiring layer 31. The protective resin film 5 is an example of a first protective resin film in the claims.

[0023] On the other hand, the protective resin film 5 does not cover the side surface of the surface structure portion 3. In this embodiment, the protective resin film 5 does not cover the side surface of the gate wiring layer 31 of the surface structure portion 3, as shown in FIG.

[0024] The material of the protective resin film 5 is, for example, a polyimide resin. Note that the material of the protective resin film 5 may be a polyamide resin, a polyolefin resin, a polybenzoxazole resin, a silicone resin, or the like.

[0025] The additional protective resin film 6 is provided so as to cover the side surfaces of the surface structure portion 3 that are not covered by the protective resin film 5. In this embodiment, as shown in FIG. 2, the additional protective resin film 6 covers the side surfaces of the gate wiring layer 31 that are not covered by the protective resin film 5. The additional protective resin film 6 is also connected to the protective resin film 5. In this manner, the protective resin film 5 does not cover the ends including the corners and sides of the surface structure portion 3, but the additional protective resin film 6 covers these ends. The additional protective resin film 6 is an example of a second protective resin film in the claims.

[0026] Furthermore, in this embodiment, the additional protective resin film 6 further covers the end 2ae of the top surface 2a of the semiconductor portion 2 and the side surface 2c of the semiconductor portion 2, in addition to the side surface of the surface structure portion 3. That is, as shown in Fig. 1, the additional protective resin film 6 is also provided between the semiconductor portion 2 and the sealing portion 7. Furthermore, in this embodiment, the additional protective resin film 6 covers up to the bottom of the side surface 2c of the semiconductor portion 2, as shown in Fig. 1.

[0027] The material of the additional protective resin film 6 is, for example, a polyimide resin. The material of the additional protective resin film 6 may be a polyamide resin, a polyolefin resin, a polybenzoxazole resin, a silicone resin, or the like. The material of the additional protective resin film 6 may be the same as or different from the material of the protective resin film 5.

[0028] 1, the sealing portion 7 is provided so as to embed at least the semiconductor portion 2, the surface structure portion 3, the protective resin film 5, and the additional protective resin film 6. In this embodiment, the sealing portion 7 further embeds the drain electrode 4 and the bonding material 9. The material of the sealing portion 7 is, for example, epoxy resin.

[0029] When the material of the sealing portion 7 is epoxy resin, the adhesion between the additional protective resin film 6 and the sealing portion 7 can be improved by using a polyimide resin as the material of the additional protective resin film 6.

[0030] The die pad 8 is a die pad (bed) in the semiconductor device 1, on which the semiconductor part 2 and the like are mounted. The die pad 8 is obtained, for example, by punching a metal plate. The material of the die pad 8 is not particularly limited, but may be, for example, copper, 42% Ni-Fe alloy (42 alloy), etc.

[0031] 1, the die pad 8 has a die pad upper surface (first die pad main surface) 8a and a die pad lower surface (second die pad main surface) 8b opposite to the die pad upper surface 8a, and the drain electrode 4 is bonded to the die pad upper surface 8a via a bonding material 9. In this embodiment, the bonding material 9 is a conductive material such as solder, and the die pad 8 is electrically connected to the drain electrode 4 via the bonding material 9.

[0032] In this embodiment, the die pad upper surface 8a and the side surface of the die pad 8 are covered by the sealing portion 7. On the other hand, the die pad lower surface 8b of the die pad 8 is not covered by the sealing portion 7 and is exposed. That is, in the semiconductor device 1, a boundary B between the sealing portion 7 and the die pad 8 is exposed. Therefore, there is a possibility that foreign matter such as moisture or ions may infiltrate from this boundary B. However, by providing the additional protective resin film 6 that covers the side surface of the gate wiring layer 31, it is possible to prevent the foreign matter infiltrating from the boundary B from reaching the side surface of the gate wiring layer 31.

[0033] The sealing form by the sealing part 7 is not limited to that shown in FIG. 1. For example, the sealing part 7 may cover a part of the die pad lower surface 8b of the die pad 8 in addition to the die pad upper surface 8a and the side surface of the die pad 8. Alternatively, the sealing part 7 may cover the die pad upper surface 8a of the die pad 8 but not cover at least a part of the side surface of the die pad 8. In any sealing form, the boundary between the sealing part 7 and the die pad 8 is exposed, and therefore, foreign matter such as moisture or ions may infiltrate from this boundary. However, according to the present embodiment, the additional protective resin film 6 that covers the side surface of the gate wiring layer 31 is provided, so that it is possible to prevent the foreign matter infiltrating from the boundary from reaching the side surface of the gate wiring layer 31.

[0034] Next, the semiconductor portion 2 in this embodiment will be described in detail with reference to FIG.

[0035] As shown in FIG. 2, the semiconductor portion 2 includes a drift region 21, a base region 22, a source region 23, a drain region (not shown), a gate insulating film 24, a field plate insulating film 25, a gate electrode 26, a field plate 27, a field plate insulating film 28, and a field plate 29.

[0036] The drift region 21 is a semiconductor region that functions as a drift region of the MOSFET. The drift region 21 is disposed above a drain region (above the drain electrode 4) not shown. The drift region 21 is, for example, an n - The n-type impurity concentration of the drift region 21 is, for example, 1×10 15 cm -3 More than 2×10 16 cm -3 The following is the result.

[0037] The base region 22 is a semiconductor region that functions as a base region of the MOSFET. In the left-right direction, the base region 22 is disposed at a position sandwiched between the gate insulating films 24, and in the up-down direction, the base region 22 is disposed on the drift region 21. When a voltage is applied to the gate electrode 26, a channel is formed in the base region 22, and carriers flow between the drift region 21 and the source region 23. The base region 22 is, for example, a p-type semiconductor region. The p-type impurity concentration of the base region 22 is, for example, 1×10 16 cm -3 More than 1×10 20 cm -3 The following is the result.

[0038] The source region 23 is a semiconductor region that functions as a source region of the MOSFET. The source region 23 is disposed between the base region 22 and the interlayer insulating film 32. The source region 23 is, for example, an n + The source region 23 has an n-type impurity concentration of, for example, 1×10 18 cm -3 More than 1×10 22 cm -3 The following is the result.

[0039] Although not shown, a drain region that functions as the drain region of the MOSFET is disposed between the drift region 21 and the drain electrode 4. This drain region is, for example, an n + The n-type impurity concentration of this drain region is, for example, 1×10 18 cm -3 More than 1×10 21 cm -3 The following is the result.

[0040] As shown in FIG. 2, the semiconductor portion 2 is provided with a plurality of gate insulating films 24 and a plurality of field plate insulating films 25 disposed thereunder. Each of the field plate insulating films 25 is provided so as to reach the drift region 21. The gate insulating film 24 and the field plate insulating film 25 are made of a dielectric material covering the side walls of a plurality of trenches provided in the upper surface 2a of the semiconductor portion 2. The gate insulating film 24 and the field plate insulating film 25 are made of a dielectric material such as silicon oxide or silicon nitride. As shown in FIG. 2, the gate insulating film 24 between the gate electrode 26 and the base region 22 is thinner than the field plate insulating film 25 between the field plate 27 and the drift region 21.

[0041] A gate electrode 26 is provided in each gate insulating film 24. The gate electrode 26 functions as a gate electrode of the MOSFET. In this embodiment, the upper end of the gate electrode 26 is located higher than the upper end of the base region 22, and the lower end of the gate electrode 26 is located lower than the lower end of the base region 22. The gate electrode 26 is disposed adjacent to (facing) the base region 22 with the gate insulating film 24 interposed therebetween.

[0042] The gate electrode 26 is made of, for example, polysilicon containing p-type or n-type impurities. The gate electrode 26 may be made of a metal such as copper, titanium, tungsten, or aluminum. The gate electrode 26 is electrically connected to the gate wiring layer 31 via the above-mentioned contact plug 41. The gate electrode 26 is electrically insulated from the semiconductor portion 2 by the gate insulating film 24.

[0043] A field plate 27 is provided in each field plate insulating film 25. The field plate 27 is made of polysilicon containing p-type or n-type impurities or the like. Each field plate 27 is electrically connected to the source electrode. By providing such a field plate 27, when the MOSFET is in the off state, a depletion layer extends from the field plate insulating film 25 to the drift region 21 due to a voltage applied between the source electrode and the drain electrode 4. This depletion layer connects to the depletion layer extending from the adjacent field plate insulating film 25, and the breakdown voltage of the semiconductor device 1 can be improved.

[0044] A plurality of field plates 29 are provided on the periphery of the semiconductor portion 2 via a plurality of field plate insulating films 28. In this embodiment, as shown in FIG. 2, two field plate insulating films 28 are provided, and a field plate 29 is provided in each field plate insulating film 28. That is, in this embodiment, two field plates 29 are provided on the periphery of the semiconductor portion 2. The number of field plates 29 may be one, or may be three or more. The field plate insulating film 28 is made of a dielectric material that covers the side walls of a plurality of field plate trenches provided on the upper surface 2a of the semiconductor portion 2. The field plate insulating film 28 is made of a dielectric material such as silicon oxide or silicon nitride.

[0045] 2, in this embodiment, the depth from the upper surface 2a of the semiconductor portion 2 to the lower end of the field plate insulating film 28 is approximately the same as the depth from the upper surface 2a of the semiconductor portion 2 to the lower end of the field plate insulating film 25. However, this is not limited to this, and the depth from the upper surface 2a of the semiconductor portion 2 to the lower end of the field plate insulating film 28 may be different from the depth from the upper surface 2a of the semiconductor portion 2 to the lower end of the field plate insulating film 25.

[0046] Each field plate 29 is electrically connected to a source electrode. By providing such field plates 29, the concentration of the reverse electric field between the gate wiring layer 31 and the drain electrode 4 can be alleviated, and the breakdown voltage of the semiconductor device 1 can be improved.

[0047] Although the configuration example of the semiconductor section 2 according to the present embodiment has been described above, the configuration of the semiconductor section 2 is not limited to the above, and may have any configuration depending on the type and function of the semiconductor device 1. The semiconductor device 1 is not limited to a MOSFET, and may be, for example, an IGBT (Insulated Gate Bipolar Transistor), a diode, a light-emitting diode, or a semiconductor laser. In the case of an IGBT, the conductivity type of the drain region of the semiconductor section 2 may be changed.

[0048] As described above, according to the semiconductor device 1 of the embodiment, the additional protective resin film 6 is provided, which is connected to the protective resin film 5 and covers the side surface of the surface structure portion 3 that is not covered by the protective resin film 5. This makes it possible to prevent foreign matter that has entered through the boundary B between the sealing portion 7 and the die pad 8 from reaching the gate wiring layer 31 of the surface structure portion 3. Therefore, for example, it is possible to prevent the gate wiring layer 31 from being oxidized (anodized, etc.) by the foreign matter. Therefore, the reliability of the semiconductor device 1 can be improved.

[0049] Furthermore, in this embodiment, the additional protective resin film 6 covers the end 2ae of the upper surface 2a of the semiconductor portion 2 and the side surface 2c of the semiconductor portion 2, in addition to the side surface of the surface structure portion 3. This makes it possible to further prevent foreign matter that has entered through the boundary B between the sealing portion 7 and the die pad 8 from reaching the gate wiring layer 31.

[0050] In this embodiment, the additional protective resin film 6 covers up to the bottom of the side surface 2c of the semiconductor portion 2. This makes it possible to further prevent foreign matter that has entered through the boundary B between the sealing portion 7 and the die pad 8 from reaching the gate wiring layer 31.

[0051] A source electrode (an emitter electrode when the semiconductor device 1 is an IGBT) may be provided instead of the gate wiring layer 31 at the position of the gate wiring layer 31 of the surface structure portion 3 shown in Fig. 2. The source electrode is usually used as a cathode, but may also be used as an anode in, for example, the switching operation of a MOSFET. Even in such a case, by providing the additional protective resin film 6, it is possible to prevent the source electrode from being oxidized (anodic oxidation, etc.) by foreign matter.

[0052] <Method of Manufacturing Semiconductor Device> Next, an example of a method for manufacturing the semiconductor device 1 according to this embodiment will be described with reference to the flowchart in FIG. 3 and the process cross-sectional views in FIGS. 4A to 4E.

[0053] First, dicing is performed to form a plurality of semiconductor device pieces 10 (step S1). More specifically, first, as shown in FIG. 4A, a semiconductor wafer 20 having an upper surface (first main surface) 2a and a lower surface (second main surface) 2b opposite to the upper surface 2a is prepared. A plurality of surface structure parts 3 including a gate wiring layer and a plurality of protective resin films 5 covering the surface structure parts 3 are formed on the upper surface 2a of the semiconductor wafer 20, and a drain electrode 4 is formed on the lower surface 2b of the semiconductor wafer 20. Although not shown, semiconductor regions such as a drift region 21, a base region 22, a source region 23, and a drain region, a gate electrode 26, field plates 27, 29, etc. are formed inside the semiconductor wafer 20.

[0054] The semiconductor wafer 20 before dicing shown in Fig. 4A is formed, for example, by the following process. A plurality of surface structures 3 including a gate wiring layer are formed on the upper surface 2a of the semiconductor wafer 20 so as to avoid the dicing line DL, and a drain electrode 4 is formed on the lower surface 2b of the semiconductor wafer 20. After that, a protective resin layer is formed on the upper surface 2a of the semiconductor wafer 20 so as to embed the plurality of surface structures 3, and a resist film (not shown) is formed to cover the upper surface of the formed protective resin layer.

[0055] Thereafter, the resist film in the dicing lines DL is removed by photolithography. Then, using the patterned resist film as a mask, the protective resin layer in the dicing lines DL is removed by etching to form a plurality of protective resin films 5. When the resist film is patterned by photolithography, the protective resin layer directly below the openings of the resist film may be removed together with the resist film to form a plurality of protective resin films 5. Thereafter, the resist film is peeled off from the upper surface of the protective resin film 5 to obtain the semiconductor wafer 20 shown in FIG. 4A.

[0056] In the above process, for example, due to misalignment of exposure in photolithography, after etching of the protective resin layer, the end of the surface structure 3 may not be covered by the protective resin film 5. Fig. 4A shows a case where the end of the surface structure 3 is not covered by the protective resin film 5.

[0057] Next, the semiconductor wafer 20 is fixed to the dicing sheet 100 so that the lower surface 2b of the semiconductor wafer 20 faces the dicing sheet 100. In this embodiment, the drain electrode 4 is fixed to the dicing sheet 100 so as to be in contact with the dicing sheet 100.

[0058] Thereafter, the semiconductor wafer 20 is divided into a plurality of semiconductor parts 2 by dicing the semiconductor wafer 20 along the dicing lines DL shown in FIG. 4A. In this embodiment, the dicing is performed until the dicing sheet 100 is reached. As a result, a plurality of semiconductor device pieces 10 are formed as shown in FIG. 4B. More specifically, each semiconductor device piece 10 includes a semiconductor part 2 having an upper surface 2a and a lower surface 2b, a surface structure part 3 including a gate wiring layer 31 provided on the upper surface 2a, a drain electrode 4 provided on the lower surface 2b, and a protective resin film 5 covering the upper surface of the surface structure part 3, and is fixed to the dicing sheet 100. In the following description, the semiconductor device piece 10 on the right side in FIG. 4B is omitted.

[0059] Next, as shown in FIG. 4C, the resin material is sprayed onto the side surface of the surface structure portion 3 (step S2). In this embodiment, the resin material is sprayed onto the side surface of the protective resin film 5, the side surface of the surface structure portion 3, the end of the upper surface 2a of the semiconductor portion 2, and the side surface 2c of the semiconductor portion 2 using a spray 200 such as an inkjet or aerosol spray. The resin material is, for example, a polyimide resin. The resin material may be a silicon resin, a polybenzoxazole resin, a polyamide resin, or a polyolefin resin. A polyimide precursor may also be used as the resin material. In the case of a resin material that dissolves in an organic solvent, a varnish-like material in which the resin material is dissolved in an organic solvent may also be sprayed.

[0060] Next, hot or warm air is applied to the sprayed resin material to semi-cure the resin material (step S3). As a result, as shown in FIG. 4D, an additional protective resin film 60 is formed that connects to the protective resin film 5 and covers the side surface of the surface structure portion 3, the end of the top surface 2a of the semiconductor portion 2, and the side surface 2c of the semiconductor portion 2. The resin material may be completely cured by this step. When a varnish-like resin material is sprayed, the resin material may be semi-cured or completely cured by applying room temperature air or by natural drying without applying air.

[0061] 4E, the upper surface of the protective resin film 5 on the semiconductor device piece 10 is adsorbed by a collet 310, and the semiconductor device piece 10 is pushed up from the lower surface of the dicing sheet 100 by a push-up pin 320 while the dicing sheet 100 is stretched. This causes the semiconductor device piece 10 to be peeled off from the dicing sheet 100 (step S4). At this time, the additional protective resin film 60 is cut along the cutting line CL.

[0062] Thereafter, although not shown, semiconductor device piece 10 is mounted on die pad 8 via a bonding material (cream solder or the like) (step S5).

[0063] Thereafter, the bonding material and the additional protective resin film 60 are annealed (step S6). This step is performed to harden the bonding material, but it is also possible to harden the additional protective resin film 60 at the same time. The additional protective resin film 60 hardens to become the additional protective resin film 6.

[0064] Thereafter, the sealing portion 7 in which the semiconductor portion 2, the surface structure portion 3, the protective resin film 5 and the additional protective resin film 6 are embedded is formed (step S7).

[0065] The above steps allow the semiconductor device 1 according to the embodiment to be manufactured. According to the manufacturing method of the semiconductor device 1 according to the embodiment, even if the end of the surface structure 3 is not covered by the protective resin film 5 due to misalignment of the exposure in the photolithography process, for example, the additional protective resin film 6 can be formed to manufacture the semiconductor device 1 in which the peripheral portion of the surface structure 3 is covered without any gaps.

[0066] The additional protective resin film 6 is formed by spraying the resin material onto the end of the surface structure portion 3 using an inkjet or an aerosol spray. This makes it possible to easily form the additional protective resin film 6 locally on the end of the surface structure portion 3.

[0067] Furthermore, the additional protective resin film 60 is semi-cured before the semiconductor device pieces 10 are peeled off from the dicing sheet 100. This allows the additional protective resin film 60 to be cut along an appropriate cutting line CL when the dicing sheet 100 is peeled off.

[0068] (Modification) Next, a semiconductor device 1A according to a modification of the embodiment will be described with reference to Fig. 5. Fig. 5 is a cross-sectional view showing details of a peripheral portion of the semiconductor device 1A according to the modification. Note that, like Fig. 2, the sealing portion 7 is omitted in Fig. 5.

[0069] One of the differences between this modified example and the above-described embodiment is the presence of a protective film 33. Hereinafter, this modified example will be described, focusing on the differences from the above-described embodiment.

[0070] 5, the surface structure portion 3 of the semiconductor device 1A according to this modification further includes a protective film 33 made of an oxide or a nitride. The protective film 33 is provided between the gate wiring layer 31 and the protective resin film 5, and between the gate wiring layer 31 and the additional protective resin film 6. That is, the protective film 33 covers the upper surface and side surfaces of the gate wiring layer 31. If the protective film 33 is an oxide, it is, for example, silicon oxide, and if it is a nitride, it is, for example, silicon nitride.

[0071] In this modification, the additional protective resin film 6 covers the side surface of the protective film 33 that is not covered by the protective resin film 5. Since the gate wiring layer 31 of the surface structure portion 3 is covered by the protective film 33 in this manner, foreign matter that has entered from the boundary between the sealing portion 7 and the die pad 8 is prevented from reaching the side surface of the gate wiring layer 31. However, for example, a thermal cycle during operation of the semiconductor device 1A may cause a crack in the protective film 33. In this case, there is a risk that foreign matter that has entered from the boundary between the sealing portion 7 and the die pad 8 may penetrate the crack and reach the side surface of the gate wiring layer 31.

[0072] In this modification, since the additional protective resin film 6 that covers the protective film 33 is provided, even if a crack occurs in the protective film 33, it is possible to prevent foreign matter that has entered from the boundary between the sealing portion 7 and the die pad 8 from reaching the side surface of the gate wiring layer 31. As a result, it is possible to further improve the reliability of the semiconductor device 1.

[0073] Although the embodiment of the present invention has been described, the embodiment and examples are presented as examples and are not intended to limit the scope of the invention. The embodiment and examples can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the gist of the invention. These embodiments and examples and their modifications are included in the scope of the invention and its equivalents described in the claims, as well as in the scope and gist of the invention.

[0074] (Appendix 1) a semiconductor portion having a first main surface and a second main surface opposite the first main surface; a surface structure provided on the first main surface and including a first electrode; a second electrode provided on the second main surface; a first protective resin film covering an upper surface of the surface structure; a second protective resin film connected to the first protective resin film and covering a side surface of the surface structure; A semiconductor device comprising: (Appendix 2) 2. The semiconductor device according to claim 1, wherein the second protective resin film covers a side surface of the first electrode. (Appendix 3) The semiconductor device described in Appendix 1 or 2, wherein the surface structure further includes a protective film made of an oxide or a nitride, the protective film being provided between the first electrode and the first protective resin film, and between the first electrode and the second protective resin film. (Appendix 4) 4. The semiconductor device according to claim 1, wherein the second protective resin film further covers a side surface of the semiconductor portion. (Appendix 5) 5. The semiconductor device according to claim 4, wherein the second protective resin film covers the bottom of the side surface of the semiconductor portion. (Appendix 6) 6. The semiconductor device according to claim 1, wherein the surface structure further includes an interlayer insulating film provided between the semiconductor portion and the first electrode. (Appendix 7) 7. The semiconductor device according to any one of claims 1 to 6, wherein the first protective resin film contains a polyimide resin, a polyamide resin, a polyolefin resin, a polybenzoxazole resin or a silicone resin. (Appendix 8) 8. The semiconductor device according to claim 1, wherein the second protective resin film contains a polyimide resin, a polyamide resin, a polyolefin resin, a polybenzoxazole resin or a silicone resin. (Appendix 9) 9. The semiconductor device according to any one of claims 1 to 8, wherein a material of the second protective resin film is the same as a material of the first protective resin film. (Appendix 10) 9. The semiconductor device according to any one of claims 1 to 8, wherein a material of the second protective resin film is different from a material of the first protective resin film. (Appendix 11) 11. The semiconductor device according to any one of claims 1 to 10, wherein the surface structure portion is not provided on an end portion of the first main surface of the semiconductor portion, and the second protective resin film covers the end portion. (Appendix 12) a die pad including a first die pad main surface and a second die pad main surface opposite to the first die pad main surface, the second electrode being bonded to the first die pad main surface via a bonding material; The semiconductor device according to any one of claims 1 to 11, further comprising a sealing portion that embeds the semiconductor portion, the surface structure portion, the first protective resin film, and the second protective resin film and exposes the second die pad main surface of the die pad. (Appendix 13) 13. The semiconductor device according to any one of claims 1 to 12, wherein the semiconductor device is a MOSFET or an IGBT. (Appendix 14) 14. The semiconductor device according to claim 13, wherein the first electrode is a gate wiring layer. (Appendix 15) preparing a semiconductor device piece fixed to a dicing sheet, the semiconductor device piece comprising: a semiconductor portion having a first main surface and a second main surface; a surface structure portion provided on the first main surface and including a first electrode; a second electrode provided on the second main surface; and a first protective resin film covering an upper surface of the surface structure portion; forming a second protective resin film connected to the first protective resin film and covering a side surface of the surface structure; Peeling the semiconductor device pieces from the dicing sheet; mounting the semiconductor device piece on a die pad via a bonding material; annealing the bonding material and the second protective resin film; forming a sealing portion in which the semiconductor portion, the surface structure portion, the first protective resin film, and the second protective resin film are embedded; A method for manufacturing a semiconductor device. (Appendix 16) 16. The method for manufacturing a semiconductor device according to claim 15, wherein the second protective resin film is formed by spraying a resin material onto the side surface of the surface structure using an inkjet or an aerosol spray. (Appendix 17) 17. The method for manufacturing a semiconductor device according to claim 15, further comprising semi-curing the second protective resin film before peeling the semiconductor device pieces from the dicing sheet. [Explanation of symbols]

[0075] 1 Semiconductor device 10 Semiconductor device piece 2. Semiconductor Department 20 Semiconductor Wafers 2a Top side 2b Bottom side 2c side 21 Drift Region 22 Base Area 23 Source Region 24 Gate insulating film 25,28 Field plate insulating film 26 Gate electrode 27,29 Field plate 3 Surface structure 31 Gate wiring layer 32 Interlayer insulating film 33 Protective film 4 Drain electrode 41 Contact plug 5 Protective resin film 6,60 Additional protective resin film 7 Sealing part 8 Die pad 8a Die pad top surface 8b Bottom surface of die pad 9 Bonding material 100 Dicing Sheet 200 sprays 310 Collet 320 Push-up pin B boundary

Claims

1. a semiconductor portion having a first major surface and a second major surface opposite the first major surface; a surface structure provided on the first main surface and including a first electrode; a second electrode provided on the second main surface; a first protective resin film covering an upper surface of the surface structure; a second protective resin film connected to the first protective resin film and covering a side surface of the surface structure; A semiconductor device comprising:

2. The semiconductor device according to claim 1 , wherein the second protective resin film covers a side surface of the first electrode.

3. 2. The semiconductor device according to claim 1, wherein the surface structure further includes a protective film made of an oxide or a nitride, the protective film being provided between the first electrode and the first protective resin film and between the first electrode and the second protective resin film.

4. The semiconductor device according to claim 1 , wherein the second protective resin film further covers a side surface of the semiconductor portion.

5. The semiconductor device according to claim 4 , wherein the second protective resin film covers the side surface of the semiconductor portion up to a bottom portion of the side surface.

6. The semiconductor device according to claim 1 , wherein the second protective resin film includes a polyimide resin, a polyamide resin, a polyolefin resin, a polybenzoxazole resin or a silicone resin.

7. 2 . The semiconductor device according to claim 1 , wherein the surface structure is not provided at an end portion of the first main surface of the semiconductor portion, and the second protective resin film covers the end portion.

8. a die pad including a first die pad main surface and a second die pad main surface opposite to the first die pad main surface, the second electrode being bonded to the first die pad main surface via a bonding material; The semiconductor device according to any one of claims 1 to 7, further comprising a sealing portion that embeds the semiconductor portion, the surface structure portion, the first protective resin film and the second protective resin film and exposes the second die pad main surface of the die pad.

9. a semiconductor device piece is provided, the semiconductor device piece including a semiconductor portion having a first main surface and a second main surface, a surface structure portion provided on the first main surface and including a first electrode, a second electrode provided on the second main surface, and a first protective resin film covering an upper surface of the surface structure portion, the semiconductor device piece being fixed to a dicing sheet; forming a second protective resin film connected to the first protective resin film and covering a side surface of the surface structure portion; Peeling the semiconductor device pieces from the dicing sheet; mounting the semiconductor device piece on a die pad via a bonding material; annealing the bonding material and the second protective resin film; forming a sealing portion in which the semiconductor portion, the surface structure portion, the first protective resin film, and the second protective resin film are embedded; A method for manufacturing a semiconductor device.

10. 10. The method for manufacturing a semiconductor device according to claim 9, wherein the second protective resin film is formed by spraying a resin material onto the side surface of the surface structure portion using an inkjet or an aerosol spray.

11. 11. The method for manufacturing a semiconductor device according to claim 9, further comprising semi-curing the second protective resin film before peeling the semiconductor device pieces from the dicing sheet.

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