Semiconductor device

Abstract

To provide a semiconductor device that prevents an increase of on-resistance.SOLUTION: A semiconductor device comprises: a first electrode; a second electrode; and a silicon carbide layer including a first silicon carbide region of a first conductivity type, a second silicon carbide region of a second conductivity type provided between the first silicon carbide region and a first surface, facing a gate electrode, and electrically connected to the first electrode, a third silicon carbide region, a fourth silicon carbide region, a fifth silicon carbide region of the first conductivity type provided between the second silicon carbide region and the first surface, and electrically connected to the first electrode, and a sixth silicon carbide region of the first conductivity type provided between the first silicon carbide region and the first electrode, provided between the second silicon carbide region and the fourth silicon carbide region, in contact with the first electrode, shallower than the depth of the second silicon carbide region, and having a first conductivity type impurity concentration higher than the first silicon carbide region.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] Silicon carbide is a material used in semiconductor devices. Compared to silicon, silicon carbide has excellent physical properties, such as a band gap approximately three times larger, a breakdown electric field strength approximately ten times larger, and a thermal conductivity approximately three times larger. By utilizing these characteristics, it is possible to realize, for example, a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) that has high breakdown voltage, low loss, and can operate at high temperatures.

[0003] A vertical MOSFET using silicon carbide has a pn junction diode as a built-in diode. For example, a MOSFET is used as a switching element connected to an inductive load. In this case, the use of a pn junction diode allows a return current to flow even when the MOSFET is off.

[0004] However, when a return current is passed through a bipolar pn junction diode, stacking faults grow in the silicon carbide layer due to the recombination energy of carriers, which causes a problem of an increase in the on-resistance of the MOSFET. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2020-47683 A Summary of the Invention [Problem to be solved by the invention]

[0006] An object of the present invention is to provide a semiconductor device that suppresses an increase in on-resistance. [Means for solving the problem]

[0007] The semiconductor device of the embodiment includes a first electrode, a second electrode, a gate electrode, and a silicon carbide layer provided between the first electrode and the second electrode, having a first surface on the side of the first electrode and a second surface on the side of the second electrode, the first surface being in contact with the first surface and facing the gate electrode, a second silicon carbide region of a first conductivity type provided between the first silicon carbide region and the first surface, facing the gate electrode and electrically connected to the first electrode, a third silicon carbide region of a second conductivity type provided between the first silicon carbide region and the first surface, facing the gate electrode and having the first region between the second silicon carbide region and the first surface, a third silicon carbide region of a second conductivity type electrically connected to the first electrode, and a third silicon carbide region of a second conductivity type provided between the first silicon carbide region and the first surface, facing the gate electrode and having the first region between the second silicon carbide region and the first surface. the second silicon carbide region being provided between the gate electrode and the second silicon carbide region and the first surface; a fourth silicon carbide region of a second conductivity type electrically connected to the first electrode; a fifth silicon carbide region of a first conductivity type provided between the second silicon carbide region and the first surface and electrically connected to the first electrode; and a sixth silicon carbide region of a first conductivity type provided between the first silicon carbide region and the first electrode, provided between the second silicon carbide region and the fourth silicon carbide region, in contact with the first electrode, having a depth shallower than depths of the second silicon carbide region and the fourth silicon carbide region and having a first conductivity type impurity concentration higher than a first conductivity type impurity concentration of the first silicon carbide region; and a gate insulating layer provided between the gate electrode and the second silicon carbide region and between the gate electrode and the third silicon carbide region. [Brief description of the drawings]

[0008] [Figure 1] 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. [Diagram 2] 1 is a schematic top view of a semiconductor device according to a first embodiment. [Diagram 3] 1 is a schematic top view of a semiconductor device according to a first embodiment. [Figure 4]FIG. 2 is an enlarged schematic cross-sectional view of a portion of the semiconductor device according to the first embodiment. [Diagram 5] 1 is an equivalent circuit diagram of the semiconductor device according to the first embodiment. [Figure 6] FIG. 4 is an equivalent circuit diagram of a semiconductor device of a comparative example. [Figure 7] FIG. 5 is a schematic cross-sectional view of a semiconductor device according to a second embodiment. [Figure 8] FIG. 5 is a schematic cross-sectional view of a semiconductor device according to a second embodiment. [Figure 9] FIG. 5 is a schematic top view of a semiconductor device according to a second embodiment. [Figure 10] FIG. 5 is a schematic top view of a semiconductor device according to a second embodiment. [Figure 11] FIG. 11 is an equivalent circuit diagram of a semiconductor device according to a second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the following description, the same reference numerals will be used to designate the same or similar components, and the description of components that have already been described may be omitted as appropriate.

[0010] In the following description, n + , n, n - And, p + , p, p - When n is used, it indicates the relative impurity concentration of each conductivity type. + has a relatively higher n-type impurity concentration than n, - indicates that the n-type impurity concentration is relatively lower than that of n. + has a relatively higher p-type impurity concentration than p, - indicates that the p-type impurity concentration is relatively lower than that of p. + shape, n - Simply put, n-type and p-type + shape, p - The shape is sometimes simply described as p-shape.

[0011] The impurity concentration can be measured by, for example, Secondary Ion Mass Spectrometry (SIMS). The relative level of the impurity concentration can also be determined from the level of the carrier concentration obtained by, for example, Scanning Capacitance Microscopy (SCM). The distances such as the width and depth of the impurity region can be obtained by, for example, SIMS. The distances such as the width and depth of the impurity region can also be obtained from, for example, an image of an SCM or an image of a Scanning Electron Microscope (SEM). The thickness of the insulating layer can also be measured on, for example, an image of a SIMS, SEM, or Transmission Electron Microscope (TEM).

[0012] In this specification, the "p-type impurity concentration" of a p-type silicon carbide region means a net p-type impurity concentration obtained by subtracting the n-type impurity concentration of the region from the p-type impurity concentration of the region. Also, the "n-type impurity concentration" of an n-type silicon carbide region means a net n-type impurity concentration obtained by subtracting the p-type impurity concentration of the region from the n-type impurity concentration of the region.

[0013] Furthermore, unless otherwise specified in the specification, the impurity concentration in a particular region means the maximum impurity concentration in that region.

[0014] (First embodiment) A semiconductor device according to a first embodiment includes a first electrode, a second electrode, a gate electrode, and a silicon carbide layer provided between the first electrode and the second electrode, having a first surface on the first electrode side and a second surface on the second electrode side, the first surface being in contact with the first surface and facing the gate electrode, a second silicon carbide region of a first conductivity type provided between the first silicon carbide region and the first surface, facing the gate electrode and electrically connected to the first electrode, a third silicon carbide region of a second conductivity type electrically connected to the first electrode, and a third silicon carbide region of a second conductivity type provided between the first silicon carbide region and the first surface, facing the gate electrode and having a first region between the second silicon carbide region and the first surface, the gate electrode and the second silicon carbide region and the third silicon carbide region, the gate electrode and the third silicon carbide region including: a fourth silicon carbide region of a second conductivity type electrically connected to the first electrode, a fifth silicon carbide region of a first conductivity type provided between the second silicon carbide region and the first surface and electrically connected to the first electrode, a sixth silicon carbide region of a first conductivity type provided between the first silicon carbide region and the first electrode, between the second silicon carbide region and the fourth silicon carbide region, in contact with the first electrode, the sixth silicon carbide region having a depth shallower than those of the second silicon carbide region and the fourth silicon carbide region and having a first conductivity type impurity concentration higher than a first conductivity type impurity concentration of the first silicon carbide region, and a gate insulating layer provided between the gate electrode and the second silicon carbide region and between the gate electrode and the third silicon carbide region.

[0015] Fig. 1 is a schematic cross-sectional view of the semiconductor device of the first embodiment. Figs. 2 and 3 are schematic top views of the semiconductor device of the first embodiment. Fig. 4 is an enlarged schematic cross-sectional view of a portion of the semiconductor device of the first embodiment.

[0016] Fig. 1 is an AA' cross section of Fig. 2 and Fig. 3. Fig. 2 is a diagram showing a layout pattern of a silicon carbide region and an electrode on a surface of a silicon carbide layer. Fig. 2 shows a state in which a part of a first electrode and an interlayer insulating layer have been removed. Fig. 3 is a diagram showing a layout pattern of a silicon carbide region on a surface of a silicon carbide layer. Fig. 3 shows a state in which a first electrode, an interlayer insulating layer, a gate electrode, and a gate insulating layer have been removed.

[0017] The semiconductor device of the first embodiment is a planar gate vertical MOSFET 100 using silicon carbide. The MOSFET 100 of the first embodiment is, for example, a Double Implantation MOSFET (DIMOSFET) in which a body region and a source region are formed by ion implantation. The MOSFET 100 of the first embodiment also includes a built-in Junction Field Effect Transistor (JFET).

[0018] In the following, an example will be described in which the first conductivity type is n-type and the second conductivity type is p-type. The MOSFET 100 is a vertical n-channel MOSFET that uses electrons as carriers.

[0019] The MOSFET 100 includes a silicon carbide layer 10, a source electrode 12 (first electrode), a drain electrode 14 (second electrode), a gate insulating layer 16, a gate electrode 18, and an interlayer insulating layer 20. The MOSFET 100 includes a plurality of MOSFET regions and a plurality of JFET regions. The source electrode 12 has a silicide layer 12a and a metal layer 12b.

[0020] In the silicon carbide layer 10, n + Drain region 22, n - a p-type drift region 24 (first silicon carbide region), a p-type body region 26, + A source region 28 (fifth silicon carbide region), p + a body contact region 30 (seventh silicon carbide region) of the n-type; + The silicon carbide region includes a high concentration region 32 (sixth silicon carbide region) having a shape similar to that of the first embodiment.

[0021] n - The drift region 24 includes an under-gate region 24x (first region) and a JFET channel region 24y.

[0022] The p-type body region 26 includes a p-type first body region 26a (second silicon carbide region), a p-type second body region 26b (third silicon carbide region), and a p-type third body region 26c (fourth silicon carbide region).

[0023] The silicon carbide layer 10 is provided between the source electrode 12 and the drain electrode 14. The silicon carbide layer 10 is made of single crystal SiC. The silicon carbide layer 10 is made of, for example, 4H—SiC.

[0024] The silicon carbide layer 10 has a first surface ("F1" in FIG. 1) and a second surface ("F2" in FIG. 1). Hereinafter, the first surface F1 may be referred to as the front surface, and the second surface F2 may be referred to as the back surface. The first surface F1 is located on the source electrode 12 side of the silicon carbide layer 10. The second surface F2 is located on the drain electrode 14 side of the silicon carbide layer 10. The first surface F1 and the second surface F2 face each other. Hereinafter, "depth" refers to the depth in the direction toward the second surface F2, based on the first surface F1.

[0025] The first surface is parallel to a first direction and a second direction, the second direction being perpendicular to the first direction.

[0026] The first face F1 is, for example, a face inclined from 0 to 8 degrees with respect to the (0001) face. The second face F2 is, for example, a face inclined from 0 to 8 degrees with respect to the (000-1) face. The (0001) face is called a silicon face. The (000-1) face is called a carbon face.

[0027] 1, the MOSFET 100 includes a number of MOSFET regions and a number of JFET regions. In the MOSFET regions, MOSFETs are formed. In the JFET regions, JFETs are formed.

[0028] The MOSFET regions extend in a first direction and are repeated in a second direction.

[0029] The JFET regions extend in a first direction. The JFET regions are repeatedly arranged in a second direction. Two MOSFET regions are provided between adjacent JFET regions in the second direction. In the MOSFET 100, the ratio of the number of MOSFET regions to the number of JFET regions is 2:1.

[0030] The ratio of the MOSFET area to the JFET area is not limited to 2:1, but may be, for example, 1:1, 3:1, or any other ratio.

[0031] n + The drain region 22 is provided on the back surface side of the silicon carbide layer 10. The drain region 22 contains, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration of the drain region 22 is, for example, 1×10 18 cm -3 More than 1×10 21 cm -3 The following is the result.

[0032] n - The n-shaped drift region 24 is provided between the drain region 22 and the first face F1. - A n-shaped drift region 24 is provided between the source electrode 12 and the drain electrode 14. - A drift region 24 of a shape is provided between the gate electrode 18 and the drain electrode 14 .

[0033] n - The n-type drift region 24 is provided on the drain region 22. The drift region 24 contains, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration of the drift region 24 is lower than the n-type impurity concentration of the drain region 22. The n-type impurity concentration of the drift region 24 is, for example, 4×10 14 cm -3 More than 1×10 17 cm -3 The thickness of the drift region 24 is, for example, not less than 5 μm and not more than 150 μm.

[0034] n - The drift region 24 has an under-gate region 24x and a JFET channel region 24y.

[0035] The gate under region 24x faces the gate electrode 18. The gate under region 24x contacts the first face F1. The gate under region 24x is provided between two adjacent body regions. For example, the gate under region 24x is provided between the first body region 26a and the second body region 26b. The gate under region 24x extends in a first direction.

[0036] The gate-under-region 24x functions as a current path for the MOSFET 100.

[0037] The JFET channel region 24y is provided between two adjacent body regions, for example, between the first body region 26a and the third body region 26c.

[0038] The JFET channel region 24y extends in a first direction. The JFET channel region 24y is in contact with the high concentration region 32.

[0039] The JFET channel region 24y functions as a current path of the JFET. The JFET channel region 24y functions as a channel region of the JFET.

[0040] The p-type body region 26 is provided between the drift region 24 and the first face F1. The body region 26 extends in a first direction. The body region 26 functions as a channel region of the MOSFET 100.

[0041] The body region 26 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration of the body region 26 is, for example, 5×10 17 cm -3 5×10 or more 19 cm -3 The following is the result.

[0042] The depth of the body region 26 is, for example, not less than 1.0 μm and not more than 3.0 μm.

[0043] The body region 26 is electrically connected to the source electrode 12. The body region 26 is fixed to the potential of the source electrode 12.

[0044] A part of the body region 26 contacts the first face F1. A part of the body region 26 faces the gate electrode 18. A part of the body region 26 becomes a channel region of the MOSFET 100. The gate insulating layer 16 is sandwiched between the part of the body region 26 and the gate electrode 18.

[0045] The first body region 26a and the second body region 26b are adjacent to each other in the second direction. The first body region 26a and the second body region 26b are, for example, spaced apart from each other in the second direction.

[0046] The first body region 26a and the third body region 26c are adjacent to each other in the second direction. The first body region 26a and the third body region 26c are, for example, spaced apart from each other in the second direction.

[0047] The first body region 26a is provided between the second body region 26b and the third body region 26c.

[0048] A gate region 24x is provided between the first body region 26a and the second body region 26b. A JFET channel region 24y is provided between the second body region 26b and the third body region 26c. The first body region 26a is sandwiched between the gate region 24x and the JFET channel region 24y.

[0049] n + A source region 28 having a shape similar to that of the first face F1 is provided between the body region 26 and the first face F1. For example, the source region 28 is provided between the first body region 26a and the first face F1. The source region 28 extends in a first direction.

[0050] The source region 28 contains, for example, phosphorus (P) or nitrogen (N) as an n-type impurity. The n-type impurity concentration of the source region 28 is higher than the n-type impurity concentration of the drift region 24. The n-type impurity concentration of the source region 28 is, for example, 1×10 19 cm-3 More than 1×10 21 cm -3 The following is the result.

[0051] The depth of the source region 28 is shallower than the depth of the body region 26. The depth of the source region 28 is, for example, not less than 0.05 μm and not more than 0.2 μm.

[0052] The source region 28 is in contact with the source electrode 12. The source region 28 is in contact with the silicide layer 12a. The source region 28 is electrically connected to the source electrode 12. The contact between the source region 28 and the source electrode 12 is, for example, an ohmic contact. The source region 28 is fixed to the potential of the source electrode 12.

[0053] p + A body contact region 30 having a shape similar to that of the first face F1 is provided between the body region 26 and the first face F1. The body contact region 30 is provided between the body region 26 and the source electrode 12. The body contact region 30 extends in a first direction.

[0054] The body contact region 30 contains, for example, aluminum (Al) as a p-type impurity. The impurity concentration of the p-type impurity in the body contact region 30 is higher than the p-type impurity concentration in the body region 26. The p-type impurity concentration in the body contact region 30 is, for example, 1×10 19 cm -3 More than 1×10 21 cm -3 The following is the result.

[0055] The depth of the body contact region 30 is, for example, not less than 0.3 μm and not more than 0.6 μm.

[0056] The body contact region 30 is in contact with the source electrode 12. The body contact region 30 is in contact with the silicide layer 12a. The body contact region 30 is electrically connected to the source electrode 12. The contact between the body contact region 30 and the source electrode 12 is, for example, an ohmic contact. The body contact region 30 is fixed to the potential of the source electrode 12.

[0057] n + A high concentration region 32 having a shape similar to that of the drift region 24 is provided between the drift region 24 and the source electrode 12. The high concentration region 32 is provided between the JFET channel region 24y and the source electrode 12. The high concentration region 32 contacts the JFET channel region 24y.

[0058] The high concentration region 32 contacts the source electrode 12. The high concentration region 32 contacts the silicide layer 12a. The contact between the high concentration region 32 and the source electrode 12 is, for example, an ohmic contact. The high concentration region 32 is fixed to the potential of the source electrode 12.

[0059] The high concentration region 32 contains, for example, phosphorus (P) or nitrogen (N) as an n-type impurity. The n-type impurity concentration of the high concentration region 32 is higher than the n-type impurity concentration of the drift region 24. The n-type impurity concentration of the high concentration region 32 is, for example, 1×10 18 cm -3 More than 1×10 20 cm -3 The following is the result.

[0060] The high concentration region 32 is provided between two adjacent body regions. For example, the high concentration region 32 is provided between the first body region 26a and the third body region 26c. For example, the high concentration region 32 contacts the first body region 26a and the third body region 26c. The high concentration region 32 is provided continuously between the first body region 26a and the third body region 26c.

[0061] The depth (d1 in FIG. 4) of the high concentration region 32 is shallower than the depth (d2 in FIG. 4) of the first body region 26a and the third body region 26c. The depth d1 of the high concentration region 32 is equal to or less than one-third of the depth of the first body region 26a and the third body region 26c.

[0062] The depth d1 of the high concentration region 32 is, for example, shallower than the depth of the body contact region 30 (d5 in FIG. 4).

[0063] The depth d1 of the high concentration region 32 is, for example, 0.5 μm or less.

[0064] The thickness (t in FIG. 4) of the high concentration region 32 in the direction from the first face F1 to the second face F2 is, for example, 0.2 μm or less.

[0065] The depth d2 of the first body region 26a and the third body region 26c is, for example, three times or more the distance between the first body region 26a and the third body region 26c (d3 in FIG. 4).

[0066] The distance d3 between the first body region 26a and the third body region 26c is, for example, smaller than the distance (d4 in FIG. 4) between the first body region 26a and the second body region 26b. The distance d3 between the first body region 26a and the third body region 26c is, for example, half or less of the distance d4 between the first body region 26a and the second body region 26b.

[0067] The distance d3 between the first body region 26a and the third body region 26c is, for example, not less than 0.05 μm and not more than 0.3 μm.

[0068] The gate electrode 18 is provided on the first face F1 side of the silicon carbide layer 10. The gate electrode 18 extends in a first direction. A plurality of the gate electrodes 18 are arranged parallel to one another in a second direction.

[0069] The gate electrode 18 is a conductive layer, for example, polycrystalline silicon containing p-type impurities or n-type impurities.

[0070] The gate electrode 18 faces the body region 26. The gate electrode 18 faces the gate lower region 24x.

[0071] The gate insulating layer 16 is provided between the gate electrode 18 and the body region 26. For example, the gate insulating layer 16 is provided between the gate electrode 18 and the first body region 26a, between the gate electrode 18 and the second body region 26b, and between the gate electrode 18 and the third body region 26c. The gate insulating layer 16 is provided between the gate electrode 18 and the gate under region 24x. The gate insulating layer 16 is provided between the gate electrode 18 and the source region 28.

[0072] The gate insulating layer 16 is, for example, silicon oxide. For example, a high-k insulating material (high dielectric constant insulating material) can be used for the gate insulating layer 16.

[0073] The interlayer insulating layer 20 is provided on the gate electrode 18 and the silicon carbide layer 10. The interlayer insulating layer 20 is, for example, silicon oxide.

[0074] The source electrode 12 is in contact with the silicon carbide layer 10. The source electrode 12 is in contact with the source region 28. The source electrode 12 is in contact with the body contact region 30. The source electrode 12 is in contact with the high concentration region 32.

[0075] The source electrode 12 includes, for example, a silicide layer 12a and a metal layer 12b. The silicide layer 12a is provided between the silicon carbide layer 10 and the metal layer 12b. The silicide layer 12a extends in a first direction.

[0076] The silicide layer 12a is in contact with the source region 28. The silicide layer 12a is in contact with the body contact region 30. The silicide layer 12a is in contact with the high concentration region 32.

[0077] The silicide layer 12a of the source electrode 12 includes a silicide, for example, nickel silicide or titanium silicide.

[0078] The contact between the source electrode 12 and the source region 28 becomes an ohmic contact by providing the silicide layer 12a. The contact between the source electrode 12 and the body contact region 30 becomes an ohmic contact by providing the silicide layer 12a. The contact between the source electrode 12 and the high concentration region 32 becomes an ohmic contact by providing the silicide layer 12a.

[0079] The source electrode 12 functions as the drain electrode of the JFET.

[0080] The metal layer 12b of the source electrode 12 includes a metal. The metal layer 12b has a laminated structure of, for example, titanium (Ti) and aluminum (Al).

[0081] The drain electrode 14 is provided on the back surface of the silicon carbide layer 10. The drain electrode 14 is in contact with the drain region 22.

[0082] The drain electrode 14 is, for example, a metal or a metal-semiconductor compound, and includes at least one material selected from the group consisting of nickel silicide, titanium (Ti), nickel (Ni), silver (Ag), and gold (Au).

[0083] The drain electrode 14 functions as the source electrode of the JFET.

[0084] When the MOSFET 100 is in an on-state, a current flows from the drain electrode 14 through the drain region 22, the gate region 24x, a channel formed in the body region 26, and the source region 28 to the source electrode 12.

[0085] When the JFET is in the on state, current flows from the source electrode 12 through the high concentration region 32, the channel formed in the JFET channel region 24y, and the drain region 22 to the drain electrode 14.

[0086] Next, the operation and effects of the MOSFET 100 of the first embodiment will be described.

[0087] 5 is an equivalent circuit diagram of the semiconductor device of the first embodiment. In the MOSFET 100, a pn junction diode is connected in parallel to the MOSFET as a built-in diode between the source electrode 12 and the drain electrode 14. In the MOSFET 100, a JFET is connected in parallel to the MOSFET between the source electrode 12 and the drain electrode 14.

[0088] In the JFET, the drain electrode 14 functions as a source electrode, and the source electrode 12 functions as a drain electrode. In the JFET, the two body regions 26 sandwiching the JFET channel region 24y function as gate electrodes. When a voltage that is positive with respect to the source electrode 12 is applied to the drain electrode 14, the JFET channel region 24y and the body region 26 are reverse biased, depleting the JFET channel region 24y and turning the JFET off.

[0089] For example, consider a case where the MOSFET 100 is used as a switching element connected to an inductive load. When the MOSFET 100 is off, a voltage that is positive with respect to the drain electrode 14 may be applied to the source electrode 12 due to an induced current caused by the inductive load. In this case, an on-current flows through the JFET. This state is also called a reverse conduction state. The current that flows in the reverse conduction state is called a reflux current.

[0090] If a MOSFET does not have a JFET, in the reverse conducting state, a forward current flows through the pn junction diode. The pn junction diode operates in a bipolar manner. When a return current flows using a pn junction diode operating in a bipolar manner, if there is a basal plane dislocation (BPD) in the silicon carbide layer, it may grow into a stacking fault due to the recombination energy of carriers. When stacking faults grow in the silicon carbide layer, a problem occurs in which the on-resistance of the MOSFET increases. The increase in the on-resistance of the MOSFET leads to a decrease in the reliability of the MOSFET.

[0091] The MOSFET 100 includes a JFET. The voltage at which an on-current starts to flow through the JFET in a reverse conduction state is lower than the forward voltage (Vf) of a pn junction diode. Therefore, the on-current flows through the JFET before the pn junction diode.

[0092] The JFET operates in a unipolar manner. Therefore, even if an on-current flows, stacking faults do not grow in the silicon carbide layer 10 due to carrier recombination energy. This prevents an increase in the on-resistance of the MOSFET 100. As a result, the reliability of the MOSFET 100 is improved.

[0093] 6 is an equivalent circuit diagram of a semiconductor device of the comparative example. In a MOSFET 900 of the comparative example, a pn junction diode is connected in parallel to the MOSFET as a built-in diode between the source electrode 12 and the drain electrode 14. In the MOSFET 900, a Schottky Barrier Diode (SBD) is connected in parallel to the MOSFET as a built-in diode between the source electrode 12 and the drain electrode 14. The MOSFET 900 of the comparative example differs from the MOSFET 100 of the first embodiment in that it includes an SBD instead of a JFET.

[0094] The forward voltage (Vf) at which a forward current starts to flow through the SBD in a reverse conducting state is lower than the forward voltage (Vf) of a pn junction diode. Therefore, a forward current flows through the SBD before the pn junction diode. In addition, the SBD performs unipolar operation. Therefore, the MOSFET 900 of the comparative example has improved reliability, similar to the MOSFET 100 of the first embodiment.

[0095] However, the forward voltage (Vf) at which a forward current begins to flow through the SBD in the reverse conducting state is higher than the voltage at which an on-current begins to flow through the JFET. For example, the contact between the high concentration region 32 and the source electrode 12 is an ohmic contact, so the on-current rises quickly. In the case of an SBD, the contact between the electrode and the n-type semiconductor region is a Schottky contact, so a forward current begins to flow only after a certain forward voltage (Vf) is exceeded.

[0096] The MOSFET 100 includes a JFET instead of an SBD, and thus reduces loss in the reverse conduction state compared to the comparative MOSFET 900. Thus, a low-loss MOSFET 100 can be realized.

[0097] From the viewpoint of making the contact between the high concentration region 32 and the source electrode 12 an ohmic contact, it is preferable that the n-type impurity concentration of the high concentration region 32 is high. The n-type impurity concentration of the high concentration region 32 is preferably 1×10 18 cm -3 It is preferable that the value is 5×10 or more. 18 cm -3 More preferably, it is 1×10 19 cm -3 More preferably, it is equal to or greater than this.

[0098] From the viewpoint of reducing the off-leak current of the JFET, the depth d1 of the high-concentration region 32 is preferably shallower than the depth d2 of the first body region 26a and the third body region 26c. The depth d1 of the high-concentration region 32 is preferably one-third or less, more preferably one-quarter or less, and further preferably one-fifth or less, of the depth of the first body region 26a and the third body region 26c.

[0099] From the viewpoint of reducing the off-leakage current of the JFET, the depth d2 of the first body region 26a and the third body region 26c is preferably three times or more, more preferably four times or more, and even more preferably five times or more, the distance d3 between the first body region 26a and the third body region 26c.

[0100] From the viewpoint of reducing the off-leak current of the JFET, it is preferable that the distance d3 between the first body region 26a and the third body region 26c is small. The distance d3 between the first body region 26a and the third body region 26c is preferably 0.3 μm or less, more preferably 0.2 μm or less, and further preferably 0.1 μm or less.

[0101] From the viewpoint of achieving both an increase in the on-current of the MOSFET 100 and a reduction in the off-leak current of the JFET, it is preferable that the distance d3 between the first body region 26a and the third body region 26c is smaller than the distance d4 between the first body region 26a and the second body region 26b. From the same viewpoint, it is more preferable that the distance d3 between the first body region 26a and the third body region 26c is equal to or smaller than one-half the distance d4 between the first body region 26a and the second body region 26b, and further more preferable that the distance d3 between the first body region 26a and the third body region 26c is equal to or smaller than one-half the distance d4 between the first body region 26a and the second body region 26b.

[0102] As described above, according to the first embodiment, a MOSFET that suppresses an increase in on-resistance is realized, and also, according to the first embodiment, a low-loss MOSFET is realized.

[0103] Second embodiment The semiconductor device of the second embodiment differs from the semiconductor device of the first embodiment in that the first silicon carbide region further has a second region in contact with the first surface, and the first electrode is in contact with the second region. Hereinafter, some of the contents that overlap with the first embodiment may be omitted.

[0104] Figures 7 and 8 are schematic cross-sectional views of the semiconductor device of the second embodiment, and Figures 9 and 10 are schematic top views of the semiconductor device of the second embodiment.

[0105] Fig. 7 is a cross section taken along line AA' in Figs. 9 and 10. Fig. 8 is a cross section taken along line BB' in Figs. 9 and 10.

[0106] Fig. 9 is a diagram showing a layout pattern of a silicon carbide region and an electrode on a silicon carbide layer surface. Fig. 9 shows a state where a part of a first electrode and an interlayer insulating layer have been removed. Fig. 10 is a diagram showing a layout pattern of a silicon carbide region on a silicon carbide layer surface. Fig. 10 shows a state where a first electrode, an interlayer insulating layer, a gate electrode, and a gate insulating layer have been removed.

[0107] The semiconductor device of the second embodiment is a planar gate vertical MOSFET 200 using silicon carbide. The MOSFET 200 of the second embodiment is, for example, a DIMOSFET in which a body region and a source region are formed by ion implantation. The MOSFET 200 of the second embodiment also includes a built-in JFET and SBD.

[0108] In the following, an example will be described in which the first conductivity type is n-type and the second conductivity type is p-type. The MOSFET 200 is a vertical n-channel MOSFET that uses electrons as carriers.

[0109] The MOSFET 200 includes a silicon carbide layer 10, a source electrode 12 (first electrode), a drain electrode 14 (second electrode), a gate insulating layer 16, a gate electrode 18, and an interlayer insulating layer 20. The MOSFET 200 includes a plurality of MOSFET regions, a plurality of JFET regions, and a plurality of SBD regions. The source electrode 12 includes a silicide layer 12a and a metal layer 12b.

[0110] In the silicon carbide layer 10, n + Drain region 22, n - a p-type drift region 24 (first silicon carbide region), a p-type body region 26, + A source region 28 (fifth silicon carbide region), p + a body contact region 30 (seventh silicon carbide region) of the n-type; + The silicon carbide region includes a high concentration region 32 (sixth silicon carbide region) having a shape similar to that of the first embodiment.

[0111] n - The drift region 24 includes a gate under region 24x (first region), a JFET channel region 24y, and a JBS region 24z (second region). JBS is an abbreviation of Junction Barrier Schottky.

[0112] The p-type body region 26 includes a p-type first body region 26a (second silicon carbide region), a p-type second body region 26b (third silicon carbide region), and a p-type third body region 26c (fourth silicon carbide region).

[0113] As shown in Fig. 7, MOSFET 200 includes a plurality of MOSFET regions and a plurality of JFET regions. MOSFETs are formed in the MOSFET regions. JFETs are formed in the JFET regions. In the cross section of Fig. 7, the plurality of MOSFET regions and the plurality of JFET regions are alternately arranged in a second direction.

[0114] As shown in Fig. 8, MOSFET 200 includes a plurality of MOSFET regions and a plurality of SBD regions. A MOSFET is formed in the MOSFET region. An SBD is formed in the SBD region. In the cross section of Fig. 8, the plurality of MOSFET regions and the plurality of SBD regions are alternately arranged in a second direction.

[0115] The plurality of JFET regions and the plurality of SBD regions are alternately arranged in a first direction.

[0116] 8, the JBS region 24z is in contact with the first face F1. The JBS region 24z is provided between two adjacent body regions. For example, the JBS region 24z is provided between the first body region 26a and the third body region 26c.

[0117] 10, the JBS region 24z is provided between two high concentration regions 32 in the first direction. The JBS region 24z is provided between two JFET channel regions 24y in the first direction.

[0118] The JBS region 24z contacts the source electrode 12. The JBS region 24z contacts the metal layer 12b. The contact between the JBS region 24z and the source electrode 12 is a Schottky contact.

[0119] The distance between the two body regions 26 sandwiching the JBS region 24z is, for example, greater than the distance between the two body regions 26 sandwiching the high-concentration region 32. For example, the distance (d6 in FIG. 8) between the first body region 26a and the third body region 26c sandwiching the JBS region 24z is greater than the distance (d3 in FIG. 7) between the first body region 26a and the third body region 26c sandwiching the high-concentration region 32.

[0120] 11 is an equivalent circuit diagram of the semiconductor device of the second embodiment. In the MOSFET 200, a pn junction diode is connected in parallel to the MOSFET as a built-in diode between the source electrode 12 and the drain electrode 14. In the MOSFET 200, a JFET is connected in parallel to the MOSFET between the source electrode 12 and the drain electrode 14. In the MOSFET 200, an SBD is connected in parallel to the MOSFET between the source electrode 12 and the drain electrode 14.

[0121] The MOSFET 200 of the second embodiment includes a JFET and an SBD, and therefore stacking faults do not grow in the silicon carbide layer 10 when a return current flows in a reverse conduction state. This suppresses an increase in the on-resistance of the MOSFET 200. As a result, the reliability of the MOSFET 200 is improved.

[0122] The MOSFET 200 of the second embodiment includes a JFET, which reduces loss in the reverse conduction state, similar to the MOSFET 100 of the first embodiment. Furthermore, the MOSFET 200 includes an SBD, which increases the current flowing in the reverse conduction state.

[0123] From the viewpoint of increasing the current flowing in the reverse conduction state, the distance between the two body regions 26 sandwiching the JBS region 24z is preferably greater than the distance between the two body regions 26 sandwiching the high-concentration region 32. The distance d6 between the first body region 26a and the third body region 26c sandwiching the JBS region 24z is preferably greater than the distance d3 between the first body region 26a and the third body region 26c sandwiching the high-concentration region 32.

[0124] As described above, according to the second embodiment, a MOSFET that suppresses an increase in on-resistance is realized. Also, according to the second embodiment, a low-loss MOSFET is realized. Also, according to the second embodiment, a MOSFET in which a current flowing in a reverse conducting state increases is realized.

[0125] In the first and second embodiments, the MOSFET has been described as having a layout pattern in which the gate electrode extends linearly, but the layout pattern of the MOSFET is not particularly limited. For example, the layout pattern of the MOSFET may be a layout pattern having a ring-shaped gate electrode or a polygonal gate electrode.

[0126] In the first and second embodiments, the crystal structure of SiC is 4H-SiC, but the present invention can be applied to devices using SiC with other crystal structures such as 6H-SiC, 3C-SiC, etc. Also, a plane other than the (0001) plane can be applied to the surface of the silicon carbide layer 10.

[0127] In the first and second embodiments, the first conductivity type is n-type and the second conductivity type is p-type as an example, but it is also possible for the first conductivity type to be p-type and the second conductivity type to be n-type.

[0128] In the first and second embodiments, aluminum (Al) is exemplified as the p-type impurity, but boron (B) can also be used. In addition, nitrogen (N) and phosphorus (P) are exemplified as the n-type impurity, but arsenic (As), antimony (Sb), etc. can also be used.

[0129] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. For example, components of one embodiment may be replaced or changed with components of another embodiment. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0130] 10 Silicon carbide layer 12 source electrode (first electrode) 14 Drain electrode (second electrode) 16 Gate insulating layer 18 Gate electrode 24 Drift region (first silicon carbide region) 24x Under-gate area (first area) 24z JBS area (second area) 26a first body region (second silicon carbide region) 26b second body region (third silicon carbide region) 26c third body region (fourth silicon carbide region) 28 source region (fifth silicon carbide region) 30 Body contact region (seventh silicon carbide region) 32 High concentration region (sixth silicon carbide region) 100 MOSFET (semiconductor device) 200 MOSFET (semiconductor device) F1 First Side F2 Second Face

Claims

1. A first electrode; A second electrode; and A gate electrode; A silicon carbide layer provided between the first electrode and the second electrode, the silicon carbide layer having a first surface on the first electrode side and a second surface on the second electrode side, a first silicon carbide region of a first conductivity type having a first region in contact with the first surface and facing the gate electrode; a second silicon carbide region of a second conductivity type provided between the first silicon carbide region and the first surface, facing the gate electrode, and electrically connected to the first electrode; a third silicon carbide region of a second conductivity type provided between the first silicon carbide region and the first surface, facing the gate electrode, the first region being provided between the third silicon carbide region and the second silicon carbide region, and electrically connected to the first electrode; a fourth silicon carbide region of a second conductivity type provided between the first silicon carbide region and the first surface, the second silicon carbide region being provided between the fourth silicon carbide region and the third silicon carbide region, and electrically connected to the first electrode; a fifth silicon carbide region of the first conductivity type provided between the second silicon carbide region and the first surface and electrically connected to the first electrode; a sixth silicon carbide region of a first conductivity type provided between the first silicon carbide region and the first electrode, between the second silicon carbide region and the fourth silicon carbide region, in contact with the first electrode, having a depth shallower than depths of the second silicon carbide region and the fourth silicon carbide region, and having a first conductivity type impurity concentration higher than a first conductivity type impurity concentration of the first silicon carbide region; A silicon carbide layer comprising: a gate insulating layer provided between the gate electrode and the second silicon carbide region and between the gate electrode and the third silicon carbide region; A semiconductor device comprising:

2. The semiconductor device according to claim 1 , wherein said sixth silicon carbide region contacts said second silicon carbide region and said fourth silicon carbide region.

3. 2 . The semiconductor device according to claim 1 , wherein a depth of said second silicon carbide region and said fourth silicon carbide region is at least three times a distance between said second silicon carbide region and said fourth silicon carbide region.

4. 2. The semiconductor device according to claim 1, wherein said second silicon carbide region and said fourth silicon carbide region have a depth of 1.0 [mu]m or more.

5. 2. The semiconductor device according to claim 1, wherein a distance between said second silicon carbide region and said fourth silicon carbide region is not more than 0.3 [mu]m.

6. 2 . The semiconductor device according to claim 1 , wherein a depth of said sixth silicon carbide region is equal to or less than one-third of a depth of said second silicon carbide region and said fourth silicon carbide region.

7. 2 . The semiconductor device according to claim 1 , wherein said sixth silicon carbide region has a thickness of not more than 0.2 μm in a direction from said first face toward said second face.

8. The sixth silicon carbide region has a first conductivity type impurity concentration of 1×10 １８ cm －３ 2. The semiconductor device according to claim 1.

9. The semiconductor device of claim 1 , wherein the contact between the sixth silicon carbide region and the first electrode is an ohmic contact.

10. 2 . The semiconductor device according to claim 1 , wherein a distance between said second silicon carbide region and said fourth silicon carbide region is smaller than a distance between said second silicon carbide region and said third silicon carbide region.

11. the silicon carbide layer further includes a seventh silicon carbide region provided between the second silicon carbide region and the first surface, the seventh silicon carbide region having a second conductivity type impurity concentration higher than a second conductivity type impurity concentration of the second silicon carbide region; The semiconductor device according to claim 1 , wherein a depth of said sixth silicon carbide region is shallower than a depth of said seventh silicon carbide region.

12. The semiconductor device according to claim 1 , wherein said first silicon carbide region further has a second region in contact with said first surface, and said first electrode is in contact with said second region.

13. The semiconductor device according to claim 12 , wherein said second region is provided between said second silicon carbide region and said fourth silicon carbide region.

14. 14. The semiconductor device according to claim 13, wherein a distance between the second silicon carbide region and the fourth silicon carbide region sandwiching the second region therebetween is greater than a distance between the second silicon carbide region and the fourth silicon carbide region sandwiching the sixth silicon carbide region therebetween.

15. The semiconductor device according to claim 12 , wherein the contact between the second region and the first electrode is a Schottky contact.

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