Semiconductor device and manufacturing method thereof

Abstract

To provide a semiconductor device capable of suppressing warping.SOLUTION: A semiconductor device according to an embodiment includes first to fourth electrodes, first to third semiconductor regions, and first and second insulating portions. The first semiconductor region is provided on the first electrode. The second semiconductor region is provided on the first semiconductor region. The third semiconductor region is selectively provided on the second semiconductor region. The second electrode is provided on the third semiconductor region. The third electrode is aligned with the second semiconductor region. The first insulating portion is provided between the second semiconductor region and the third electrode. The fourth electrode is aligned with the first semiconductor region. The second insulating portion is provided between the first semiconductor region and the fourth electrode. The fourth electrode includes a first side portion, a second side portion, and a void portion. The void portion is located between the first side portion and the second side portion.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device and a method for manufacturing a semiconductor device. [Background technology]

[0002] A semiconductor device having a field plate electrode (hereinafter, referred to as an "FP electrode") is known to improve the breakdown voltage or reduce the on-resistance. There is a demand for suppressing warpage of this semiconductor device. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 6426642 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a semiconductor device capable of suppressing warpage and a method for manufacturing the semiconductor device. [Means for solving the problem]

[0005] The semiconductor device according to the embodiment includes a first electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a second electrode, a third electrode, a first insulating portion, a fourth electrode, and a second insulating portion. The first semiconductor region is provided on the first electrode. The second semiconductor region is provided on the first semiconductor region. The third semiconductor region is selectively provided on the second semiconductor region. The second electrode is provided on the third semiconductor region. The second electrode is electrically connected to the third semiconductor region. The third electrode is aligned with the second semiconductor region in a second direction. The second direction is perpendicular to a first direction from the first semiconductor region to the second semiconductor region. The first insulating portion is provided between the second semiconductor region and the third electrode in the second direction. The fourth electrode is aligned with the first semiconductor region in the second direction. The second insulating portion is provided between the first semiconductor region and the fourth electrode in the second direction. The fourth electrode has a first side portion, a second side portion, and a gap. The gap is located between the first side portion and the second side portion in the second direction.

[0006] A manufacturing method of a semiconductor device according to an embodiment includes the steps of forming a trench in a semiconductor region, forming an insulating portion along a bottom surface and a side surface of the trench, and forming a conductive portion including a void portion inside the insulating portion. [Brief description of the drawings]

[0007] [Figure 1] 1 is a plan view illustrating a semiconductor device according to a first embodiment. [Diagram 2] 1 is an enlarged plan view illustrating a portion of a semiconductor device according to a first embodiment. [Diagram 3] 1 is a cross-sectional view illustrating a portion of a semiconductor device according to a first embodiment. [Figure 4] 1 is a cross-sectional view illustrating a portion of a semiconductor device according to a first embodiment. [Diagram 5] 1 is a cross-sectional view illustrating a portion of a semiconductor device according to a first embodiment. [Figure 6] 1 is a cross-sectional view illustrating a portion of a semiconductor device according to a first embodiment. [Figure 7] FIG. 4 is a cross-sectional view illustrating a part of a semiconductor device according to a modified example of the first embodiment. [Figure 8] FIG. 11 is an enlarged plan view illustrating a portion of a semiconductor device according to a second embodiment. [Figure 9] FIG. 11 is a cross-sectional view illustrating a portion of a semiconductor device according to a second embodiment. [Figure 10] FIG. 11 is a cross-sectional view illustrating a portion of a semiconductor device according to a second embodiment. [Figure 11] FIG. 11 is a cross-sectional view illustrating a portion of a semiconductor device according to a second embodiment. [Figure 12] FIG. 11 is a cross-sectional view illustrating a portion of a semiconductor device according to a second embodiment. [Figure 13] 13(a) to 13(d) are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 14] 14(a) to 14(d) are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Each embodiment will be described below with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as the actual ones. Even when the same part is shown, the dimensions and ratios of each part may be different depending on the drawing. Furthermore, in this specification and each drawing, elements similar to those explained with reference to the previous drawings are given the same reference numerals, and detailed explanations are omitted as appropriate.

[0009] For ease of understanding, the following description will use an XYZ Cartesian coordinate system to explain the arrangement and configuration of each part. The X-axis, Y-axis, and Z-axis are mutually perpendicular. The direction in which the X-axis extends is called the "X-direction," the direction in which the Y-axis extends is called the "Y-direction," and the direction in which the Z-axis extends is called the "Z-direction." For ease of understanding, the direction of the arrow in the Z-direction is called the upward direction, and the opposite direction is called the downward direction, but these directions are unrelated to the direction of gravity. Viewing from above is called "planar view."

[0010] In the following, the notations + and - indicate the relative level of the impurity concentration in each conductivity type. Specifically, a notation with "+" indicates a higher impurity concentration than a notation with neither "+" nor "-". A notation with "-" indicates a lower impurity concentration than a notation with neither "+" nor "-". Here, "impurity concentration" refers to the net impurity concentration after both donor and acceptor impurities are offset in the case where each region contains both donor and acceptor impurities.

[0011] (First embodiment) FIG. 1 is a plan view illustrating a semiconductor device according to a first embodiment. FIG. 2 is an enlarged plan view illustrating a portion of the semiconductor device according to the first embodiment. FIG. 3 is a cross-sectional view illustrating a portion of the semiconductor device according to the first embodiment. FIG. 4 is a cross-sectional view illustrating a portion of the semiconductor device according to the first embodiment. FIG. 5 is a cross-sectional view illustrating a portion of the semiconductor device according to the first embodiment. FIG. 6 is a cross-sectional view illustrating a portion of the semiconductor device according to the first embodiment. FIG. 2 is an enlarged plan view of region II shown in FIG. FIG. 3 is a cross-sectional view taken along line III-III shown in FIG. FIG. 4 is a cross-sectional view taken along line IV-IV shown in FIG. FIG. 5 is a cross-sectional view taken along line VV shown in FIG. FIG. 6 is a cross-sectional view taken along line VI-VI shown in FIG.

[0012] 1 to 6, the semiconductor device 100 according to the first embodiment is a vertical MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). The semiconductor device 100 is a MOSFET in which trench-shaped FP electrodes are provided and a trench-shaped gate electrode is provided between the FP electrodes.

[0013] The semiconductor device 100 includes a drain electrode 11 (first electrode), a source electrode 12 (second electrode), a gate electrode 13 (third electrode), an FP electrode 14 (fourth electrode), a gate wiring layer 15, a source connection portion 16, an FP connection portion 17, a gate connection portion 18, n - A p-type drift region 21 (first semiconductor region), a p-type base region 22 (second semiconductor region), + A source region 23 (third semiconductor region), n + Drain region 24, p + The semiconductor device includes a gate contact region 25, a gate insulating portion 31 (first insulating portion), an FP insulating portion 32 (second insulating portion), and an upper insulating portion 33. In this example, the first conductivity type is n-type, and the second conductivity type is p-type.

[0014] In the following, the direction from the first electrode 11 to the second electrode 12 is referred to as the first direction. The direction perpendicular to the first direction is referred to as the second direction. The direction perpendicular to the first direction and intersecting the second direction is referred to as the third direction. The first direction is, for example, the Z direction. The second direction is, for example, the Y direction. The third direction is, for example, the X direction.

[0015] A drain electrode 11 is provided on the bottom of the semiconductor device 100. On the drain electrode 11, + Through the drain region 24, - A drift region 21 is provided. - The drift region 21 is + The n-type drain region 24 is electrically connected to the drain electrode 11. - A p-type base region 22 is provided on the p-type drift region 21. An n-type+ The source region 23 and p + In this example, an n-type contact region 25 is selectively provided on a portion of the p-type base region 22. + A p-type source region 23 is provided on another part of the p-type base region 22. + A contact area 25 is provided. + The p-type contact region 25 is aligned with the p-type base region 22 in the Y direction.

[0016] The p-type base region 22 and the n + An upper insulating portion 33 is provided on the source region 23. A source electrode 12 and a gate wiring layer 15 are provided on the upper insulating portion 33. The source electrode 12 is connected to a source connection portion 16 and a p + The source electrode 12 is electrically connected to the p-type base region 22 via the source contact region 25. The source electrode 12 is electrically connected to the n-type base region 22 via the source connection portion 16. + 2 shows a plan view of a portion below the upper insulating portion 33. In addition, in FIG. 2, the positions of the source electrode 12 and the gate wiring layer 15 are indicated by two-dot chain lines.

[0017] The gate electrode 13 is aligned with the p-type base region 22 in the Y direction. In this example, a part of the gate electrode 13 is aligned with the n-type base region 22 in the Y direction. + In this example, a portion of the gate electrode 13 is aligned with the p + The gate electrode 13 is aligned with the source contact region 25. In this example, a part of the gate electrode 13 is aligned with a part of the source connection portion 16 in the Y direction.

[0018] The gate insulating portion 31 is provided between the gate electrode 13 and the p-type base region 22 in the Y direction. In this example, a part of the gate insulating portion 31 is disposed between the gate electrode 13 and the n-type base region 22 in the Y direction. - In this example, a part of the gate insulating portion 31 is disposed between the gate electrode 13 and the n-type drift region 21 in the Y direction. +In this example, a part of the gate insulating portion 31 is disposed between the gate electrode 13 and the n-type source region 23 in the Z direction. - The gate insulating portion 31 is provided between the gate electrode 13 and the upper insulating portion 33 in the Z direction. In this example, a part of the gate insulating portion 31 is provided between the gate electrode 13 and the upper insulating portion 33 in the Z direction. In this manner, the gate electrode 13 is surrounded by the gate insulating portion 31. The gate electrode 13 is provided inside the gate insulating portion 31.

[0019] 5, the gate electrode 13 is electrically connected to the gate wiring layer 15 at one end in the X direction via a gate connection portion 18. The gate wiring layer 15 is electrically isolated from the source electrode 12. The gate wiring layer 15 is electrically connected to, for example, a gate pad (not shown).

[0020] The FP electrode 14 has n - In this example, a portion of the FP electrode 14 is aligned with the p-type drift region 21 in the Y direction. In this example, a portion of the FP electrode 14 is aligned with the n-type base region 22 in the Y direction. + In this example, a portion of the FP electrode 14 is aligned with the p + The FP electrode 14 is aligned with the source contact region 25 in the Y direction. In this example, a portion of the FP electrode 14 is aligned with a portion of the source connection portion 16 in the Y direction. In this example, a portion of the FP electrode 14 is aligned with the gate electrode 13 in the Y direction.

[0021] The FP electrode 14 has a first side portion 14a, a second side portion 14b, a third side portion 14c, a fourth side portion 14d, a bottom portion 14e, and a gap portion 40. The second side portion 14b is aligned with the first side portion 14a in the Y direction. The second side portion 14b faces the first side portion 14a in the Y direction. The fourth side portion 14d is aligned with the third side portion 14c in the X direction. The fourth side portion 14d faces the third side portion 14c in the Y direction. One end of the first side portion 14a in the X direction is connected to one end of the third side portion 14c in the Y direction. The other end of the first side portion 14a in the X direction is connected to one end of the fourth side portion 14d in the Y direction. One end of the second side portion 14b in the X direction is connected to the other end of the third side portion 14c in the Y direction. The other end of the second side portion 14b in the X direction is connected to the other end of the fourth side portion 14d in the Y direction. That is, the first side portion 14a, the second side portion 14b, the third side portion 14c, and the fourth side portion 14d surround the four sides. The bottom portion 14e connects the lower end of the first side portion 14a, the lower end of the second side portion 14b, the lower end of the third side portion 14c, and the lower end of the fourth side portion 14d. The first side portion 14a, the second side portion 14b, the third side portion 14c, the fourth side portion 14d, and the bottom portion 14e function as an FP electrode.

[0022] The gap 40 is located between the first side surface portion 14a and the second side surface portion 14b in the Y direction. The gap 40 is located between the third side surface portion 14c and the fourth side surface portion 14d in the X direction. In other words, the gap 40 is located inside the area surrounded by the first side surface portion 14a, the second side surface portion 14b, the third side surface portion 14c, the fourth side surface portion 14d, and the bottom surface portion 14e.

[0023] The gap 40 is aligned with the center of the FP electrode 14 in the Z direction in the X and Y directions, for example. That is, the upper end of the gap 40 is located, for example, above the center of the FP electrode 14 in the Z direction. The lower end of the gap 40 is located, for example, below the center of the FP electrode 14 in the Z direction. The upper end of the gap 40 is aligned with the center of the FP electrode 14 in the Z direction in the X and Y directions, for example. -The void 40 is located above the upper end of the FP drift region 21. In addition, the length from the lower end of the void 40 to the lower end of the FP electrode 14 is shorter than, for example, the length from the lower end of the FP electrode 14 to the lower end of the FP insulating portion 32. The ratio of the Z-direction length of the void 40 to the Z-direction length of the FP electrode 14 is, for example, not less than 1 / 2 and not more than 4 / 5.

[0024] In this example, the FP electrode 14 further has a partitioning portion 14x that partitions the gap 40. The partitioning portion 14x is provided between the first side surface portion 14a and the second side surface portion 14b in the Y direction and at a position separated from the first side surface portion 14a and the second side surface portion 14b. The partitioning portion 14x is provided between the third side surface portion 14c and the fourth side surface portion 14d in the X direction and at a position separated from the third side surface portion 14c and the fourth side surface portion 14d. That is, the partitioning portion 14x is provided inside the area surrounded by the first side surface portion 14a, the second side surface portion 14b, the third side surface portion 14c, the fourth side surface portion 14d, and the bottom surface portion 14e and at a position separated from the first side surface portion 14a, the second side surface portion 14b, the third side surface portion 14c, and the fourth side surface portion 14d.

[0025] The gap 40 is divided by the partition 14x into a first gap region 41, a second gap region 42, a third gap region 43, and a fourth gap region 44. The first gap region 41 is located between the first side surface portion 14a and the partition 14x in the Y direction. The second gap region 42 is located between the second side surface portion 14b and the partition 14x in the Y direction. The third gap region 43 is located between the third side surface portion 14c and the partition 14x in the X direction. The fourth gap region 44 is located between the fourth side surface portion 14d and the partition 14x in the X direction.

[0026] The FP electrode 14 further includes a first insulating region 14p and a second insulating region 14q. The first insulating region 14p is located between the bottom surface portion 14e and the partition portion 14x in the Z direction. In this example, a part of the first insulating region 14p is located between the bottom surface portion 14e and the void portion 40 in the Z direction. That is, in this example, a part of the first insulating region 14p is provided below the void portion 40. In this example, a part of the first insulating region 14p is located between the first side surface portion 14a and the partition portion 14x and between the second side surface portion 14b and the partition portion 14x in the Y direction. In this example, a part of the first insulating region 14p is located between the third side surface portion 14c and the partition portion 14x and between the fourth side surface portion 14d and the partition portion 14x in the X direction.

[0027] The second insulating region 14q is provided between the gap 40 and the upper insulating portion 33 in the Z direction. That is, the second insulating region 14q is provided above the gap 40. The second insulating region 14q is located between the first side surface portion 14a and the partition portion 14x and between the second side surface portion 14b and the partition portion 14x in the Y direction. The second insulating region 14q is located between the third side surface portion 14c and the partition portion 14x and between the fourth side surface portion 14d and the partition portion 14x in the X direction.

[0028] The FP insulating portion 32 is separated from the FP electrode 14 in the X direction and the Y direction by n - In this example, a portion of the FP insulating portion 32 is provided between the FP electrode 14 and the p-type drift region 21 in the Y direction. In this example, a portion of the FP insulating portion 32 is provided between the FP electrode 14 and the n-type base region 22 in the Y direction. + In this example, a part of the FP insulating portion 32 is disposed between the FP electrode 14 and the p-type source region 23 in the Y direction. + In this example, a part of the FP insulating portion 32 is provided between the FP electrode 14 and the source connection portion 16 in the Y direction. In this example, a part of the FP insulating portion 32 is provided between the FP electrode 14 and the n-type contact region 25 in the Z direction. -FP electrode 14 is provided between FP insulating portion 32 and drift region 21. In this manner, FP electrode 14 is surrounded by FP insulating portion 32. FP electrode 14 is provided inside FP insulating portion 32.

[0029] As shown in FIG. 4, the FP electrode 14 is electrically connected to the source electrode 12 via an FP connection portion 17 at the other end in the X direction.

[0030] There are provided a plurality of gate electrodes 13 surrounded by the gate insulating portion 31 and a plurality of FP electrodes 14 surrounded by the FP insulating portion 32. In a plan view, the gate electrodes 13 surrounded by the gate insulating portion 31 and the FP electrodes 14 surrounded by the FP insulating portion 32 are alternately arranged in the Y direction.

[0031] An example of the material of each component of the semiconductor device 100 will be described.

[0032] The drain electrode 11, the source electrode 12, and the gate wiring layer 15 include a metal such as aluminum or copper. The gate electrode 13 and the FP electrode 14 include a conductive material such as polysilicon. Impurities may be added to the conductive material.

[0033] n - p-type drift region 21, p-type base region 22, n + Shape source region 23, n + shaped drain region 24, and + The contact region 25 includes silicon, silicon carbide, gallium nitride, or gallium arsenide as a semiconductor material. When silicon is used as the semiconductor material, arsenic, phosphorus, or antimony can be used as a donor impurity. Boron can be used as an acceptor impurity.

[0034] The gate insulating portion 31 and the FP insulating portion 32 include an insulating material. The gate insulating portion 31 includes, for example, silicon oxide (SiO). The FP insulating portion 32 includes, for example, at least one of silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), and hafnium oxide (HfO).

[0035] The operation of the semiconductor device 100 will now be described. With a positive voltage applied to the drain electrode 11 relative to the source electrode 12, a voltage equal to or greater than the threshold is applied to the gate electrode 13. This forms a channel (inversion layer) in the p-type base region 22, turning the semiconductor device 100 on. Electrons flow from the source electrode 12 to the drain electrode 11 through the channel. When the voltage applied to the gate electrode 13 then becomes lower than the threshold, the channel in the p-type base region 22 disappears, turning the semiconductor device 100 off.

[0036] When the semiconductor device 100 is switched to the off state, the positive voltage applied to the drain electrode 11 with respect to the source electrode 12 increases. - The potential difference between the n-type drift region 21 and the FP electrode 14 increases. - From the interface with the drift region 21, - The depletion layer spreads toward the n-type drift region 21. This spread of the depletion layer can increase the breakdown voltage of the semiconductor device 100. Alternatively, the breakdown voltage of the semiconductor device 100 can be increased while maintaining the breakdown voltage of the n-type drift region 21. - By increasing the concentration of impurities that act as donors in the drift region 21, the on-resistance of the semiconductor device 100 can be reduced.

[0037] If the inside of the FP electrode 14 is filled with a conductive material, the FP insulating portion 32, which has a compressive stress, cannot expand, and warping may occur.

[0038] In contrast, in the semiconductor device 100 according to the embodiment, a void 40 is provided inside the FP electrode 14. As a result, when the FP insulating portion 32 expands, the void 40 can absorb the stress, thereby suppressing warpage. Furthermore, even in a chip state, the effect of suppressing warpage can be maintained.

[0039] FIG. 7 is a cross-sectional view illustrating a part of a semiconductor device according to a modification of the first embodiment. FIG. 7 is a cross-sectional view taken at a position corresponding to FIG. As shown in FIG. 7, the semiconductor device 100A according to the modified example of the first embodiment is substantially the same as the semiconductor device 100 according to the first embodiment, except that the partition portion 14x and the first insulating region 14p are not provided.

[0040] In this way, the partitions 14x are provided as necessary and can be omitted. Furthermore, when the partitions 14x are omitted, the first insulating regions 14p can be omitted.

[0041] Second embodiment FIG. 8 is an enlarged plan view illustrating a portion of the semiconductor device according to the second embodiment. FIG. 9 is a cross-sectional view illustrating a portion of the semiconductor device according to the second embodiment. FIG. 10 is a cross-sectional view illustrating a portion of the semiconductor device according to the second embodiment. FIG. 11 is a cross-sectional view illustrating a portion of the semiconductor device according to the second embodiment. FIG. 12 is a cross-sectional view illustrating a portion of the semiconductor device according to the second embodiment. FIG. 8 is an enlarged plan view at a position corresponding to FIG. FIG. 9 is a cross-sectional view taken along line IX-IX shown in FIG. FIG. 10 is a cross-sectional view taken along the line XX shown in FIG. FIG. 11 is a cross-sectional view taken along line XI-XI shown in FIG. FIG. 12 is a cross-sectional view taken along line XII-XII shown in FIG.

[0042] 8 to 12, the semiconductor device 200 according to the second embodiment is substantially the same as the semiconductor device 100 according to the first embodiment, except that a gate electrode 13 is provided on an FP electrode 14. In Fig. 8, the positions of the gate electrode 13, the source electrode 12, and the gate wiring layer 15 are indicated by two-dot chain lines.

[0043] In this example, the gate electrode 13 is disposed in the Y direction between the p-type base region 22 and the n + The FP electrode 14 is aligned with the n-type source region 23 and a portion of the source connection 16. In this example, the FP electrode 14 is aligned with the n-type source region 23 and a portion of the source connection 16 in the Y direction.- A p-type drift region 21, a p-type base region 22, and a p + The gate electrode 13 is aligned with the FP electrode 14 in the Z direction. In this example, the gate electrode 13 is aligned with the FP electrode 14 in the Z direction. In this example, a part of the gate insulation portion 31 is located between the gate electrode 13 and the FP electrode 14 in the Z direction.

[0044] In this example, the FP electrode 14 also has an internal void 40. This allows the void 40 to absorb stress when the FP insulating section 32 expands, thereby suppressing warpage. Furthermore, the effect of suppressing warpage can be maintained even in a chip state.

[0045] (Method of manufacturing a semiconductor device) 13(a) to 13(d) are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. 14(a) to 14(d) are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. As shown in Figures 13(a) to 13(d) and 14(a) to 14(d), the manufacturing method of the semiconductor device of the embodiment includes the steps of forming a trench 65 in a semiconductor region 60, forming an insulating portion 70 along a bottom surface 65a and a side surface 65b of the trench 65, and forming a conductive portion (a first conductive portion 75 and a second conductive portion 85) including a void portion 40 inside the insulating portion 70. The step of forming the conductive portion includes, for example, a step of forming a first conductive portion 75 along the bottom surface portion 70a and the side surface portion 70b of the insulating portion 70, a step of forming an insulating film (first insulating film 80) along the bottom surface portion 75a and the side surface portion 75b of the first conductive portion 75, a step of forming a second conductive portion 85 inside the insulating film (first insulating film 80), a step of removing the second conductive portion 85 until the insulating film (first insulating film 80) is exposed, and a step of forming a gap portion 40 between the first conductive portion 75 and the second conductive portion 85 by removing the insulating film (first insulating film 80) except for the lowermost portion. Each step will be described below.

[0046] First, as shown in FIG. 13A, a trench 65 is formed in a semiconductor region 60. The semiconductor region 60 is, for example,- The semiconductor region 60 corresponds to, for example, the p-type base region 22 and the n-type drift region 21 described above. + The trench 65 may include a portion corresponding to at least one of the source regions 23. The trench 65 is formed by, for example, RIE (reactive ion etching).

[0047] 13(b), an insulating portion 70 is formed along the bottom surface 65a and the side surface 65b of the trench 65. The insulating portion 70 includes, for example, a bottom surface portion 70a formed on the bottom surface 65a of the trench 65, a side surface portion 70b formed inside the side surface 65b of the trench 65, and an upper surface portion 70c formed on the upper surface 60a of the semiconductor region 60. The insulating portion 70 corresponds to, for example, the above-mentioned FP insulating portion 32. The insulating portion 70 is formed by, for example, thermal oxidation or CVD (chemical vapor deposition).

[0048] Next, as shown in FIG. 13(c), a first conductive portion 75 is formed along the bottom surface portion 70a and the side surface portion 70b of the insulating portion 70. The first conductive portion 75 includes, for example, a bottom surface portion 75a formed on the bottom surface portion 70a of the insulating portion 70, a side surface portion 75b formed inside the side surface portion 70b of the insulating portion 70, and an upper surface portion 75c formed on the upper surface portion 70c of the insulating portion 70. The first conductive portion 75 corresponds to, for example, a part of the above-mentioned FP electrode 14 (the first side surface portion 14a, the second side surface portion 14b, the third side surface portion 14c, the fourth side surface portion 14d, and the bottom surface portion 14e). The first conductive portion 75 is formed, for example, by CVD.

[0049] 13(d), a first insulating film 80 is formed along the bottom surface portion 75a and the side surface portion 75b of the first conductive portion 75. The first insulating film 80 includes, for example, a bottom surface portion 80a formed on the bottom surface portion 75a of the first conductive portion 75, a side surface portion 80b formed inside the side surface portion 75b of the first conductive portion 75, and an upper surface portion 80c formed on the upper surface portion 75c of the first conductive portion 75. The first insulating film 80 corresponds to, for example, a part (first insulating region 14p) of the above-mentioned FP electrode 14. The first insulating film 80 is formed by, for example, thermal oxidation or CVD (chemical vapor deposition).

[0050] 14(a), a second conductive portion 85 is formed inside the first insulating film 80. The second conductive portion 85 includes, for example, a filling portion 85a formed on the bottom surface portion 80a and inside the side surface portion 80b of the first insulating film 80, and an upper surface portion 85b formed on the upper surface portion 80c of the first insulating film 80. The second conductive portion 85 corresponds to, for example, a part (partition portion 14x) of the above-mentioned FP electrode 14. The second conductive portion 85 is formed by, for example, CVD.

[0051] 14(b), the second conductive portion 85 is removed until the first insulating film 80 is exposed. In this step, the upper surface portion 85b of the second conductive portion 85 and a part of the filling portion 85a of the second conductive portion 85 are removed. The second conductive portion 85 is removed by, for example, etching.

[0052] Next, as shown in FIG. 14(c), the first insulating film 80 is removed leaving the lowest part, thereby forming the gap 40 between the first conductive part 75 and the second conductive part 85. In this process, the upper surface part 80c of the first insulating film 80 and a part of the side surface part 80b of the first insulating film 80 are removed. The part from which the first insulating film 80 is removed becomes the gap 40. In this process, the bottom surface part 80a of the first insulating film 80 and a part of the side surface part 80b of the first insulating film 80 are left without being removed. The part of the first insulating film 80 that is left without being removed corresponds to a part (first insulating region 14p) of the FP electrode 14 described above. By leaving a part of the first insulating film 80, the second conductive part 85 can be maintained in a state of being bonded to the bottom surface part 75a of the first conductive part 75. The removal of the first insulating film 80 is performed by, for example, etching.

[0053] Next, as shown in FIG. 14(d), the first conductive portion 75 is removed until the insulating portion 70 is exposed. In this step, the upper surface portion 75c of the first conductive portion 75 is removed. The first insulating film 80 is removed by, for example, etching or CMP (chemical mechanical polishing). Next, as shown in FIG. 14(d), a second insulating film 90 is formed on the insulating portion 70, the first conductive portion 75, and the second conductive portion 85. The second insulating film 90 includes, for example, a lid portion 90a that closes the upper portion of the void portion 40, and an upper surface portion 90b formed on the upper surface portion 70c of the insulating portion 70, the first conductive portion 75, the second conductive portion 85, and the lid portion 90a. The second insulating film 90 corresponds to, for example, a part (second insulating region 14q) of the above-mentioned FP electrode 14. The second insulating film 90 is formed by, for example, CVD.

[0054] With such a manufacturing method, the semiconductor device according to the embodiment can be easily manufactured.

[0055] The above-mentioned steps are steps for forming the FP electrode 14. When the gate electrode 13 and the FP electrode 14 are aligned in the Y direction as in the semiconductor device 100 according to the first embodiment, the FP electrode 14 may be formed before or after the gate electrode 13. When the gate electrode 13 is provided on the FP electrode 14 as in the semiconductor device 200 according to the second embodiment, the FP electrode 14 is formed before the gate electrode 13.

[0056] The embodiment may include the following features.

[0057] (Configuration 1) A first electrode; a first semiconductor region of a first conductivity type provided on the first electrode; a second semiconductor region of a second conductivity type provided on the first semiconductor region; a third semiconductor region of the first conductivity type selectively provided on the second semiconductor region; a second electrode provided on the third semiconductor region and electrically connected to the third semiconductor region; a third electrode aligned with the second semiconductor region in a second direction perpendicular to a first direction from the first electrode toward the second electrode; a first insulating portion provided between the second semiconductor region and the third electrode in the second direction; a fourth electrode aligned with the first semiconductor region in the second direction; a second insulating portion provided between the first semiconductor region and the fourth electrode in the second direction; Equipped with The fourth electrode has a first side portion, a second side portion, and a gap portion located between the first side portion and the second side portion in the second direction.

[0058] (Configuration 1) The fourth electrode is a bottom surface portion connecting a lower end of the first side surface portion and a lower end of the second side surface portion; a partition portion located between the first side portion and the second side portion in the second direction and partitioning the gap portion; a first insulating region located between the bottom surface portion and the partition portion in the first direction; a second insulating region provided above the gap and positioned between the first side portion and the partition portion and between the second side portion and the partition portion in the second direction; and The semiconductor device of configuration 1, wherein the void portion has a first void region located between the first side portion and the partition portion in the second direction, and a second void region located between the second side portion and the partition portion in the second direction.

[0059] (Configuration 3) forming a trench in a semiconductor region; forming an insulating portion along a bottom and side of the trench; forming a conductive portion including a void portion inside the insulating portion; The manufacturing method of a semiconductor device comprising the steps of:

[0060] (Configuration 4) The step of forming the conductive portion includes: forming a first conductive portion along a bottom surface and a side surface of the insulating portion; forming an insulating film along a bottom surface and a side surface of the first conductive portion; forming a second conductive portion inside the insulating film; removing the second conductive portion until the insulating film is exposed; removing the insulating film except for a lowermost portion to form the gap between the first conductive portion and the second conductive portion; 4. A method for producing the semiconductor device according to claim 3, comprising:

[0061] As described above, according to the embodiment, a semiconductor device capable of suppressing warpage and a method for manufacturing the semiconductor device are provided.

[0062] Although some embodiments of the present invention have been illustrated above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, modifications, etc. can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are included in the scope of the invention and its equivalents described in the claims. In addition, the above-mentioned embodiments can be implemented in combination with each other. [Explanation of symbols]

[0063] 11: Drain electrode (first electrode) 12: Source electrode (second electrode) 13: Gate electrode (third electrode) 14:FP electrode (4th electrode) 14a: First side part 14b: Second side part 14c: Third side part 14d: 4th side part 14e: Bottom part 14p: First insulating region 14q: Second insulating region 14x: Compartment 15: Gate wiring layer 16: Source connection 17: FP connection part 18: Gate connection 21:n - Drift region (first semiconductor region) 22: p-type base region (second semiconductor region) 23:n + Source region (third semiconductor region) 24:n + Shaped drain region 25:p + Contact area 25 31: Gate insulation part (first insulation part) 32: FP insulation part (second insulation part) 33: Upper insulation part 40:Void part 41:First void area 42:Second void area 43:Third void area 44: 4th void area 60: Semiconductor area 60a:Top surface 65: Trench 65a: Bottom 65b: Side 70: Insulation section 70a: Bottom part 70b: Side part 70c:Top part 75: First conductive part 75a: Bottom part 75b: Side part 75c:Top part 80: First insulating film 80a: Bottom part 80b: Side part 80c:Top part 85: Second conductive part 85a: Filling section 85b:Top part 90: Second insulating film 90a: Lid 90b:Top part 100, 100A, 200: Semiconductor device

Claims

1. A first electrode; a first semiconductor region of a first conductivity type provided on the first electrode; a second semiconductor region of a second conductivity type provided on the first semiconductor region; a third semiconductor region of the first conductivity type selectively provided on the second semiconductor region; a second electrode provided on the third semiconductor region and electrically connected to the third semiconductor region; a third electrode aligned with the second semiconductor region in a second direction perpendicular to a first direction from the first electrode toward the second electrode; a first insulating portion provided between the second semiconductor region and the third electrode in the second direction; a fourth electrode aligned with the first semiconductor region in the second direction; a second insulating portion provided between the first semiconductor region and the fourth electrode in the second direction; Equipped with The fourth electrode has a first side portion, a second side portion, and a gap portion located between the first side portion and the second side portion in the second direction.

2. The fourth electrode is a bottom surface portion connecting a lower end of the first side surface portion and a lower end of the second side surface portion; a partition portion located between the first side portion and the second side portion in the second direction and partitioning the gap portion; a first insulating region located between the bottom surface portion and the partition portion in the first direction; a second insulating region provided above the gap and positioned between the first side portion and the partition portion and between the second side portion and the partition portion in the second direction; and 2. The semiconductor device according to claim 1, wherein the void portion has a first void region located between the first side portion and the partition portion in the second direction, and a second void region located between the second side portion and the partition portion in the second direction.

3. forming a trench in a semiconductor region; forming an insulating portion along a bottom and side of the trench; forming a conductive portion including a void portion inside the insulating portion; The manufacturing method of a semiconductor device comprising the steps of:

4. The step of forming the conductive portion includes: forming a first conductive portion along a bottom surface and a side surface of the insulating portion; forming an insulating film along a bottom surface and a side surface of the first conductive portion; forming a second conductive portion inside the insulating film; removing the second conductive portion until the insulating film is exposed; removing the insulating film except for a lowermost portion to form the gap between the first conductive portion and the second conductive portion; The method for manufacturing a semiconductor device according to claim 3 , comprising:

Images