Semiconductor device

Abstract

To provide a semiconductor device capable of reducing a switching loss.SOLUTION: A semiconductor device of an embodiment, comprises: a first conductive shaped first semiconductor region in a semiconductor layer; a second conductive shaped second semiconductor region on the first semiconductor region; a first conductive shaped third semiconductor region on the second semiconductor region; a second conductive shaped fourth semiconductor region and a first conductive shaped fifth semiconductor region that are alternately arranged in a first direction on the third semiconductor region; a first conductive shaped sixth semiconductor region in which a first conductive shaped impurity concentration between the third semiconductor region and the fourth semiconductor region is higher than that of the third semiconductor region, and is lower than that of the fifth semiconductor region; a first trench that is separated from the sixth semiconductor region; a gate electrode in the first trench; a transistor region that contains a first electrode that includes a first part, and of which a bottom surface of the first part is contacted to the third semiconductor region, and a side surface of the first part is contacted to the fourth, fifth, and sixth semiconductor regions, and a second electrode; and a diode region.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] An example of a power semiconductor device is an insulated gate bipolar transistor (IGBT). In an IGBT, for example, a p-type collector region, an n-type drift region, and a p-type base region are provided on a collector electrode. A gate electrode is provided in a trench that penetrates the p-type base region and reaches the n-type drift region, with a gate insulating film sandwiched therebetween. Furthermore, an n-type emitter region connected to an emitter electrode is provided in a region adjacent to the trench on the surface of the p-type base region.

[0003] In recent years, reverse-conducting IGBTs (RC-IGBTs), in which an IGBT and a freewheeling diode are formed on the same semiconductor chip, have been widely developed and commercialized. RC-IGBTs are used, for example, as switching elements in inverter circuits. The freewheeling diode has the function of passing a current in the opposite direction to the on-current of the IGBT. Forming the IGBT and the freewheeling diode on the same semiconductor chip has many advantages, including a reduction in chip size by sharing the termination area and dispersion of heat generation points.

[0004] In RC-IGBT, the operation of the IGBT and the operation of the diode may interfere with each other, degrading the element characteristics of the RC-IGBT. For example, when the diode is turned off, holes that were injected from the IGBT region at the boundary with the diode region may not be discharged, increasing the reverse recovery current of the diode. When the reverse recovery current of the diode increases, the switching loss of the diode increases, and the switching loss of the RC-IGBT increases. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Patent No. 5034461 Summary of the Invention [Problem to be solved by the invention]

[0006] An object of the present invention is to provide a semiconductor device that includes an RC-IGBT having an IGBT and a diode, and that enables a reduction in switching loss. [Means for solving the problem]

[0007] A semiconductor device according to an embodiment includes a semiconductor layer having a first surface and a second surface opposite to the first surface, a first semiconductor region of a first conductivity type provided in the semiconductor layer, a second semiconductor region of a second conductivity type provided in the semiconductor layer and between the first semiconductor region and the first surface, a third semiconductor region of the first conductivity type provided in the semiconductor layer and between the second semiconductor region and the first surface, and a third semiconductor region of the first conductivity type provided in the semiconductor layer and between the third semiconductor region and the first surface, the third semiconductor region being alternately arranged in a first direction parallel to the first surface. a fourth semiconductor region of a second conductivity type and a fifth semiconductor region of a first conductivity type; a sixth semiconductor region of a first conductivity type provided between the third semiconductor region and the fourth semiconductor region, the sixth semiconductor region having a first conductivity type impurity concentration higher than a first conductivity type impurity concentration of the third semiconductor region and lower than a first conductivity type impurity concentration of the fifth semiconductor region; and a sixth semiconductor region of a first conductivity type provided on a side of the first surface in the semiconductor layer, extending in the first direction, and repeatedly arranged in a second direction parallel to the first surface and perpendicular to the first direction, the sixth semiconductor region being ... between the second semiconductor region, the third semiconductor region, the fourth semiconductor region and the sixth semiconductor region. a first trench in contact with the fifth semiconductor region and the sixth semiconductor region and separated from the sixth semiconductor region; a gate electrode provided in the first trench; a gate insulating film provided between the gate electrode and the third semiconductor region; a first electrode provided on the first surface side of the semiconductor layer and having a first portion, a bottom surface of the first portion being in contact with the third semiconductor region and a side surface of the first portion being in contact with the fourth semiconductor region, the fifth semiconductor region, and the sixth semiconductor region; a transistor region including a second electrode in contact with a body region, the semiconductor layer, the second semiconductor region, a seventh semiconductor region of a second conductivity type provided in the semiconductor layer and between the second semiconductor region and the second surface, the seventh semiconductor region having a second conductivity type impurity concentration higher than a second conductivity type impurity concentration of the second semiconductor region, an eighth semiconductor region of a first conductivity type provided in the semiconductor layer and between the second semiconductor region and the first surface, the first electrode electrically connected to the eighth semiconductor region, and the second electrode in contact with the seventh semiconductor region;and a diode region including: [Brief description of the drawings]

[0008] [Figure 1] 1 is a schematic diagram of a semiconductor device according to a first embodiment; [Diagram 2] 1 is a schematic cross-sectional view of a portion of a semiconductor device according to a first embodiment. [Diagram 3] FIG. 2 is a schematic top view of a portion of the semiconductor device according to the first embodiment. [Figure 4] 1 is a schematic cross-sectional view of a portion of a semiconductor device according to a first embodiment. [Diagram 5] FIG. 13 is a schematic cross-sectional view of a portion of a semiconductor device of a comparative example. [Figure 6] FIG. 13 is a schematic top view of a portion of a semiconductor device of a comparative example. [Figure 7] FIG. 13 is a schematic cross-sectional view of a portion of a semiconductor device of a comparative example. [Figure 8] 10A to 10C are diagrams illustrating problems with a semiconductor device according to a comparative example. [Figure 9] 5A to 5C are explanatory diagrams illustrating the operation and effects of the semiconductor device according to the first embodiment. [Figure 10] 5A to 5C are explanatory diagrams illustrating the operation and effects of the semiconductor device according to the first embodiment. [Figure 11] FIG. 4 is a schematic cross-sectional view of a portion of a semiconductor device according to a first modified example of the first embodiment. [Figure 12] FIG. 4 is a schematic top view of a part of a semiconductor device according to a first modified example of the first embodiment. [Figure 13] FIG. 4 is a schematic cross-sectional view of a portion of a semiconductor device according to a first modified example of the first embodiment. [Figure 14] FIG. 4 is a schematic cross-sectional view of a portion of a semiconductor device according to a second modified example of the first embodiment. [Figure 15] FIG. 4 is a schematic top view of a portion of a semiconductor device according to a second modified example of the first embodiment. [Figure 16] FIG. 4 is a schematic cross-sectional view of a portion of a semiconductor device according to a second modified example of the first embodiment. [Figure 17] FIG. 6 is a schematic cross-sectional view of a portion of a semiconductor device according to a second embodiment. [Figure 18] FIG. 11 is a schematic top view of a portion of a semiconductor device according to a second embodiment. [Figure 19] FIG. 6 is a schematic cross-sectional view of a portion of a semiconductor device according to a second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the following description, the same reference numerals will be used to designate the same or similar components, and the description of components that have already been described will be omitted as appropriate.

[0010] In this specification, n + shape, n shape, n - When there is a notation with shape, n + shape, n shape, n - This means that the n-type impurity concentration decreases in the order of p + shape, p shape, p - If there is a form notation, p + shape, p shape, p - This means that the p-type impurity concentration decreases in the order of the p-type.

[0011] In this specification, the n-type impurity concentration does not indicate the actual n-type impurity concentration, but indicates the effective n-type impurity concentration after compensation. Similarly, the p-type impurity concentration does not indicate the actual p-type impurity concentration, but indicates the effective p-type impurity concentration after compensation. For example, when the actual n-type impurity concentration is greater than the actual p-type impurity concentration, the concentration obtained by subtracting the p-type impurity concentration from the actual n-type impurity concentration is taken as the n-type impurity concentration. The same applies to the p-type impurity concentration.

[0012] In this specification, the distribution and absolute value of the impurity concentration of the semiconductor region can be measured, for example, by using secondary ion mass spectrometry (SIMS). The relative magnitude relationship between the impurity concentrations of two semiconductor regions can be determined, for example, by using scanning capacitance microscopy (SCM). The distribution and absolute value of the impurity concentration can be measured, for example, by using spreading resistance analysis (SRA). In SCM and SRA, the relative magnitude relationship and absolute value of the carrier concentration of the semiconductor region can be obtained. By assuming the activation rate of the impurities, it is possible to obtain the relative magnitude relationship between the impurity concentrations of the two semiconductor regions, the distribution of the impurity concentration, and the absolute value of the impurity concentration from the measurement results of SCM and SRA.

[0013] (First embodiment) The semiconductor device according to the first embodiment is A semiconductor layer having a first surface and a second surface opposite to the first surface, a first semiconductor region of a first conductivity type provided in the semiconductor layer, a second semiconductor region of a second conductivity type provided in the semiconductor layer and between the first semiconductor region and the first surface, a third semiconductor region of the first conductivity type provided in the semiconductor layer and between the second semiconductor region and the first surface, and a fourth semiconductor region of the second conductivity type provided in the semiconductor layer and between the third semiconductor region and the first surface, the fourth semiconductor region of the second conductivity type being alternately arranged in a first direction parallel to the first surface. a conductor region and a fifth semiconductor region of a first conductivity type; a sixth semiconductor region of a first conductivity type provided between the third semiconductor region and the fourth semiconductor region, the sixth semiconductor region having a first conductivity type impurity concentration higher than the first conductivity type impurity concentration of the third semiconductor region and lower than the first conductivity type impurity concentration of the fifth semiconductor region; a second semiconductor region, a third semiconductor region, a fourth semiconductor region, and a sixth semiconductor region provided on the first surface side of the semiconductor layer, extending in a first direction and repeatedly arranged in a second direction parallel to the first surface and perpendicular to the first direction; a first trench in contact with the fifth semiconductor region and separated from the sixth semiconductor region; a gate electrode provided in the first trench; a gate insulating film provided between the gate electrode and the third semiconductor region; a first electrode provided on the first surface side of the semiconductor layer and having a first portion, a bottom surface of the first portion in contact with the third semiconductor region and a side surface of the first portion in contact with the fourth semiconductor region, the fifth semiconductor region, and the sixth semiconductor region; and a second electrode provided on the second surface side of the semiconductor layer and in contact with the first semiconductor region. the diode region including a transistor region including a first semiconductor region, a semiconductor layer, a second semiconductor region, a seventh semiconductor region of a second conductivity type provided in the semiconductor layer, between the second semiconductor region and the second surface, and having a second conductivity type impurity concentration higher than a second conductivity type impurity concentration of the second semiconductor region, an eighth semiconductor region of a first conductivity type provided in the semiconductor layer, between the second semiconductor region and the first surface, a first electrode electrically connected to the eighth semiconductor region, and a second electrode in contact with the seventh semiconductor region.

[0014] The semiconductor device of the first embodiment is an RC-IGBT100 in which an IGBT and a free wheel diode are formed on the same semiconductor chip. The RC-IGBT100 has a trench-gate type IGBT with a gate electrode in a trench formed in a semiconductor layer. Below, an example will be described in which the first conductivity type is p-type and the second conductivity type is n-type.

[0015] FIG. 1 is a schematic diagram of a semiconductor device according to the first embodiment.

[0016] 2 is a schematic cross-sectional view of a portion of the semiconductor device according to the first embodiment, taken along line AA' of FIG.

[0017] Fig. 3 is a schematic top view of a part of the semiconductor device of the first embodiment, Fig. 3 is a top view on a first face F1, Fig. 2 is a cross section taken along line AA' of Fig. 3.

[0018] 4 is a schematic cross-sectional view of a portion of the semiconductor device according to the first embodiment, taken along line BB' of FIG.

[0019] The semiconductor device of the first embodiment is an RC-IGBT 100. The RC-IGBT 100 has a transistor region 101 and a diode region 102. The transistor region 101 operates as an IGBT. The diode region 102 operates as a freewheeling diode.

[0020] The RC-IGBT 100 of the first embodiment includes a semiconductor layer 10, an upper electrode 12 (first electrode), a lower electrode 14 (second electrode), a gate electrode 16, a first conductive layer 18, a second conductive layer 20, a gate insulating film 22, a first insulating film 24, a second insulating film 26, an interlayer insulating layer 28, and a gate electrode pad 103.

[0021] The upper electrode 12 has a first trench contact portion 12x (first portion).

[0022] In the semiconductor layer 10, a gate trench 31 (first trench), a first dummy trench 32 (second trench), a second dummy trench 33 (third trench), a collector region 41 (first semiconductor region), a drift region 42 (second semiconductor region), a base region 43 (third semiconductor region), an emitter region 44 (fourth semiconductor region), a cell contact region 45 (fifth semiconductor region), a resistance reduction region 46 (sixth semiconductor region), a barrier region 47 (tenth semiconductor region), a cathode region 51 (seventh semiconductor region), an anode region 52 (eighth semiconductor region), and a diode contact region 53 (ninth semiconductor region) are provided.

[0023] The semiconductor layer 10 has a first face F1 and a second face F2 opposing the first face F1. The first face F1 and the second face F2 are, for example, substantially parallel to each other.

[0024] The semiconductor layer 10 is, for example, single crystal silicon, and has a thickness of, for example, 40 μm or more and 700 μm or less.

[0025] In this specification, a direction parallel to the first face F1 is referred to as a first direction. A direction parallel to the first face F1 and perpendicular to the first direction is referred to as a second direction. In this specification, the term "depth" is defined as the distance from the first face F1 toward the second face F2.

[0026] The transistor region 101 includes a semiconductor layer 10, an upper electrode 12 (first electrode), a lower electrode 14 (second electrode), a gate electrode 16, a first conductive layer 18, a gate insulating film 22, a first insulating film 24, and an interlayer insulating layer .

[0027] In the semiconductor layer 10 of the transistor region 101, a gate trench 31 (first trench), a first dummy trench 32 (second trench), a collector region 41 (first semiconductor region), a drift region 42 (second semiconductor region), a base region 43 (third semiconductor region), an emitter region 44 (fourth semiconductor region), a cell contact region 45 (fifth semiconductor region), a resistance reduction region 46 (sixth semiconductor region), and a barrier region 47 (tenth semiconductor region) are provided.

[0028] The upper electrode 12 is provided on the first face F1 side of the semiconductor layer 10. In the transistor region 101, the upper electrode 12 functions as an emitter electrode of the IGBT.

[0029] The upper electrode 12 has a first trench contact portion 12x. The first trench contact portion 12x is formed in a trench provided in the semiconductor layer 10. The first trench contact portion 12x extends in a first direction.

[0030] A bottom surface of the first trench contact portion 12x contacts the base region 43. A side surface of the first trench contact portion 12x contacts, for example, the base region 43, the emitter region 44, the cell contact region 45, and the resistance reduction region 46. The first trench contact portion 12x is electrically connected to the base region 43, the emitter region 44, the cell contact region 45, and the resistance reduction region 46.

[0031] The contact between the first trench contact portion 12x and the base region 43 is, for example, a Schottky contact. The contact between the first trench contact portion 12x and the emitter region 44 and the cell contact region 45 is, for example, an ohmic contact. The contact between the trench contact portion 12x and the resistance reducing region 46 is a Schottky contact or an ohmic contact. The contact between the trench contact portion 12x and the resistance reducing region 46 is preferably an ohmic contact.

[0032] The upper electrode 12 is, for example, a metal or a metal compound. The first trench contact portion 12x and a portion other than the first trench contact portion 12x are formed of, for example, the same material. The first trench contact portion 12x and a portion other than the first trench contact portion 12x may be formed of different materials.

[0033] The lower electrode 14 is provided on the second face F2 side of the semiconductor layer 10. At least a portion of the lower electrode 14 contacts the second face F2 of the semiconductor layer 10. In the transistor region 101, the lower electrode 14 functions as a collector electrode of the IGBT.

[0034] The lower electrode 14 is in contact with the collector region 41 in the transistor region 101. The lower electrode 14 is electrically connected to the collector region 41 in the transistor region 101.

[0035] The bottom electrode 14 is, for example, a metal or a metal compound.

[0036] The collector region 41 is p + The collector region 41 is a semiconductor region having a shape similar to that of the first face F2. The collector region 41 is in contact with the second face F2. The collector region 41 is electrically connected to the lower electrode 14. The collector region 41 is in contact with the lower electrode 14. The collector region 41 serves as a source of holes when the IGBT is in an on-state.

[0037] The collector region 41 contains a p-type impurity. The p-type impurity is, for example, boron (B). The p-type impurity concentration of the collector region 41 is, for example, 1×10 18 cm -3 More than 1×10 21 cm -3 The following is the result.

[0038] The drift region 42 has n - The drift region 42 is provided between the collector region 41 and the first face F1.

[0039] The drift region 42 serves as a path for an on-current when the IGBT is in an on-state, and has a function of being depleted when the IGBT is in an off-state, thereby maintaining the breakdown voltage of the IGBT.

[0040] The drift region 42 contains an n-type impurity. The n-type impurity is, for example, phosphorus (P) or arsenic (As). The n-type impurity concentration of the drift region 42 is, for example, 1×10 15 cm -3 More than 1×10 18 cm -3 The following is the result.

[0041] The base region 43 is p - The base region 43 is a semiconductor region having a shape similar to that of the drift region 42. The base region 43 is provided between the drift region 42 and the first face F1. The drift region 42 is sandwiched between the base region 43 and the collector region 41.

[0042] The depth of the base region 43 is, for example, 5 μm or less. When the IGBT is in the on state, an n-type inversion layer is formed in a region of the base region 43 facing the gate electrode 16. The base region 43 functions as a channel region of the IGBT.

[0043] The base region 43 contains a p-type impurity. The p-type impurity is, for example, boron (B). The p-type impurity concentration of the base region 43 is, for example, 5×10 16 cm -3 5×10 or more 17 cm -3 The following is the result.

[0044] The emitter region 44 is + The emitter region 44 is a semiconductor region having a shape similar to that of the first face F1. The emitter region 44 is provided between the base region 43 and the first face F1. The emitter region 44 is in contact with the first face F1.

[0045] The emitter region 44 contacts the gate trench 31 and the first dummy trench 32. The emitter region 44 contacts the gate insulating film 22 and the first insulating film 24.

[0046] The emitter region 44 contacts the first trench contact portion 12x of the upper electrode 12. The emitter region 44 is electrically connected to the upper electrode 12. The emitter region 44 serves as a supply source of electrons when the IGBT is in an on-state.

[0047] The emitter region 44 contains an n-type impurity. The n-type impurity is, for example, phosphorus (P) or arsenic (As). The n-type impurity concentration of the emitter region 44 is higher than the n-type impurity concentration of the drift region 42. The n-type impurity concentration of the emitter region 44 is, for example, 1×10 19 cm -3 More than 1×10 21 cm -3 The following is the result.

[0048] The cell contact region 45 is p + The cell contact region 45 is a semiconductor region having a shape similar to that of the base region 43. The cell contact region 45 is provided between the base region 43 and the first face F1. The cell contact region 45 contacts the first face F1.

[0049] The cell contact region 45 contacts the gate trench 31 and the first dummy trench 32. The cell contact region 45 contacts the gate insulating film 22 and the first insulating film .

[0050] The cell contact region 45 contacts the first trench contact portion 12x of the upper electrode 12. The cell contact region 45 is electrically connected to the upper electrode 12.

[0051] The cell contact region 45 contains a p-type impurity. The p-type impurity is, for example, boron (B). The p-type impurity concentration of the cell contact region 45 is higher than the p-type impurity concentration of the base region 43. The p-type impurity concentration of the cell contact region 45 is, for example, 5×10 19 cm -3 More than 1×10 21 cm -3 The following is the result.

[0052] 3, the emitter regions 44 and the cell contact regions 45 are alternately arranged in the first direction on the first face F1. The width of the emitter regions 44 in the first direction on the first face F1 is, for example, smaller than the width of the cell contact regions 45 in the first direction on the first face F1.

[0053] The resistance reducing region 46 is a p-type semiconductor region. The resistance reducing region 46 is provided between the base region 43 and the emitter region 44. The resistance reducing region 46 contacts the base region 43 and the emitter region 44, for example.

[0054] The resistance reducing region 46 is provided, for example, between the base region 43 and the cell contact region 45. The resistance reducing region 46 is in contact with, for example, the base region 43 and the cell contact region 45. The resistance reducing region 46 extends, for example, in a first direction.

[0055] The resistance reducing region 46 contacts the first trench contact portion 12x of the upper electrode 12. The resistance reducing region 46 contacts a side surface of the first trench contact portion 12x. The resistance reducing region 46 is electrically connected to the upper electrode 12.

[0056] The resistance reduction region 46 is separated from the gate trench 31. The resistance reduction region 46 is separated from the gate insulating film 22. The resistance reduction region 46 is provided, for example, between the gate trench 31 and the first trench contact portion 12x. For example, a base region 43 is provided between the resistance reduction region 46 and the gate trench 31. The base region 43 between the resistance reduction region 46 and the gate trench 31 functions as a channel region of the IGBT.

[0057] The resistance reducing region 46 contacts the first dummy trench 32. The resistance reducing region 46 contacts the first insulating film 24.

[0058] The depth of the resistance reducing region 46 is shallower than the depth of the first trench contact portion 12x.

[0059] The resistance reduction region 46 reduces the electrical resistance below the emitter region 44. The resistance reduction region 46 functions as a path for holes to escape to the upper electrode 12 when the IGBT is in an off-operation state. The provision of the resistance reduction region 46 suppresses the operation of a parasitic npn transistor, improving the latch-up resistance of the RC-IGBT 100. In addition, the resistance reduction region 46 in contact with the first dummy trench 32 allows the hole current to be discharged along the sidewall of the first dummy trench 32, so that the resistance reduction region 46 acts effectively. Therefore, the latch-up resistance can be improved more than when the resistance reduction region 46 is not in contact with the first dummy trench 32.

[0060] The resistance reducing region 46 contains a p-type impurity. The p-type impurity is, for example, boron (B). The p-type impurity concentration of the resistance reducing region 46 is higher than the p-type impurity concentration of the base region 43 and lower than the p-type impurity concentration of the cell contact region 45. The p-type impurity concentration of the resistance reducing region 46 is, for example, 5×10 17 cm -3 More than 1×10 19 cm -3 The following is the result.

[0061] The barrier region 47 is an n-type semiconductor region and is provided between the drift region 42 and the base region 43.

[0062] The barrier region 47 has the function of promoting the accumulation of carriers and reducing the on-resistance when the IGBT is in the on-state.

[0063] The barrier region 47 contains an n-type impurity. The n-type impurity is, for example, phosphorus (P) or arsenic (As). The n-type impurity concentration of the barrier region 47 is, for example, 5×10 15 cm -3 5×10 or more 18 cm -3 The following is the result.

[0064] The gate trench 31 is provided on the first face F1 side of the semiconductor layer 10. The gate trench 31 is a groove provided in the semiconductor layer 10. The gate trench 31 is a part of the semiconductor layer 10.

[0065] 3, the gate trench 31 extends in a first direction parallel to the first face F1 in the first face F1. The gate trench 31 has a stripe shape. The multiple gate trenches 31 are repeatedly arranged in a second direction perpendicular to the first direction.

[0066] The gate trench 31 contacts the drift region 42, the barrier region 47, the base region 43, the emitter region 44, and the cell contact region 45. The gate trench 31 is separated from the resistance reducing region 46. This is because if the resistance reducing region contacts the gate trench 31, the impurity concentration therein is higher than that of the base region 43, and the threshold value becomes higher than a desired value, making it difficult to drive. The gate trench 31 penetrates the base region 43 and the barrier region 47 and reaches the drift region 42. The depth of the gate trench 31 is, for example, 8 μm or less.

[0067] The gate electrode 16 is provided in the gate trench 31. The gate electrode 16 is, for example, a semiconductor or a metal. The gate electrode 16 is, for example, amorphous silicon or polycrystalline silicon containing n-type impurities or p-type impurities. The gate electrode 16 is electrically connected to the gate electrode pad 103.

[0068] The gate insulating film 22 is provided between the gate electrode 16 and the semiconductor layer 10. The gate insulating film 22 is provided between the gate electrode 16 and the drift region 42, between the gate electrode 16 and the base region 43, between the gate electrode 16 and the emitter region 44, and between the gate electrode 16 and the cell contact region 45. The gate insulating film 22 is, for example, silicon oxide.

[0069] The first dummy trench 32 is provided on the first face F1 side of the semiconductor layer 10. The first dummy trench 32 is a groove provided in the semiconductor layer 10. The first dummy trench 32 is a part of the semiconductor layer 10.

[0070] 3, the first dummy trench 32 extends in the first face F1 in a first direction parallel to the first face F1. The first dummy trench 32 has a stripe shape. The first dummy trenches 32 are repeatedly arranged in a second direction perpendicular to the first direction. The first dummy trench 32 is provided between two adjacent gate trenches 31.

[0071] The first dummy trench 32 contacts the drift region 42, the barrier region 47, the base region 43, the emitter region 44, the cell contact region 45, and the resistance reducing region 46. The first dummy trench 32 penetrates the base region 43 and the barrier region 47 to reach the drift region 42. The depth of the first dummy trench 32 is, for example, 8 μm or less.

[0072] The first conductive layer 18 is provided in the first dummy trench 32. The first conductive layer 18 is, for example, a semiconductor or a metal. The first conductive layer 18 is, for example, amorphous silicon or polycrystalline silicon containing n-type impurities or p-type impurities.

[0073] The first conductive layer 18 is electrically connected to, for example, the upper electrode 12. It is also possible to connect the first conductive layer 18 to an electrode other than the upper electrode 12 and apply a voltage to the first conductive layer 18 different from that to the upper electrode 12. The first conductive layer 18 may be electrically connected to, for example, the gate electrode pad 103.

[0074] The first insulating film 24 is provided between the first conductive layer 18 and the semiconductor layer 10. The first insulating film 24 is provided between the first conductive layer 18 and the drift region 42, between the first conductive layer 18 and the base region 43, between the first conductive layer 18 and the emitter region 44, between the first conductive layer 18 and the cell contact region 45, and between the first conductive layer 18 and the resistance reducing region 46. The first insulating film 24 is, for example, silicon oxide.

[0075] The interlayer insulating layer 28 is provided between the gate electrode 16 and the upper electrode 12. The interlayer insulating layer 28 electrically separates the gate electrode 16 from the upper electrode 12. For example, the first conductive layer 18 and the upper electrode 12 are electrically connected to each other using an opening provided in the interlayer insulating layer 28. The interlayer insulating layer 28 is made of, for example, silicon oxide.

[0076] The diode region 102 includes a semiconductor layer 10, an upper electrode 12 (first electrode), a lower electrode 14 (second electrode), a second conductive layer 20, and a second insulating film .

[0077] In the semiconductor layer 10 of the diode region 102, a second dummy trench 33 (third trench), a drift region 42 (second semiconductor region), a cathode region 51 (seventh semiconductor region), an anode region 52 (eighth semiconductor region), and a diode contact region 53 (ninth semiconductor region) are provided.

[0078] The upper electrode 12 functions as an anode electrode of the diode in the diode region 102. The upper electrode 12 is in contact with the anode region 52 and the diode contact region 53. The upper electrode 12 is electrically connected to the anode region 52 and the diode contact region 53.

[0079] The contact between the upper electrode 12 and the diode contact region 53 is, for example, an ohmic contact, and the contact between the upper electrode 12 and the anode region 52 is, for example, a Schottky contact.

[0080] The upper electrode 12 and the anode region 52 are in contact with each other at a first face F1. The position where the upper electrode 12 and the anode region 52 are in contact with each other is shallower than the depth of the diode contact region 53.

[0081] The lower electrode 14 functions as a cathode electrode of the diode in the diode region 102. The lower electrode 14 is in contact with the cathode region 51.

[0082] The cathode region 51 is n + The cathode region 51 is a semiconductor region having a shape similar to that of the first face F2. The cathode region 51 serves as a source of electrons when the diode is in an on-state. The cathode region 51 is in contact with the lower electrode 14.

[0083] The drift region 42 has n - The drift region 42 is provided between the cathode region 51 and the first face F1. The n-type impurity concentration of the drift region 42 is lower than the n-type impurity concentration of the cathode region 51.

[0084] The drift region 42 serves as a path for an on-current when the diode is in an on-state.

[0085] The anode region 52 is a p-type semiconductor region. The anode region 52 is provided between the drift region 42 and the first face F1. The anode region 52 and the cathode region 51 sandwich the drift region 42 therebetween.

[0086] The anode region 52 provides a source of holes when the diode is in the on state.

[0087] The diode contact region 53 is p + The diode contact region 53 is provided between the anode region 52 and the first face F1.

[0088] The diode contact region 53 is in contact with the upper electrode 12. The diode contact region 53 is electrically connected to the upper electrode 12.

[0089] The p-type impurity concentration of the diode contact region 53 is higher than the p-type impurity concentration of the anode region 52 .

[0090] The second dummy trench 33 is provided on the first face F1 side of the semiconductor layer 10. The second dummy trench 33 is a groove provided in the semiconductor layer 10. The second dummy trench 33 is a part of the semiconductor layer 10.

[0091] 3, the second dummy trench 33 extends on the first face F1 in a first direction parallel to the first face F1. The second dummy trench 33 has a stripe shape. The second dummy trenches 33 are repeatedly arranged in a second direction perpendicular to the first direction.

[0092] The second dummy trench 33 contacts the drift region 42, the anode region 52, and the diode contact region 53. The second dummy trench 33 penetrates the anode region 52 and reaches the drift region 42. The depth of the second dummy trench 33 is, for example, 8 μm or less.

[0093] The second conductive layer 20 is provided in the second dummy trench 33. The second conductive layer 20 is, for example, a semiconductor or a metal. The second conductive layer 20 is, for example, amorphous silicon or polycrystalline silicon containing n-type impurities or p-type impurities.

[0094] The second conductive layer 20 is electrically connected to, for example, the upper electrode 12. It is also possible to connect the second conductive layer 20 to an electrode other than the upper electrode 12 and apply a voltage to the second conductive layer 20 different from that to the upper electrode 12.

[0095] The second insulating film 26 is provided between the second conductive layer 20 and the semiconductor layer 10. The second insulating film 26 is provided between the second conductive layer 20 and the drift region 42, between the second conductive layer 20 and the anode region 52, and between the second conductive layer 20 and the diode contact region 53. The second insulating film 26 is in contact with the drift region 42, the anode region 52, and the diode contact region 53. The second insulating film 26 is, for example, silicon oxide.

[0096] The interlayer insulating layer 28 is provided between the second conductive layer 20 and the upper electrode 12. For example, the second conductive layer 20 and the upper electrode 12 are electrically connected to each other using an opening provided in the interlayer insulating layer 28.

[0097] The gate electrode pad 103 is provided on the first face F1 side of the semiconductor layer 10. The gate electrode pad 103 is electrically connected to the gate electrode 16. The gate electrode pad 103 and the gate electrode 16 are connected by, for example, a metal wiring (not shown).

[0098] A gate voltage is applied to the gate electrode pad 103 .

[0099] Next, the operation and effects of the semiconductor device of the first embodiment will be described.

[0100] The RC-IGBT100 of the first embodiment can achieve both reduced switching loss and improved latch-up resistance. The RC-IGBT100 includes a first trench contact portion 12x and a resistance reducing region 46 in a transistor region 101. The bottom surface of the first trench contact portion 12x contacts the base region 43. In particular, the RC-IGBT100 includes the above configuration, which can achieve both reduced switching loss and improved latch-up resistance. This will be described in detail below.

[0101] Fig. 5 is a schematic cross-sectional view of a part of a semiconductor device of a comparative example, taken along line XX' in Fig. 6. Fig. 5 is a view corresponding to Fig. 2 of the first embodiment.

[0102] Fig. 6 is a schematic top view of a part of a semiconductor device of a comparative example, taken on a first face F1, and corresponding to Fig. 3 of the first embodiment.

[0103] Fig. 7 is a schematic cross-sectional view of a part of a semiconductor device of a comparative example, taken along line YY' in Fig. 6. Fig. 7 is a view corresponding to Fig. 4 of the first embodiment.

[0104] The semiconductor device of the comparative example is an RC-IGBT 900. The RC-IGBT 900 differs from the RC-IGBT 100 of the first embodiment in that it does not include a resistance reducing region 46 and that a p-type region 55 is provided.

[0105] The p-type region 55 is a p-type semiconductor region. The p-type region 55 is provided between the base region 43 and the first trench contact portion 12x. The p-type region 55 contacts the bottom surface of the first trench contact portion 12x.

[0106] The p-type impurity concentration of the p-type region 55 is higher than the p-type impurity concentration of the base region 43. The contact between the first trench contact portion 12x and the p-type region 55 is, for example, an ohmic contact.

[0107] The RC-IGBT900 of the comparative example includes a p-type region 55 in contact with the bottom surface of the first trench contact portion 12x. By including the p-type region 55, the discharge of holes from the p-type region 55 to the upper electrode 12 during the turn-off operation of the IGBT is promoted. Therefore, the operation of the parasitic npn transistor in the transistor region is suppressed. Therefore, the latch-up resistance of the RC-IGBT900 is improved.

[0108] Fig. 8 is an explanatory diagram of the problem of the semiconductor device of the comparative example, and is a diagram corresponding to Fig. 5. Fig. 8 is a diagram showing the flow of holes during steady operation of the diode.

[0109] 8, in the transistor region 101 close to the boundary with the diode region 102, the amount of holes injected from the base region 43 to the drift region 42 is large during steady-state operation of the diode. Therefore, the amount of holes injected from the transistor region 101 to the drift region 42 of the diode region 102 becomes large during steady-state operation of the diode.

[0110] The reason why the amount of holes injected into the transistor region 101 of the RC-IGBT 900 of the comparative example is large is believed to be because the amount of holes injected from the p-type region 55 at the bottom of the first trench contact portion 12x is large.

[0111] Fig. 9 is an explanatory diagram of the operation and effect of the semiconductor device of the first embodiment, and corresponds to Fig. 2. Fig. 9 is a diagram showing the flow of holes during steady operation of the diode.

[0112] 9, the amount of holes injected into the transistor region 101 close to the boundary with the diode region 102 is smaller than that in the comparative example. The RC-IGBT 100 of the first embodiment does not include a p-type region 55 at the bottom of the first trench contact portion 12x. Therefore, it is believed that the injection of holes from the bottom of the first trench contact portion 12x does not occur.

[0113] Furthermore, in the RC-IGBT 100 of the first embodiment, during steady-state operation of the diode, electrons are discharged to the upper electrode 12 through the contact surface between the bottom surface of the first trench contact portion 12x, which is a Schottky contact, and the base region 43. Therefore, it is considered that the injection of holes from the base region 43 to the drift region 42 is suppressed.

[0114] Fig. 10 is an explanatory diagram of the operation and effect of the semiconductor device of the first embodiment, and is a diagram showing the diode current characteristics of the RC-IGBT 100 of the first embodiment and the RC-IGBT 900 of the comparative example.

[0115] During steady-state operation of the diode, if the amount of holes injected from the transistor region 101 near the boundary with the diode region 102 to the diode region 102 is large, the amount of holes to be discharged to the upper electrode 12 during the turn-off operation of the diode increases. If the amount of holes to be discharged from the upper electrode 12 increases, the reverse recovery current of the diode increases. If the reverse recovery current of the diode increases, the switching loss of the diode increases.

[0116] In the RC-IGBT100 of the first embodiment, the amount of holes injected from the transistor region 101 to the diode region 102 during steady-state operation of the diode is smaller than that of the RC-IGBT900 of the comparative example. Therefore, as shown in Fig. 10, the RC-IGBT100 of the first embodiment has a smaller diode reverse recovery current than the RC-IGBT900 of the comparative example. Therefore, the RC-IGBT100 of the first embodiment has a smaller diode switching loss.

[0117] The RC-IGBT 100 of the first embodiment does not include a p-type region 55 at the bottom of the first trench contact portion 12x. However, the RC-IGBT 100 includes a p-type resistance reducing region 46 between the base region 43 and the emitter region 44. The p-type resistance reducing region 46 contacts the side surface of the first trench contact portion 12x.

[0118] The RC-IGBT100 of the first embodiment includes the resistance reducing region 46 in contact with the side surface of the first trench contact portion 12x, which promotes the discharge of holes from the resistance reducing region 46 to the upper electrode 12 during the turn-off operation of the IGBT. This suppresses the operation of the parasitic npn transistor in the transistor region 101. This improves the latch-up resistance of the RC-IGBT100.

[0119] As described above, according to the RC-IGBT 100 of the first embodiment, it is possible to achieve both a reduction in switching loss and an improvement in latch-up resistance.

[0120] From the viewpoint of promoting the discharge of holes from the resistance reducing region 46 to the upper electrode 12, it is preferable that the p-type impurity concentration of the resistance reducing region 46 is high. The p-type impurity concentration of the resistance reducing region 46 is higher than the p-type impurity concentration of the base region 43. The p-type impurity concentration of the resistance reducing region 46 is 5×10 17 cm -3 It is preferable that the concentration is 1×10 or more. 18 cm -3 More preferably, it is 5×10 or more. 18 cm -3 More preferably, it is equal to or greater than this.

[0121] From the viewpoint of stabilizing the threshold voltage of the IGBT, it is preferable that the p-type impurity concentration of the resistance reduction region 46 adjacent to the channel region of the IGBT is low. The p-type impurity concentration of the resistance reduction region 46 is lower than the p-type impurity concentration of the cell contact region 45. The p-type impurity concentration of the resistance reduction region 46 is 1×10 19 cm -3 It is preferable that:

[0122] From the viewpoint of facilitating the formation of the resistance reduction region 46, it is preferable to provide the first dummy trench 32 in contact with the resistance reduction region 46. This allows the width of the resistance reduction region 46 in the second direction to be increased, making it easier to form the resistance reduction region 46.

[0123] From the viewpoint of improving the latch-up resistance, it is preferable to provide the first dummy trench 32. In particular, the first conductive layer 18 in the first dummy trench 32 is electrically connected to the upper electrode 12, so that holes can easily flow along the side surface of the first dummy trench 32 during the turn-off operation of the IGBT. This promotes the discharge of holes from the resistance reduction region 46 to the upper electrode 12. This improves the latch-up resistance of the RC-IGBT 100.

[0124] From the viewpoint of improving the latch-up resistance, it is preferable that the width in the first direction of the emitter region 44 is small. From the viewpoint of improving the latch-up resistance, it is preferable that the width in the first direction of the emitter region 44 on the first face F1 is smaller than the width in the first direction of the cell contact region 45 on the first face F1. In addition, by adjusting the width of the emitter region 44 and the width of the cell contact region 45, the mutual conductance can be adjusted, and the short-circuit resistance can be improved.

[0125] From the viewpoint of promoting the discharge of electrons to the upper electrode 12 during steady-state operation of the diode and suppressing the injection of holes into the drift region 42, it is preferable that the base region 43 contacts the side surface of the first trench contact portion 12x.

[0126] 1 shows an example in which there is one transistor region 101 and one diode region 102, but each of the transistor region 101 and the diode region 102 may be divided into multiple regions and arranged alternately. By dividing the regions into multiple regions, the heat generated by the IGBTs and the diodes can be made uniform.

[0127] (First Modification) The semiconductor device of the first modified example of the first embodiment differs from the semiconductor device of the first embodiment in that the diode region further includes a tenth semiconductor region between the second semiconductor region and the eighth semiconductor region.

[0128] Fig. 11 is a schematic cross-sectional view of a part of a semiconductor device according to a first modified example of the first embodiment. Fig. 11 is a cross-section taken along line CC' in Fig. 12. Fig. 11 is a view corresponding to Fig. 2 of the first embodiment.

[0129] Fig. 12 is a schematic top view of a part of a semiconductor device according to a first modification of the first embodiment. Fig. 12 is a top view on a first face F1. Fig. 12 is a view corresponding to Fig. 3 of the first embodiment.

[0130] Fig. 13 is a schematic cross-sectional view of a part of a semiconductor device according to a first modified example of the first embodiment. Fig. 13 is a cross-sectional view taken along line DD' in Fig. 12. Fig. 13 is a view corresponding to Fig. 4 of the first embodiment.

[0131] The semiconductor device according to the first modification of the first embodiment is an RC-IGBT 110. The RC-IGBT 110 differs from the RC-IGBT 100 of the first embodiment in that the diode region 102 includes a barrier region 47.

[0132] The barrier region 47 is an n-type semiconductor region and is provided between the drift region 42 and the anode region 52.

[0133] The barrier region 47 contains an n-type impurity. The n-type impurity is, for example, phosphorus (P) or arsenic (As). The n-type impurity concentration of the barrier region 47 is, for example, 5×10 15 cm -3 5×10 or more 18 cm -3 The following is the result.

[0134] The barrier region 47 has a function of suppressing the injection of holes into the drift region 42 when the diode is in the on state. Therefore, the amount of holes to be discharged to the upper electrode 12 during the turn-off operation of the diode is reduced. The amount of holes to be discharged from the upper electrode 12 is reduced, and the reverse recovery current of the diode is reduced. When the reverse recovery current of the diode is reduced, the switching loss of the diode is reduced.

[0135] Therefore, according to the RC-IGBT 110 of the first modified example of the first embodiment, the switching loss is further reduced.

[0136] (Second Modification) The semiconductor device of the second modified example of the first embodiment differs from the semiconductor device of the first embodiment in that the diode region further includes an eleventh semiconductor region of a first conductivity type having a first conductivity type impurity concentration higher than the first conductivity type impurity concentration of the eighth semiconductor region, the first electrode of the diode region includes a second portion, a side surface of the second portion contacts the eighth semiconductor region, a bottom surface of the second portion contacts the eleventh semiconductor region, and the eleventh semiconductor region is provided between the eighth semiconductor region and the second portion.

[0137] Fig. 14 is a schematic cross-sectional view of a part of a semiconductor device according to a second modified example of the first embodiment. Fig. 14 is a cross-sectional view taken along line EE' of Fig. 15. Fig. 14 is a view corresponding to Fig. 2 of the first embodiment.

[0138] Fig. 15 is a schematic top view of a part of a semiconductor device according to a second modified example of the first embodiment. Fig. 15 is a top view on a first face F1. Fig. 15 is a view corresponding to Fig. 3 of the first embodiment.

[0139] Fig. 16 is a schematic cross-sectional view of a part of a semiconductor device according to a second modified example of the first embodiment. Fig. 16 is a cross-sectional view taken along line FF' in Fig. 15. Fig. 16 is a view corresponding to Fig. 4 of the first embodiment.

[0140] The semiconductor device of the second modified example of the first embodiment is an RC-IGBT 120. The RC-IGBT 120 differs from the RC-IGBT 100 of the first embodiment in that the diode region 102 includes a trench bottom p-type region 56 (an eleventh semiconductor region) and that the upper electrode 12 of the diode region 102 has a second trench contact portion 12y (a second portion).

[0141] The second trench contact portion 12y is formed in a trench provided in the semiconductor layer 10. The second trench contact portion 12y extends in the first direction.

[0142] A bottom surface of the second trench contact portion 12y contacts the trench bottom p-type region 56. A side surface of the second trench contact portion 12y contacts the anode region 52. The second trench contact portion 12y is electrically connected to the trench bottom p-type region 56 and the anode region 52.

[0143] The trench bottom p-type region 56 is a p-type semiconductor region. The trench bottom p-type region 56 is provided between the anode region 52 and the second trench contact portion 12y. The trench bottom p-type region 56 contacts the second trench contact portion 12y.

[0144] The p-type impurity concentration of the trench bottom p-type region 56 is higher than the p-type impurity concentration of the anode region 52. The contact between the second trench contact portion 12y and the trench bottom p-type region 56 is, for example, an ohmic contact.

[0145] According to the RC-IGBT 120 of the second modified example of the first embodiment, for example, the first trench contact portion 12x in the transistor region 101 and the second trench contact portion 12y in the diode region 102 can be manufactured in a common process.

[0146] As described above, according to the first embodiment and its modifications, a semiconductor device capable of achieving both reduced switching loss and improved latch-up resistance can be provided.

[0147] Second embodiment The semiconductor device of the second embodiment differs from the semiconductor device of the first embodiment in that the transistor region does not include a second trench. In the following, some of the contents common to the first embodiment may be omitted.

[0148] The semiconductor device of the second embodiment is an RC-IGBT200 in which an IGBT and a free wheel diode are formed on the same semiconductor chip. The RC-IGBT200 has a trench-gate type IGBT with a gate electrode in a trench formed in a semiconductor layer. Below, an example will be described in which the first conductivity type is p-type and the second conductivity type is n-type.

[0149] Fig. 17 is a schematic cross-sectional view of a part of the semiconductor device of the second embodiment. Fig. 17 is a cross-sectional view taken along line GG' of Fig. 18. Fig. 17 is a view corresponding to Fig. 2 of the first embodiment.

[0150] Fig. 18 is a schematic top view of a part of the semiconductor device of the second embodiment, taken along the first face F1, and corresponding to Fig. 3 of the first embodiment.

[0151] Fig. 19 is a schematic cross-sectional view of a part of the semiconductor device of the second embodiment. Fig. 19 is a cross-sectional view taken along line HH' of Fig. 18. Fig. 19 is a view corresponding to Fig. 4 of the first embodiment.

[0152] The semiconductor device of the second embodiment is an RC-IGBT 200. The RC-IGBT 200 has a transistor region 101 and a diode region .

[0153] The transistor region 101 operates as an IGBT, and the diode region 102 operates as a freewheeling diode.

[0154] The RC-IGBT 200 of the second embodiment includes a semiconductor layer 10, an upper electrode 12 (first electrode), a lower electrode 14 (second electrode), a gate electrode 16, a second conductive layer 20, a gate insulating film 22, a second insulating film 26, an interlayer insulating layer 28, and a gate electrode pad 103.

[0155] The upper electrode 12 has a first trench contact portion 12x (first portion).

[0156] Provided in the semiconductor layer 10 are a gate trench 31 (first trench), a second dummy trench 33 (third trench), a collector region 41 (first semiconductor region), a drift region 42 (second semiconductor region), a base region 43 (third semiconductor region), an emitter region 44 (fourth semiconductor region), a cell contact region 45 (fifth semiconductor region), a resistance reduction region 46 (sixth semiconductor region), a barrier region 47 (tenth semiconductor region), a cathode region 51 (seventh semiconductor region), an anode region 52 (eighth semiconductor region), and a diode contact region 53 (ninth semiconductor region).

[0157] The semiconductor device RC-IGBT 200 of the second embodiment can achieve both reduced switching loss and improved latch-up resistance, similar to the RC-IGBT 100 of the first embodiment.

[0158] Furthermore, the RC-IGBT200 of the semiconductor device of the second embodiment has a higher occupancy rate of the gate trench 31 in the transistor region 101 than the RC-IGBT100 of the first embodiment. Therefore, for example, the RC-IGBT200 having a lower on-resistance and a higher on-current than the RC-IGBT100 of the first embodiment can be realized.

[0159] As described above, according to the second embodiment, it is possible to provide a semiconductor device that can achieve both reduced switching loss and improved latch-up resistance.

[0160] In the first and second embodiments, the semiconductor layer is described as being single crystal silicon, but the semiconductor layer is not limited to being single crystal silicon. For example, the semiconductor layer may be made of other single crystal semiconductors, such as single crystal silicon carbide.

[0161] In the first and second embodiments, the first conductivity type is p-type and the second conductivity type is n-type as an example, but it is also possible for the first conductivity type to be n-type and the second conductivity type to be p-type.

[0162] In the first and second embodiments, the case where the second dummy trench 33 is provided in the diode region 102 has been described as an example. However, it is also possible not to provide the second dummy trench 33 in the diode region 102.

[0163] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. For example, components of one embodiment may be replaced or changed with components of another embodiment. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0164] 10 Semiconductor layer 12 Upper electrode (first electrode) 12x First Trench Contact Part (First Part) 12y second trench contact portion (second portion) 14 Lower electrode (second electrode) 16 Gate electrode 18 First conductive layer 20 Second conductive layer 22 Gate insulating film 24 First insulating film 26 Second insulating film 28 Interlayer insulation layer 31 Gate trench (first trench) 32 First dummy trench (second trench) 33 Second dummy trench (third trench) 41 Collector region (first semiconductor region) 42 drift region (second semiconductor region) 43 Base region (third semiconductor region) 44 Emitter region (fourth semiconductor region) 45 cell contact region (fifth semiconductor region) 46 Resistance reduction region (6th semiconductor region) 47 Barrier region (10th semiconductor region) 51 Cathode region (seventh semiconductor region) 52 anode region (eighth semiconductor region) 53 Diode contact region (9th semiconductor region) 56 Trench bottom p-type region (11th semiconductor region) 100 RC-IGBT (semiconductor device) 101 Transistor Area 102 Diode Region 103 Gate electrode pad 110 RC-IGBT (semiconductor device) 120 RC-IGBT (semiconductor device) 200 RC-IGBT (semiconductor device) F1 First Side F2 Second Face

Claims

1. a semiconductor layer having a first surface and a second surface opposite to the first surface; a first semiconductor region of a first conductivity type provided in the semiconductor layer; a second semiconductor region of a second conductivity type provided in the semiconductor layer and between the first semiconductor region and the first surface; a third semiconductor region of a first conductivity type provided in the semiconductor layer and between the second semiconductor region and the first surface; a fourth semiconductor region of a second conductivity type and a fifth semiconductor region of a first conductivity type provided in the semiconductor layer, between the third semiconductor region and the first surface, and alternately arranged in a first direction parallel to the first surface; a sixth semiconductor region of a first conductivity type provided between the third semiconductor region and the fourth semiconductor region, the sixth semiconductor region having a first conductivity type impurity concentration higher than a first conductivity type impurity concentration of the third semiconductor region and a first conductivity type impurity concentration lower than a first conductivity type impurity concentration of the fifth semiconductor region; a first trench provided on the first surface side in the semiconductor layer, extending in the first direction, repeatedly arranged in a second direction parallel to the first surface and perpendicular to the first direction, contacting the second semiconductor region, the third semiconductor region, the fourth semiconductor region, and the fifth semiconductor region, and separated from the sixth semiconductor region; a gate electrode disposed in the first trench; a gate insulating film provided between the gate electrode and the third semiconductor region; a first electrode provided on the first surface side of the semiconductor layer, the first electrode having a first portion, a bottom surface of the first portion being in contact with the third semiconductor region, and a side surface of the first portion being in contact with the fourth semiconductor region, the fifth semiconductor region, and the sixth semiconductor region; a second electrode provided on the second surface side of the semiconductor layer and in contact with the first semiconductor region; a transistor region including The semiconductor layer; the second semiconductor region; a seventh semiconductor region of a second conductivity type provided in the semiconductor layer, between the second semiconductor region and the second surface, and having a second conductivity type impurity concentration higher than a second conductivity type impurity concentration of the second semiconductor region; an eighth semiconductor region of a first conductivity type provided in the semiconductor layer and between the second semiconductor region and the first surface; the first electrode electrically connected to the eighth semiconductor region; the second electrode in contact with the seventh semiconductor region; a diode region including A semiconductor device comprising:

2. 2. The semiconductor device according to claim 1, wherein said sixth semiconductor region extends in said first direction, and said fifth semiconductor region is provided between said sixth semiconductor region and said first surface.

3. The semiconductor device according to claim 1 , wherein said sixth semiconductor region is provided between said first trench and said first portion.

4. The transistor region is a second trench provided on the first surface side in the semiconductor layer, between two adjacent first trenches, extending in the first direction, and in contact with the second semiconductor region, the third semiconductor region, the fourth semiconductor region, the fifth semiconductor region, and the sixth semiconductor region; a first conductive layer disposed in the second trench; 2. The semiconductor device according to claim 1, further comprising a first insulating film provided between said first conductive layer and said third semiconductor region.

5. 5. The semiconductor device according to claim 4, wherein said first conductive layer is electrically connected to said first electrode.

6. 2. The semiconductor device according to claim 1, wherein the width of said fourth semiconductor region in said first direction is smaller than the width of said fifth semiconductor region in said first direction.

7. 2. The semiconductor device according to claim 1, wherein the diode region is provided in the semiconductor layer, and further includes a ninth semiconductor region of a first conductivity type provided between the eighth semiconductor region and the first surface, the ninth semiconductor region having a first conductivity type impurity concentration higher than a first conductivity type impurity concentration of the eighth semiconductor region, and the first electrode is in contact with the ninth semiconductor region.

8. 2. The semiconductor device according to claim 1, wherein the transistor region further includes a tenth semiconductor region of the second conductivity type provided between the second semiconductor region and the third semiconductor region and having a higher second conductivity type impurity concentration than the second semiconductor region.

9. 9. The semiconductor device according to claim 8, wherein said diode region further includes said tenth semiconductor region between said second semiconductor region and said eighth semiconductor region.

10. the diode region further includes an eleventh semiconductor region of a first conductivity type having a first conductivity type impurity concentration higher than a first conductivity type impurity concentration of the eighth semiconductor region, the first electrode of the diode region includes a second portion, a side surface of the second portion contacts the eighth semiconductor region, and a bottom surface of the second portion contacts the eleventh semiconductor region; The semiconductor device according to claim 1 , wherein said eleventh semiconductor region is provided between said eighth semiconductor region and said second portion.

11. The diode region is a third trench provided on the first surface side in the semiconductor layer, extending in the first direction, and in contact with the second semiconductor region and the eighth semiconductor region; a second conductive layer disposed in the third trench; 2. The semiconductor device according to claim 1, further comprising: a second insulating film provided between said second conductive layer and said eighth semiconductor region.

12. The semiconductor device according to claim 11 , wherein the second conductive layer is electrically connected to the first electrode.

13. 2. The semiconductor device according to claim 1, wherein a side surface of said first portion contacts said third semiconductor region.

14. 2. The semiconductor device according to claim 1, wherein a depth of said sixth semiconductor region is shallower than a depth of said first portion.

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