Semiconductor device

Abstract

To improve durability of a semiconductor device.SOLUTION: A semiconductor device 100 comprises: a semiconductor element 2 that is mounted onto an insulation substrate 1, and includes an electrode 21 onto a front surface 2a; a bonding wire 3 that is bonded to the electrode 21, and electrically connects the semiconductor element 2; and a first resin material 4 that coats a bonding part 31 of the electrode 21 and the bonding wire 3. The bonding part 31 contains a non-bonding region 32 where the electrode 21 and the bonding wire 3 are not bonded.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The embodiments relate to a semiconductor device. [Background technology]

[0002] A semiconductor device has been developed that has an insulating substrate having a conductor pattern, a semiconductor element having a front surface on which electrodes are provided and a back surface bonded to the conductor pattern, and a bonding wire bonded to the electrode. In such a semiconductor device, there is room for improvement in terms of durability, as the bonding portion between the electrode and the bonding wire breaks when the device is used repeatedly. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 8-115941 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the embodiment is to improve the durability of a semiconductor device. [Means for solving the problem]

[0005] The semiconductor device according to the embodiment includes a semiconductor element mounted on an insulating substrate and having electrodes on its surface, a bonding wire bonded to the electrode and electrically connecting the semiconductor element, and a first resin material covering a bonded portion between the electrode and the bonding wire. The bonded portion includes a non-bonded region where the electrode and the bonding wire are not bonded. [Brief description of the drawings]

[0006] [Figure 1] 1 is a cross-sectional view of a main part of a semiconductor device 100 according to an embodiment. [Diagram 2] 1 is an enlarged cross-sectional view of a semiconductor device 100. FIG. [Diagram 3] FIG. 2 is an enlarged plan view of the semiconductor device 100. [Figure 4] 2A to 2C are diagrams illustrating a manufacturing method of the semiconductor device 100. [Diagram 5] 2 of a semiconductor device R according to a reference example. FIG. [Figure 6] 3 and illustrates a semiconductor device 100 according to a first modified example. FIG. [Figure 7] 2 and illustrates a semiconductor device 100 according to a second modified example. FIG. [Figure 8] 2 and illustrates a semiconductor device 100 according to a third modified example. FIG. [Figure 9] FIG. 13 is a diagram showing the analysis results of a creep analysis. [Figure 10] FIG. 13 is a diagram showing the analysis results of a creep analysis. [Figure 11] FIG. 13 is a diagram showing an analytical model for estimating the width of an inelastic region. [Figure 12] FIG. 13 is a diagram showing the results of an analysis for estimating the width of the inelastic region. [Figure 13] FIG. 13 is a diagram showing the results of an analysis for estimating the width of the inelastic region. [Figure 14] FIG. 13 is a diagram showing the results of an analysis for estimating the width of the inelastic region. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] <1. Embodiment> (1.1. Semiconductor Device 100) Hereinafter, an embodiment will be described. In the figures shown below, directions may be indicated by the X-axis, Y-axis, and Z-axis shown in Fig. 1 and Fig. 3. Specifically, the X-axis direction along the X-axis indicates the extension direction of the bonding wire 3 in Fig. 1. The Y-axis direction along the Y-axis indicates the direction perpendicular to the X-axis direction on a horizontal plane. The Z-axis direction along the Z-axis indicates the vertical direction. Also, the positive direction on the Z-axis is upward, and the negative direction on the Z-axis is downward.

[0008] Fig. 1 is a cross-sectional view of a main part of a semiconductor device according to an embodiment. As shown in Fig. 1, the semiconductor device 100 mainly includes an insulating substrate 1, a semiconductor element 2, and a bonding wire 3. The semiconductor device 100 may further include a base plate on which the insulating substrate 1 is placed, a case for accommodating the insulating substrate 1, the semiconductor element 2, and the bonding wire 3, and a heat sink for dissipating heat from the semiconductor element 2.

[0009] The insulating substrate 1 has a front surface 1a and a back surface 1b. The back surface 1b is the surface opposite to the front surface 1a. The insulating substrate 1 is made of, for example, alumina (Al2O3), aluminum nitride (AlN), or the like.

[0010] A conductor pattern 12 is provided on the insulating substrate 1. The conductor pattern 12 is made of, for example, copper (Cu).

[0011] The semiconductor element 2 has a front surface 2a and a back surface 2b. The back surface 2b is the surface opposite to the front surface 2a. As an example, the semiconductor element 2 may be a power semiconductor element having a vertical structure in which a current flows from the front surface 2a side to the back surface 2b side. The semiconductor element 2 may be a switching element such as an IGBT (Insulated Gate Bipolar Transistor) or a vertical MOSFET (Metal Oxide Semiconductor Field Effect Transistor), or a rectifying element such as a Schottky barrier diode.

[0012] As an example, the semiconductor element 2 is formed using single crystal silicon (Si). However, the semiconductor material constituting the semiconductor element 2 is not limited to this. As another example, the semiconductor element 2 may be formed using a semiconductor material having a wide band gap, such as silicon carbide (SiC) or silicon nitride (GaN).

[0013] An electrode 21 is provided on the surface 2a of the semiconductor element 2. As an example, the electrode 21 is made of an Al alloy containing Al or Si. The electrode 21 may further have a coating layer. The coating layer may be made of, for example, Ni, Au, or a structure in which these are laminated.

[0014] The bonding wire 3 is a metal wire that electrically connects the semiconductor element 2 and the lead frame 11. For example, Au, Al, Cu, etc. are used for the bonding wire 3. The electrode 21 has a joint 31 that is joined to the bonding wire 3. As an example, the joint 31 is formed into a rectangular shape in a plan view by ultrasonic bonding.

[0015] In the bonding portion 31, the bonding wire 3 and the electrode 21 are bonded along the extending direction of the bonding wire 3 (hereinafter also simply referred to as the extending direction). The bonding portion 31 includes a non-bonded region 32 where the electrode 21 and the bonding wire 3 are not bonded. In the example shown in Figures 2 and 3, the non-bonded region 32 is formed by providing a recess 33 on the upper surface 21a of the electrode 21.

[0016] Specifically, as shown in Fig. 2, the recess 33 is formed in a groove shape having a rectangular cross section extending in the Y-axis direction, and is provided in the center of the joining portion 31 in the extension direction. As shown in Fig. 3, the recess 33 is formed in a rectangular shape in a plan view. In this manner, a non-jointed region 32 is formed in the joining portion 31 by the opening 34 of the recess 33 in the upper surface 21a.

[0017] The ratio of the length W2 of the recess 33 to the length W1 of the joint 31 in the X-axis direction (i.e., the extension direction of the bonding wire 3) is preferably 6% or more, and more preferably 10% or more. Also, it is preferable that the length D2 of the recess 33 is longer than the length D1 of the joint 31 in the Y-axis direction. In this way, an area of ​​the opening 34 that is not covered by the bonding wire 3 is generated, and it becomes easy to fill the first resin material 4 into the inside of the recess 33.

[0018] The joint portion 31 is covered with a first resin material 4. In the example shown in Figs. 1 to 3, the bonding wire 3 around the joint portion 31 is covered with the first resin material 4. However, the first resin material 4 does not need to cover the entire bonding wire 3 around the joint portion 31. As an example, the first resin material 4 may cover the gap between the bonding wire 3 and the electrode 21 at both ends of the joint portion 31 in the extension direction without covering the bonding wire 3 above the joint portion 31.

[0019] The first resin material 4 functions as a reinforcing material that reinforces the bond at the bonded portion 31. The Young's modulus of the first resin material 4 is preferably 1000 MPa or more. An example of a material used for the first resin material 4 is polyimide.

[0020] As shown in FIG. 1, the second resin material 6 is filled inside the case of the semiconductor device 100. As a result, the second resin material 6 seals the insulating substrate 1, the semiconductor element 2, and the bonding wires 3. The second resin material 6 has insulating properties. The second resin material 6 preferably has a lower Young's modulus than the first resin material 4. This makes it possible to prevent the second resin material 6 from peeling off from the surface of the semiconductor element 2 due to the difference in thermal expansion coefficient between the second resin material 6 and the semiconductor element 2. More specifically, the elastic modulus of the second resin material 6 is preferably 0.1 MPa or less. An example of a material used for the second resin material is silicone gel.

[0021] (1.2. Method for Manufacturing Semiconductor Device 100) The following describes the manufacturing process of the semiconductor device 100 according to the embodiment. The manufacturing process of the semiconductor device 100 includes a recess forming step, a bonding step, a covering step, and a sealing step.

[0022] First, a recess forming step is performed. As shown in Fig. 4(a), in the recess forming step, a recess 33 is formed. The recess 33 is formed, for example, by irradiating the electrode 21 with a laser beam L from a laser beam irradiation source S. The laser beam L is irradiated onto a portion to which the bonding wire 3 is joined to become a joint 31. The laser beam irradiation source S is, for example, a carbon dioxide gas laser processing machine.

[0023] 4(b), in a bonding step, the bonding wire 3 is bonded to the electrode 21 of the semiconductor element 2. For example, the bonding wire 3 containing Al and the electrode 21 containing an Al alloy containing Si are bonded at a bonding portion 31 of the electrode 21 by ultrasonic bonding.

[0024] 4(c), in a covering step, a liquid first resin material 4 is supplied to the joint 31. As an example, when the first resin material 4 is a resin, a mixture of a base agent and a curing agent may be dripped near the joint 31.

[0025] In the covering step, the supplied liquid first resin material 4 hardens. As an example, when the first resin material 4 is a resin, the liquid first resin material 4 is held at room temperature, whereby the first resin material 4 hardens. As another example, when the first resin material 4 is a solder alloy, the liquid first resin material 4 is cooled, whereby the first resin material 4 hardens. As a result, the joint portion 31 is covered with the first resin material 4.

[0026] Next, in the sealing process, the semiconductor element 2, the bonding wires 3, and the first resin material 4 are housed in the case of the semiconductor device 100. Then, a liquid second resin material 6 is supplied into the inside of the case. By hardening this liquid second resin material 6, the insulating substrate 1, the semiconductor element 2, and the bonding wires 3 are sealed with the second resin material 6, as shown in FIG.

[0027] (1.3.Summary) According to the embodiment described above, the semiconductor device 100 includes a semiconductor element 2 mounted on an insulating substrate 1 and having an electrode 21 on a surface 2a, a bonding wire 3 bonded to the electrode 21 and electrically connecting the semiconductor element 2, and a first resin material 4 covering a bonding portion 31 between the electrode 21 and the bonding wire 3. The bonding portion 31 includes a non-bonding region 32 where the electrode 21 and the bonding wire 3 are not bonded. With this configuration, it is possible to suppress thermal stress caused by the difference in thermal expansion coefficient between the bonding wire 3 and the electrode 21 when electricity is repeatedly applied to the bonding wire 3. This makes it possible to suppress the occurrence of a fracture inside the bonding wire 3 near the bonding portion 31, thereby improving the durability of the semiconductor device 100.

[0028] More specifically, in the semiconductor device R as a reference example shown in FIG. 5, for example, thermal stress occurs over a distance T1 between both ends of the bonding portion 31 in the extension direction. On the other hand, as shown in FIG. 2, in the semiconductor device 100 according to the embodiment, a recess 33 is provided in the center of the extension direction of the bonding portion 31, and a non-bonding region 32 is formed accordingly. Therefore, the region where thermal stress may occur is divided by the non-bonding region 32, and thermal stress occurs in a distance T2 from the end of the bonding portion 31 to the end of the non-bonding region 32 on both sides of the recess 33. Since the distance T2 is shorter than the distance T1, the amount of deformation due to thermal expansion occurring in the semiconductor device 100 is smaller than that of the semiconductor device R, and the thermal stress generated is also smaller. In this way, in the semiconductor device 100 according to the present embodiment, since the bonding portion 31 includes the non-bonding region 32, it is possible to disperse thermal stress that may occur inside the bonding wire 3.

[0029] (1.4. Modifications) With reference to Figs. 6 to 8, a semiconductor device 100 according to a modification of this embodiment will be described, focusing on differences from the above embodiment. Fig. 6 is an enlarged plan view of the semiconductor device 100 according to the first modification. In the first modification, the semiconductor device 100 is different from the above embodiment in that a plurality of recesses 33 are provided on the upper surface 21a of the electrode 21. In the example shown in Fig. 6, two recesses 33 are provided in parallel along the extension direction on the upper surface 21a of the electrode 21. With this configuration, it becomes possible to distribute the thermal stress generated by the passage of electricity through the bonding wire 3 more finely along the extension direction. Note that the example shown in Fig. 6 is just one example, and the number of recesses 33 provided on the upper surface 21a of the electrode 21 may be three or more.

[0030] Fig. 7 is an enlarged plan view of a semiconductor device 100 according to Modification 2. In Modification 2, the shape of a recess 33 provided on an upper surface 21a of an electrode 21 is different from that of the above embodiment. In the example shown in Fig. 7, a recess 33 having a bottom surface with a sawtooth cross section is formed on an upper surface 21a of an electrode 21. With this configuration, it is possible to achieve the same effects as the above embodiment.

[0031] FIG. 8 is an enlarged plan view of the semiconductor device 100 according to the third modification. The third modification is different from the above embodiment in that a shielding layer 35 is provided instead of a recess 33 being formed on the upper surface 21a of the electrode 21. In the example shown in FIG. 8, a shielding layer 35 containing a third resin material is laminated on the upper surface 21a of the electrode 21. As a result, a non-bonding region 32 where the electrode 21 and the bonding wire 3 cannot be ultrasonically bonded is formed in a part of the bonding portion 31. The third resin material may be, for example, an insulating material, and specifically, polyimide, polyimide silicone, polyamideimide, epoxy resin, phenolic resin, or a resin containing a filler that is a conductive material, or the like. Note that, for example, metal or ceramics may be used as the filler. By adding a filler, it is possible to improve thermal conductivity and electrical conductivity. Note that the shielding layer 35 is not limited to a resin material, and may be, for example, an Ag sintered body or a solder material, as long as it is a material that shields the ultrasonic bonding between the electrode 21 and the bonding wire 3. With this configuration, it is possible to achieve the same effects as the above embodiment.

[0032] <2. Examples> An example of the semiconductor device 100 according to this embodiment will be described below. As an example, creep analysis and estimation of the width of the non-bonded region will be described below.

[0033] (2.1. Creep analysis) The results of the creep analysis as an example will be described with reference to FIGS. In the creep analysis, the inelastic strain energy density range and life ratio were calculated for the two examples and three comparative examples shown below. Semiconductor device 100A according to the embodiment (width of non-bonding region 32: 200 μm) Semiconductor device 100B according to the embodiment (width of non-bonding region 32: 100 μm) Semiconductor device 200A according to a first comparative example (without non-bonding region 32 / without first resin material 4) Semiconductor device 200B according to a second comparative example (without non-bonding region 32) Semiconductor device 200C according to a third comparative example (width of non-bonding region 32: 200 μm / no first resin material 4)

[0034] As a thermal condition, the current flowing through the semiconductor element 2 was assumed to be ON for 2 seconds and OFF for 8 seconds, and the temperature was assumed to change from 40°C to 140°C. As a result, the heat density given to the semiconductor element 2 and the bonding wires 3 was 6.3 (W / mm 3 ), and bonding wire 3 is 0.45 (W / mm 3 ) was.

[0035] The mesh model was divided into mesh elements of 10 μm × 10 μm. It was assumed that in the non-bonding region 32 of the bonding portion 31, the mesh elements of the electrode 21 and the mesh elements of the bonding wire were not adjacent to each other. The inelastic strain energy density range was obtained from both ends of the bonding portion 31 in the X-axis direction. The inelastic strain energy density range means the inelastic strain energy generated per unit amount.

[0036] 9 is a diagram showing the calculation results by creep analysis. As shown in FIG. 9, the semiconductor devices 100A and 100B according to the embodiment have a higher inelastic strain energy density range (J / m 3 ) could be reduced by two orders of magnitude. That is, it can be seen from this example that the semiconductor devices 100A and 100B according to the embodiment have the above-mentioned configuration, and therefore it is possible to suppress the energy of the thermal strain generated inside the bonding wire 3.

[0037] In addition, the semiconductor devices 100A and 100B according to the embodiment have a calculated life ratio of about 5000 times that of the first comparative example. That is, it can be seen from this example that the semiconductor devices 100A and 100B can have high durability by suppressing the energy of thermal strain generated inside the bonding wire 3.

[0038] 10 is a diagram showing the distribution of thermal stress generated in the bonding wire 3 in a creep analysis. In Fig. 10(a) and Fig. 10(b), the areas in the bonding wire 3 where the thermal stress is stronger are shown in darker gray.

[0039] As shown in Fig. 10(a), in the semiconductor device 200A according to the first comparative example, strong stress was generated at both ends of the bonding portion 31 in the extension direction. On the other hand, as shown in Fig. 10(b), in the semiconductor device 100B according to the embodiment, strong thermal stress was not generated at both ends of the bonding portion 31 in the extension direction. That is, it can be read from this example that in the semiconductor device 100B, the generation of thermal stress due to the difference in thermal expansion coefficient between the bonding wire 3 and the electrode 21 can be suppressed.

[0040] (2.2. Estimation of the Width of the Non-Bonded Region 32) 11 to 14, the results of estimating the width of the non-bonded region 32 as an example will be described. FIG. 11 shows a model M corresponding to the electrode 21 in the vicinity of the bonded portion 31. The model M includes an end portion 41, a bonding layer 42, a relaxation layer 43, and a lower layer 44. The end portion 41 corresponds to the end portion of the bonded portion 31. The bonding layer 42 corresponds to the bonded portion 31 of the electrode 21. The relaxation layer 43 corresponds to the recessed portion 33 provided in the electrode 21. The lower layer 44 corresponds to a layer below the recessed portion 33 of the electrode 21.

[0041] First, for the semiconductor device 200C according to the third comparative example not including the first resin material 4, a change F1 in the stress σ1 generated inside the model M when the Young's modulus E2 of the relaxation layer 43 was changed was calculated. Here, assuming that the pressure on the bonding layer 42 is P1 and the pressure on the lower layer is P2, the formula (3) was derived from the following conditional formulas (1) and (2).

[0042]

number

number

number

[0043] Next, for the semiconductor device 100A according to the embodiment including the first resin material, a change F2 in the stress σ1 generated inside the model M when the Young's modulus E2 of the relaxation layer 43 is changed was calculated. Here, the formula (5) was derived from the following conditional formula (4).

[0044]

number

number

[0045] From the above equations (3) and (5), the change F1 in stress σ1 in the semiconductor device 200C of the comparative example and the change F2 in stress σ1 in the semiconductor device 100A of the embodiment when the Young's modulus E2 of the relaxation layer 43 is changed were obtained as shown in Figure 12.

[0046] Next, in the creep analysis described above, the equivalent stress generated in the bonding portion 31 was estimated for the semiconductor device 200C according to the comparative example and the semiconductor device 100A according to the embodiment. Fig. 13(a) is a diagram showing the change over time in the equivalent stress generated in the bonding portion 31 of the semiconductor device 200C according to the comparative example in the creep analysis. From Fig. 13(a), it can be seen that an equivalent stress of up to about 60 MPa is generated while converging with time.

[0047] Fig. 13(b) is a diagram showing the time change of the equivalent stress generated in the bond 31 of the semiconductor device 100A according to the embodiment in the creep analysis. From Fig. 13(b), it can be seen that the equivalent stress of about 35 MPa at maximum is generated while converging with time.

[0048] 12 shows a line L1 (red line) indicating the Young's modulus E2 when the stress σ1 is 60 MPa in the semiconductor device 200C according to the comparative example, and a line L2 (blue line) indicating the Young's modulus E2 when the stress σ1 is 35 MPa in the semiconductor device 100A according to the embodiment. Here, in the above-mentioned creep analysis, since the bonding portion 31 of the semiconductor device 200C shows elastic plasticity and the bonding portion 31 of the semiconductor device 100A shows elasticity, it was estimated that the Young's modulus E2 of the relaxation layer 43 is between the lines L1 and L2. In this analysis, the Young's modulus E2 of the relaxation layer 43 was estimated to be 10000 MPa. At this time, it was estimated that a stress of at least 55 MPa was generated in the bonding portion 31 from the value of F2 at E2=10000 Pa in FIG. 12.

[0049] Next, from the above-mentioned formula (5), the change F3 in the stress σ1 generated inside the model M when the length l2 of the relaxation layer 43 is changed for the semiconductor device 100A according to the embodiment was calculated. F3 was obtained as shown in FIG. 14. For F3 in FIG. 14, the width of the relaxation layer 43 corresponding to the stress of 55 MPa estimated above was obtained to be 0.03 mm (= 30 μm). From this, it was obtained that the length in the extension direction of the recess 33 corresponding to the relaxation layer 43 is preferably 30 μm or more. In addition, since the length of the joint 31 along the extension direction of the bonding wire 3 in this analysis was 480 μm, it was estimated that the ratio of the length of the recess 33 to the length of the joint 31 along the extension direction is preferably 6% or more.

[0050] <3. Other embodiments> Although the embodiment of the present disclosure has been described above, the present disclosure is not limited to the above. For example, in the above embodiment, the recess 33 provided on the upper surface 21a of the electrode 21 is provided at the center in the extension direction of the joint 31, but the present disclosure is not limited to this embodiment, and the recess 33 may be provided at a position other than the center in the extension direction.

[0051] In the above embodiment, the length D2 of the recess 33 is longer than the length D1 of the joint 31 in the Y-axis direction, but this is not limited to the above. For example, the length D2 of the recess 33 in the Y-axis direction may be the same as the length D1 of the joint 31, or may be shorter than the length D1 of the joint 31.

[0052] The recess 33 may have a shape other than the above-mentioned form. Specifically, for example, the recess 33 may be formed by providing a plurality of dimple-shaped irregularities on the surface of the joint portion 31 of the electrode 21. In these other embodiments, the same effects as those of the above-mentioned embodiment can be achieved by applying the technical ideas of the present disclosure.

[0053] Although several embodiments of the present invention have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims.

[0054] The present invention includes the following aspects. (Appendix 1) A semiconductor element mounted on an insulating substrate and having electrodes on its surface; a bonding wire joined to the electrode and electrically connecting the semiconductor element; a first resin material that covers a joint between the electrode and the bonding wire; The bonding portion includes a non-bonded region where the electrode and the bonding wire are not bonded. (Appendix 2) a second resin material that encapsulates the semiconductor element, the bonding wires, and the first resin material; 2. The semiconductor device according to claim 1, wherein the second resin material has a Young's modulus lower than the Young's modulus of the first resin material. (Appendix 3) 3. The semiconductor device according to claim 1, wherein the first resin material has a Young's modulus of 1000 MPa or more. (Appendix 4) A recess is provided on the upper surface of the electrode, 4. The semiconductor device according to claim 1, wherein the non-bonding region is formed by an opening of the recess in the upper surface. (Appendix 5) At the bonding portion, the bonding wire and the electrode are bonded along an extending direction of the bonding wire, 5. The semiconductor device according to claim 4, wherein a ratio of a length of the recess to a length of the joint along the extension direction is 6% or more. (Appendix 6) At the bonding portion, the bonding wire and the electrode are bonded along an extending direction of the bonding wire, 5. The semiconductor device according to claim 4, wherein the recess is provided at a center of the joint in the extension direction. (Appendix 7) 7. The semiconductor device according to claim 1, wherein the non-bonding region has a shielding layer between the electrode and the bonding wire that prevents ultrasonic bonding. [Explanation of symbols]

[0055] 1: insulating substrate, 2: semiconductor element, 3: bonding wire, 4: first resin material, 6: second resin material, 11: lead frame, 12: conductor pattern, 21: electrode, 22: surface electrode, 24: laser light irradiation source, 31: bonding portion, 32: non-bonding region, 33: recess, 34: opening, 35: shielding layer, 100: semiconductor device

Claims

1. A semiconductor element mounted on an insulating substrate and having electrodes on its surface; a bonding wire joined to the electrode and electrically connecting the semiconductor element; a first resin material that covers a joint between the electrode and the bonding wire; The bonding portion includes a non-bonded region where the electrode and the bonding wire are not bonded.

2. a second resin material that encapsulates the semiconductor element, the bonding wires, and the first resin material; The semiconductor device according to claim 1 , wherein the second resin material has a Young's modulus lower than that of the first resin material.

3. The semiconductor device according to claim 1 , wherein the first resin material has a Young's modulus of 1000 MPa or more.

4. A recess is provided on the upper surface of the electrode, 4. The semiconductor device according to claim 1, wherein the non-bonding region is formed by an opening of the recess in the upper surface.

5. At the bonding portion, the bonding wire and the electrode are bonded along an extending direction of the bonding wire, The semiconductor device according to claim 4 , wherein a ratio of a length of the recess to a length of the joint along the extension direction is 6% or more.

6. At the bonding portion, the bonding wire and the electrode are bonded along an extending direction of the bonding wire, The semiconductor device according to claim 4 , wherein the recess is provided at a center of the joint in the extension direction.

7. 4. The semiconductor device according to claim 1, wherein the non-bonding region has a shielding layer between the electrode and the bonding wire that cannot be ultrasonically bonded.

Images