Doherty amplifier circuit

Abstract

To suppress deterioration of a quality of a high-frequency output signal.SOLUTION: A Doherty amplifier circuit comprises: a first bias circuit that includes a first bias output terminal that outputs a first bias current or a voltage based on a first bias control signal to a carrier amplifier, and a first monitor terminal that outputs a first monitor signal expressing a state of the first bias current or the voltage; a second bias circuit that includes a second bias output terminal that outputs a second bias current or a voltage based on a second bias control signal to a peak amplifier, and a second monitor terminal that outputs a second monitor signal expressing a state of the second bias current or the voltage; a first differential amplifier that outputs the first bias control signal on the basis of a difference between the first monitor signal and a constant voltage; a second differential amplifier that outputs an amplification signal on the basis of a difference between the second monitor signal and the first monitor signal; and an inverse amplifier that outputs the second bias control signal obtained by inverting and amplifying the amplification signal.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a Doherty amplifier circuit. [Background technology]

[0002] A Doherty amplifier circuit is known as a highly efficient power amplifier circuit. A Doherty amplifier circuit is generally configured in parallel with a carrier amplifier that operates regardless of the power level of an input signal, and a peak amplifier that is turned off when the power level of the input signal is low and turned on when the power level of the input signal is high. In this configuration, when the power level of a high-frequency input signal is high, the carrier amplifier operates while maintaining saturation at the saturated output power level. This allows the Doherty amplifier circuit to improve efficiency compared to a normal power amplifier circuit.

[0003] The following Patent Document 1 describes a technique for controlling the bias of a peak amplifier. The technique described in Patent Document 1 detects saturation of a carrier amplifier by a bias circuit of the carrier amplifier, and controls the bias circuit of the peak amplifier according to the detection signal. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] US Patent Application Publication No. 2016 / 0241209 Summary of the Invention [Problem to be solved by the invention]

[0005] In the technology described in Patent Document 1, it is difficult to sufficiently activate the peak amplifier with a slight increase in the drive level of the carrier amplifier. In other words, it is difficult to operate the peak amplifier with high sensitivity in the technology described in Patent Document 1. Therefore, it is difficult to maintain high quality of the high frequency output signal in the technology described in Patent Document 1.

[0006] The present disclosure has been made in consideration of the above, and has an object to suppress deterioration in the quality of a high-frequency output signal. [Means for solving the problem]

[0007] A Doherty amplifier circuit according to one aspect of the present disclosure includes a first bias circuit having a carrier amplifier that amplifies a first high frequency signal, a peak amplifier that amplifies a second high frequency signal, a first bias control terminal to which a first bias control signal is input, a first bias output terminal to which a first bias current or a first bias voltage based on the first bias control signal is output to the carrier amplifier, and a first monitor terminal to which a first monitor signal representing a state of the first bias current or the first bias voltage is output, a second bias control terminal to which a second bias control signal is input, a second bias output terminal to which a second bias current or a second bias voltage based on the second bias control signal is output to the peak amplifier, and a first differential amplifier having a first input terminal to which a constant voltage is input, a second input terminal electrically connected to the first monitor terminal, and an output terminal electrically connected to the first bias control terminal, and outputting a first bias control signal to the first bias control terminal based on a difference between the first monitor signal and the constant voltage; a second differential amplifier having a first input terminal electrically connected to the first monitor terminal and a second input terminal electrically connected to the second monitor terminal, and outputting an amplified signal from an output terminal based on the difference between the second monitor signal and the first monitor signal; and an inverting amplifier that inverts and amplifies the amplified signal and outputs a second bias control signal to the second bias control terminal. Effect of the Invention

[0008] According to the present disclosure, it is possible to suppress deterioration in the quality of a high frequency output signal. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a diagram illustrating a configuration of a Doherty amplifier circuit according to a first embodiment. [Diagram 2]FIG. 2 is a diagram illustrating a configuration of a Doherty amplifier circuit according to the second embodiment. [Diagram 3] FIG. 3 is a diagram illustrating a configuration of a Doherty amplifier circuit according to the third embodiment. [Figure 4] FIG. 4 is a diagram illustrating a configuration of a Doherty amplifier circuit according to the fourth embodiment. [Diagram 5] FIG. 5 is a diagram illustrating a configuration of a Doherty amplifier circuit according to the fifth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, the embodiments of the present disclosure will be described in detail with reference to the drawings. Note that the present invention is not limited to these embodiments. Each embodiment is an example, and it goes without saying that partial replacement or combination of the configurations shown in different embodiments is possible. From the second embodiment onwards, a description of matters common to the first embodiment will be omitted, and only the differences will be described. In particular, similar effects resulting from similar configurations will not be mentioned in each embodiment.

[0011] <First embodiment> (composition) 1 is a diagram showing a configuration of a Doherty amplifier circuit according to a first embodiment. The Doherty amplifier circuit 1 includes a first die 2 and a second die 3.

[0012] In the embodiment, the first die 2 is a GaAs (gallium arsenide) die and has a bipolar transistor formed thereon. The bipolar transistor is exemplified by a heterojunction bipolar transistor (HBT), but the present disclosure is not limited thereto. The second die 3 is a Si (silicon) die and has a field effect transistor (FET) formed thereon.

[0013] The transistor may be a multi-finger transistor in which a plurality of unit transistors are electrically connected in parallel. A unit transistor is the minimum configuration that constitutes a transistor.

[0014] The source of a FET corresponds to the emitter of a bipolar transistor, the gate corresponds to the base of the bipolar transistor, and the drain corresponds to the collector of the bipolar transistor.

[0015] The first die 2 has die terminals 2a to 2d. The second die 3 has die terminals 3a to 3d. Die terminals 2a and 3a are electrically connected. Die terminals 2b and 3b are electrically connected. Die terminals 2c and 3c are electrically connected. Die terminals 2d and 3d are electrically connected.

[0016] The second die 3 outputs a first bias control signal S11 from the die terminal 3a to the die terminal 2a of the first die 2. The first die 2 outputs a first monitor signal S13 from the die terminal 2b to the die terminal 3b of the second die 3. The second die 3 outputs a second bias control signal S21 from the die terminal 3c to the die terminal 2c of the first die 2. The first die 2 outputs a second monitor signal S23 from the die terminal 2d to the die terminal 3d of the second die 3. These signals will be described later.

[0017] In the embodiment, the first bias control signal S11, the first monitor signal S13, the second bias control signal S21, and the second monitor signal S23 are voltage signals, but the present disclosure is not limited to this.

[0018] The first die 2 includes a first bias circuit 11, a carrier amplifier 12, a DC blocking capacitor 13, a choke coil 14, a second bias circuit 21, a peak amplifier 22, a DC blocking capacitor 23, and a choke coil 24.

[0019] The first bias circuit 11 has a first bias control terminal 11a, a first bias output terminal 11b, and a first monitor terminal 11c.

[0020] The first bias control terminal 11a is electrically connected to the die terminal 2a, and a first bias control signal S11 is input from the second die 3.

[0021] The first bias output terminal 11b is electrically connected to the carrier amplifier 12. The first bias circuit 11 outputs a first bias current or a first bias voltage S12 based on a first bias control signal S11 from the first bias output terminal 11b to the carrier amplifier 12.

[0022] The first monitor terminal 11c is electrically connected to the die terminal 2b. The first bias circuit 11 outputs a first monitor signal S13 representing the state of the first bias current or the first bias voltage S12 to the second die 3 from the first monitor terminal 11c.

[0023] The first bias circuit 11 includes transistors 31 to 34 which are N-channel bipolar transistors, and resistors 35 to 37 .

[0024] The collector and base of the transistor 31 are electrically connected to the first bias control terminal 11a and the node N11. The emitter of the transistor 31 is electrically connected to the collector of the transistor 32. The emitter of the transistor 32 is electrically connected to a reference potential. The reference potential is exemplified by a ground potential, but the present disclosure is not limited thereto.

[0025] The transistor 31 and the transistor 32 generate a potential at the node N11 according to the first bias control signal S11.

[0026] The collector of the transistor 33 is electrically connected to the power supply potential Vcc. The base of the transistor 33 is electrically connected to the node N11. The emitter of the transistor 33 is electrically connected to one end of the resistor 35. The other end of the resistor 35 is electrically connected to the first bias output terminal 11b. In other words, the transistor 33 and the resistor 35 are connected in an emitter-follower manner. The transistor 33 outputs a first bias current or a first bias voltage S12 according to the potential of the node N11 from the first bias output terminal 11b to the carrier amplifier 12.

[0027] The transistor 33 corresponds to an example of a "first output transistor" of the present disclosure.

[0028] One end of the resistor 36 is electrically connected to the emitter of the transistor 33. The other end of the resistor 36 is electrically connected to the base of the transistor 32. The resistor 36 adjusts the potential level of the emitter potential of the transistor 33 and inputs it to the base of the transistor 32. As a result, the first bias circuit 11 has a first negative feedback path from the emitter of the transistor 33 to the resistor 36 to the base of the transistor 32 to the collector of the transistor 32 to the emitter of the transistor 31 to the base of the transistor 31 to the node N11 to the base of the transistor 33. In other words, the first bias circuit 11 has a first negative feedback path from the emitter to the base of the transistor 33.

[0029] The first bias circuit 11 has a first negative feedback path, and thereby increases the base potential of the transistor 33 so as to compensate for a drop in the base-emitter voltage of the transistor 33. Therefore, the first bias circuit 11 can stabilize the first bias current or the first bias voltage S12 and suppress a drop in the output of the carrier amplifier 12.

[0030] The first negative feedback path is composed of an NPN bipolar transistor. Since an NPN bipolar transistor has electrons as majority carriers, it can operate at a higher speed than a PNP bipolar transistor. Therefore, the first bias circuit 11 can respond quickly to fluctuations in the emitter potential of the transistor 33 by the first negative feedback path.

[0031] One end of the resistor 37 is electrically connected to the emitter of the transistor 33. The other end of the resistor 37 is electrically connected to the base of the transistor 34. The resistor 37 adjusts the potential level of the emitter potential of the transistor 33 and outputs it to the base of the transistor 34.

[0032] The emitter of the transistor 34 is electrically connected to the reference potential. The collector of the transistor 34 is electrically connected to the first monitor terminal 11c. The collector current of the transistor 34 flows through a path from the die terminal 3b to the die terminal 2b to the first monitor terminal 11c to the collector of the transistor 34. The collector current of the transistor 34 decreases when the emitter potential of the transistor 33 decreases, and increases when the emitter potential of the transistor 33 increases. The collector potential of the transistor 34 increases when the collector current of the transistor 34 decreases, and decreases when the collector current of the transistor 34 increases. The collector potential of the transistor 34 is the first monitor signal S13.

[0033] The carrier amplifier 12 includes a transistor 41 which is an N-channel bipolar transistor. The emitter of the transistor 41 is electrically connected to a reference potential. The collector of the transistor 41 is electrically connected to a power supply potential Vcc via a choke coil 14. The base of the transistor 41 is electrically connected to a first bias output terminal 11b, and a first bias current or a first bias voltage S12 is input to the base of the transistor 41. A high-frequency signal RFin1 is input to one end of a DC cut capacitor 13. The other end of the DC cut capacitor 13 is electrically connected to the base of the transistor 41. The DC cut capacitor 13 removes the DC component of the high-frequency signal RFin1 and outputs it to the base of the transistor 41. The transistor 41 amplifies the high-frequency signal RFin1 and outputs a high-frequency signal RFout1 from the collector.

[0034] The second bias circuit 21 has a second bias control terminal 21a, a second bias output terminal 21b, and a second monitor terminal 21c.

[0035] The second bias control terminal 21a is electrically connected to the die terminal 2c, and a second bias control signal S21 is input from the second die 3.

[0036] The second bias output terminal 21b is electrically connected to the peak amplifier 22. The second bias circuit 21 outputs a second bias current or a second bias voltage S22 based on a second bias control signal S21 to the peak amplifier 22 from the second bias output terminal 21b.

[0037] The second monitor terminal 21c is electrically connected to the die terminal 2d. The second bias circuit 21 outputs a second monitor signal S23 representing the state of the second bias current or the second bias voltage S22 to the second die 3 from the second monitor terminal 21c.

[0038] The second bias circuit 21 includes transistors 51 to 54 which are N-channel bipolar transistors, and resistors 55 to 57 .

[0039] The collector and the base of the transistor 51 are electrically connected to the second bias control terminal 21a and the node N21. The emitter of the transistor 51 is electrically connected to the collector of the transistor 52. The emitter of the transistor 52 is electrically connected to the reference potential.

[0040] The transistor 51 and the transistor 52 generate a potential at the node N21 according to the second bias control signal S21.

[0041] The collector of the transistor 53 is electrically connected to the power supply potential Vcc. The base of the transistor 53 is electrically connected to the node N21. The emitter of the transistor 53 is electrically connected to one end of the resistor 55. The other end of the resistor 55 is electrically connected to the second bias output terminal 21b. In other words, the transistor 53 and the resistor 55 are connected in an emitter-follower manner. The transistor 53 outputs a second bias current or a second bias voltage S22 according to the potential of the node N21 from the second bias output terminal 21b to the peak amplifier 22.

[0042] The transistor 53 corresponds to an example of a "second output transistor" of the present disclosure.

[0043] One end of the resistor 56 is electrically connected to the emitter of the transistor 53. The other end of the resistor 56 is electrically connected to the base of the transistor 52. The resistor 56 adjusts the potential level of the emitter potential of the transistor 53 and inputs it to the base of the transistor 52. As a result, the second bias circuit 21 has a second negative feedback path from the emitter of the transistor 53 to the resistor 56 to the base of the transistor 52 to the collector of the transistor 52 to the emitter of the transistor 51 to the base of the transistor 51 to the node N21 to the base of the transistor 53. In other words, the second bias circuit 21 has a second negative feedback path from the emitter to the base of the transistor 53.

[0044] The second bias circuit 21 has a second negative feedback path, and thereby increases the base potential of the transistor 33 so as to compensate for the drop in the base-emitter voltage of the transistor 53. Therefore, the second bias circuit 21 can stabilize the second bias current or the second bias voltage S22 and suppress a drop in the output of the peak amplifier 22.

[0045] The second negative feedback path is composed of an NPN bipolar transistor. Since an NPN bipolar transistor has electrons as majority carriers, it can operate at a higher speed than a PNP bipolar transistor. Therefore, the second bias circuit 21 can respond quickly to fluctuations in the emitter potential of the transistor 53 by the second negative feedback path.

[0046] One end of the resistor 57 is electrically connected to the emitter of the transistor 53. The other end of the resistor 57 is electrically connected to the base of the transistor 54. The resistor 57 adjusts the potential level of the emitter potential of the transistor 53 and outputs it to the base of the transistor 54.

[0047] The emitter of the transistor 54 is electrically connected to the reference potential. The collector of the transistor 54 is electrically connected to the second monitor terminal 21c. The collector current of the transistor 54 flows through a path from the die terminal 3d to the die terminal 2d to the second monitor terminal 21c to the collector of the transistor 54. The collector current of the transistor 54 increases when the emitter potential of the transistor 53 increases, and decreases when the emitter potential of the transistor 53 decreases. The collector potential of the transistor 54 increases when the collector current of the transistor 54 decreases, and decreases when the collector current of the transistor 54 increases. The collector potential of the transistor 54 is the second monitor signal S23.

[0048] The peak amplifier 22 includes a transistor 61 which is an N-channel bipolar transistor. The emitter of the transistor 61 is electrically connected to a reference potential. The collector of the transistor 61 is electrically connected to a power supply potential Vcc via a choke coil 24. The base of the transistor 61 is electrically connected to the second bias output terminal 21b, and a second bias current or a second bias voltage S22 is input to the base of the transistor 61. The high frequency signal RFin2 is input to one end of the DC cut capacitor 23. The other end of the DC cut capacitor 23 is electrically connected to the base of the transistor 61. The DC cut capacitor 23 removes the DC component of the high frequency signal RFin2 and outputs it to the base of the transistor 61. The transistor 61 amplifies the high frequency signal RFin2 and outputs a high frequency signal RFout2 from the collector.

[0049] The second die 3 includes a first differential amplifier 71, a second differential amplifier 72, a third differential amplifier 73, transistors 74 to 76 which are P-channel FETs, and a constant current source 77. The first differential amplifier 71, the second differential amplifier 72, and the third differential amplifier 73 are each composed of a FET.

[0050] The source of the transistor 74 is electrically connected to the power supply potential Vcc. The gate and drain of the transistor 74 are electrically connected to the node N31. That is, the transistor 74 is diode-connected. One end of the constant current source 77 is electrically connected to the node N31. The other end of the constant current source 77 is electrically connected to the reference potential. The transistor 74 and the constant current source 77 generate a constant potential at the node N31.

[0051] The source of the transistor 75 is electrically connected to the power supply potential Vcc. The gate and drain of the transistor 75 are electrically connected to the die terminal 3b. That is, the transistor 75 is diode-connected. The voltage of the die terminal 3b increases when the collector current of the transistor 34 decreases, and decreases when the collector current of the transistor 34 increases.

[0052] The source of transistor 76 is electrically connected to power supply potential Vcc. The gate and drain of transistor 76 are electrically connected to die terminal 3d. That is, transistor 76 is diode-connected. The voltage at die terminal 3d increases when the collector current of transistor 54 decreases, and decreases when the collector current of transistor 54 increases.

[0053] The inverting input terminal (- terminal) of the first differential amplifier 71 is electrically connected to the node N31. The non-inverting input terminal (+ terminal) of the first differential amplifier 71 is electrically connected to the die terminal 3b. The output terminal of the first differential amplifier 71 is electrically connected to the die terminal 3a.

[0054] The inverting input terminal (- terminal) of the first differential amplifier 71 corresponds to an example of a "first input terminal" in the present disclosure. The non-inverting input terminal (+ terminal) of the first differential amplifier 71 corresponds to an example of a "second input terminal" in the present disclosure.

[0055] Based on the difference between the first monitor signal S13 and the constant potential of node N31, the first differential amplifier 71 outputs a first bias control signal S11 from the die terminal 3a to the die terminal 2a of the first die 2. As a result, the Doherty amplifier circuit 1 has a third negative feedback path from the emitter of transistor 33 → resistor 37 → base of transistor 34 → collector of transistor 34 → non-inverting input terminal of the first differential amplifier 71 → output terminal of the first differential amplifier 71 → node N11 → base of transistor 33.

[0056] The Doherty amplifier 1 has the third negative feedback path, and thereby increases the base potential of the transistor 33 so as to compensate for a drop in the base-emitter voltage of the transistor 33. As a result, the Doherty amplifier 1 can stabilize the first bias current or the first bias voltage S12 and suppress a drop in the output of the carrier amplifier 12.

[0057] The third negative feedback path is composed of the first differential amplifier 71. The first differential amplifier 71 has a very high gain and is highly sensitive compared to, for example, a general single-ended amplifier. Therefore, the Doherty amplifier circuit 1 can respond with high sensitivity to fluctuations in the emitter potential of the transistor 33 by the third negative feedback path.

[0058] The inverting input terminal (- terminal) of the second differential amplifier 72 is electrically connected to the die terminal 3b. The non-inverting input terminal (+ terminal) of the second differential amplifier 72 is electrically connected to the die terminal 3d. The output terminal of the second differential amplifier 72 is electrically connected to the inverting input terminal (- terminal) of the third differential amplifier 73.

[0059] The inverting input terminal (- terminal) of the second differential amplifier 72 corresponds to an example of a "first input terminal" in the present disclosure. The non-inverting input terminal (+ terminal) of the second differential amplifier 72 corresponds to an example of a "second input terminal" in the present disclosure.

[0060] The second differential amplifier 72 outputs an amplified signal S31 to the inverting input terminal (- terminal) of the third differential amplifier 73 based on the difference between the first monitor signal S13 and the second monitor signal S23.

[0061] The non-inverting input terminal (+ terminal) of the third differential amplifier 73 is electrically connected to the reference potential. In other words, the third differential amplifier 73 is an inverting amplifier. The output terminal of the third differential amplifier 73 is electrically connected to the die terminal 3c.

[0062] The inverting input terminal (- terminal) of the third differential amplifier 73 corresponds to an example of a "first input terminal" in the present disclosure. The non-inverting input terminal (+ terminal) of the third differential amplifier 73 corresponds to an example of a "second input terminal" in the present disclosure.

[0063] Based on the difference between the reference potential and the amplified signal S31, the third differential amplifier 73 outputs the second bias control signal S21 from the die terminal 3c to the die terminal 2c of the first die 2. As a result, the Doherty amplifier circuit 1 has a fourth negative feedback path from the emitter of the transistor 53 → the resistor 57 → the base of the transistor 54 → the collector of the transistor 54 → the non-inverting input terminal of the second differential amplifier 72 → the output terminal of the second differential amplifier 72 → the output terminal of the third differential amplifier 73 → node N21 → the base of the transistor 53.

[0064] The Doherty amplifier 1 has the fourth negative feedback path, and thereby increases the base potential of the transistor 53 so as to compensate for a drop in the base-emitter voltage of the transistor 53. As a result, the Doherty amplifier 1 can stabilize the second bias current or the second bias voltage S22 and suppress a drop in the output of the peak amplifier 22.

[0065] The fourth negative feedback path is composed of a second differential amplifier 72 and a third differential amplifier 73. The second differential amplifier 72 and the third differential amplifier 73 have a very high gain and high sensitivity compared to, for example, a general single-ended amplifier. Therefore, the Doherty amplifier circuit 1 can respond with high sensitivity to fluctuations in the emitter potential of the transistor 53 by the fourth negative feedback path.

[0066] (Operation when the carrier amplifier drive level increases) When the drive level of the carrier amplifier 12 rises (approaches saturation) and the base potential of the transistor 41 drops, the emitter potential of the transistor 33 drops, the base potential of the transistor 34 drops, the collector current of the transistor 34 decreases, and the potential of the first monitor terminal 11c rises. In other words, a first monitor signal S13 indicating the state of the first bias current or first bias voltage supplied to the carrier amplifier 12 is output from the first monitor terminal 11c.

[0067] The first monitor terminal 11c is electrically connected to the non-inverting input terminal (+ terminal) of the first differential amplifier 71. Therefore, as the drive level of the carrier amplifier 12 increases, the voltage of the first bias control signal S11 increases, the potential of the node N11 increases, and the drop in the base potential of the transistor 33 is suppressed. In other words, the first bias current or the first bias voltage based on the first bias control signal S11 is output from the transistor 33 of the first bias circuit 11 to the carrier amplifier 12. This suppresses the drop in the emitter potential of the transistor 33, and suppresses the output drop of the carrier amplifier 12.

[0068] Moreover, the first monitor terminal 11c is electrically connected to the inverting input terminal (- terminal) of the second differential amplifier 72. As the drive level of the carrier amplifier 12 increases, the voltage of the amplified signal S31 decreases. The third differential amplifier 73 is an inverting amplifier. Therefore, as the drive level of the carrier amplifier 12 increases, the voltage of the second bias control signal S21 increases, the potential of the node N21 increases, and the base potential of the transistor 53 increases.

[0069] In this way, when the emitter potential of transistor 33 drops, the Doherty amplifier circuit 1 raises the base potential of transistor 53 via a path 150 from the emitter of transistor 33 → resistor 37 → base of transistor 34 → collector of transistor 34 → inverting input terminal of the second differential amplifier 72 → output terminal of the second differential amplifier 72 → inverting input terminal of the third differential amplifier 73 → output terminal of the third differential amplifier 73 → node N21 → base of transistor 53, thereby activating the peak amplifier 22.

[0070] (effect) Path 150 includes a second differential amplifier 72 and a third differential amplifier 73. The second differential amplifier 72 and the third differential amplifier 73 have very high gain and high sensitivity.

[0071] Therefore, the Doherty amplifier circuit 1 can detect a slight drop in the emitter potential of the transistor 33 with high sensitivity and start up the peak amplifier 22. This allows the Doherty amplifier circuit 1 to suppress deterioration in the quality of the radio frequency output signal synthesized from the radio frequency signals RFout1 and RFout2.

[0072] The first negative feedback path is composed of a bipolar transistor. A bipolar transistor can operate at a higher speed than an FET. The third negative feedback path is composed of a first differential amplifier 71. The first differential amplifier 71 has a very high gain and a high sensitivity.

[0073] Therefore, the Doherty amplifier circuit 1 can respond quickly to fluctuations in the emitter potential of the transistor 33 through the first negative feedback path, and can respond with high sensitivity to fluctuations in the emitter potential of the transistor 33 through the third negative feedback path. In other words, the Doherty amplifier circuit 1 can suppress a drop in the base potential of the transistor 33 quickly and with high sensitivity when the emitter potential of the transistor 33 drops, through both the first and third negative feedback paths. As a result, the Doherty amplifier circuit 1 can suppress a decrease in the output of the carrier amplifier 12 and suppress a deterioration in the quality of the radio frequency signal RFout1 even when the drive level of the carrier amplifier 12 increases (approaches saturation).

[0074] The second negative feedback path is composed of a bipolar transistor. A bipolar transistor can operate at a higher speed than an FET. The fourth negative feedback path is composed of a second differential amplifier 72 and a third differential amplifier 73. The second differential amplifier 72 and the third differential amplifier 73 have a very high gain and high sensitivity.

[0075] Therefore, the Doherty amplifier 1 can respond quickly to fluctuations in the emitter potential of the transistor 53 through the second negative feedback path, and can respond with high sensitivity to fluctuations in the emitter potential of the transistor 53 through the fourth negative feedback path. In other words, the Doherty amplifier 1 can suppress a drop in the base potential of the transistor 53 quickly and with high sensitivity when the emitter potential of the transistor 53 drops, through both the second negative feedback path and the fourth negative feedback path. This allows the Doherty amplifier 1 to suppress a decrease in the output of the peak amplifier 22 when the peak amplifier 22 approaches a saturated state, and suppress a decrease in the quality of the radio frequency signal RFout2.

[0076] <Second embodiment> (composition) FIG. 2 is a diagram illustrating a configuration of a Doherty amplifier circuit according to the second embodiment.

[0077] Compared to the Doherty amplifier circuit 1 (see FIG. 1), the Doherty amplifier circuit 1A includes a second die 3A instead of the second die 3.

[0078] In the second embodiment, the non-inverting input terminal (+ terminal) of the third differential amplifier 73 is electrically connected to the die terminal 3d, and receives the second monitor signal S23.

[0079] Compared to the second die 3, the second die 3A further includes a potential level adjustment circuit 78.

[0080] The potential level adjustment circuit 78 includes a transistor 81 which is a P-channel type FET, and a constant current source 82. The source of the transistor 81 is electrically connected to a power supply potential Vcc. The gate and drain of the transistor 81 are electrically connected to a node N32. In other words, the transistor 81 is diode-connected. One end of the constant current source 82 is electrically connected to the node N32. The other end of the constant current source 82 is electrically connected to a reference potential. The transistor 81 and the constant current source 82 generate a constant potential at the node N32.

[0081] The potential level adjustment circuit 78 adjusts the potential level of the amplified signal S31 to the potential level of the second monitor signal S23 by adjusting the amount of current of the constant current source 82. Note that the "potential level of the second monitor signal S23" mentioned here does not only refer to the same potential level as the potential level of the second monitor signal S23, but also includes a potential level slightly shifted from the potential level of the second monitor signal S23 (approximately the same potential level).

[0082] (effect) The Doherty amplifier circuit 1A has a fifth negative feedback path from the emitter of the transistor 53 to the resistor 57 to the base of the transistor 54 to the collector of the transistor 54 to the non-inverting input terminal of the third differential amplifier 73 to the output terminal of the third differential amplifier 73 to the node N21 to the base of the transistor 53. The third differential amplifier 73 has a very high gain and high sensitivity.

[0083] Therefore, the Doherty amplifier circuit 1A can more reliably suppress the decrease in the base potential of the transistor 53, and can enhance the effect of negative feedback that suppresses the decrease in the output of the peak amplifier 22.

[0084] <Third embodiment> (composition) FIG. 3 is a diagram illustrating a configuration of a Doherty amplifier circuit according to the third embodiment.

[0085] Compared to the Doherty amplifier circuit 1 (see FIG. 1), the Doherty amplifier circuit 1B includes a first die 2B instead of the first die 2. Moreover, the Doherty amplifier circuit 1B includes a second die 3B instead of the second die 3.

[0086] Compared to the second die 3, the second die 3B does not include the third differential amplifier 73. Then, the second differential amplifier 72 outputs the amplified signal S31 from the die terminal 3c to the die terminal 2c of the first die 2B.

[0087] Compared to the first die 2, the first die 2B includes a second bias circuit 21B instead of the second bias circuit 21. In addition, the first die 2B further includes an inverting amplifier 91.

[0088] Compared to the second bias circuit 21, the second bias circuit 21B does not include the transistor 51, the transistor 52, and the resistor 56. The base of the transistor 53 is electrically connected to the node N11 of the first bias circuit 11.

[0089] The inverting amplifier 91 inverts the amplified signal S31 and outputs a second bias control signal S21 to the second bias control terminal 21a. The second bias control terminal 21a is electrically connected to the other end of the resistor 55.

[0090] The inverting amplifier 91 includes a transistor 101 and a resistor 102 .

[0091] The emitter of the transistor 101 is electrically connected to a reference potential. The base of the transistor 101 is electrically connected to the die terminal 2c, and receives the amplified signal S31. The collector of the transistor 101 is electrically connected to one end of the resistor 102. The other end of the resistor 102 is electrically connected to the other end of the resistor 55.

[0092] When the base potential (amplified signal S31) of the transistor 101 drops, the collector current decreases. This causes the potential of the die terminal 2c to rise. When the base potential (amplified signal S31) of the transistor 101 rises, the collector current increases. This causes the emitter voltage of the transistor 53 to drop.

[0093] (operation) Generally, when the drive level of a carrier amplifier is high, it requires a large base current, and the base-emitter voltage of the output transistor of the carrier bias circuit becomes large. This causes the output power of the carrier bias circuit to decrease.

[0094] However, the first bias circuit 11 of the embodiment has the above-mentioned first negative feedback path, and thus supplies a stable first bias current or first bias voltage S12 to the carrier amplifier 12. This is because the first negative feedback path operates to compensate for the increasing base-emitter voltage drop of the transistor 33. In other words, since the first bias circuit 11 has the first negative feedback path, the base potential of the transistor 33 (potential of the node N11) increases together with the increase in the drive level of the carrier amplifier 12.

[0095] The second bias circuit 21B inputs this rising potential of the node N11 to the base of the transistor 53, thereby increasing the second bias current or the second bias voltage S22 as the drive level of the carrier amplifier 12 rises, and can start the peak amplifier 22. This operation can be achieved using only bipolar transistors. Bipolar transistors can operate at higher speeds than FETs. Therefore, the second bias circuit 21B can start the peak amplifier 22 at high speed in response to the rise in the drive level of the carrier amplifier 12.

[0096] Furthermore, when the drive level of the carrier amplifier 12 rises, the amplified signal S31, which is the output signal of the second differential amplifier 72, falls. This causes the base potential of the transistor 101 to fall, and the collector current of the transistor 101 to decrease. As a result, the voltage drop occurring in the resistor 55 due to the collector current of the transistor 101 decreases, and the base potential of the transistor 61 of the peak amplifier 22 rises, and the peak amplifier 22 is started up. This operation can be realized by using the second differential amplifier 72. The second differential amplifier 72 has a very high gain and is highly sensitive. Therefore, the Doherty amplifier circuit 1B can start up the peak amplifier 22 with high sensitivity in response to an increase in the drive level of the carrier amplifier 12.

[0097] (effect) The Doherty amplifier circuit 1B can start up the peak amplifier 22 quickly and with high sensitivity in response to an increase in the drive level of the carrier amplifier 12.

[0098] <Fourth embodiment> FIG. 4 is a diagram illustrating a configuration of a Doherty amplifier circuit according to the fourth embodiment.

[0099] Compared to the Doherty amplifier circuit 1 (see FIG. 1), the Doherty amplifier circuit 1C includes a first die 2C instead of the first die 2.

[0100] Compared to the first die 2, the first die 2C includes a first bias circuit 11C instead of the first bias circuit 11. Moreover, the first die 2C includes a second bias circuit 21C instead of the second bias circuit 21.

[0101] Compared to the first bias circuit 11, the first bias circuit 11C does not include a resistor 36. And, the base of the transistor 32 is electrically connected to the collector. That is, the transistor 32 is diode-connected. Therefore, compared to the first bias circuit 11, the first bias circuit 11C does not have a first negative feedback path.

[0102] However, the Doherty amplifier circuit 1C has a third negative feedback path, similar to the Doherty amplifier circuit 1. Therefore, the Doherty amplifier circuit 1C can suppress a drop in the base potential of the transistor 33, stabilize the first bias current or the first bias voltage S12, suppress a decrease in the output of the carrier amplifier 12, and suppress a decrease in the quality of the radio frequency signal RFout1.

[0103] Compared to the second bias circuit 21, the second bias circuit 21C does not include a resistor 56. The base of the transistor 52 is electrically connected to the collector. That is, the transistor 52 is diode-connected. Therefore, compared to the second bias circuit 21, the second bias circuit 21C does not have a second negative feedback path.

[0104] However, the Doherty amplifier circuit 1C has a fourth negative feedback path, similar to the Doherty amplifier circuit 1. Therefore, the Doherty amplifier circuit 1C can suppress a drop in the base potential of the transistor 53, stabilize the second bias current or the second bias voltage S22, suppress a decrease in the output of the peak amplifier 22, and suppress a deterioration in the quality of the radio frequency signal RFout2.

[0105] <Fifth embodiment> FIG. 5 is a diagram illustrating a configuration of a Doherty amplifier circuit according to the fifth embodiment.

[0106] Compared to the Doherty amplifier circuit 1B (see FIG. 3), the Doherty amplifier circuit 1D includes a first die 2D instead of the first die 2B.

[0107] Compared to the first die 2C (see FIG. 4), the first die 2D includes a second bias circuit 21D instead of the second bias circuit 21C.

[0108] The second bias circuit 21D further includes a constant current source 58 in comparison with the second bias circuit 21C.

[0109] The node N21 of the second bias circuit 21D is not electrically connected to the second bias control terminal 21a. Instead, a constant current source 58 is electrically connected to the node N21. The constant current source 58 outputs a constant current to the node N21. The transistors 51 and 52 generate, at the node N21, a potential corresponding to the constant current output from the constant current source 58. In addition, the other end of the resistor 55 is electrically connected to the second bias control terminal 21a.

[0110] The second bias circuit 21D does not have a second negative feedback path. However, the Doherty amplifier circuit 1D has a fourth negative feedback path, similar to the Doherty amplifier circuit 1. Therefore, the Doherty amplifier circuit 1D can suppress a drop in the base potential of the transistor 53, stabilize the second bias current or the second bias voltage S22, suppress a decrease in the output of the peak amplifier 22, and suppress a decrease in the quality of the radio frequency signal RFout2.

[0111] <Configuration Example of the Present Disclosure> The present disclosure may also have the following configurations.

[0112] (1) a carrier amplifier that amplifies the first high frequency signal; a peak amplifier for amplifying the second high frequency signal; a first bias circuit including: a first bias control terminal to which a first bias control signal is input; a first bias output terminal to output a first bias current or a first bias voltage based on the first bias control signal to the carrier amplifier; and a first monitor terminal to output a first monitor signal representing a state of the first bias current or the first bias voltage; a second bias circuit including: a second bias control terminal to which a second bias control signal is input; a second bias output terminal to output a second bias current or a second bias voltage based on the second bias control signal to the peak amplifier; and a second monitor terminal to output a second monitor signal representing a state of the second bias current or the second bias voltage; a first differential amplifier having a first input terminal to which a constant voltage is input, a second input terminal electrically connected to the first monitor terminal, and an output terminal electrically connected to the first bias control terminal, the first differential amplifier outputting the first bias control signal to the first bias control terminal based on a difference between the first monitor signal and the constant voltage; a second differential amplifier having a first input terminal electrically connected to the first monitor terminal and a second input terminal electrically connected to the second monitor terminal, and outputting an amplified signal from an output terminal based on a difference between the second monitor signal and the first monitor signal; an inverting amplifier that inverts and amplifies the amplified signal and outputs the second bias control signal to the second bias control terminal; Doherty amplifier circuit.

[0113] (2) The Doherty amplifier circuit according to (1) above, The inverting amplifier is a third differential amplifier having a first input terminal electrically connected to the output terminal of the second differential amplifier, a second input terminal electrically connected to a reference potential, and an output terminal electrically connected to the second bias control terminal; Doherty amplifier circuit.

[0114] (3) The Doherty amplifier circuit according to (1) above, The inverting amplifier is a third differential amplifier having a first input terminal electrically connected to the output terminal of the second differential amplifier, a second input terminal electrically connected to the second monitor terminal, and an output terminal electrically connected to the second bias control terminal; Doherty amplifier circuit.

[0115] (4) The Doherty amplifier circuit according to (3) above, a potential level adjustment circuit electrically connected between the output terminal of the second differential amplifier and the first input terminal of the third differential amplifier, for adjusting a potential level of the amplified signal to a potential level of the second monitor signal; Doherty amplifier circuit.

[0116] (5) The Doherty amplifier circuit according to (1) above, The inverting amplifier is a transistor having a base or a gate to which the amplified signal is input, a collector or a drain electrically connected to the second bias control terminal, and an emitter or a source electrically connected to a reference potential; Doherty amplifier circuit.

[0117] (6) A Doherty amplifier circuit according to any one of (1) to (5), The first bias circuit includes: a first output transistor for outputting the first bias current or the first bias voltage, the first output transistor having a first negative feedback path from an emitter or a source to a base or a gate of the first output transistor; Doherty amplifier circuit.

[0118] (7) A Doherty amplifier circuit according to any one of (1) to (6), The second bias circuit includes: a second output transistor for outputting the second bias current or the second bias voltage, the second output transistor having a second negative feedback path from an emitter or a source to a base or a gate of the second output transistor; Doherty amplifier circuit.

[0119] (8) A Doherty amplifier circuit according to any one of (1) to (7), The second bias circuit includes: a second output transistor that outputs the second bias current or the second bias voltage, the base or gate of the second output transistor being electrically connected to the base or gate of the first output transistor; Doherty amplifier circuit.

[0120] The above-described embodiment is for the purpose of facilitating understanding of the present invention, and is not intended to limit the present invention. The present invention may be modified or improved without departing from the spirit of the present invention, and equivalents thereof are also included in the present invention. [Explanation of symbols]

[0121] 1, 1A, 1B, 1C, 1D Doherty amplifier circuit 2, 2B, 2D 1st die 3, 3A, 3B 2nd die 11, 11C First bias circuit 12 Carrier Amplifier 21, 21B, 21C, 21D Second bias circuit 22 Peak Amplifier 71 First differential amplifier 72 Second Differential Amplifier 73 Third Differential Amplifier 78 Potential level adjustment circuit

Claims

1. a carrier amplifier that amplifies the first high frequency signal; a peak amplifier for amplifying the second high frequency signal; a first bias circuit including: a first bias control terminal to which a first bias control signal is input; a first bias output terminal to output a first bias current or a first bias voltage based on the first bias control signal to the carrier amplifier; and a first monitor terminal to output a first monitor signal representing a state of the first bias current or the first bias voltage; a second bias circuit including: a second bias control terminal to which a second bias control signal is input; a second bias output terminal to output a second bias current or a second bias voltage based on the second bias control signal to the peak amplifier; and a second monitor terminal to output a second monitor signal representing a state of the second bias current or the second bias voltage; a first differential amplifier having a first input terminal to which a constant voltage is input, a second input terminal electrically connected to the first monitor terminal, and an output terminal electrically connected to the first bias control terminal, the first differential amplifier outputting the first bias control signal to the first bias control terminal based on a difference between the first monitor signal and the constant voltage; a second differential amplifier having a first input terminal electrically connected to the first monitor terminal and a second input terminal electrically connected to the second monitor terminal, and outputting an amplified signal from an output terminal based on a difference between the second monitor signal and the first monitor signal; an inverting amplifier that inverts and amplifies the amplified signal and outputs the second bias control signal to the second bias control terminal; Including, Doherty amplifier circuit.

2. 2. The Doherty amplifier circuit of claim 1 , The inverting amplifier is a third differential amplifier having a first input terminal electrically connected to the output terminal of the second differential amplifier, a second input terminal electrically connected to a reference potential, and an output terminal electrically connected to the second bias control terminal; Doherty amplifier circuit.

3. 2. The Doherty amplifier circuit of claim 1 , The inverting amplifier is a third differential amplifier having a first input terminal electrically connected to the output terminal of the second differential amplifier, a second input terminal electrically connected to the second monitor terminal, and an output terminal electrically connected to the second bias control terminal; Doherty amplifier circuit.

4. 4. The Doherty amplifier circuit according to claim 3, a potential level adjustment circuit electrically connected between an output terminal of the second differential amplifier and a first input terminal of the third differential amplifier, the potential level adjustment circuit adjusting a potential level of the amplified signal to a potential level of the second monitor signal; Doherty amplifier circuit.

5. 2. The Doherty amplifier circuit of claim 1 , The inverting amplifier is a transistor having a base or a gate to which the amplified signal is input, a collector or a drain electrically connected to the second bias control terminal, and an emitter or a source electrically connected to a reference potential; Doherty amplifier circuit.

6. 6. A Doherty amplifier circuit according to claim 1, The first bias circuit includes: a first output transistor for outputting the first bias current or the first bias voltage, the first output transistor having a first negative feedback path from an emitter or a source to a base or a gate of the first output transistor; Doherty amplifier circuit.

7. 7. A Doherty amplifier circuit as claimed in claim 6, The second bias circuit includes: a second output transistor for outputting the second bias current or the second bias voltage, the second output transistor having a second negative feedback path from an emitter or a source to a base or a gate of the second output transistor; Doherty amplifier circuit.

8. 7. A Doherty amplifier circuit as claimed in claim 6, The second bias circuit includes: a second output transistor that outputs the second bias current or the second bias voltage, the base or gate of the second output transistor being electrically connected to the base or gate of the first output transistor; Doherty amplifier circuit.

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