Semiconductor device

Abstract

To provide a semiconductor device capable of reducing a leakage current.SOLUTION: A semiconductor device according to an embodiment, comprises: a first electrode; a first conductive shaped first semiconductor region; a second conductive shaped second semiconductor region; a first conductive shaped third semiconductor region; a gate electrode; a second conductive shaped fourth semiconductor region; a second electrode; and a second conductive shaped fifth semiconductor region. The first semiconductor region contains: a first part; and a second part provided to the circumference of the first part. The second semiconductor region is provided onto the first part. The fourth semiconductor region is provided onto the second part. The second electrode contains a first metal part and a second metal part. The first metal part is contacted to the first part and the second semiconductor region. The second metal part is contacted to the second part and the fourth semiconductor region. The first and second metal parts contain at least one first element selected from a group of titanium, molybdenum, and vanadium. The fifth semiconductor region is provided to a side lower from the fourth semiconductor region, and is positioned to just under the second metal part.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] Semiconductor devices such as metal oxide semiconductor field effect transistors (MOSFETs) are used for applications such as power conversion, etc. It is desirable for the leakage current of semiconductor devices to be small. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 6649183 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a semiconductor device capable of reducing leakage current. [Means for solving the problem]

[0005] The semiconductor device according to the embodiment includes a first electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a gate electrode, a fourth semiconductor region of a second conductivity type, a second electrode, and a fifth semiconductor region of a second conductivity type. The first semiconductor region is provided on the first electrode. The first semiconductor region includes a first portion and a second portion provided around the first portion along a first surface perpendicular to a first direction from the first electrode to the first portion. The second semiconductor region is provided on the first portion. The third semiconductor region is provided on the second semiconductor region. The gate electrode faces the second semiconductor region via a gate insulating layer. The fourth semiconductor region is provided on the second portion and is located around the second semiconductor region along the first surface. The second electrode includes a first metal portion and a second metal portion. The first metal part is in contact with the first portion and the second semiconductor region, and contains at least one first element selected from the group consisting of titanium, molybdenum, and vanadium. The second metal part is in contact with the second portion and the fourth semiconductor region, and contains the first element. The second electrode is provided on the second semiconductor region, the third semiconductor region, and the fourth semiconductor region. The fifth semiconductor region is provided below the fourth semiconductor region and is located directly below the second metal part. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is a plan view showing a semiconductor device according to an embodiment. [Diagram 2] FIG. 2 is an enlarged plan view of a portion II of FIG. [Diagram 3] FIG. 3 is a cross-sectional view taken along line III-III of FIG. [Figure 4] FIG. 4 is a cross-sectional view taken along line IV-IV of FIG. [Diagram 5] 5(a) and 5(b) are cross-sectional views showing a method for manufacturing a semiconductor device according to the embodiment. [Figure 6] 6(a) and 6(b) are cross-sectional views showing a method for manufacturing a semiconductor device according to the embodiment. [Figure 7] 7(a) and 7(b) are cross-sectional views showing a method for manufacturing a semiconductor device according to the embodiment. [Figure 8] 8(a) and 8(b) are plan views showing another example of the semiconductor device according to the embodiment. [Figure 9] FIG. 9 is a cross-sectional view showing a part of a semiconductor device according to a first modification of the embodiment. [Figure 10] FIG. 10 is a cross-sectional view showing a part of a semiconductor device according to a first modification of the embodiment. [Figure 11] FIG. 11 is a cross-sectional view showing a part of a semiconductor device according to a second modification of the embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, each embodiment of the present invention will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as the actual ones. Even when the same part is shown, the dimensions and ratios of each part may be different depending on the drawing. In this specification and each drawing, elements similar to those already explained are given the same reference numerals, and detailed explanations are omitted as appropriate. In the following description, n + , n, n - and p + , p, p - The notation indicates the relative level of impurity concentration in each conductivity type. + has a relatively higher n-type impurity concentration than n, - indicates that the n-type impurity concentration is relatively lower than that of n. + has a relatively higher p-type impurity concentration than p, - indicates that the p-type impurity concentration is relatively lower than that of p. Each embodiment described below may be implemented by inverting the p-type and n-type of each semiconductor region.

[0008] Fig. 1 is a plan view showing a semiconductor device according to an embodiment, Fig. 2 is an enlarged plan view of a portion II in Fig. 1, Fig. 3 is a cross-sectional view taken along line III-III in Fig. 2, Fig. 4 is a cross-sectional view taken along line IV-IV in Fig. 2. The semiconductor device according to the embodiment is a MOSFET. As shown in FIGS. 1 to 4, the semiconductor device 100 according to the embodiment has n - p-type (first conductivity type) drift region 1 (first semiconductor region), p-type (second conductivity type) base region 2 (second semiconductor region), n + a p-type source region 3 (third semiconductor region), a p-type semiconductor region 4 (fourth semiconductor region), - Shield region 5 (fifth semiconductor region), p - Resurf region 6, n-type semiconductor region 7, n + 8, p-type drain region + Contact area 9a,p + The semiconductor device includes a contact region 9b, a gate electrode 10, an insulating layer 15, a drain electrode 21 (first electrode), a source electrode 22 (second electrode), and a gate pad 23. Note that the insulating layer 15 is omitted in Fig. 1. In Fig. 2, the insulating layer 15 and a part of the source electrode 22 are omitted.

[0009] In the description of the embodiment, an XYZ orthogonal coordinate system is used. - The direction toward a part (first portion 1a) of the drift region 1 is defined as the Z direction (first direction). Two directions that are perpendicular to the Z direction and perpendicular to each other are defined as the X direction (second direction) and the Y direction (third direction). - The direction toward the n-type drift region 1 is called "up" and the opposite direction is called "down." These directions are - The shape is based on the relative position to the drift region 1 and is independent of the direction of gravity.

[0010] 1, a source electrode 22 and a gate pad 23 are provided on the upper surface of the semiconductor device 100. The source electrode 22 and the gate pad 23 are spaced apart from each other.

[0011] As shown in FIG. 2, under the source electrode 22, + p-type source region 3, p-type semiconductor region 4, - Shape RESURF region 6, p + Contact area 9a,p + A contact region 9b and a gate electrode 10 are provided. In addition, in Fig. 2, a source electrode 22 is indicated by a dashed line.

[0012] As shown in FIGS. 3 and 4, a drain electrode 21 is provided on the bottom surface of the semiconductor device 100. + The drain region 8 is provided on the drain electrode 21 and is electrically connected to the drain electrode 21. - The drift region 1 is n + The n-type drain region 8 is provided on the n-type drain region 8. - The n-type impurity concentration of the n-type drift region 1 is + The n-type impurity concentration of the n-type drain region 8 is lower than that of the n-type drain region 8 .

[0013] n - The drift region 1 includes a first portion 1a and a second portion 1b as shown by the two-dot chain line in FIG. - The second portion 1b is located at the center of the XY plane (first surface) of the drift region 1. The second portion 1b is provided around the first portion 1a along the XY plane.

[0014] As shown in FIG. 3, the p-type base region 2 is provided on the first portion 1a. + Shape source region 3 and p + The p-type contact region 9a is selectively provided on the p-type base region 2. + The p-type impurity concentration of the p-type contact region 9 a is higher than the p-type impurity concentration of the p-type base region 2 .

[0015] The gate electrode 10 faces a part of the p-type base region 2 in the Z direction via the gate insulating layer 11. The gate electrode 10 is electrically connected to a gate pad 23. The gate electrode 10 and the source electrode 22 are electrically isolated from each other by an insulating layer 15.

[0016] p-type base region 2, n + Shape source area 3, p + The p-type contact region 9a and the gate electrode 10 are provided in a plurality in the X direction. + Shape source area 3, each p + The contact region 9a and each gate electrode 10 extend in the Y direction.

[0017] As shown in FIG. 4, the p-type semiconductor region 4 is provided on the second portion 1b. The p-type semiconductor region 4 is located around the multiple p-type base regions 2 along the XY plane. The end of the p-type base region 2 in the Y direction may be connected to the p-type semiconductor region 4. A plurality of p-type semiconductor regions 4 are provided in the direction from the first portion 1a to the second portion 1b. The multiple p-type semiconductor regions 4 are separated from each other. The distance between the p-type semiconductor regions 4 is wider than the distance between adjacent p-type base regions 2 in the X direction.

[0018] p + The p-type contact region 9b is selectively provided on the p-type semiconductor region 4. + The p-type impurity concentration of the p-type contact region 9b is higher than the p-type impurity concentration of the p-type semiconductor region 4.

[0019] p - The resurf region 6 is provided around the p-type semiconductor region 4 along the XY plane and is in contact with the p-type semiconductor region 4. - The p-type impurity concentration of the resurf region 6 is lower than the p-type impurity concentration of the p-type semiconductor region 4. - By providing the RESURF region 6, the depletion layer can be expanded further toward the outer periphery of the semiconductor device 100, and the breakdown voltage of the semiconductor device 100 can be improved.

[0020] The n-type semiconductor region 7 is p - A p - The n-type semiconductor region 7 is separated from the resurf region 6. The n-type impurity concentration of the n-type semiconductor region 7 is -The n-type impurity concentration is higher than the n-type impurity concentration of the n-type drift region 1. The n-type semiconductor region 7 is provided along the outer periphery of the semiconductor device 100. By providing the n-type semiconductor region 7, it is possible to prevent a depletion layer spreading toward the outer periphery of the semiconductor device 100 from reaching an end face of the semiconductor device 100.

[0021] The source electrode 22 is connected to the p-type base region 2, + p-type source region 3, p-type semiconductor region 4, + Contact region 9a and p + The contact regions 9b are located on the contact regions 9a and are electrically connected to these semiconductor regions.

[0022] More specifically, the source electrode 22 includes a first metal portion 22a and a second metal portion 22b, as shown in Figs. 1 to 4. In Fig. 1, the first metal portion 22a and the second metal portion 22b are indicated by dashed lines. The first metal portion 22a is located on the first portion 1a and is in contact with the first portion 1a and the p-type base region 2. The second metal portion 22b is located on the second portion 1b and is in contact with the p-type semiconductor region 4 and the p + The contact region 9b is in contact with the contact area 9c.

[0023] A plurality of first metal portions 22a are provided in the X direction, and each first metal portion 22a extends in the Y direction. The second metal portion 22b is provided around the plurality of gate electrodes 10 and the plurality of first metal portions 22a along the XY plane.

[0024] 2, one first metal portion 22a and one or more gate electrodes 10 are provided alternately in the X direction. The multiple p-type base regions 2 include p-type base regions 2a and p-type base regions 2b. One end of the p-type base region 2a in the X direction faces the gate electrode 10, and the other end of the p-type base region 2a contacts the first metal portion 22a. Both ends of the p-type base region 2b in the X direction face two gate electrodes 10, respectively.

[0025] A Schottky junction is formed between the first portion 1a and the first metal portion 22a, and between the second portion 1b and the second metal portion 22b. That is, the semiconductor device 100 includes a Schottky barrier diode D1 formed from the first portion 1a and the first metal portion 22a, and a Schottky barrier diode D2 formed from the second portion 1b and the second metal portion 22b.

[0026] The source electrode 22 may further include a silicide region 22c as shown in Figures 3 and 4. Note that the silicide region 22c is omitted in Figure 2. The silicide region 22c is an n + Shape source region 3 and p + 9a, and + Shape source region 3 and p + The contact region 9a is in ohmic contact with the contact region 9a.

[0027] p - The p-type shield region 5 is provided below the p-type semiconductor region 4 and is located directly below the second metal portion 22b. More specifically, the p-type semiconductor regions 4 are separated from each other via a part of the second portion 1b. The second metal portion 22b contacts the part of the second portion 1b. - The shaped shielding region 5 is located under the part of the second portion 1b. - The shape shielding region 5 is provided in an annular shape along the second metal portion 22b.

[0028] 3, the first portion 1a may include a first region r1 and a second region r2. The first region r1 contacts the p-type base region 2 and the first metal portion 22a. The first region r1 may be further provided directly below the gate electrode 10. The second region r2 is located between the drain electrode 21 and the first region r1 in the Z direction. The n-type impurity concentration of the first region r1 is higher than the n-type impurity concentration of the second region r2.

[0029] As shown in FIG. 4, the second portion 1b may include a third region r3 and a fourth region r4. The third region r3 includes a p-type semiconductor region 4, a p -The third region r3 is in contact with the drain electrode 21 and the second metal portion 22b. The third region r3 is separated from the first region r1. The fourth region r4 is located between the drain electrode 21 and the third region r3 in the Z direction. The n-type impurity concentration of the third region r3 is higher than the n-type impurity concentration of the fourth region r4.

[0030] An example of the material of each component will be described. n - p-type drift region 1, p-type base region 2, n + p-type source region 3, p-type semiconductor region 4, - Shape shield area 5, p - Resurf region 6, n-type semiconductor region 7, n + 8, p-type drain region + Contact region 9a and p + The contact region 9b includes a semiconductor material such as silicon, silicon carbide, gallium nitride, or gallium arsenide. The semiconductor material is preferably silicon carbide. The n-type impurity may be nitrogen, arsenic, phosphorus, or antimony. The p-type impurity may be aluminum or boron.

[0031] The gate electrode 10 includes a conductive material such as polysilicon. The gate insulating layer 11 and the insulating layer 15 include an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. The drain electrode 21 and the gate pad 23 include a metal material such as aluminum.

[0032] The first metal portion 22a and the second metal portion 22b contain at least one first element selected from the group consisting of titanium, molybdenum, and vanadium. Since the first metal portion 22a and the second metal portion 22b contain the first element, Schottky junctions are formed between the first portion 1a and the first metal portion 22a, and between the second portion 1b and the second metal portion 22b. The silicide region 22c contains nickel silicide. Portions of the source electrode 22 other than the first metal portion 22a, the second metal portion 22b, and the silicide region 22c contain aluminum.

[0033] The operation of the semiconductor device 100 will be described. With a positive voltage applied to the drain electrode 21 relative to the source electrode 22, a voltage equal to or greater than the threshold is applied to the gate electrode 10. This forms a channel (inversion layer) in the p-type base region 2, turning the semiconductor device 100 on. Electrons flow from the source electrode 22 to the drain electrode 21 through the channel. When the voltage applied to the gate electrode 10 becomes lower than the threshold, the channel in the p-type base region 2 disappears, turning the semiconductor device 100 off.

[0034] When the semiconductor device 100 is in an off state, a positive voltage may be applied to the source electrode 22 with respect to the drain electrode 21. At this time, a current flows from the source electrode 22 to the drain electrode 21 through the Schottky barrier diodes D1 and D2.

[0035] 5(a) to 7(b) are cross-sectional views showing a method for manufacturing a semiconductor device according to the embodiment. First, n - Semiconductor layer 1x and n + A semiconductor substrate including a semiconductor layer 8x is prepared. - The semiconductor layer 1x is + The semiconductor layer 8x is provided on the semiconductor layer 8x. - As shown in FIG. 5(a), p-type impurities and n-type impurities are sequentially ion-implanted into the upper surface of the n-type semiconductor layer 1x to form an n-type semiconductor region 1y, an n-type semiconductor region 1z, and a p-type semiconductor region 1y. - Forming a semiconductor region 5x. - The upper surface of the p-type semiconductor layer 1x is ion-implanted with p-type impurities. - After forming the semiconductor region 5x, - The epitaxially grown n-type semiconductor layer may be epitaxially grown. - By selectively implanting n-type impurities into the n-type semiconductor layer, n-type semiconductor regions 1y and 1z are formed. The n-type semiconductor regions 1y and 1z are separated from each other. - The n-type semiconductor region 5x is located below the n-type semiconductor region 1z.

[0036] n -A photoresist is formed on the n-type semiconductor layer 1x, the n-type semiconductor region 1y, and the n-type semiconductor region 1z. The photoresist is patterned by photolithography and reactive ion etching (RIE). As a result, masks M1 to M3 are formed as shown in FIG. 5(b). The mask M1 is formed on the n-type semiconductor region 1y. The position of the mask M1 corresponds to the position of the gap between the p-type base regions 2. The mask M2 is formed on the n-type semiconductor region 1z. The position of the mask M2 corresponds to the position of the gap between the p-type semiconductor regions 4. The mask M3 is formed on the n-type semiconductor region 1z. The position of the mask M3 corresponds to the position of the gap between the p-type semiconductor regions 4. - The mask M2 is formed on the outer peripheral portion of the semiconductor layer 1x. For example, the width (dimension in the X direction) of the mask M2 is wider than the width of the mask M1.

[0037] n - A p-type impurity is ion-implanted into the upper surfaces of the n-type semiconductor layer 1x, the n-type semiconductor region 1y, and the n-type semiconductor region 1z. As shown in FIG. 6(a), a p-type semiconductor region 2x and a p-type semiconductor region 4x are formed in the regions not covered by the masks M1 to M3.

[0038] After removing the masks M1 to M3, as shown in FIG. + Shape source area 3, p - Resurf region 6, n-type semiconductor region 7, p + Contact area 9a,p + Then, a contact region 9b, a gate electrode 10, a gate insulating layer 11, and an insulating layer 15 are formed. A known method can be applied to the formation of these elements.

[0039] A first metal portion 22a is formed on the n-type semiconductor region 1y, and a second metal portion 22b is formed on the n-type semiconductor region 1z. + p-type source region 3, p-type semiconductor region 4, + Contact region 9a and p + A silicide region 22c is formed on the contact region 9b. As shown in Fig. 7(a), an aluminum layer 22d is formed on the first metal portion 22a, the second metal portion 22b, and the silicide region 22c.

[0040] n + The n-type semiconductor layer 8x is then grown to a predetermined thickness. + The bottom surface of the n-type semiconductor layer 8x is ground. As shown in FIG. + A drain electrode 21 is formed on the lower surface of the shaped semiconductor layer 8x. Through the above steps, the semiconductor device 100 according to the embodiment is manufactured.

[0041] n shown in Fig. 7(b) - The n-type semiconductor layer 1x corresponds to the second region r2 of the first portion 1a and the fourth region r4 of the second portion 1b shown in FIG. 3 and FIG. 4. The n-type semiconductor region 1y corresponds to the first region r1 of the first portion 1a. The n-type semiconductor region 1z corresponds to the third region r3 of the second portion 1b. The p-type semiconductor region 2x corresponds to the p-type base region 2. The p-type semiconductor region 4x corresponds to the p-type semiconductor region 4. - The semiconductor region 5x is p - It corresponds to the shielded area 5. + The semiconductor layer 8x is + 4 corresponds to the drain region 8.

[0042] Advantages of the embodiment will be described. The semiconductor device 100 has n - A parasitic diode consisting of a p-type drift region 1 and a p-type base region 2, and - The parasitic diode is made up of a p-type drift region 1 and a p-type semiconductor region 4. When these parasitic diodes are activated, - A large number of carriers are injected into the drift region 1. Therefore, when the parasitic diode operates, it takes a long time for reverse recovery. In addition, the charge amount Qrr during reverse recovery is large, so the power loss also increases.

[0043] Regarding this problem, the semiconductor device 100 includes Schottky barrier diodes D1 and D2. The forward voltages of the Schottky barrier diodes D1 and D2 are lower than the forward voltage of the parasitic diode. Therefore, when a positive voltage is applied to the source electrode 22, the Schottky barrier diodes D1 and D2 operate before the parasitic diode operates. When a current flows through the Schottky barrier diodes D1 and D2, the increase in the voltage of the source electrode 22 is suppressed. Therefore, the parasitic diodes are less likely to operate, and the power loss of the semiconductor device 100 can be reduced.

[0044] However, when the Schottky barrier diodes D1 and D2 are provided, a leakage current may flow through the Schottky barrier diodes D1 and D2 when the semiconductor device 100 is in an off state. If a leakage current flows through the semiconductor device 100, power loss increases. For this reason, it is desirable that the leakage current through the Schottky barrier diodes D1 and D2 be small.

[0045] Regarding the Schottky barrier diode D1, the leakage current can be sufficiently reduced by adjusting the dimensions and arrangement of the p-type base region 2. For example, the leakage current due to the Schottky barrier diode D1 can be reduced by narrowing the interval between the p-type base regions 2 and reducing the contact area between the first portion 1a and the first metal portion 22a.

[0046] On the other hand, in the Schottky barrier diode D2, it is difficult to narrow the interval between the p-type semiconductor regions 4. For example, the interval between the p-type base regions 2 and the interval between the p-type semiconductor regions 4 correspond to the width of the mask M1 and the width of the mask M2 shown in FIG. 5(b), respectively. A large number of masks M1 are formed on the first portion 1a. On the other hand, only a small number of masks M2 are formed on the second portion 1b. Under the conditions for forming a large number of fine masks M1, it is difficult to simultaneously process a small number of masks M2 separated from the large number of masks M1 with high accuracy and with reduced variation. That is, it is difficult to narrow the width of the mask M2 while forming a large number of fine masks M1.

[0047] Moreover, in order to suppress the operation of the parasitic diode in the outer periphery of the semiconductor device 100 in which the p-type semiconductor region 4 is provided, it is preferable that the width of the mask M2 is formed wide and the contact area between the second metal portion 22b and the second portion 1b is large. On the other hand, the larger the contact area between the second metal portion 22b and the second portion 1b, the more the leakage current of the Schottky barrier diode D2 increases.

[0048] As described above, with regard to the Schottky barrier diode D2, it is not easy to reduce the leakage current by adjusting the dimensions and arrangement of the p-type semiconductor region 4 due to restrictions on the manufacturing method and the need to suppress the operation of the parasitic diode.

[0049] The semiconductor device 100 according to the embodiment has a p - The shielding area 5 is provided. - By providing the shield region 5, it is possible to reduce the electric field strength in the vicinity of the Schottky barrier diode D2. This makes it possible to reduce the leakage current through the Schottky barrier diode D2 when the semiconductor device 100 is in an off state. According to the embodiment, it is possible to reduce the leakage current through the Schottky barrier diode D2, and therefore the power loss of the semiconductor device 100.

[0050] p - It is preferable that the p-type impurity concentration of the p-type shield region 5 is lower than the p-type impurity concentration of the p-type semiconductor region 4. - The electric field strength at the outer peripheral edge of the conductive shield region 5 can be reduced, and the breakdown voltage of the semiconductor device 100 can be further increased.

[0051] p - The position of the p-type shield region 5 in the Z direction can be changed as appropriate. - If the distance between the p-type semiconductor region 4 and the p-type shield region 5 is too short, the effect of the Schottky barrier diode D2 in suppressing the operation of the parasitic diode may be weakened. - If the distance between the shielding region 5 is too long,- The effect of reducing the electric field strength by the p-type shield region 5 is weakened. - The distance in the Z direction between the shaped shielding regions 5 is preferably longer than 0.2 μm and shorter than 1.0 μm.

[0052] As shown in Fig. 3, the first portion 1a preferably includes a first region r1. When the first region r1 is provided, the electrical resistance in the current path around the p-type base region 2 can be reduced when the Schottky barrier diode D1 operates. This can suppress the rise in voltage in the p-type base region 2, and - Therefore, the parasitic diode formed by the p-type drift region 1 and the p-type base region 2 becomes difficult to operate.

[0053] Similarly, the second portion 1b also preferably includes a third region r3 as shown in Fig. 4. When the third region r3 is provided, the electrical resistance in the current path around the p-type semiconductor region 4 can be reduced when the Schottky barrier diode D2 operates. This can suppress the rise in voltage of the p-type semiconductor region 4, - Therefore, the parasitic diode formed by the p-type drift region 1 and the p-type semiconductor region 4 becomes difficult to operate.

[0054] This embodiment is particularly suitable for so-called SiC devices in which each semiconductor region contains silicon carbide. When each semiconductor region contains silicon carbide, crystal defects called basal plane dislocations exist in the silicon carbide crystal. When the parasitic diode operates, the basal plane dislocations become stacking faults due to the recombination energy of the injected electrons and holes, degrading the electrical characteristics of the semiconductor device. For example, an increase in leakage current and an increase in on-resistance may occur. According to this embodiment, the operation of the parasitic diode can be suppressed, so that the basal plane dislocations of silicon carbide can be suppressed from growing into stacking faults. The deterioration of the characteristics of the semiconductor device 100 can be suppressed, and the reliability of the semiconductor device 100 can be improved. In addition, by using silicon carbide in each semiconductor region, the breakdown voltage of each of the semiconductor device 100, the Schottky barrier diode D1, and the Schottky barrier diode D2 can be increased. The leakage current of the Schottky barrier diodes D1 and D2 can also be suppressed.

[0055] 8(a) and 8(b) are plan views showing another example of the semiconductor device according to the embodiment. As shown in FIG. 8(a), multiple second metal portions 22b may be arranged along the outer periphery of the p-type semiconductor region 4. The multiple second metal portions 22b are separated from each other. As shown in FIG. 8(b), multiple second metal portions 22b may be provided in the direction from the first portion 1a to the second portion 1b. Each second metal portion 22b surrounds multiple first metal portions 22a along the XY plane. In both of the examples shown in FIG. 8(a) and FIG. 8(b), directly below the second metal portion 22b, p - A shaped shielding area 5 is provided.

[0056] As shown in Figures 8(a) and 8(b), the arrangement of the second metal portion 22b can be changed as appropriate. More preferably, as shown in Figure 1 or 8(b), the second metal portion 22b surrounds a plurality of first metal portions 22a along the XY plane. This allows current to flow evenly around the periphery of the p-type semiconductor region 4 when the Schottky barrier diode D2 operates.

[0057] (First Modification) 9 and 10 are cross-sectional views showing a part of a semiconductor device according to a first modification of the embodiment. In the semiconductor device 100, p - The p-type shield region 5 is separated from the p-type semiconductor region 4. In the semiconductor device 110 or 120 according to the first modification, as shown in FIG. - The p-type shield region 5 is connected to the p-type semiconductor region 4. - The p-type shield region 5 is electrically connected to the source electrode 22 via the p-type semiconductor region 4. - The potential of the shape shield region 5 is substantially the same as the potential of the source electrode 22 .

[0058] As shown in Figure 9, - At the inner circumference of the shielding area 5, - The p-type shield region 5 may be connected to the p-type semiconductor region 4, or as shown in FIG. - On the outer side of the shielding area 5, - The p-type shield region 5 may be connected to the p-type semiconductor region 4. In either case, the third region r3 is connected to the fourth region r4.

[0059] According to the first variant, p - This makes it possible to prevent the potential of the shape shield region 5 from being in a floating state, and thus makes it possible to further stabilize the operation of the semiconductor device 110 or 120.

[0060] (Second Modification) FIG. 11 is a cross-sectional view showing a part of a semiconductor device according to a second modification of the embodiment. In the semiconductor device 130 shown in FIG. 11, the width of the third region r3 is wider than that of the third region r3 of the semiconductor device 100. The third region r3 is connected to the first region r1. - On the outer periphery of the shielding region 5, - A semiconductor region 5a is provided. - The semiconductor region 5a is p-shaped along the XY plane. - For example, a plurality of p- A semiconductor region 5a is provided, and each p - The semiconductor region 5a is p - The shaped shielding area 5 is surrounded by the conductor 4 .

[0061] By connecting the third region r3 to the first region r1, the electrical resistance in the lateral direction from the third region r3 to the first region r1 can be reduced. By reducing the electrical resistance, the voltage applied to the parasitic diode formed by the third region r3 and the p-type semiconductor region 4 is reduced. As a result, - The operation of the parasitic diode formed by the p-type drift region 1 and the p-type semiconductor region 4 can be further suppressed. - If the contact area between the third region r3 and the p-type semiconductor region 4 increases without the p-type shield region 5, the leakage current through the Schottky barrier diode D2 may increase. - The provision of the p-type shield region 5 makes it possible to suppress leakage current caused by an increase in the contact area between the third region r3 and the p-type semiconductor region 4. That is, according to the second modification, it is possible to suppress leakage current caused by an increase in the contact area between the third region r3 and the p-type semiconductor region 4, and furthermore to more reliably suppress the operation of the parasitic diode.

[0062] p - By providing the semiconductor region 5a, - At the height where the shaped shield region 5 is provided, the depletion layer can be spread further toward the periphery. - The electric field strength at the outer peripheral end of the shape shield region 5 can be reduced, and the breakdown voltage of the semiconductor device 130 can be increased.

[0063] Embodiments of the invention include the following features. (Feature 1) A first electrode; a first semiconductor region of a first conductivity type provided on the first electrode, the first semiconductor region including a first portion and a second portion provided around the first portion along a first surface perpendicular to a first direction from the first electrode toward the first portion; a second semiconductor region of a second conductivity type provided on the first portion; a third semiconductor region of the first conductivity type provided on the second semiconductor region; a gate electrode facing the second semiconductor region via a gate insulating layer; a fourth semiconductor region of a second conductivity type provided on the second portion and positioned around the second semiconductor region along the first surface; a first metal portion in contact with the first portion and the second semiconductor region and including at least one first element selected from the group consisting of titanium, molybdenum, and vanadium; a second metal portion in contact with the second portion and the fourth semiconductor region and containing the first element; a second electrode provided on the second semiconductor region, the third semiconductor region, and the fourth semiconductor region; a fifth semiconductor region of the second conductivity type provided below the fourth semiconductor region and positioned directly below the second metal portion; A semiconductor device comprising: (Feature 2) 2. The semiconductor device according to feature 1, wherein the fifth semiconductor region has a lower impurity concentration of the second conductivity type than the fourth semiconductor region. (Feature 3) 3. The semiconductor device according to feature 1 or 2, wherein the fifth semiconductor region is in contact with the fourth semiconductor region. (Feature 4) the second semiconductor region, the third semiconductor region, the gate electrode, and the first metal portion are each provided in a plurality of portions above the first portion in a second direction perpendicular to the first direction; the fourth semiconductor region is provided around a plurality of the second semiconductor regions along the first surface; 4. The semiconductor device according to any one of features 1 to 3, wherein the second metal portion is provided around a plurality of the first metal portions along the first surface. (Feature 5) the fourth semiconductor region is provided in a plurality of portions in a direction from the first portion toward the second portion, the second metal portion is in contact with the plurality of fourth semiconductor regions and a part of the second portion located between the plurality of fourth semiconductor regions; The semiconductor device of feature 4, wherein the fifth semiconductor region is located under the portion of the second portion. (Feature 6) The first portion is a first region in contact with the second semiconductor region and the first metal portion; a second region located between the first electrode and the first region; Including, 6. The semiconductor device according to any one of features 1 to 5, wherein a concentration of the first conductive type impurity in the first region is higher than a concentration of the first conductive type impurity in the second region. (Feature 7) The second portion is a third region that contacts the fourth semiconductor region and the second metal portion and is located between the fifth semiconductor region and the second metal portion; a fourth region located between the first electrode and the third region; Including, 7. The semiconductor device according to any one of features 1 to 6, wherein a concentration of the first conductive type impurity in the third region is higher than a concentration of the first conductive type impurity in the fourth region. (Feature 8) 8. The semiconductor device according to any one of features 1 to 7, wherein the first semiconductor region, the second semiconductor region, the third semiconductor region, the fourth semiconductor region, and the fifth semiconductor region contain silicon carbide.

[0064] In each of the embodiments described above, the relative level of the impurity concentration between each semiconductor region can be confirmed, for example, by using a scanning capacitance microscope (SCM). The carrier concentration in each semiconductor region can be considered to be equal to the concentration of the activated impurities in each semiconductor region. Therefore, the relative level of the carrier concentration between each semiconductor region can also be confirmed by using the SCM. The impurity concentration in each semiconductor region can also be measured, for example, by SIMS (secondary ion mass spectrometry).

[0065] Although some embodiments of the present invention have been illustrated above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, modifications, etc. can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are included in the scope of the invention and its equivalents described in the claims. In addition, the above-mentioned embodiments can be implemented in combination with each other. [Explanation of symbols]

[0066] 1:n - Shape drift region, 1a: first portion, 1b: second portion, 1x: n - type semiconductor layer, 1y,1z:n type semiconductor region, 2,2a,2b:p type base region, 2x:p type semiconductor region, 3:n + type source region, 4:p type semiconductor region, 4x:p type semiconductor region, 5:p - Shape shield area, 5a:p - shaped semiconductor region, 5x:p - Semiconductor area, 6:p - 7: n-type semiconductor region, 8: n + Shaped drain region, 8x:n + Semiconductor layer, 9a, 9b:p + contact region, 10: gate electrode, 11: gate insulating layer, 15: insulating layer, 21: drain electrode, 22: source electrode, 22a: first metal portion, 22b: second metal portion, 22c: silicide region, 22d: aluminum layer, 23: gate pad, 100-130: semiconductor device, D1, D2: Schottky barrier diodes, M1-M3: masks, r1: first region, r2: second region, r3: third region, r4: fourth region

Claims

1. A first electrode; a first semiconductor region of a first conductivity type provided on the first electrode, the first semiconductor region including a first portion and a second portion provided around the first portion along a first surface perpendicular to a first direction from the first electrode toward the first portion; a second semiconductor region of a second conductivity type provided on the first portion; a third semiconductor region of the first conductivity type provided on the second semiconductor region; a gate electrode facing the second semiconductor region via a gate insulating layer; a fourth semiconductor region of a second conductivity type provided on the second portion and positioned around the second semiconductor region along the first surface; a first metal portion in contact with the first portion and the second semiconductor region and containing at least one first element selected from the group consisting of titanium, molybdenum, and vanadium; a second metal portion in contact with the second portion and the fourth semiconductor region and containing the first element; a second electrode provided on the second semiconductor region, the third semiconductor region, and the fourth semiconductor region; a fifth semiconductor region of the second conductivity type provided below the fourth semiconductor region and located directly below the second metal portion; A semiconductor device comprising:

2. 2 . The semiconductor device according to claim 1 , wherein a concentration of the second conductive type impurity in said fifth semiconductor region is lower than a concentration of the second conductive type impurity in said fourth semiconductor region.

3. The semiconductor device according to claim 1 , wherein the fifth semiconductor region is in contact with the fourth semiconductor region.

4. the second semiconductor region, the third semiconductor region, the gate electrode, and the first metal portion are each provided in a plurality of portions above the first portion in a second direction perpendicular to the first direction; the fourth semiconductor region is provided around the second semiconductor regions along the first surface; The semiconductor device according to claim 1 , wherein the second metal portion is provided around a plurality of the first metal portions along the first surface.

5. The fourth semiconductor region is provided in a plurality of portions in a direction from the first portion toward the second portion, the second metal portion is in contact with the plurality of fourth semiconductor regions and a part of the second portion located between the plurality of fourth semiconductor regions; The semiconductor device according to claim 4 , wherein the fifth semiconductor region is located under the part of the second portion.

6. The first portion is a first region in contact with the second semiconductor region and the first metal portion; a second region located between the first electrode and the first region; Including, 3. The semiconductor device according to claim 1, wherein a concentration of the first conductive type impurity in said first region is higher than a concentration of the first conductive type impurity in said second region.

7. The second portion is a third region in contact with the fourth semiconductor region and the second metal portion and located between the fifth semiconductor region and the second metal portion; a fourth region located between the first electrode and the third region; Including, 3. The semiconductor device according to claim 1, wherein a concentration of the first conductive type impurity in said third region is higher than a concentration of the first conductive type impurity in said fourth region.

8. The semiconductor device according to claim 1 , wherein the first semiconductor region, the second semiconductor region, the third semiconductor region, the fourth semiconductor region, and the fifth semiconductor region contain silicon carbide.

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