Method for manufacturing semiconductor device and semiconductor device

Abstract

To provide a method for manufacturing a semiconductor device that is capable of shortening the time required to form a lifetime control region.SOLUTION: A method for manufacturing a semiconductor device includes forming a semiconductor portion having a transistor region and a diode region, forming a first lifetime control region at a lower portion of a semiconductor portion in the diode region by ions irradiated from above the semiconductor portion, and forming a second lifetime control region, simultaneously with the first life time region, at an upper portion of the semiconductor portion by ions irradiated from above through a mask such that the second lifetime control region does not overlap the first lifetime control region.SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] An embodiment of the present invention relates to a method for manufacturing a semiconductor device, and a semiconductor device. [Background technology]

[0002] One known semiconductor device is the RC (Reverse Conductive)-IGBT (Insulated Gate Bipolar Transistor). In the RC-IGBT, a transistor region in which an IGBT is provided and a diode region in which an FWD (Free Wheeling Diode) connected in inverse parallel to the IGBT are provided are formed on the same substrate. In other words, the IGBT and the FWD are formed on a single semiconductor chip.

[0003] The semiconductor device described above has technical issues, such as worsening recovery loss due to a tail current caused by accumulated carriers in the diode region during recovery operation of the FWD and parasitic diode operation that induces hole injection from the transistor region to the diode region during on-operation of the FWD.

[0004] In order to solve the above technical problems, a technique is known in which a lifetime control region is provided by generating lattice defects by irradiating ions into the transistor region and the diode region. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] International Publication No. 2021 / 251011 Summary of the Invention [Problem to be solved by the invention]

[0006] In order to reduce the tail current, it is effective to form a lifetime control region below the diode region. On the other hand, in order to suppress the parasitic diode operation, it is effective to form a lifetime control region above the boundary between the transistor region and the diode region. In this way, when multiple lifetime control regions are locally formed at different locations, multiple ion irradiations are required. Therefore, it takes a lot of time to form the lifetime control region.

[0007] An object of the present invention is to provide a semiconductor device and a manufacturing method thereof that are capable of shortening the time required for forming a lifetime control region. [Means for solving the problem]

[0008] A method for manufacturing a semiconductor device according to one embodiment includes forming a semiconductor portion having a transistor region and a diode region, forming a first lifetime control region in the lower part of the semiconductor portion in the diode region by ions irradiated from above the semiconductor portion, and simultaneously forming a second lifetime control region in the upper part of the semiconductor portion by ions irradiated from above through a mask so as not to overlap the first lifetime control region. [Brief description of the drawings]

[0009] [Figure 1] 1 is a cross-sectional view of the semiconductor device according to the first embodiment cut in the vertical direction. [Diagram 2] 5A to 5C are diagrams illustrating process flows before and after a lifetime control region forming process of the semiconductor device according to the first embodiment. [Diagram 3] 11A to 11C are cross-sectional views for explaining a surface element structure forming step. [Figure 4] 1 is a cross-sectional view illustrating a resist pattern forming step. [Diagram 5] FIG. 11 is a cross-sectional view for explaining a metal mask mounting step. [Figure 6] FIG. 11 is a cross-sectional view for explaining an ion irradiation step. [Figure 7] FIG. 11 is a cross-sectional view for explaining a back grinding step. [Figure 8] 11 is a cross-sectional view for explaining a back surface diffusion layer forming step. FIG. [Figure 9] FIG. 11 is a cross-sectional view illustrating a first electrode step. [Figure 10] 1 is a cross-sectional view of a semiconductor device according to a comparative example taken along a vertical direction; [Figure 11] 10A to 10C are cross-sectional views for explaining a first metal mask mounting step and a first ion irradiation step. [Figure 12] 11 is a cross-sectional view for explaining a second metal mask attaching step and a second ion irradiation step. FIG. [Figure 13] 10 is a cross-sectional view of the semiconductor device according to the second embodiment cut in the vertical direction. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, an embodiment of the present invention will be described with reference to the drawings, but the present invention is not limited to the embodiment.

[0011] (First embodiment) FIG. 1 is a cross-sectional view of the semiconductor device according to the first embodiment cut in the vertical direction. In the following description, the arrangement and configuration of each part of the semiconductor device may be described using the X-axis, Y-axis, and Z-axis shown in each figure. The X-axis, Y-axis, and Z-axis are mutually orthogonal and represent the X-direction, Y-direction, and Z-direction, respectively. In addition, the Z-direction may be described as upward and the opposite direction as downward. In this embodiment, the X-direction and the Y-direction correspond to the second direction and the third direction, respectively, and represent in-plane directions parallel to the front surface (or rear surface) of the semiconductor device 1. The Z-direction corresponds to the first direction and represents the out-of-plane direction perpendicular to the front surface (or rear surface) of the semiconductor device 1.

[0012] Also, p, p + The notation means that the p-type impurity concentration increases in this order. - , n, n +The notation indicates that the n-type impurity concentration increases in this order.

[0013] The impurity concentration can be measured by, for example, SIMS (Secondary Ion Mass Spectrometry). The relative level of the impurity concentration can also be determined from the level of the carrier concentration obtained by, for example, SCM (Scanning Capacitance Microscopy). The distance, such as the depth of the semiconductor region, can also be obtained by, for example, SIMS.

[0014] The semiconductor device 1 shown in FIG. 1 is an RC-IGBT. The semiconductor device 1 includes a first electrode 10, a second electrode 20, and a semiconductor section 30. The semiconductor section 30 includes a transistor region 30a in which a transistor element such as an IGBT is provided, and a diode region 30b in which a diode element such as an FWD is provided. The transistor region 30a and the diode region 30b are alternately arranged along the x direction. Note that a separation region in which neither a transistor element nor a diode element is provided may be provided between the transistor region 30a and the diode region 30b.

[0015] The first electrode 10 is provided on the back surface of the semiconductor portion 30. The first electrode 10 can be formed using a metal such as aluminum. The first electrode 10 functions as a collector electrode in the transistor region 30a, and functions as a cathode electrode in the diode region 30b.

[0016] The second electrode 20 faces the first electrode in the Z direction across the semiconductor portion 30. The second electrode can be formed using a metal such as aluminum. The second electrode 20 functions as an emitter electrode in the transistor region 30a and as an anode electrode in the diode region 30b.

[0017] The semiconductor portion 30 is p + Collector region 31, n + Cathode region 32, n buffer region 33, n -Base region 34, p base region 35, p anode region 36, n + The semiconductor device includes an emitter region 37, a gate electrode 38, and a gate insulating film 39. + The collector region 31 corresponds to a p-type third semiconductor region. + The cathode region 32 corresponds to an n-type fourth semiconductor region. The n-buffer region 33 corresponds to an n-type second semiconductor region. - The base region 34 corresponds to an n-type first semiconductor region.

[0018] p + The collector region 31 is provided on the first electrode 10 in the transistor region 30a. + The cathode region 32 is provided on the first electrode 10 in the diode region 30b. + The thickness of the cathode region 32 is p + The thickness of the collector region 31 is approximately the same as that of the collector region 31. That is, n + Cathode region 32 and p + The collector regions 31 are formed in layers that are the same in depth from the surface of the semiconductor portion 30. However, n + The thickness of the cathode region 32 is p + It is not necessary that the thickness is the same as that of the collector region 31, but it may be different.

[0019] The n buffer area 33 is + On the collector region 31 and + The n-type buffer region 33 is provided on the cathode region 32. - A base region 34 is provided.

[0020] n - The base region 34 is provided with a first lifetime control region 41 and a second lifetime control region 42. Each of the first lifetime control region 41 and the second lifetime control region 42 has lattice defects formed therein that function as lifetime killers.

[0021] The first lifetime control region 41 is n -The second lifetime control region 42 is disposed below the base region 34, in other words, at the boundary with the n buffer region 33. - It is provided above the base region 34, at the boundary between the transistor region 30a and the diode region 30b.

[0022] The first lifetime control region 41 and the second lifetime control region 42 are formed by irradiating hydrogen ions, helium ions, or the like. At this time, in order to simultaneously form the first lifetime control region 41 and the second lifetime control region 42, these two lifetime control regions are formed so as not to overlap in the Z direction. In other words, the first lifetime control region 41 and the second lifetime control region 42 are formed so as to be shifted from each other in the X direction.

[0023] n located in the transistor region 30a - A p-type base region 35 is provided on the base region 34. In addition, an n-type - A p-anode region 36 is provided on the base region 34. In this embodiment, the p-type impurity concentration contained in the p-base region 35 is the same as the p-type impurity concentration contained in the p-anode region 36. However, the p-type impurity concentrations do not need to be the same between the p-base region 35 and the p-anode region 36, and may be different. The p-base region 35 and the p-anode region 36 having different p-type impurity concentrations can be formed, for example, by separate ion implantation.

[0024] In this embodiment, the thickness of the p base region 35 is greater than the thickness of the p anode region 36. In other words, the p base region 35 is formed to a position deeper from the surface of the semiconductor portion 30 than the p anode region 36. However, the thickness of the p base region 35 does not need to be greater than the thickness of the p anode region 36, and may be the same as or smaller than the thickness of the p anode region 36.

[0025] The p base region 35 has n + The emitter region 37 is in contact with+ The emitter region 37 is in contact with the second electrode 20. When the voltage between the gate electrode 38 and the second electrode 20 (emitter electrode) becomes equal to or higher than the threshold voltage, an n-channel is formed in the p-base region 35. As a result, in the transistor region 30a, + From the collector region 31 through the n-channel + A current path is created to the emitter region 37 .

[0026] The gate electrode 38 is connected to the p-base region 35 and the n-type base region 36 via a gate insulating film 39. + The gate electrode 38 faces the emitter region 37. The gate electrode 38 can be formed of, for example, polysilicon. The gate insulating film 39 is, for example, a silicon oxide film (SiO2).

[0027] In this embodiment, the gate electrode 38 and the gate insulating film 39 are provided not only in the transistor region 30a but also in the diode region 30b. + There is no emitter region 37. Therefore, the gate electrode 38 provided in the diode region 30b is a dummy gate electrode.

[0028] In the semiconductor device 1, if the tail current due to the accumulated carriers in the diode region 30b is large during the recovery operation of the FWD, the recovery loss of the FWD increases. - A first lifetime control region 41 is formed below the base region 34. Since lattice defects, which are lifetime killers, are formed in the first lifetime control region 41, it is possible to reduce the tail current. This makes it possible to reduce the recovery loss.

[0029] In the semiconductor device 1, when the FWD is turned on, the p-type base region 35 of the transistor region 30a and the n-type base region 30b of the diode region 30b are +When the cathode region 32 operates as a parasitic diode, holes are injected from the transistor region 30a to the diode region 30b. As a result, the recovery loss of the FWD may worsen. Therefore, in this embodiment, the n - The second lifetime control region 42 is formed on the upper part of the base region 34. Since the second lifetime control region 42 also has lattice defects, which are lifetime killers, the operation of the parasitic diode can be suppressed. This makes it possible to reduce recovery loss. If the second lifetime control region 42 is formed on the surface of the transistor region 30a, the on-characteristics of the IGBT may deteriorate. Furthermore, the gate threshold voltage (Vth) may vary due to damage to the gate insulating film 39 during the formation of the second lifetime control region 42. Therefore, in this embodiment, the formation region of the second lifetime control region 42 is limited to the surface of the boundary between the transistor region 30a and the diode region 30b. This makes it possible to suppress the parasitic diode operation while suppressing disadvantages such as deterioration of the on-characteristics of the IGBT and fluctuations in the gate threshold voltage (Vth).

[0030] 2 to 9, a method for manufacturing the semiconductor device 1 according to this embodiment will be described. Here, a lifetime control region forming step for forming the first lifetime control region 41 and the second lifetime control region 42, and manufacturing steps before and after the lifetime control region forming step will be mainly described.

[0031] 2 is a diagram showing a process flow before and after a lifetime control region forming process of the semiconductor device 1 according to this embodiment. As shown in FIG. 2, before the lifetime control region forming process (step S2), there is a front surface element structure forming process (step S1). After the lifetime control region forming process, there is a back surface element structure forming process (step S3). After the back surface element structure forming process (step S3), there is a dicing process (step S4).

[0032] 3 is a cross-sectional view for explaining a surface element structure forming step. In the surface element structure forming step, first, n - The base region 34 is formed.

[0033] Next, in the transistor region 30a, - On the base region 34, a p base region 35, an n + An emitter region 37, a gate electrode 38, and a gate insulating film 39 are formed in sequence. - A p-anode region 36, a gate electrode 38, and a gate insulating film 39 are formed in this order on the base region 34. However, the gate electrode 38 formed in the diode region 30b is a dummy gate electrode.

[0034] Finally, the second electrode 20 is formed. The p-base region 35 to the gate insulating film 39 and the second electrode 20 can be formed by a commonly used manufacturing method, and therefore a detailed description thereof will be omitted.

[0035] Next, the lifetime control region forming process will be described. The lifetime control region forming process includes a resist pattern forming process, a metal mask mounting process, and an ion irradiation process.

[0036] 4 is a cross-sectional view for explaining the resist pattern forming process. In the resist pattern forming process, first, the resist 40 is applied to the entire upper surface of the second electrode 20. Then, the resist 40 applied to the region of the upper surface of the second electrode 20 facing the boundary between the transistor region 30a and the diode region 30b and the resist 40 applied to the region facing the diode region 30b are removed by exposure and development. As a result, as shown in FIG. 4, a pattern of the resist 40 is formed so as to expose the region facing the boundary between the transistor region 30a and the diode region 30b and the region facing the diode region 30b.

[0037] 5 is a cross-sectional view for explaining the metal mask attachment step. In the metal mask attachment step, a metal mask 50 is placed above the resist 40. The metal mask 50 contains, for example, aluminum or nickel.

[0038] The metal mask 50 is patterned so as to shield the area where the second lifetime control region 42 is to be formed, while exposing the area where the first lifetime control region 41 is to be formed. The thickness of the metal mask 50 is designed to a value that allows ions irradiated in the subsequent ion irradiation process to remain in the area where the second lifetime control region 42 is to be formed.

[0039] 6 is a cross-sectional view for explaining the ion irradiation process. In the ion irradiation process, ions including hydrogen or helium are irradiated from above the metal mask 50 at n - The base region 34 is irradiated with the laser beam. - In the exposed portion of the base region 34 that is not shielded by the metal mask 50, the ions irradiated are n - This reaches a position at a predetermined depth in the base region 34. As a result, the first lifetime control region 41 is formed.

[0040] Also, n - In the portion of the base region 34 that is shielded only by the metal mask 50, i.e., the boundary portion between the transistor region 30a and the diode region 30b, the irradiated ions are n - It reaches the upper part of the base region 34. As a result, the second lifetime control region 42 and the first lifetime control region 41 are formed at the same time.

[0041] In addition, n - The irradiated ions do not reach the areas of the base region 34 that are shielded by both the resist 40 and the metal mask 50. After the ion irradiation step, the resist 40 is peeled off. This completes the lifetime control region formation step.

[0042] Next, the back surface element structure forming process will be described. The back surface element structure forming process includes a back surface grinding process, a back surface diffusion layer forming process, and a first electrode process.

[0043] FIG. 7 is a cross-sectional view for explaining the back grinding process. In the back grinding process, n - The base region 34 is ground from its back surface. As a result, the first lifetime control region 41 is - It is located below the base region 34 .

[0044] 8 is a cross-sectional view for explaining the back diffusion layer forming step. In the back diffusion layer forming step, n - An n-buffer region 33 is formed under the base region 34. Then, in the transistor region 30a, a p + A collector region 31 is formed. On the other hand, in the diode region 30b, an n-type + The cathode region 32 is formed. + Collector region 31, n + The cathode region 32 and the n-buffer region 33 can be formed by a commonly used manufacturing method, and therefore a detailed description thereof will be omitted.

[0045] 9 is a cross-sectional view for explaining the first electrode step. In the first electrode step, the first electrode 10 is + Under the collector region 31 and + It is formed under the cathode region 32. This completes the back surface device structure formation process.

[0046] In the final dicing step, a blade is used to cut the semiconductor wafer 11 shown in Fig. 9 into a lattice pattern, resulting in the semiconductor wafer 11 being divided into a plurality of semiconductor chips.

[0047] Here, a comparative example to be compared with this embodiment will be described.

[0048] Fig. 10 is a vertical cross-sectional view of a semiconductor device according to a comparative example, in which the same components as those in the semiconductor device 1 described above are denoted by the same reference numerals, and duplicated explanations will be omitted.

[0049] In the semiconductor device 100 according to this comparative example, the first lifetime control region 41 and the second lifetime control region 42 overlap in the Z direction as shown in Fig. 10. Therefore, the first lifetime control region 41 and the second lifetime control region 42 of the comparative example cannot be formed simultaneously. The lifetime control region forming process according to the comparative example will be described below.

[0050] The lifetime control region forming process according to the comparative example is comprised of a first metal mask mounting step, a first ion irradiation step, a second metal mask mounting step, and a second ion irradiation step.

[0051] FIG. 11 is a cross-sectional view for illustrating the first metal mask attaching step and the first ion irradiation step.

[0052] In the first metal mask attachment step, a first metal mask 51 is placed above the second electrode 20. The first metal mask 51 shields the transistor region 30a while exposing the diode region 30b. The thickness of the first metal mask 51 is designed to a value that does not allow the passage of ions irradiated in the subsequent first ion irradiation step.

[0053] In the first ion irradiation step, ions containing hydrogen or helium are irradiated from above the first metal mask 51. - The base region 34 is irradiated with the laser beam. - In the exposed portion of the base region 34 that is not shielded by the metal mask 50, i.e., the diode region 30b, the irradiated ions are - It reaches a position at a predetermined depth in the base region 34. As a result, the first lifetime control region 41 according to the comparative example is formed.

[0054] FIG. 12 is a cross-sectional view for illustrating the second metal mask attaching step and the second ion irradiation step.

[0055] In the second metal mask attachment step, the second metal mask 52 is placed above the second electrode 20. The second metal mask 52 shields the area except for the boundary between the transistor region 30a and the diode region 30b. The thickness of the second metal mask 52 is designed to a value that does not allow the passage of ions irradiated in the subsequent second ion irradiation step.

[0056] In the second ion irradiation step, ions containing hydrogen or helium are irradiated from above the second metal mask 52. - The ions are irradiated toward the base region 34. At this time, the ions are - The light is irradiated so as to reach the exposed portion of the base region 34 that is not shielded by the second metal mask 52, i.e., the upper portion of the boundary portion between the transistor region 30a and the diode region 30b. As a result, the second lifetime control region 42 according to the comparative example is formed.

[0057] The lifetime control region forming process according to this comparative example requires two metal masks, a first metal mask 51 and a second metal mask 52, and two ion irradiation processes, a first ion irradiation process and a second ion irradiation process. Therefore, it takes a long time to form the first lifetime control region 41 and the second lifetime control region 42. As a result, the process cost is high.

[0058] In contrast, in this embodiment, a metal mask 50 that is thinned to reduce its shielding ability so that ions can pass through is used in combination with the resist 40. This makes it possible to simultaneously form the first lifetime control region 41 and the second lifetime control region 42 using one metal mask 50 and one ion irradiation. This makes it possible to shorten the time required for the lifetime control region formation process, and as a result, reduce process costs.

[0059] Second embodiment Fig. 13 is a vertical cross-sectional view of the semiconductor device according to the second embodiment. In Fig. 13, the same components as those in the semiconductor device 1 according to the first embodiment are denoted by the same reference numerals, and duplicated explanations will be omitted.

[0060] In the semiconductor portion 30 of the semiconductor device 2 shown in FIG. 13, an isolation region 30c is provided between the transistor region 30a and the diode region 30b. In the isolation region 30c, an n-buffer region 33, an n-type buffer region 34, and an n-type diode region 30b are provided. - A base region 34 and a p-anode region 36 are laminated in this order between the first electrode 10 and the second electrode 20.

[0061] In addition, n of the isolation region 30c - A gate electrode 38 and a gate insulating film 39 are provided on the base region 34 and the p anode region 36. However, this gate electrode 38 is a dummy gate electrode, similar to the gate electrode 38 provided in the diode region 30b.

[0062] Furthermore, in the semiconductor device 2 according to this embodiment, the first lifetime control region 41 is a n - It is provided below the base region 34. This first lifetime control region 41 can reduce the tail current due to accumulated carriers in the diode region 30b during the recovery operation of the FWD.

[0063] On the other hand, the second lifetime control region 42 is n - The n-type junction between the upper portion of the base region 34 and the boundary between the isolation region 30c and the transistor region 30a - It is provided across the upper part of the base region 34. This second lifetime control region 42 can suppress the operation of a parasitic diode during the on-operation of the FWD.

[0064] In this embodiment, similarly to the first embodiment, the first lifetime control region 41 and the second lifetime control region 42 are arranged offset from each other in the X direction and do not overlap in the Z direction. Therefore, similarly to the first embodiment, by using a metal mask 50 and a resist 40 in combination, the first lifetime control region 41 and the second lifetime control region 42 can be formed simultaneously by one metal mask 50 and one ion irradiation.

[0065] Therefore, according to this embodiment, it is possible to shorten the process time for forming the lifetime control region, and as a result, the process cost can be reduced.

[0066] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope of the invention and its equivalents described in the claims, as well as in the scope and spirit of the invention. [Explanation of symbols]

[0067] 1: Semiconductor device 10: 1st electrode 20:Second electrode 30: Semiconductor Division 30a: Transistor area 30b: Diode region 30c: Separation area 31:p + Collector region (third semiconductor region) 32:n + Cathode region (fourth semiconductor region) 33:n buffer region (second semiconductor region) 34:n - Base region (first semiconductor region) 40: Resist 41: First lifetime control region 42: Second lifetime control region 50: Metal Mask

Claims

1. forming a semiconductor portion having a transistor region and a diode region; forming a first lifetime control region below the semiconductor portion in the diode region by ions irradiated from above the semiconductor portion; A method for manufacturing a semiconductor device, comprising: forming a second lifetime control region and a first lifetime control region simultaneously on the upper part of the semiconductor portion by ions irradiated from above the semiconductor portion through a mask so as not to overlap the first lifetime control region.

2. 2. The method for manufacturing a semiconductor device according to claim 1, wherein said second lifetime control region is formed above a boundary portion between said transistor region and said diode region.

3. forming an isolation region between the transistor region and the diode region; 2. The method for manufacturing a semiconductor device according to claim 1, wherein said second lifetime control region is formed above a boundary portion between said transistor region and said isolation region.

4. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the first lifetime control region and the second lifetime control region are formed in a state where a resist that does not allow the ions to pass therethrough is disposed between the transistor region and the mask.

5. 3. The method for manufacturing a semiconductor device according to claim 1, wherein the mask is a metal mask containing aluminum or nickel.

6. 3. The method for manufacturing a semiconductor device according to claim 1, wherein the ions are hydrogen ions or helium ions.

7. 3 . The method for manufacturing a semiconductor device according to claim 1 , further comprising forming the first lifetime control region and the second lifetime control region in an n-type first semiconductor region of the semiconductor portion.

8. After forming the first lifetime control region and the second lifetime control region, forming an n-type second semiconductor region under the first semiconductor region; forming a p-type third semiconductor region below the second semiconductor region in the transistor region; forming an n-type fourth semiconductor region below the second semiconductor region in the diode region; The method for manufacturing a semiconductor device according to claim 7 , further comprising forming a first electrode below said third semiconductor region and below said fourth semiconductor region.

9. 9. The method for manufacturing a semiconductor device according to claim 8, wherein the first lifetime control region and the second lifetime control region are formed in a state in which a second electrode is formed on the semiconductor portion.

10. 3. The method for manufacturing a semiconductor device according to claim 1, further comprising forming an IGBT (Insulated Gate Bipolar Transistor) in the transistor region, and forming an FWD (Free Wheeling Diode) in the diode region.

11. A first electrode; a second electrode facing the first electrode in a first direction; a semiconductor portion provided between the first electrode and the second electrode and having a transistor region and a diode region; a first lifetime control region provided below the diode region; a second lifetime control region provided on an upper portion of the semiconductor portion so as not to overlap with the first lifetime control region in the first direction.

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