Manufacturing method of semiconductor device and semiconductor device

Abstract

To provide a semiconductor device manufacturing method capable of suppressing dimensional and shape variations of voids, and a semiconductor device manufactured by the manufacturing method.SOLUTION: In a manufacturing method for a semiconductor device according to an embodiment, an opening is formed in an upper surface of a first semiconductor region of a first conductivity type. In the manufacturing method, a first insulating layer is formed in an upper portion of the opening to close the opening, thereby forming a gap in a lower portion of the opening by an atomic layer deposition method. In the atomic layer deposition method, adsorption of an inhibitor to an inner surface of a lower portion of the opening or termination of dangling bonds of a semiconductor material present on the inner surface of the lower portion and adsorption of a precursor to an inner surface of an upper portion of the opening are repeatedly performed.SELECTED DRAWING: Figure 7

Description

[Technical field]

[0001] An embodiment of the present invention relates to a method for manufacturing a semiconductor device and a semiconductor device. [Background technology]

[0002] There is a semiconductor device having a void formed therein. For this semiconductor device, there is a demand for a technique that can suppress variations in the size and shape of the void. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2017-162909 A Summary of the Invention [Problem to be solved by the invention]

[0004] An embodiment of the present invention provides a method for manufacturing a semiconductor device that can suppress variations in size and shape of a gap, and also provides a semiconductor device manufactured by the manufacturing method. [Means for solving the problem]

[0005] In a method for manufacturing a semiconductor device according to an embodiment, an opening is formed in an upper surface of a first semiconductor region of a first conductivity type. In the method, a first insulating layer is formed by atomic layer deposition over the upper portion of the opening to close the opening, thereby forming a gap in the lower portion of the opening. In the atomic layer deposition, adsorption of an inhibitor onto the inner surface of the lower portion of the opening or termination of dangling bonds of a semiconductor material present on the inner surface of the lower portion and adsorption of a precursor onto the inner surface of the upper portion of the opening are repeatedly performed. [Brief description of the drawings]

[0006] [Figure 1]FIG. 1 is a plan view showing a semiconductor device manufactured by a manufacturing method according to an embodiment. [Diagram 2] FIG. 2 is a plan view showing the semiconductor device manufactured by the manufacturing method according to the embodiment. [Diagram 3] FIG. 3 is a plan view showing a semiconductor device manufactured by the manufacturing method according to the embodiment. [Figure 4] Fig. 4(a) is a cross-sectional view taken along line AA' in Fig. 2 and Fig. 3. Fig. 4(b) is a cross-sectional view taken along line BB' in Fig. 2 and Fig. 3. [Diagram 5] FIG. 5 is a cross-sectional view taken along the line CC' in FIGS. [Figure 6] 6(a) to 6(d) are cross-sectional views showing the steps of a method for manufacturing a semiconductor device according to the embodiment. [Figure 7] 7(a) to 7(d) are cross-sectional views showing the steps of a method for manufacturing a semiconductor device according to the embodiment. [Figure 8] 8(a) to 8(d) are cross-sectional views showing the steps of a method for manufacturing a semiconductor device according to the embodiment. [Figure 9] 9(a) to 9(d) are cross-sectional views showing the steps of a method for manufacturing a semiconductor device according to the embodiment. [Figure 10] 10A and 10B are cross-sectional views illustrating the steps of a method for manufacturing a semiconductor device according to the embodiment. [Figure 11] 11(a) to 11(f) are cross-sectional views illustrating steps in a manufacturing method according to a modified example of the embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, each embodiment of the present invention will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as the actual ones. Even when the same part is shown, the dimensions and ratios of each part may be different depending on the drawing. In this specification and each drawing, elements similar to those already explained are given the same reference numerals, and detailed explanations are omitted as appropriate. In the following description, n + , n - and p + The notation p indicates the relative impurity concentration in each conductivity type. + is - This indicates that the n-type impurity concentration is relatively higher than that of p + indicates that the p-type impurity concentration is relatively higher than p. When both p-type and n-type impurities are contained in each region, these notations represent the relative levels of the net impurity concentration after the impurities compensate for each other. In each embodiment described below, the p-type and n-type of each semiconductor region may be reversed to implement each embodiment.

[0008] (Semiconductor Device) Figures 1 to 3 are plan views showing a semiconductor device manufactured by a manufacturing method according to an embodiment. Figure 4(a) is a cross-sectional view taken along line A-A' in Figures 2 and 3. Figure 4(b) is a cross-sectional view taken along line B-B' in Figures 2 and 3. Figure 5 is a cross-sectional view taken along line C-C' in Figures 2 and 3.

[0009] The semiconductor device 100 shown in FIGS. 1 to 5 is a MOSFET. - p-type (first conductivity type) drift region 1 (first semiconductor region), p-type (second conductivity type) base region 2 (second semiconductor region), n + Source region 3 (third semiconductor region), p + Contact area 4, n + The field plate electrode (hereinafter, referred to as FP electrode) 10 includes a drain region 5, an FP electrode 10 (conductive portion), an insulating layer 11, a gate electrode 20, a gate insulating layer 21, an insulating layer 25, a drain electrode 31 (first electrode), a source electrode 32 (second electrode), a gate pad 33, and a wiring portion 33a. In Fig. 2, the insulating layer 25, the source electrode 32, and the wiring portion 33a are each partially transparent in order to show the gate electrode 20. In Fig. 3, the gate electrode 20, the insulating layer 25, the source electrode 32, and the wiring portion 33a are each partially transparent in order to show the field plate electrode (hereinafter, referred to as FP electrode) 10.

[0010] In the description of the embodiment, an XYZ orthogonal coordinate system is used. - The direction toward the drift region 1 is defined as the Z direction (first direction). Two directions that are perpendicular to the Z direction and perpendicular to each other are defined as the X direction (third direction) and the Y direction (second direction). - The direction toward the n-type drift region 1 is called "up" and the opposite direction is called "down." These directions are - The shape is based on the relative position to the drift region 1 and is independent of the direction of gravity.

[0011] 1, the source electrode 32 and the gate pad 33 are provided on the upper surface of the semiconductor device 100. The source electrode 32 and the gate pad 33 are separated from each other and electrically isolated. A wiring portion 33a is electrically connected to the gate pad 33. The wiring portion 33a is provided around the source electrode 32. The upper surface of the semiconductor device 100 is covered with an insulating layer 25 except for the source electrode 32, the gate pad 33, and the wiring portion 33a.

[0012] 2, a plurality of gate electrodes 20 are provided in the X and Y directions, each extending in the Y direction. In addition, the end of each gate electrode 20 in the Y direction is electrically connected to the wiring portion 33a via a connection portion C1.

[0013] A part of the FP electrode 10 is provided under the gate electrode 20. As shown in Fig. 3, a plurality of FP electrodes 10 are provided in the X direction and the Y direction, and each extends in the Y direction. In addition, the end of the FP electrode 10 in the Y direction is electrically connected to the source electrode 32 via a connection part C2.

[0014] As shown in FIGS. 4(a), 4(b), and 5, a drain electrode 31 is provided on the bottom surface of the semiconductor device 100. + The drain region 5 is provided on the drain electrode 31 and is electrically connected to the drain electrode 31. - The drift region 1 is n+ The n-type drain region 5 is provided on the n-type drain region 5. - The n-type impurity concentration of the n-type drift region 1 is + The n-type impurity concentration of the n-type drain region 5 is lower than that of the n-type drain region 5 .

[0015] The FP electrode 10 is connected to the n - The FP electrode 10 is provided in the drift region 1. The FP electrode 10 includes a first conductive portion 10a and a second conductive portion 10b. The first conductive portion 10a is located under the gate electrode 20 and extends in the Y direction. The second conductive portion 10b is located at an end of the FP electrode 10 in the Y direction and is connected to a connection portion C2 of the source electrode 32. The length in the Z direction of the second conductive portion 10b is longer than the length in the Z direction of the first conductive portion 10a.

[0016] The insulating layer 11 is provided around the upper part of the first conductive portion 10a and is located above the gap G. The gate electrode 20 is provided on the first conductive portion 10a with the insulating layer 11 interposed therebetween.

[0017] As shown in FIG. 4(a), the p-type base region 2 is - The p-type base region 2 faces the gate electrode 20 via the gate insulating layer 21 in the X direction. + Shape source region 3 and p + The p-type contact region 4 is provided on the p-type base region 2 .

[0018] The source electrode 32 is + Shape source region 3 and p + The source electrode 32 is located on the n-type contact region 4 and is electrically connected to these semiconductor regions. + The source region 3 is aligned in the X direction. + The contact region 4 is provided under that part of the source electrode 32. An insulating layer 25 is provided between the gate electrode 20 and the source electrode 32, and these electrodes are electrically separated from each other.

[0019] The operation of the semiconductor device 100 will now be described. When a voltage equal to or higher than the threshold is applied to the gate electrode 20, a channel (inversion layer) is formed in the vicinity of the gate insulating layer 21 of the p-type base region 2. When a channel is formed with a positive voltage applied to the drain electrode 31 with respect to the source electrode 32, electrons pass through the channel and are transported from the source electrode 32 to the n-type - The electrons flow into the drift region 1. This causes the semiconductor device 100 to be turned on.

[0020] Thereafter, when the voltage applied to the gate electrode 20 becomes less than the threshold, the semiconductor device 100 is turned off. When the semiconductor device 100 is switched from the on state to the off state, n - The pn junction between the p-type drift region 1 and the p-type base region 2 is - The depletion layer expands toward the drift region 1. At the same time, the potential difference between the FP electrode 10 and the drain electrode 31 causes the gap G and - The interface with the drift region 1 also has n - The depletion layer spreads toward the n-type drift region 1. - By promoting the depletion of the drift region 1, the breakdown voltage of the semiconductor device can be improved. - This makes it possible to increase the n-type impurity concentration in the n-type drift region 1, thereby reducing the on-resistance of the semiconductor device.

[0021] An example of the material of each component will be described. n - p-type drift region 1, p-type base region 2, n + Shape source area 3, p + shaped contact region 4, and n +The FP drain region 5 includes silicon, silicon carbide, gallium nitride, or gallium arsenide as a semiconductor material. When silicon is used as the semiconductor material, arsenic, phosphorus, or antimony can be used as an n-type impurity. Boron can be used as a p-type impurity. The FP electrode 10 and the gate electrode 20 include a conductive material such as polysilicon. The insulating layer 11, the gate insulating layer 21, and the insulating layer 25 include an insulating material such as silicon oxide or silicon nitride. The drain electrode 31, the source electrode 32, the gate pad 33, and the wiring portion 33a include a metal material such as titanium or aluminum.

[0022] (Manufacturing method) 6(a) to 10(b) are cross-sectional views showing the steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention. In each of Fig. 6(a) to 10(b), the left side shows the steps of a manufacturing process at a portion of the position indicated by line A-A' in Fig. 3, and the right side shows the steps of a manufacturing process at a portion of the position indicated by line B-B' in Fig. 3.

[0023] First, n + Semiconductor layers 5a and n - A semiconductor substrate including a semiconductor layer 1a is prepared. - The semiconductor layer 1a is + As shown in FIG. - A plurality of openings OP1 extending in the Y direction are formed on the upper surface of the shaped semiconductor layer 1a. As shown in FIG. 6(b), a first layer L1 is formed along the inner surface of the opening OP1. The material of the first layer L1 is arbitrary as long as it is different from the material of the insulating layer IL1 described later. For example, the first layer L1 is silicon nitride formed by chemical vapor deposition (CVD). Alternatively, the first layer L1 is n - It may be a silicon oxide layer formed by thermal oxidation of the insulating semiconductor layer 1a.

[0024] A conductive layer is formed on the first layer L1. The conductive layer is etched to form an FP electrode 10 including a first conductive portion 10a and a second conductive portion 10b, as shown in FIG. 6(c). A part of the first layer L1 is removed by wet etching so that the upper end of the first layer L1 around the first conductive portion 10a is positioned lower than the upper end of the first conductive portion 10a, as shown in FIG. 6(d). In the illustrated example, the first layer L1 is removed except for the bottom of the opening OP1.

[0025] After that, an insulating layer is formed on the FP electrode 10 by atomic layer deposition (ALD). Specifically, ALD includes the steps shown in Fig. 7(a) to Fig. 7(d). First, as shown in Fig. 7(a), particles called inhibitors are attached to the inner surface of the opening OP1 and the surface of the FP electrode 10. The inhibitors i suppress the attachment of precursors, which will be described later, to the inner surface of the opening OP1. Self-assembled monolayers (SAMs) or small molecule inhibitors (SMIs) can be used as the inhibitors i.

[0026] The semiconductor substrate with the inhibitor i attached thereto is exposed to plasma of an inert gas. The plasma removes a portion of the attached inhibitor i. At this time, the plasma does not easily enter the lower portion of the opening OP1. As a result, as shown in FIG. 7(b), the inhibitor i attached to the inner surface of the upper portion of the opening OP1 and the upper surface of the FP electrode 10 is removed.

[0027] Next, a precursor p is supplied to the semiconductor substrate. The precursor p does not adhere to the surface to which the inhibitor i is adhered. Therefore, as shown in FIG. 7(c), the precursor p selectively adheres to the inner surface at the top of the opening OP1 and the upper surface of the FP electrode 10. When silicon oxide is formed by ALD, a Si-containing component such as trisdimethylaminosilane (TDMAS), Orthrus (registered trademark) manufactured by Air Liquid, or bisdiethylaminosilane (SAM24) can be used as a precursor. Then, a gas that reacts with the precursor is supplied to the semiconductor substrate. When silicon oxide is formed, an oxygen-containing gas is used. When silicon nitride is formed, a nitrogen-containing gas is used. The precursor reacts with the gas to form an insulating thin film F.

[0028] As shown in Fig. 7(d), the inhibitor i attached to the inner surface of the opening OP1 and the surface of the FP electrode 10 is removed. For example, the inhibitor i is removed by reducing the pressure in the processing chamber in which the semiconductor substrate is placed. Thereafter, the process shown in Fig. 7(a) is performed again. In the process shown in Fig. 7(b), the inhibitor i attached to the thin film F is removed.

[0029] If the attached inhibitor i is still functional after the thin film F is formed, the steps shown in Figures 7(a) and 7(b) may be omitted and the step shown in Figure 7(c) may be performed. In that case, the steps shown in Figures 7(a) and 7(b) are appropriately performed when the function of the inhibitor i is reduced.

[0030] By repeating the steps shown in FIG. 7(a) to FIG. 7(d), the thin film F gradually becomes thicker. As a result, as shown in FIG. 8(a), an insulating layer IL1 (first insulating layer) is formed. The upper part of the opening OP1 is blocked by the insulating layer IL1. The insulating layer IL1 is separated from the first layer L1 in the Z direction, and a gap G is formed between the first layer L1 and the insulating layer IL1. If the width of the opening OP1 is wide and it is difficult to block the opening OP1 by ALD alone, CVD may be performed after ALD. Since the width of the opening OP1 is narrowed by ALD, the opening OP1 can be blocked with good controllability even when CVD is used.

[0031] Instead of using the inhibitor i, dangling bonds of the semiconductor material present on the inner surface below the opening OP1, the side surface of the FP electrode 10, and the bottom surface of the FP electrode 10 may be terminated. By terminating the dangling bonds, the precursor p does not adhere to the inner surface below the opening OP1. As a result, similar to the case where the inhibitor i is used, the insulating layer IL1 is not formed on the inner surface below the opening OP1, the side surface of the FP electrode 10, and the bottom surface of the FP electrode 10.

[0032] For example, after the process shown in FIG. 6(d) is performed, the surface of the opening OP1 and the surface of the FP electrode 10 are exposed to nitrogen plasma or hydrogen plasma. This terminates the dangling bonds of the semiconductor material (e.g., silicon) present on these surfaces. Then, an etching gas is supplied to the processing chamber in which the semiconductor substrate is placed. At this time, the concentration of the etching gas is set low, or the etching gas is supplied for only a short time. As a result, the nitrogen gas or hydrogen gas attached to the inner surface of the upper part of the opening OP1 and the upper surface of the FP electrode 10 is desorbed. The state in which the dangling bonds of silicon are terminated is maintained on the inner surface of the lower part of the opening OP1 and the side surface of the FP electrode 10. Then, similarly to the process shown in FIG. 7(c), a precursor p is supplied, so that the precursor p can be selectively attached to the inner surface of the upper part of the opening OP1 and the upper surface of the FP electrode 10.

[0033] A portion of the insulating layer IL1 formed along the inner surface above the opening OP1 is removed by wet etching, exposing the inner surface above the opening OP1. An insulating layer IL2 (second insulating layer) is formed along the exposed inner surface by thermal oxidation, as shown in FIG. 8(b). A conductive layer is formed on the insulating layer IL2, and the upper surface of this conductive layer is recessed. As a result, inside the opening OP1, a gate electrode 20 is formed on the insulating layer IL1, as shown in FIG. 8(c). As shown in FIG. 8(d), the insulating layer IL2 provided around the second conductive portion 10b is removed.

[0034] After that, wet etching is performed. At this time, a chemical solution flows into the opening OP1 in the portion where the second conductive portion 10b is provided. The chemical solution is selected so that the first layer L1 is selectively removed with respect to the insulating layer IL1 and the insulating layer IL2. By this process, the n - The first layer L1 between the crystalline semiconductor layer 1a and the FP electrode 10 is removed. As shown in FIG. 9(a), the FP electrode 10 and the n - The gap G between the first layer L1 and the insulating layer IL1 and IL2 is enlarged. As an example, when the first layer L1 contains silicon nitride and the insulating layers IL1 and IL2 contain silicon oxide, the first layer L1 can be selectively removed with respect to the insulating layers IL1 and IL2 by wet etching using phosphoric acid.

[0035] As shown in FIG. 9B, an insulating layer IL3 is formed on the second conductive portion 10b and the gate electrode 20. In the portion where the second conductive portion 10b is provided, the opening OP1 is closed by the insulating layer IL3. A part of the insulating layer IL3 is removed to close the n-type insulating layer IL3 adjacent to the gate electrode 20. - The upper surface of the n-type semiconductor layer 1a is exposed. - 9(c), p-type impurities and n-type impurities are sequentially ion-implanted into the upper surface of the semiconductor layer 1a. + A source region 3 is formed.

[0036] As shown in Figure 9(d), + An opening OP2 is formed through the p-type source region 3 and reaches the p-type base region 2. A p-type impurity is ion-implanted into a part of the p-type base region 2 through the opening OP2. + The contact region 4 is formed. An opening is formed in the insulating layer IL3 to expose the upper surface of the second conductive portion 10b. + Shape source area 3, p + A metal layer is formed to cover the contact region 4 and the insulating layer IL3, and then this metal layer is patterned. As a result, as shown in Fig. 10(a), a source electrode 32 is formed. Also, a gate pad 33 (not shown) is formed.

[0037] n +The n-type semiconductor layer 5a is then heated to a predetermined thickness. + The back surface of the semiconductor layer 5a is ground. + A metal layer is formed on the back surface of the crystalline semiconductor layer 5a to form the drain electrode 31, as shown in Fig. 10(b). Through the above steps, the semiconductor device 100 shown in Figs. 1 to 5 is manufactured.

[0038] Around the FP electrode 10, - An insulating portion is provided to electrically separate the shaped semiconductor layer 1a and the FP electrode 10. In the semiconductor device 100, a gap G is provided as the insulating portion. The relative dielectric constant of the gap G is smaller than the relative dielectric constant of an insulating material such as silicon oxide or silicon nitride. By using the gap G as the insulating portion, the insulating portion can be made thinner than when an insulating layer made of an insulating material is used. This can improve the withstand voltage of the semiconductor device 100.

[0039] The reason why the insulating portion can be made thinner by using the gap G is as follows. Here, the channel resistance when the semiconductor device 100 is in the on-state is R ch Let xA be the channel length, L be the pitch of the gate electrode 20, P be the channel mobility, C be the gate capacitance, and V be the overdrive voltage. The overdrive voltage V corresponds to the value obtained by subtracting the threshold voltage from the voltage applied to the gate electrode 20. The relationship between these values ​​is expressed by the following formula 1. (Formula 1) R ch ×A=(L×P) / (2μ×C×V)

[0040] The amount of charge Q generated in the channel is expressed by the following formula 2. The gate capacitance C is expressed by the following formula 3. In formula 3, ε ox is the relative dielectric constant of the insulating part provided around the FP electrode 10. ox is the thickness of the insulation. (Formula 2) Q = C × V (Formula 3) C=ε ox / T ox

[0041] Channel resistance R ch If the cell pitch P, gate capacitance C, etc. are constant, then from equation 3, the relative dielectric constant ε ox The smaller the thickness of the insulation, T ox It can be seen that it is possible to reduce

[0042] Advantages of the embodiment will be described. Conventionally, the gap G has been formed by depositing an insulating layer by CVD and closing the opening OP1. For example, by increasing the film formation rate of CVD, the deposition of material below the opening OP1 can be suppressed, and the gap G can be formed. However, in the method using CVD, the shape and size of the deposited insulating layer vary greatly. As a result, the size and shape of the gap G also vary greatly, and the characteristics of the semiconductor device 100 fluctuate.

[0043] Regarding this problem, in the manufacturing method according to the embodiment, as shown in Figs. 7(a) to 7(d), an insulating layer IL1 is formed by ALD. In ALD, by performing an inhibitor i attachment or termination process, it is possible to suppress attachment of the precursor p to the lower part of the opening OP1. This makes it possible to selectively form an insulating layer only on the inner surface of the upper part of the opening OP1 to which the precursor p is attached. Therefore, it is possible to reduce the variation in the size and shape of the gap G compared to the case where CVD is used. As a result, it is possible to manufacture a semiconductor device 100 with smaller variation in characteristics.

[0044] According to the embodiment, a method for manufacturing a semiconductor device capable of suppressing the variation in size and shape of a gap is provided. Furthermore, by using the manufacturing method, a semiconductor device with small variation in size and shape of a gap can be obtained.

[0045] In the manufacturing method according to the embodiment, the first layer L1 is provided to support the FP electrode 10 until the insulating layer IL1 is formed. If the first layer L1 is insulating, the first layer L1 may remain without being removed. More preferably, the first layer L1 is removed after the insulating layer IL1 is formed, as shown in FIG. 9(a). After the first layer L1 is removed, the region where the first layer L1 was provided becomes a void. This can further improve the breakdown voltage of the semiconductor device 100.

[0046] (Modification) 11(a) to 11(f) are cross-sectional views illustrating steps in a manufacturing method according to a modified example of the embodiment. 6(a) to 10(b) show an example of a manufacturing method in which the semiconductor device 100 includes the FP electrode 10. The semiconductor device 100 does not have to include the FP electrode 10. In that case, there is no need to form the first layer L1 and the FP electrode 10.

[0047] First, similarly to the process shown in FIG. - An opening OP1 is formed in the semiconductor layer 1a. Next, as shown in FIG. 11(a), an inhibitor i is attached to the inner surface of the opening OP1. As shown in FIG. 11(b), the inhibitor i attached to the inner surface of the upper part of the opening OP1 is removed. As shown in FIG. 11(c), a precursor p is attached to the inner surface of the upper part of the opening OP1. Thereafter, a gas is supplied and the precursor p is reacted with the gas to form an insulating thin film F. As shown in FIG. 11(d), the inhibitor i is removed.

[0048] The steps shown in FIG. 11(a) to FIG. 11(d) are repeated. As a result, an insulating layer IL1a is formed on the upper part of the opening OP1 as shown in FIG. 11(e). An insulating layer IL1b is formed on the insulating layer IL1a by CVD as shown in FIG. 11(f). The upper part of the opening OP1 is blocked by the insulating layer IL1a and the insulating layer IL1b, forming a gap G. When the width of the opening OP1 is narrow, the upper part of the opening OP1 may be blocked by the insulating layer IL1a. In that case, the step shown in FIG. 11(f) can be omitted. Next, a part of the insulating layer IL1a and the insulating layer IL1b is removed to expose the inner surface of the upper part of the opening OP1 as shown in FIG. 11(g). Thereafter, a step similar to the step shown in FIG. 8(b) is performed.

[0049] According to the manufacturing method shown in FIG. 11(a) to FIG. 11(g), it is possible to suppress the variation in the size and the shape of the gap G formed below the gate electrode 20. Furthermore, by forming the gap G, it is possible to relieve the stress generated during the processing of the semiconductor substrate. By relieving the stress, the warping of the semiconductor substrate is reduced. Alternatively, the stress may cause the n - This can suppress the occurrence of cracks in the crystalline semiconductor layer 1a, thereby improving the yield of the manufactured semiconductor devices.

[0050] In each of the embodiments described above, the relative level of the impurity concentration between each semiconductor region can be confirmed, for example, by using a scanning capacitance microscope (SCM). The carrier concentration in each semiconductor region can be considered to be equal to the concentration of the activated impurities in each semiconductor region. Therefore, the relative level of the carrier concentration between each semiconductor region can also be confirmed by using the SCM. The impurity concentration in each semiconductor region can also be measured, for example, by secondary ion mass spectrometry (SIMS).

[0051] Although some embodiments of the present invention have been illustrated above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, modifications, etc. can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are included in the scope of the invention and its equivalents described in the claims. In addition, the above-mentioned embodiments can be implemented in combination with each other. [Explanation of symbols]

[0052] 1:n - Shape drift region, 1a:n - 1: p-type semiconductor layer; 2: p-type base region; 3: n + Shape source area, 4:p + Shape contact area, 5:n + shaped drain region, 5a:n + Semiconductor layer, 10: FP electrode, 10a: first conductive portion, 10b: second conductive portion, 11: insulating layer, 20: gate electrode, 21: gate insulating layer, 25: insulating layer, 31: drain electrode, 32: source electrode, 33: gate pad, 33a: wiring portion, 100: semiconductor device, C1, C2: connection portion, F: thin film, G: gap, IL1, IL1a, IL1b, IL2, IL3: insulating layer, L1: first layer, OP1, OP2: opening, i: inhibitor, p: precursor

Claims

1. forming an opening in an upper surface of a first semiconductor region of a first conductivity type; A method for manufacturing a semiconductor device, comprising: forming a first insulating layer on the upper part of the opening and closing it by an atomic layer deposition method that repeatedly performs adsorption of an inhibitor onto the inner surface of the lower part of the opening or a termination process for dangling bonds of a semiconductor material present on the inner surface of the lower part, and adsorption of a precursor onto the inner surface of the upper part of the opening, thereby forming a gap in the lower part of the opening.

2. 2. The method for manufacturing a semiconductor device according to claim 1, further comprising the step of forming a gate electrode on said first insulating layer inside said opening after said gap is formed.

3. After the opening is formed, a first layer is formed at a bottom of the opening, and a conductive portion is formed on the first layer; The method for manufacturing a semiconductor device according to claim 2 , wherein the first insulating layer is formed along an inner surface of the upper portion of the opening and an upper surface of the conductive portion.

4. After forming the gap, a portion of the first insulating layer formed along the inner surface of the upper portion is removed; forming a second insulating layer along the interior surface of the top portion by thermal oxidation; The method for manufacturing a semiconductor device according to claim 3 , wherein the gate electrode is formed after the second insulating layer is formed.

5. The method for manufacturing a semiconductor device according to claim 4 , wherein the first layer is removed after the gate electrode is formed.

Images