Semiconductor device

Abstract

To provide a semiconductor device that can improve current measurement accuracy.SOLUTION: A semiconductor device 1 of one embodiment comprises: a first circuit 3 for driving a load LD connectable to a first terminal T4 by supplying a load current Idrv to the load LD; and a third circuit 4 that includes a second circuit 5 which copies the load current and outputs a copied first current Imr1 based on a first voltage VOUT at the first terminal, and that monitors a second current Icm based on the first current. The third circuit further includes a fourth circuit 6 which regulates the second current when the load current is not supplied to the load.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] 2. Description of the Related Art There is known a semiconductor device that includes a driver circuit that drives an external load and a current monitor circuit that monitors a current flowing through the load. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 6487280 [Patent Document 2] JP 2007-166861 A [Patent Document 3] Patent Publication No. 2021-139665 Summary of the Invention [Problem to be solved by the invention]

[0004] A semiconductor device capable of improving the accuracy of current measurement is provided. [Means for solving the problem]

[0005] The semiconductor device according to the embodiment includes a first circuit for driving a load by supplying a load current to the load connectable to a first terminal, a second circuit for copying the load current based on a first voltage of the first terminal and outputting the copied first current, and a third circuit for monitoring a second current based on the first current. The third circuit further includes a fourth circuit for adjusting the second current when the load current is not supplied to the load. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is a circuit diagram showing an example of the configuration of the semiconductor device according to the first embodiment. [Diagram 2]FIG. 2 is a diagram showing the distribution of voltage applied to the inverting input terminal of the operational amplifier when there is an input offset voltage and no load in the semiconductor device according to the first embodiment. [Diagram 3] FIG. 3 is a diagram showing a distribution of monitor currents output from the current monitor terminals when there is an input offset voltage and no load in the semiconductor device according to the first embodiment. [Figure 4] FIG. 4 is a circuit diagram showing the connection relationship during the determination operation of the semiconductor device according to the first embodiment. [Diagram 5] FIG. 5 is a circuit diagram showing connections during the first adjustment operation of the semiconductor device according to the first embodiment. [Figure 6] FIG. 6 is a diagram showing an example of the relationship between the transition of the current value and the transition of the value of the voltage comparison result when the first adjusting operation is performed in the semiconductor device according to the first embodiment. [Figure 7] FIG. 7 is a circuit diagram showing the connections during the second adjusting operation of the semiconductor device in accordance with the first embodiment. [Figure 8] FIG. 8 is a diagram showing an example of the relationship between the transition of the current value and the transition of the value of the voltage comparison result when the second adjusting operation is performed in the semiconductor device according to the first embodiment. [Figure 9] FIG. 9 is a flowchart showing an example of a current adjusting operation of the semiconductor device according to the first embodiment. [Figure 10] FIG. 10 is a flowchart showing an example of a current monitoring operation of the semiconductor device according to the first embodiment. [Figure 11] FIG. 11 is a circuit diagram showing the connections during the current monitoring operation of the semiconductor device according to the first embodiment. [Figure 12] FIG. 12 is a circuit diagram showing the connections during the current monitoring operation of the semiconductor device according to the first embodiment. [Figure 13] FIG. 13 is a circuit diagram showing an example of the configuration of the semiconductor device according to the second embodiment. [Figure 14] FIG. 14 is a circuit diagram showing the connections during the first adjustment operation of the semiconductor device according to the second embodiment. [Figure 15]FIG. 15 is a circuit diagram showing the connections during the second adjustment operation of the semiconductor device according to the second embodiment. [Figure 16] FIG. 16 is a circuit diagram showing an example of the configuration of the semiconductor device according to the third embodiment. [Figure 17] FIG. 17 is a circuit diagram showing an example of a configuration of a semiconductor device according to a modification of the third embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, the embodiments will be described with reference to the drawings. In the following description, components having substantially the same functions and configurations are given the same reference numerals, and repeated description may be omitted. When elements having similar configurations are particularly distinguished from each other, different letters or numbers may be added to the end of the same reference numerals. In addition, all descriptions of one embodiment are also applicable to descriptions of other embodiments, unless expressly or obviously excluded.

[0008] 1. First embodiment The semiconductor device according to the first embodiment will be described.

[0009] 1.1 Configuration 1.1.1 Circuit configuration of semiconductor device The circuit configuration of the semiconductor device according to this embodiment will be described with reference to Fig. 1. Fig. 1 is a circuit diagram showing an example of the configuration of the semiconductor device. In the following description, when the source and drain of a transistor are not limited, either the source or the drain of the transistor will be referred to as "one end of the transistor", and the other either the source or the drain of the transistor will be referred to as "the other end of the transistor".

[0010] The semiconductor device 1 is, for example, an IC (Integrated Circuit) chip. The semiconductor device 1 drives an external load LD by supplying a current to the load LD. The load LD is, for example, a motor. Hereinafter, the current supplied to (flowing through) the load LD is referred to as a "load current." In addition, the semiconductor device 1 monitors the load current.

[0011] As shown in FIG. 1, the semiconductor device 1 includes a first power supply voltage terminal T1, a second power supply voltage terminal T2, a ground voltage terminal T3, an input / output terminal T4, a current monitor terminal T5, a control circuit 2, a driver circuit 3, and a current monitor circuit 4.

[0012] The first power supply voltage terminal T1 is a terminal that supplies a power supply voltage VCC to a circuit (eg, the current monitor circuit 4) within the semiconductor device 1. The power supply voltage VCC is supplied from outside the semiconductor device 1 to the first power supply voltage terminal T1.

[0013] The second power supply voltage terminal T2 is a terminal that supplies a power supply voltage VB to circuits (e.g., the driver circuit 3 and the current monitor circuit 4) in the semiconductor device 1. The voltage VB is, for example, a voltage higher than the voltage VCC. The power supply voltage VB is supplied to the second power supply voltage terminal T2 from outside the semiconductor device 1.

[0014] The ground voltage terminal T3 is a terminal that supplies a ground voltage GND to circuits (for example, the driver circuit 3 and the current monitor circuit 4) within the semiconductor device 1. The ground voltage terminal T3 is supplied with a ground voltage GND from outside the semiconductor device 1. The ground voltage terminal T3 may be grounded.

[0015] The input / output terminal T4 is a terminal that supplies a load current to the load LD. The input / output terminal T4 is connected to the load LD. The load current is input to the input / output terminal T4 or output from the input / output terminal T4. The voltage VOUT of the input / output terminal T4 is input to the input / output terminal T4 or output from the input / output terminal T4.

[0016] The current monitor terminal T5 is a terminal that outputs a monitor current, which will be described later. The monitor current is, for example, a current that is 1 / k times (k is an integer equal to or greater than 1) the load current. The current monitor terminal T5 is connected, for example, to one end of a resistive element RL outside the semiconductor device 1. The other end of the resistive element RL is grounded. The monitor current can be detected by detecting the voltage VCM of the current monitor terminal T5.

[0017] The control circuit 2 is a circuit that controls the overall operation of the semiconductor device 1. The control circuit 2 controls the operations of the driver circuit 3 and the current monitor circuit 4 based on a request signal (e.g., a signal received from outside the semiconductor device 1) not shown. For example, the control circuit 2 generates control signals CS1 and CS2 that control the driver circuit 3 and a control signal CS3 that controls the current monitor circuit 4 based on the request signal.

[0018] The driver circuit 3 is a circuit that drives the load LD by supplying a load current to the load LD. The driver circuit 3 will be described in detail later.

[0019] The current monitor circuit 4 is a circuit that monitors the load current flowing through the load LD, more specifically, the current based on the load current. The current monitor circuit 4 also adjusts the current based on the load current. The current monitor circuit 4 will be described in detail later.

[0020] 1.1.2 Driver circuit configuration The circuit configuration of the driver circuit 3 will be described.

[0021] 1, the driver circuit 3 includes n-channel Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) N1 and N2. Hereinafter, the n-channel MOSFETs will be referred to as "NMOS transistors."

[0022] The NMOS transistor N1 has, for example, a gate width W1. The gate of the NMOS transistor N1 is connected to a node ND1. A control signal CS1 is input to the node ND1 from the control circuit 2. That is, the control signal CS1 is input to the gate of the NMOS transistor N1. One end of the NMOS transistor N1 is connected to a second power supply voltage terminal T2. The other end of the NMOS transistor N1 is connected to a node ND3.

[0023] The NMOS transistor N2 has, for example, a gate width W2. The gate of the NMOS transistor N2 is connected to a node ND2. A control signal CS2 is input to the node ND2 from the control circuit 2. That is, the control signal CS2 is input to the gate of the NMOS transistor N2. The control signal CS2 is a signal obtained by inverting the logical level of the control signal CS1. One end of the NMOS transistor N2 is connected to a node ND3. The other end of the NMOS transistor N2 is connected to a ground voltage terminal T3.

[0024] The input / output terminal T4 is connected to the node ND3. That is, the other end of the NMOS transistor N1 and one end of the NMOS transistor N2 are connected to the input / output terminal T4.

[0025] When the control signal CS1 is at the “H” level and the control signal CS2 is at the “L” level, the NMOS transistor N1 is turned on and the NMOS transistor N2 is turned off, causing a load current to flow from the second power supply voltage terminal T2 through the NMOS transistor N1 and the input / output terminal T4 to the load LD.

[0026] On the other hand, when the control signal CS1 is at the "L" level and the control signal CS2 is at the "H" level, the NMOS transistor N1 is turned off and the NMOS transistor N2 is turned on. This causes a load current to flow through the load LD. That is, the load current flows from the load LD to the ground voltage terminal T3 via the input / output terminal T4 and the NMOS transistor N2. Hereinafter, the load current is referred to as "load current Idrv." FIG. 1 shows the load current Idrv flowing from the load LD to the ground voltage terminal T3 via the input / output terminal T4 and the NMOS transistor N2.

[0027] 1.1.3 Configuration of current monitor circuit The following describes the circuit configuration of the current monitor circuit 4. The semiconductor device 1 according to this embodiment monitors the load current Idrv when the load LD is driven by the NMOS transistor N2 of the driver circuit 3. That is, the current monitor circuit 4 is a current monitor circuit for low-side driving.

[0028] As shown in FIG. 1, the current monitor circuit 4 includes a mirror circuit 5, p-channel MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) P1 and P2, switches SW1 and SW2, variable current sources 41 and 42, and a current adjustment circuit 6. Hereinafter, the p-channel MOSFET is referred to as a "PMOS transistor".

[0029] The mirror circuit 5 is a circuit that copies the load current Idrv based on the voltage VOUT of the input / output terminal T4 and outputs the copied current. As shown in FIG. 1, the mirror circuit 5 includes NMOS transistors N3 and N4, and an operational amplifier AMP.

[0030] The NMOS transistor N3 has, for example, a gate width w2 (w2 < W2). The gate of the NMOS transistor N3 is connected to the node ND2. That is, the control signal CS2 is input to the gate of the NMOS transistor N3. One end of the NMOS transistor N3 is connected to the node ND5. The other end of the NMOS transistor N3 is connected to the ground voltage terminal T3.

[0031] The operational amplifier AMP has a first input terminal, a second input terminal, and an output terminal. The first input terminal of the operational amplifier AMP is a non-inverting input terminal. The second input terminal of the operational amplifier AMP is an inverting input terminal. The first input terminal of the operational amplifier AMP is connected to the node ND3. That is, the voltage VOUT of the input / output terminal T4 is applied to the first input terminal of the operational amplifier AMP. The second input terminal of the operational amplifier AMP is connected to the node ND5. That is, the voltage V5 of the node ND5 is applied to the second input / output terminal of the operational amplifier AMP. The operational amplifier AMP outputs a voltage Va from the output terminal based on the voltage VOUT and the voltage V5. The output terminal of the operational amplifier AMP is connected to the node ND4.

[0032] The gate of the NMOS transistor N4 is connected to the node ND4. That is, a voltage Va is applied to the gate of the NMOS transistor N4. One end of the NMOS transistor N4 is connected to a node ND6. The other end of the NMOS transistor N4 is connected to a node ND5.

[0033] The gate of the PMOS transistor P1 is connected to a node ND6. One end of the PMOS transistor P1 is connected to the first power supply voltage terminal T1. The other end of the PMOS transistor P1 is connected to the node ND6.

[0034] The gate of the PMOS transistor P2 is connected to a node ND6, one end of the PMOS transistor P2 is connected to the first power supply voltage terminal T1, and the other end of the PMOS transistor P2 is connected to a node ND7.

[0035] The switch SW1 is an element that switches between connection and disconnection between the first power supply voltage terminal T1 and the variable current source 41. One end of the switch SW1 is connected to the first power supply voltage terminal T1. The other end of the switch SW1 is connected to a node ND8.

[0036] The switch SW2 is an element that switches between connection and disconnection between the node ND6 and the variable current source 42. One end of the switch SW2 is connected to the node ND6. The other end of the switch SW2 is connected to a node ND9.

[0037] The variable current source 41 supplies a current In1 from the first power supply voltage terminal T1 to a node ND6. The current In1 is variable. One end of the variable current source 41 is connected to a node ND8. The other end of the variable current source 41 is connected to the node ND6.

[0038] The variable current source 42 supplies a current Ip1 from the node ND6 to the ground voltage terminal T3. The current Ip1 is variable. One end of the variable current source 42 is connected to the node ND9. The other end of the variable current source 42 is connected to the ground voltage terminal T3.

[0039] By the operational amplifier AMP and the NMOS transistor N4, the operational amplifier AMP outputs a voltage Va such that the voltage VOUT and the voltage V5 are equal. That is, the voltage V5 is controlled to be equal to the voltage VOUT. Therefore, when the load LD is driven by the NMOS transistor N2 and the load current Idrv flows to the load LD, a current Idrv×(w2 / W2) flows from the first power supply voltage terminal T1 to the ground voltage terminal T3 via the PMOS transistor P1, the NMOS transistor N4, and the NMOS transistor N3. Hereinafter, this current is referred to as a “copy current Imr1”. Since the PMOS transistor P1 and the PMOS transistor P2 form a current mirror, a current of the same magnitude as the current Imr1 also flows from the first power supply voltage terminal T1 to the node ND7 via the PMOS transistor P2. Hereinafter, this current is referred to as a “monitor current Icm”. By connecting the node ND7 to the current monitor terminal T5, the monitor current Icm can be monitored at the current monitor terminal T5. Since the monitor current Icm is smaller than the load current Idrv, the power consumption of the current monitor circuit 4 can be reduced.

[0040] The operational amplifier AMP may have an input offset voltage. The input offset voltage changes over time. The input offset voltage also changes due to temperature and stress. When the operational amplifier AMP has an input offset voltage, the input offset voltage causes the voltage V5 of the node ND5 to be a voltage shifted to the positive side from the voltage VOUT of the input / output terminal T4, or a voltage shifted to the negative side from the voltage VOUT.

[0041] When the voltage V5 deviates from the voltage VOUT to the positive side, the voltage between the gate and source of the NMOS transistor N4 increases, and the copy current Imr1 becomes larger than when the voltage V5 and the voltage VOUT are equal.

[0042] On the other hand, when the voltage V5 deviates more negatively than the voltage VOUT, the gate-source voltage of the NMOS transistor N4 decreases, and the copy current Imr1 becomes smaller than when the voltage V5 and the voltage VOUT are equal.

[0043] Here, consider the case where the load current Idrv is not supplied to the load LD, that is, the load current Idrv is 0. Hereinafter, the case where the load current Idrv is not supplied to the load LD is also referred to as the "no load case." When there is no load and the voltage V5 is equal to the voltage VOUT, the copy current Imr1 becomes 0 and the monitor current Icm also becomes 0. On the other hand, when there is no load and the voltage V5 deviates from the voltage VOUT to the positive side, the copy current Imr1 becomes larger than the current value (=0) when the voltage V5 is equal to the voltage VOUT, as described above, and the monitor current Icm also becomes larger than 0. On the other hand, when there is no load and the voltage V5 deviates from the voltage VOUT to the negative side, the copy current Imr1 becomes smaller than the current value (=0) when the voltage V5 is equal to the voltage VOUT, as described above. At this time, the monitor current Icm can only be output as 0.

[0044] From the above, when the operational amplifier AMP has an input offset voltage and there is no load, the voltage V5 shows a distribution as shown in Figure 2. Figure 2 is a diagram showing the distribution of the voltage V5 when there is an input offset voltage and there is no load. The vertical axis is the number of samples. The horizontal axis is the voltage V5 when there is no load.

[0045] As described above, when the voltage V5 deviates more positively than the voltage VOUT, the monitor current Icm is distributed on the positive side of 0. When the voltage V5 deviates more negatively than the voltage VOUT, the monitor current Icm becomes 0.

[0046] When there is no load and the voltage V5 deviates from the voltage VOUT to the negative side, the copy current Imr1 becomes smaller than 0 as described above. That is, the copy current Imr1 becomes a negative value. Therefore, in reality, the copy current Imr1 does not flow to the nodes ND5 and ND6, and the monitor current Icm does not flow to the node ND7. That is, the monitor current Icm is only output as 0 from the current monitor terminal T5. As a result, when the operational amplifier AMP has an input offset voltage and there is no load, the monitor current Icm output from the current monitor terminal T5 shows a distribution as shown in FIG. 3. FIG. 3 is a diagram showing the distribution of the monitor current Icm output from the current monitor terminal T5 when there is an input offset voltage and there is no load. The vertical axis is the number of samples. The horizontal axis is the monitor current Icm when there is no load. In FIG. 3, the distribution of the deviation of the monitor Icm from 0 when the voltage V5 deviates from the voltage VOUT is shown by a broken line.

[0047] 3, when the voltage V5 deviates from the voltage VOUT to the positive side, the monitor current Icm output from the current monitor terminal T5 is distributed on the positive side of 0. When the voltage V5 deviates from the voltage VOUT to the negative side, the monitor current Icm output from the current monitor terminal T5 is not distributed on the negative side of 0, but is distributed at 0.

[0048] In this way, when the operational amplifier AMP has an input offset voltage and there is no load, the monitor current Icm may not become 0 due to the influence of the input offset voltage. That is, an error in the monitor current Icm (deviation from 0 to the positive side or deviation from 0 to the negative side) may occur.

[0049] When the load LD is driven, a relatively large current Idrv flows through the load LD. When the load current Idrv is relatively large, the error in the monitor current Icm is small compared to the load current Idrv. In this case, the measurement accuracy of the monitor current Icm is unlikely to deteriorate. However, when the load current Idrv is 0, the error in the monitor current Icm is large compared to 0. In this case, the measurement accuracy of the monitor current Icm may deteriorate.

[0050] The current adjustment circuit 6 is a circuit that adjusts the monitor current Icm so that it approaches 0 when there is no load. More specifically, the current adjustment circuit 6 adjusts the monitor current Icm so that the distribution of deviations of the monitor current Icm from 0, which is shown by the dashed line in Fig. 3, converges to 0. As shown in Fig. 1, the current adjustment circuit 6 includes switches SW3 and SW4, a resistor element Rm, a comparator CMP, and a trimming control circuit 61.

[0051] The switch SW3 is an element that switches between connection and disconnection between the node ND7 and the current monitor terminal T5. One end of the switch SW3 is connected to the node ND7. The other end of the switch SW3 is connected to a node ND12.

[0052] The switch SW4 is an element that switches between connection and disconnection between the node ND7 and the resistor element Rm. One end of the switch SW4 is connected to the node ND7. The other end of the switch SW4 is connected to a node ND10.

[0053] One end of the resistor element Rm is connected to the node ND10. The other end of the resistor element Rm is connected to the ground voltage terminal T3. The resistance value of the resistor element Rm is set, for example, taking into consideration the amount of trimming described below.

[0054] The comparator CMP has a first input terminal, a second input terminal, and an output terminal. The first input terminal of the comparator CMP is an inverting input terminal. The second input terminal of the comparator CMP is a non-inverting input terminal. The first input terminal of the comparator CMP is connected to the node ND10. That is, the voltage Vm of the node ND10 is applied to the first input terminal of the comparator CMP. The reference voltage Vref is applied to the second input terminal of the comparator CMP. The comparator CMP compares the voltage Vm with the voltage Vref, and outputs the comparison result from the output terminal. Hereinafter, the comparison result is referred to as the "comparison result RES". When the voltage Vm is equal to or higher than the voltage Vref, the comparator CMP outputs a signal of the "L" level as the comparison result RES. On the other hand, when the voltage Vm is less than the voltage Vref, the comparator CMP outputs a signal of the "H" level as the comparison result RES. The output terminal of the comparator CMP is connected to the node ND11. The reference voltage Vref is set, for example, taking into consideration a value obtained by converting the input offset voltage into a current and the resistance value of the resistor Rm. The reference voltage Vref is set to a voltage such that the monitor current Icm flows through the node ND10 when the voltage Vm is equal to or higher than the voltage Vref, and the monitor current Icm does not flow through the node ND10 when the voltage Vm is less than the voltage Vref. For example, if the resistor Rm is 200 kΩ and the trimming amount dI described later is 1 μA, the reference voltage Vref is set to 0.1 V.

[0055] The trimming control circuit 61 is a circuit that adjusts the monitor current Icm based on the comparison result RES. More specifically, the trimming control circuit 61 adjusts the monitor current Icm by adjusting the current value of the variable current source 41 or the current value of the variable current source 42 based on the comparison result RES. Hereinafter, adjusting the current value of the variable current source 41 or the current value of the variable current source 42 is also referred to as "trimming". In addition, the trimming control circuit 61 controls the switches SW1 to SW4. As shown in FIG. 1, the trimming control circuit 61 includes a register 62.

[0056] The register 62 is a circuit that stores the result of adjustment by the current adjustment circuit 6. The result of adjustment by the current adjustment circuit 6 includes, for example, the current value of the variable current source 41 and the current value of the variable current source .

[0057] As described above, the current adjustment circuit 6 compares the voltage Vm obtained by converting the monitor current Icm into a voltage with the reference voltage Vref, and adjusts the monitor current Icm so that it approaches zero based on the comparison result RES.

[0058] 1.2 Operation The semiconductor device 1 includes a load driving operation, a current monitoring operation, and a current adjusting operation. The load driving operation is an operation of driving the load LD by supplying a load current Idrv to the load LD. The current monitoring operation is an operation of monitoring a monitor current Icm based on the load current Idrv. The current adjusting operation is an operation of adjusting the monitor current Icm to approach 0 when there is no load.

[0059] 1.2.1 Current adjustment operation The current adjustment operation will be described. The current adjustment operation includes a determination operation, a first adjustment operation, and a second adjustment operation. First, each of the determination operation, the first adjustment operation, and the second adjustment operation will be described below.

[0060] (judgment action) The judgment operation is an operation to judge whether the monitor current Icm deviates to the positive or negative side from the current value (=0) when the voltage V5 of the node ND5 and the voltage VOUT of the input / output terminal T4 are equal when there is no load.

[0061] FIG. 4 is a circuit diagram showing the connection relationship during the determination operation of the semiconductor device 1. As shown in FIG. 4, when the determination operation is started, the trimming control circuit 61 turns off the switches SW1 to SW3 and turns on the switch SW4. Then, based on the comparison result RES output from the comparator CMP, the trimming control circuit 61 determines whether the monitor current Icm is deviated from 0 to the positive side or the negative side. When there is no load and the monitor current Icm flows through the node ND10, the voltage Vm of the node ND10 becomes equal to or higher than the reference voltage Vref. On the other hand, when there is no load and the monitor current Icm does not flow through the node ND10, the voltage Vm of the node ND10 becomes less than the reference voltage Vref. Therefore, when the comparison result RES is at the “L” level, the trimming control circuit 61 determines that the monitor current Icm is deviated from 0 to the positive side. On the other hand, when the comparison result RES is at the “H” level, the trimming control circuit 61 determines that the monitor current Icm is deviated from 0 to the negative side.

[0062] (1st adjustment operation) The first adjustment operation is an operation for adjusting the monitor current Icm to approach 0 when there is no load and when the judgment operation judges that the monitor current Icm deviates from 0 to the positive side (when the voltage Vm is greater than or equal to the reference voltage Vref).

[0063] 5 is a circuit diagram showing the connections during the first adjustment operation of the semiconductor device 1. Hereinafter, the current flowing through the node ND5 is referred to as "current Ind5," and the current flowing through the node ND6 is referred to as "current Ind6."

[0064] 5, when the first adjustment operation is started, the trimming control circuit 61 turns on the switches SW1 and SW4 and turns off the switches SW2 and SW3. Then, the trimming control circuit 61 increases the current In1 of the variable current source 41 and selects the value of the current In1 during the first loop processing described below, which is one cycle before the comparison result RES output from the comparator CMP transitions from the “L” level to the “H” level.

[0065] A method for selecting the value of the current In1 will be described with reference to Fig. 6. Fig. 6 is a diagram showing an example of the relationship between the transition of the value of the current In1 and the transition of the value of the comparison result RES when the first adjusting operation is performed.

[0066] When there is no load, when the first adjustment operation is started, the trimming control circuit 61 sets the value of the current In1 of the variable current source 41 to 0. At this time, there is no load, and the monitor current Icm flows through the node ND10. That is, the monitor current Icm shifts from 0 to the positive side. As a result, the comparison result RES becomes the “L” level.

[0067] The trimming control circuit 61 reduces the monitor current Icm to bring the monitor current Icm closer to 0. For example, the trimming control circuit 61 reduces the monitor current Icm by a predetermined trimming amount dI (increases the current In1 by the trimming amount dI). The trimming amount dI is, for example, 10 μA. Then, the trimming control circuit 61 determines whether the comparison result RES has transitioned from the “L” level to the “H” level.

[0068] If the comparison result RES has not transitioned to the “H” level, the monitor current Icm flows through the node ND10. Therefore, the trimming control circuit 61 further reduces the monitor current Icm by the trimming amount dI, and judges whether the comparison result RES has transitioned from the “L” level to the “H” level. For example, the trimming control circuit 61 further reduces the monitor current Icm by the trimming amount dI than when the monitor current Icm is reduced by the trimming amount dI (the current In1 is further increased by the trimming amount dI than when the current In1 is increased by the trimming amount dI). That is, the trimming control circuit 61 sets the total amount of reduction in the monitor current Icm to −2×dI (the value of the current In1 is set to 2×dI). Then, the trimming control circuit 61 judges whether the comparison result RES has transitioned from the “L” level to the “H” level. Thereafter, if the comparison result RES has not transitioned to the “H” level, as described above, a combination of the process of decreasing the monitor current Icm by the trimming amount dI (the process of increasing the current In1 by the trimming amount dI) and the process of determining whether or not the logical level of the comparison result RES has transitioned (hereinafter, these processes are collectively referred to as the “first loop process”) is repeated.

[0069] On the other hand, when the comparison result RES transitions to the “H” level, the monitor current Icm does not flow through the node ND10. Therefore, the trimming control circuit 61 selects the value of the current In1 at the time of the immediately previous trimming (first loop processing). In the example of FIG. 6, when the trimming control circuit 61 sets the value of the current In1 to 6×dI, the comparison result RES transitions to the “H” level. Therefore, the trimming control circuit 61 selects 6×dI as the value of the current In1.

[0070] In this way, the trimming control circuit 61 repeatedly executes the first loop process, and selects, as the current In1, the value of the current In1 at the time of the first loop process one cycle before when the logical level of the comparison result RES transitions. Then, the trimming control circuit 61 adjusts the value of the current In1 to the selected value of the current In1.

[0071] The example in Fig. 6 will be further described with reference to Fig. 5. In the example in Fig. 6, the error (deviation from 0 to the positive side) of the monitor current Icm is 6×dI.

[0072] As shown in Figure 5, when current In1 = 0, current In1 does not flow to node ND8. Current Ind5 = Imr1 = 6 x dI flows to node ND5. Current Ind6 = Ind5 - In1 = 6 x dI flows to node ND6. As a result, monitor current Icm = Ind6 = 6 x dI flows to node ND10.

[0073] When the current In1=dI, the current In1=dI flows through the node ND8. The current Ind5=6×dI flows through the node ND5. The current Ind6=5×dI flows through the node ND6. This causes the monitor current Icm=5×dI to flow through the node ND10.

[0074] When the current In1=2×dI, the current In1=2×dI flows through the node ND8. The current Ind5=6×dI flows through the node ND5. The current Ind6=4×dI flows through the node ND6. This causes the monitor current Icm=4×dI to flow through the node ND10.

[0075] When the current In1=3×dI, the current In1=3×dI flows through the node ND8. The current Ind5=6×dI flows through the node ND5. The current Ind6=3×dI flows through the node ND6. This causes the monitor current Icm=3×dI to flow through the node ND10.

[0076] When the current In1=4×dI, the current In1=4×dI flows through the node ND8. The current Ind5=6×dI flows through the node ND5. The current Ind6=2×dI flows through the node ND6. This causes the monitor current Icm=2×dI to flow through the node ND10.

[0077] When the current In1=5×dI, the current In1=5×dI flows through the node ND8. The current Ind5=6×dI flows through the node ND5. The current Ind6=dI flows through the node ND6. As a result, the monitor current Icm=dI flows through the node ND10.

[0078] When the current In1=6×dI, the current In1=6×dI flows through the node ND8. The current Ind5=6×dI flows through the node ND5. The current Ind6 does not flow through the node ND6 (Ind6=0). As a result, the monitor current Icm does not flow through the node ND10 (Icm=0).

[0079] From the above, the trimming control circuit 61 selects 6×dI as the value of the current In1. By performing the first adjustment operation in this manner, the monitor current Icm is adjusted to approach zero.

[0080] (Second adjustment operation) The second adjustment operation is an operation for adjusting the monitor current Icm to approach 0 when there is no load and when the judgment operation determines that the monitor current Icm deviates from 0 to the negative side (when the voltage Vm is less than the reference voltage Vref).

[0081] 7 is a circuit diagram showing the connections during the second adjustment operation of the semiconductor device 1. Hereinafter, the current flowing through the node ND9 will be referred to as "current Ind9."

[0082] 7, when the second adjustment operation is started, the trimming control circuit 61 turns on the switches SW2 and SW4 and turns off the switches SW1 and SW3. Then, the trimming control circuit 61 increases the current Ip1 of the variable current source 42 and selects the value of the current Ip1 during the second loop process described below, which is one cycle before the comparison result RES transitions from the “H” level to the “L” level.

[0083] A method for selecting the value of the current Ip1 will be described with reference to Fig. 8. Fig. 8 is a diagram showing an example of the relationship between the transition of the value of the current Ip1 and the transition of the value of the comparison result RES when the second adjusting operation is performed.

[0084] When there is no load, when the second adjustment operation is started, the trimming control circuit 61 sets the value of the current Ip1 of the variable current source 42 to 0. At this time, there is no load, and the monitor current Icm does not flow to the node ND10. That is, the monitor current Icm shifts from 0 to the negative side. As a result, the comparison result RES becomes the “H” level.

[0085] The trimming control circuit 61 increases the monitor current Icm to bring the monitor current Icm closer to 0. For example, the trimming control circuit 61 increases the monitor current Icm by the trimming amount dI (increases the current Ip1 by the trimming amount dI). Then, the trimming control circuit 61 determines whether the comparison result RES has transitioned from the “H” level to the “L” level.

[0086] If the comparison result RES has not transitioned to the “L” level, the monitor current Icm does not flow through the node ND10. Therefore, the trimming control circuit 61 further increases the monitor current Icm by the trimming amount dI, and judges whether the comparison result RES has transitioned from the “H” level to the “L” level. For example, the trimming control circuit 61 further increases the monitor current Icm by the trimming amount dI than when the monitor current Icm is increased by the trimming amount dI (the current Ip1 is further increased by the trimming amount dI than when the current Ip1 is increased by the trimming amount dI). That is, the trimming control circuit 61 sets the total increase amount of the monitor current Icm to +2×dI (the value of the current Ip1 is set to 2×dI). Then, the trimming control circuit 61 judges whether the comparison result RES has transitioned from the “H” level to the “L” level. Thereafter, if the comparison result RES has not transitioned to the “L” level, as described above, a combination of the process of increasing the monitor current Icm by the trimming amount dI (the process of increasing the current Ip1 by the trimming amount dI) and the process of determining whether or not the logical level of the comparison result RES has transitioned (hereinafter, these processes are collectively referred to as “second loop processing”) is repeated.

[0087] On the other hand, when the comparison result RES transitions to the “L” level, the monitor current Icm flows through the node ND10. Therefore, the trimming control circuit 61 selects the value of the current Ip1 at the time of the immediately previous trimming (second loop processing). In the example of FIG. 8, when the trimming control circuit 61 sets the value of the current Ip1 to 7×dI, the comparison result RES transitions to the “L” level. Therefore, the trimming control circuit 61 selects 6×dI as the value of the current Ip1.

[0088] In this way, the trimming control circuit 61 repeatedly executes the second loop process to select, as the current Ip1, the value of the current Ip1 at the time of the second loop process immediately before when the logical level of the comparison result RES transitions. Then, the trimming control circuit 61 adjusts the value of the current Ip1 to the selected value of the current Ip1.

[0089] The example of Fig. 8 will be further described with reference to Fig. 7. In the example of Fig. 8, the error (deviation from 0 to the negative side) of the monitor current Icm is -6 x dI.

[0090] As shown in Figure 7, when the current Ip1=0, the current Ip1 does not flow through the node ND9. The current Ind5 does not flow through the node ND5 (Ind5=Imr1=-6×dI). The current Ind6 does not flow through the node ND6 (Ind6=Ind5+Ip1=-6×dI). The monitor current Icm does not flow through the node ND10 (Icm=Ind6=-6×dI).

[0091] When the current Ip1=dI, the current Ip1=dI flows through the node ND9. The current Ind5 does not flow through the node ND5 (Ind5=-6×dI). The current Ind6 does not flow through the node ND6 (Ind6=-5×dI). The monitor current Icm does not flow through the node ND10 (Icm=-5×dI).

[0092] When the current Ip1=2×dI, the current Ip1=2×dI flows through the node ND9. The current Ind5 does not flow through the node ND5 (Ind5=-6×dI). The current Ind6 does not flow through the node ND6 (Ind6=-4×dI). The monitor current Icm does not flow through the node ND10 (Icm=-4×dI).

[0093] When the current Ip1=3×dI, the current Ip1=3×dI flows through the node ND9. The current Ind5 does not flow through the node ND5 (Ind5=-6×dI). The current Ind6 does not flow through the node ND6 (Ind6=-3×dI). The monitor current Icm does not flow through the node ND10 (Icm=-3×dI).

[0094] When the current Ip1=4×dI, the current Ip1=4×dI flows through the node ND9. The current Ind5 does not flow through the node ND5 (Ind5=-6×dI). The current Ind6 does not flow through the node ND6 (Ind6=-2×dI). The monitor current Icm does not flow through the node ND10 (Icm=-2×dI).

[0095] When the current Ip1=5×dI, the current Ip1=5×dI flows through the node ND9. The current Ind5 does not flow through the node ND5 (Ind5=-6×dI). The current Ind6 does not flow through the node ND6 (Ind6=-dI). The monitor current Icm does not flow through the node ND10 (Icm=-dI).

[0096] When the current Ip1=6×dI, the current Ip1=6×dI flows through the node ND9. The current Ind5 does not flow through the node ND5 (Ind5=-6×dI). The current Ind6 does not flow through the node ND6 (Ind6=0). The monitor current Icm does not flow through the node ND10 (Icm=0).

[0097] When the current In1=7×dI, the current Ip1=7×dI flows through the node ND9. The current Ind5 does not flow through the node ND5 (Ind5=-6×dI). The current Ind6=dI flows through the node ND6. The monitor current Icm=dI flows through the node ND10.

[0098] From the above, the trimming control circuit 61 selects 6×dI as the value of the current Ip1. By performing the second adjustment operation in this manner, the monitor current Icm is adjusted to approach zero.

[0099] (flowchart) FIG. 9 is a flowchart showing an example of the current adjustment operation of the semiconductor device 1.

[0100] When the semiconductor device 1 is powered on, or when the semiconductor device 1 receives a request signal requesting execution of a current adjustment operation (adjustment of the monitor current Icm) from the outside, the control circuit 2 generates an "L" level signal as the control signal CS3, and transmits the generated "L" level control signal CS3 to the current monitor circuit 4. The "L" level control signal CS3 is, for example, a signal instructing execution of a current adjustment operation.

[0101] When the control signal CS3 of "L" level is received from the control circuit 2, steps S101 to S115 are executed. Steps S101 to S103 correspond to the determination operation. Steps S104 to S109 correspond to the first adjustment operation. Steps S110 to S115 correspond to the second adjustment operation.

[0102] First, the trimming control circuit 61 turns off the switches SW1 to SW3 and turns on the switch SW4 (S101). Next, the comparator CMP compares the voltage Vm of the node ND10 with the reference voltage Vref (S102). Next, the trimming control circuit 61 determines whether the comparison result RES of step S102 is at the “L” level (S103).

[0103] In step S103, when it is determined that the comparison result RES is at the “L” level (S103_Yes), the trimming control circuit 61 turns on the switch SW1 (S104). Next, the trimming control circuit 61 increases the value of the current In1 of the variable current source 41 by the trimming amount dI (S105). Next, the comparator CMP compares the voltage Vm with the voltage Vref (S106). Next, the trimming control circuit 61 determines whether the comparison result RES of step S106 has transitioned from the “L” level to the “H” level (S107).

[0104] In step S107, when it is determined that the logic level of the comparison result RES has not transitioned (S107_No), the trimming control circuit 61 executes step S105.

[0105] In step S107, when it is determined that the logical level of the comparison result RES has transitioned (S107_Yes), the trimming control circuit 61 stores "0" as the adjustment flag TFLG in the register 62 (S108). Next, the trimming control circuit 61 stores, in the register 62, the value of the current In1 at the time of the first loop processing one time before when the comparison result RES has transitioned, as the set value In1s of the current In1 (S109).

[0106] On the other hand, if it is determined in step S103 that the comparison result RES is not at the “L” level (S103_No), the trimming control circuit 61 turns on the switch SW2 (S110). Next, the trimming control circuit 61 increases the value of the current Ip1 by the trimming amount dI (S111). Next, the comparator CMP compares the voltage Vm with the voltage Vref (S112). Next, the trimming control circuit 61 determines whether the comparison result RES of step S112 has transitioned from the “H” level to the “L” level (S113).

[0107] In step S113, when it is determined that the logic level of the comparison result RES has not transitioned (S113_No), the trimming control circuit 61 executes step S111.

[0108] When it is determined in step S113 that the logical level of the comparison result RES has transitioned (S113_Yes), the trimming control circuit 61 stores "1" as the adjustment flag TFLG in the register 62 (S114). Next, the trimming control circuit 61 stores, in the register 62, the value of the current Ip1 at the time of the second loop processing one time before when the comparison result RES has transitioned, as the set value Ip1s of the current Ip1 (S115).

[0109] 1.2.2 Current monitor operation The current monitor operation will now be described. The current monitor operation includes a setting operation and a monitor execution operation. The setting operation is an operation for setting the current value of the variable current source 41 or the current value of the variable current source 42 to a current value adjusted by the current adjustment operation. The monitor execution operation is an operation for executing monitoring of the monitor current Icm.

[0110] (flowchart) FIG. 10 is a flowchart showing an example of the current monitoring operation of the semiconductor device 1.

[0111] When the current adjustment operation is completed, the control circuit 2 generates an “H” level signal as the control signal CS3 and transmits the generated “H” level control signal CS3 to the current monitor circuit 4. The “H” level control signal CS3 is, for example, a signal that instructs the execution of a current monitor operation.

[0112] Steps S201 to S208 are executed when an "H" level control signal CS3 is received from the control circuit 2. Steps S201 to S205, and S207 and S208 correspond to a setting operation.

[0113] First, the trimming control circuit 61 turns off the switches SW1, SW2, and SW4, and turns on the switch SW3 (S201). Next, the trimming control circuit 61 acquires the adjustment flag TFLG, the set value In1s, and the set value Ip1s from the register 62 (S202). Next, the trimming control circuit 61 determines whether the adjustment flag TFLG is "0" (S203).

[0114] If the adjustment flag TFLG is "0" (S203_Yes), the trimming control circuit 61 sets the value of the current In1 of the variable current source 41 to a set value In1s (S204). Next, the trimming control circuit 61 turns on the switch SW1 (S205). The connections of the semiconductor device 1 at this time are shown in Fig. 11. Fig. 11 is a circuit diagram showing the connections during the current monitoring operation of the semiconductor device 1 when the value of the current In1 of the variable current source 41 is adjusted to the set value In1s by the current adjustment operation.

[0115] On the other hand, if the adjustment flag TFLG is not "0" (S203_No), the trimming control circuit 61 sets the value of the current Ip1 of the variable current source 42 to the set value Ip1s (S207). Next, the trimming control circuit 61 turns on the switch SW2 (S208). The connections of the semiconductor device 1 at this time are shown in Fig. 12. Fig. 12 is a circuit diagram showing the connections during the current monitoring operation of the semiconductor device 1 when the value of the current Ip1 of the variable current source 42 is adjusted to the set value Ip1s by the current adjustment operation.

[0116] When step S205 or step S208 ends, the current monitor circuit 4 starts a monitor execution operation (S206). The current monitor circuit 4 can monitor the monitor current Icm in a state in which the current In1 is set to a current value In1s adjusted by the current adjustment operation, or in a state in which the current Ip1 is set to a current value Ip1s adjusted by the current adjustment operation. That is, the current monitor circuit 4 can monitor the monitor current Icm in a state in which the monitor current Icm is adjusted. Therefore, the current monitor circuit 4 can detect the monitor current Icm having a value relatively close to 0 in the case of no load.

[0117] 1.3 Effects of this embodiment In a semiconductor device including a driver circuit that drives an external load and a current monitor circuit that monitors the current flowing through the load, as described above, when the operational amplifier AMP has an input offset voltage and there is no load, the measurement accuracy of the monitor current Icm may deteriorate.

[0118] The semiconductor device 1 according to the present embodiment includes a driver circuit 3 and a current monitor circuit 4. The driver circuit 3 drives the load LD by supplying a load current Idrv to the load LD connectable to the input / output terminal T4. The current monitor circuit 4 includes a mirror circuit 5 that copies the load current Idrv based on the voltage VOUT of the input / output terminal T4, outputs the copied current Imr1, and monitors the monitor current Icm based on the current Imr1. The current monitor circuit 4 also includes a current adjustment circuit 6 that adjusts the monitor current Icm when there is no load. The current adjustment circuit 6 performs a current adjustment operation, so that the current monitor circuit 4 can monitor the monitor current Icm in a state where adjustment by the current adjustment operation has been performed. The adjustment performed by the current adjustment circuit 6 is an adjustment that takes into account the input offset voltage. Therefore, when there is no load, the current monitor circuit 4 can detect the monitor current Icm having a value relatively close to 0. Therefore, according to the present embodiment, the current measurement accuracy of the monitor current Icm can be improved.

[0119] 2. Second embodiment A semiconductor device according to a second embodiment will be described. In a semiconductor device 1A according to the second embodiment, the configuration of a current monitor circuit 4 is different from that of the first embodiment. In the following description, the differences from the first embodiment will be described.

[0120] 2.1 Circuit configuration of semiconductor device The circuit configuration of the semiconductor device 1A according to this embodiment will be described with reference to Fig. 13. Fig. 13 is a circuit diagram showing an example of the configuration of the semiconductor device 1A.

[0121] As shown in Fig. 13, the semiconductor device 1A includes a first power supply voltage terminal T1, a second power supply voltage terminal T2, a ground voltage terminal T3, an input / output terminal T4, a current monitor terminal T5, a control circuit 2, a driver circuit 3, and a current monitor circuit 4A. The configuration other than the current monitor circuit 4A is the same as the configuration shown in Fig. 1 in the first embodiment. Fig. 13 shows a state in which a load current Idrv flows from the second power supply voltage terminal T2 to a load LD via an NMOS transistor N1 and the input / output terminal T4.

[0122] 2.2 Circuit Configuration of Current Monitor Circuit The circuit configuration of the current monitor circuit 4A will be described. The semiconductor device 1A according to the present embodiment monitors the load current Idrv when driving the load LD by the NMOS transistor N1 of the driver circuit 3. That is, the current monitor circuit 4A is a current monitor circuit for high-side driving.

[0123] As shown in FIG. 13, the current monitor circuit 4A includes a mirror circuit 5A, PMOS transistors P1 and P2, NMOS transistors N6 and N7, switches SW1 and SW2, variable current sources 41 and 42, and a current adjustment circuit 6. The configurations other than the mirror circuit 5A and the NMOS transistors N6 and N7 are the same as those in the configuration of FIG. 1 shown in the first embodiment.

[0124] The mirror circuit 5A includes an NMOS transistor N5, a PMOS transistor P3, and an operational amplifier AMP. The configuration of the operational amplifier AMP is the same as that in the configuration of FIG. 1 shown in the first embodiment.

[0125] The NMOS transistor N5 has, for example, a gate width w1 (w1 < W1). The gate of the NMOS transistor N5 is connected to the node ND1. That is, the control signal CS1 is input to the gate of the NMOS transistor N5. One end of the NMOS transistor N5 is connected to the node ND21. The other end of the NMOS transistor N5 is connected to the second power supply voltage terminal T2.

[0126] The first input terminal of the operational amplifier AMP is connected to the node ND3. That is, the voltage VOUT of the input / output terminal T4 is applied to the first input terminal of the operational amplifier AMP. The second input terminal of the operational amplifier AMP is connected to the node ND21. That is, the voltage V21 of the node ND21 is applied to the second input / output terminal of the operational amplifier AMP. The operational amplifier AMP outputs a voltage Va from the output terminal based on the voltage VOUT and the voltage V21. The output terminal of the operational amplifier AMP is connected to the node ND4.

[0127] The gate of the PMOS transistor P3 is connected to the node ND4. That is, a voltage Va is applied to the gate of the PMOS transistor P3. One end of the PMOS transistor P3 is connected to the node ND22. The other end of the PMOS transistor P3 is connected to the node ND21.

[0128] The gate of the NMOS transistor N6 is connected to the node ND22. One end of the NMOS transistor N6 is connected to the node ND22. The other end of the NMOS transistor N6 is connected to the ground voltage terminal T3.

[0129] The gate of the NMOS transistor N7 is connected to the node ND22, one end of the NMOS transistor N7 is connected to the node ND6, and the other end of the NMOS transistor N7 is connected to the ground voltage terminal T3.

[0130] The switch SW1 is an element that switches between connection and disconnection between the node ND22 and the variable current source 41. One end of the switch SW1 is connected to the node ND22. The other end of the switch SW1 is connected to a node ND23.

[0131] The switch SW2 is an element that switches between connection and disconnection between the node ND6 and the variable current source 42. One end of the switch SW2 is connected to the node ND6. The other end of the switch SW2 is connected to a node ND24.

[0132] The variable current source 41 supplies a current In1 from the node ND22 to the ground voltage terminal T3. One end of the variable current source 41 is connected to the node ND23. The other end of the variable current source 41 is connected to the ground voltage terminal T3.

[0133] The variable current source 42 supplies a current Ip1 from the node ND6 to the ground voltage terminal T3. One end of the variable current source 42 is connected to the node ND24. The other end of the variable current source 42 is connected to the ground voltage terminal T3.

[0134] By the operational amplifier AMP and the PMOS transistor P3, the operational amplifier AMP outputs a voltage Va that makes the voltage VOUT equal to the voltage V21. That is, the voltage V21 is controlled to be equal to the voltage VOUT. Therefore, when the load LD is driven by the NMOS transistor N1 and the load current Idrv flows to the load LD, a copy current Imr1=Idrv×(w1 / W1) flows from the second power supply voltage terminal T2 to the ground voltage terminal T3 via the NMOS transistor N5, the PMOS transistor P3, and the NMOS transistor N6. Since the NMOS transistor N6 and the NMOS transistor N7 form a current mirror, a current of the same magnitude as the current Imr1 also flows from the first power supply voltage terminal T1 to the ground voltage terminal T3 via the PMOS transistor P1 and the NMOS transistor N7. Hereinafter, this current will be referred to as a "copy current Imr1'". Furthermore, since the PMOS transistor P1 and the PMOS transistor P2 form a current mirror, a monitor current Icm having the same magnitude as the current Imr1 also flows from the first power supply voltage terminal T1 to the node ND7 via the PMOS transistor P2.

[0135] 2.3 Operation The load driving operation, current monitoring operation, and current adjusting operation of the semiconductor device 1A are the same as those in the first embodiment. The first adjusting operation and the second adjusting operation will be described below.

[0136] (1st adjustment operation) 14 is a circuit diagram showing the connection relationship during the first adjustment operation of the semiconductor device 1A. Hereinafter, the current flowing through node ND21 is referred to as "current Ind21." The current flowing through node ND22 is referred to as "current Ind22." The current flowing through node ND6 is referred to as "current Ind6."

[0137] A case where the error (deviation from 0 to the positive side) of the monitor current Icm is 6×dI as in the example of FIG. 6 shown in the first embodiment will be described with reference to FIG.

[0138] As shown in Fig. 14, when the current In1 = 0, the current In1 does not flow to the node ND23. The current Ind21 = Imr1 = 6 x dI flows to the node ND21. The current Ind22 = Ind21 - In1 = 6 x dI flows to the node ND22. As a result, the current Imr1' = Ind22 = 6 x dI flows to the node ND6, and the monitor current Icm = Ind6 = 6 x dI flows to the node ND10.

[0139] When the current In1=dI, the current In1=dI flows through the node ND23. The current Ind21=6×dI flows through the node ND21. The current Ind22=5×dI flows through the node ND22. As a result, the current Imr1′=5×dI flows through the node ND6, and the monitor current Icm=5×dI flows through the node ND10.

[0140] When the current In1=2×dI, the current In1=2×dI flows through the node ND23. The current Ind21=6×dI flows through the node ND21. The current Ind22=4×dI flows through the node ND22. As a result, the current Imr1′=4×dI flows through the node ND6, and the monitor current Icm=4×dI flows through the node ND10.

[0141] When the current In1=3×dI, the current In1=3×dI flows through the node ND23. The current Ind21=6×dI flows through the node ND21. The current Ind22=3×dI flows through the node ND22. As a result, the current Imr1′=3×dI flows through the node ND6, and the monitor current Icm=3×dI flows through the node ND10.

[0142] When the current In1=4×dI, the current In1=4×dI flows through the node ND23. The current Ind21=6×dI flows through the node ND21. The current Ind22=2×dI flows through the node ND22. As a result, the current Imr1′=2×dI flows through the node ND6, and the monitor current Icm=2×dI flows through the node ND10.

[0143] When the current In1=5×dI, the current In1=5×dI flows through the node ND23. The current Ind21=6×dI flows through the node ND21. The current Ind22=dI flows through the node ND22. As a result, the current Imr1′=dI flows through the node ND6, and the monitor current Icm=dI flows through the node ND10.

[0144] When the current In1=6×dI, the current In1=6×dI flows through the node ND23. The current Ind21=6×dI flows through the node ND21. The current Ind22 does not flow through the node ND22 (Ind22=0). As a result, the current Imr1′ does not flow through the node ND6 (Imr1′=0), and the monitor current Icm does not flow through the node ND10 (Icm=0).

[0145] From the above, the trimming control circuit 61 selects 6×dI as the value of the current In1. By performing the first adjustment operation in this manner, the monitor current Icm is adjusted to approach zero.

[0146] (Second adjustment operation) FIG. 15 is a circuit diagram showing the connections during the second adjusting operation of the semiconductor device 1A.

[0147] 15, a copy current Imr1' having the same magnitude as the copy current Imr1 flows through node ND6. Therefore, similar to the first embodiment, the monitor current Icm is adjusted to approach 0 by adjusting the value of the current Ip1 of the variable current source 42 connected to node ND6. Therefore, as in the example of FIG. 8 shown in the first embodiment, when the error (deviation from 0 to the negative side) of the monitor current Icm is 6×dI, the second adjustment operation is performed, similar to the first embodiment, and the monitor current Icm is adjusted to approach 0.

[0148] 2.4 Effects of this embodiment According to this embodiment, the same effects as those of the first embodiment are achieved.

[0149] 3. Third embodiment A semiconductor device according to a third embodiment will be described. The semiconductor device 1B according to the third embodiment differs from the first embodiment in that a current detection circuit is included and the ground voltage terminal T3 and the current monitor terminal T5 are eliminated. In the following description, the differences from the first embodiment will be described.

[0150] 3.1 Circuit configuration of semiconductor device The circuit configuration of the semiconductor device 1B according to this embodiment will be described with reference to Fig. 16. Fig. 16 is a circuit diagram showing an example of the configuration of the semiconductor device 1B.

[0151] As shown in Fig. 16, the semiconductor device 1B includes a first power supply voltage terminal T1, a second power supply voltage terminal T2, an input / output terminal T4, a control circuit 2, a driver circuit 3, a current monitor circuit 4, and a current detection circuit 7. The configuration other than the current detection circuit 7 is similar to the configuration shown in Fig. 1 in the first embodiment. Fig. 16 shows a state in which the switches SW1 and SW3 are turned on and the switches SW2 and SW4 are turned off during a current monitoring operation.

[0152] The current detection circuit 7 is a circuit that detects the monitor current Icm. The current detection circuit 7 is connected to a node ND12. One end of the resistance element RL is connected to the node ND12.

[0153] The load driving operation, current monitoring operation, and current adjustment operation of the semiconductor device 1B are similar to those of the first embodiment. The current detection circuit 7 can detect the monitor current Icm by detecting the voltage of the node ND12.

[0154] 3.2 Effects of this embodiment According to this embodiment, the same effects as those of the first embodiment can be obtained. Of course, this embodiment can also be applied to the semiconductor device 1A according to the second embodiment.

[0155] 3.3 Variations A semiconductor device according to a modification of the third embodiment will be described. The semiconductor device 1C according to the modification of the third embodiment differs from the third embodiment in that the current detection circuit 7 is replaced with an A / D converter 8. In the following description, the differences from the third embodiment will be described.

[0156] 3.3.1 Circuit configuration of semiconductor device The circuit configuration of a semiconductor device 1C according to this modification will be described with reference to Fig. 17. Fig. 17 is a circuit diagram showing an example of the configuration of the semiconductor device 1C.

[0157] As shown in Fig. 17, the semiconductor device 1C includes a first power supply voltage terminal T1, a second power supply voltage terminal T2, an input / output terminal T4, a control circuit 2, a driver circuit 3, a current monitor circuit 4, and an A / D converter 8. The configuration other than the A / D converter 8 is similar to the configuration in Fig. 16 shown in the third embodiment. Fig. 17 shows a state in which the switches SW1 and SW3 are turned on and the switches SW2 and SW4 are turned off during a current monitor operation.

[0158] The A / D converter 8 is a circuit that converts the voltage V12 (analog value) of the node ND12 into a digital value (hereinafter, referred to as "voltage V12'"). The A / D converter 8 is connected to the node ND12. One end of the resistor element RL is connected to the node ND12.

[0159] The load driving operation, current monitoring operation, and current adjustment operation of the semiconductor device 1C are the same as those of the first embodiment. Since the voltage V12 is converted to a voltage V12' by the A / D converter 8, the monitor current Icm can be detected by detecting the converted voltage V12'.

[0160] 3.3.2 Effects of this modification This modification provides the same effects as those of the first embodiment. Of course, this modification can also be applied to the semiconductor device 1A according to the second embodiment.

[0161] 4. Modifications, etc. As described above, the semiconductor device (1) according to the embodiment includes a first circuit (3) that drives a load (LD) connectable to a first terminal (T4) by supplying a load current (Idrv) to the load, and a third circuit (4) that includes a second circuit (5) that copies the load current (Idrv) based on a first voltage (VOUT) of the first terminal (T4) and outputs the copied first current (Imr1) and monitors a second current (Icm) based on the first current. The third circuit (4) further includes a fourth circuit (6) that adjusts the second current (Icm) when the load current (Idrv) is not supplied to the load (LD).

[0162] The embodiment is not limited to the above-described embodiment, and various modifications are possible.

[0163] Furthermore, in the flowcharts described in the above embodiments, the order of the processes can be changed as much as possible.

[0164] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope of the invention and its equivalents described in the claims, as well as in the scope and spirit of the invention. [Explanation of symbols]

[0165] Reference Signs List 1, 1A, 1B, 1C...semiconductor device, 2...control circuit, 3...driver circuit, 4, 4A...current monitor circuit, 5, 5A...mirror circuit, 6...current adjustment circuit, 7...current detection circuit, 8...A / D converter, 41, 42...variable current source, 61...trimming control circuit, 62...register, T1...first power supply voltage terminal, T2...second power supply voltage terminal, T3...ground voltage terminal, T4...input / output terminal, T5...current monitor terminal, N1 to N7...NMOS transistors, P1 to P3...PMOS transistors, AMP...operational amplifier, SW1 to SW4...switch, CMP...converter, RL, Rm...resistance element, LD...load

Claims

1. a first circuit configured to supply a load current to a load connectable to the first terminal, thereby driving the load; a second circuit that copies the load current based on a first voltage of the first terminal and outputs a copied first current, and a third circuit that monitors a second current based on the first current; Equipped with The third circuit is a fourth circuit for regulating the second current when the load current is not supplied to the load; Further comprising: Semiconductor device.

2. the fourth circuit compares a second voltage obtained by converting the second current into a voltage with a reference voltage, and adjusts the second current to approach zero based on a result of the comparison. The semiconductor device according to claim 1.

3. When the semiconductor device is powered on, the fourth circuit adjusts the second current. The semiconductor device according to claim 1.

4. when the semiconductor device receives a signal requesting execution of adjustment of the second current from an external source, the fourth circuit adjusts the second current. The semiconductor device according to claim 1.

5. The fourth circuit is monitoring the second current while the second current is regulated; The semiconductor device according to claim 1.

6. The second circuit is a first transistor having a gate to which a control signal is input, one end connected to a first node, and the other end connected to a second terminal; an operational amplifier having a first input terminal to which the first voltage is applied, a second input terminal to which the third voltage of the first node is applied, and an output terminal to which a fourth voltage is output based on the first voltage and the third voltage; a second transistor having a gate to which the fourth voltage is applied, one end connected to the second node, and the other end connected to the first node; Including, The third circuit is a third transistor having a gate connected to the second node, one end connected to a third terminal, and the other end connected to the second node; a fourth transistor having a gate connected to the second node, one end connected to the third terminal, and the other end connected to the third node; a first switch having one end connected to the third terminal and the other end connected to a fourth node; a second switch having one end connected to the second node and the other end connected to a fifth node; a first variable current source having one end connected to the fourth node and the other end connected to the second node; a second variable current source having one end connected to the fifth node and the other end connected to the second terminal; Further comprising: The fourth circuit is a third switch having one end connected to the third node and the other end connected to a sixth node; a fourth switch having one end connected to the third node and the other end connected to a seventh node; a resistive element having one end connected to the seventh node and the other end connected to the second terminal; a comparator that compares the fifth voltage at the seventh node with a reference voltage and outputs the comparison result; a control circuit that adjusts the second current to approach zero based on the result; Including, The semiconductor device according to claim 1.

7. If the fifth voltage is equal to or greater than the reference voltage, the control circuit turns on the first switch and turns off the second switch to increase the current of the first variable current source; If the fifth voltage is less than the reference voltage, the control circuit turns the first switch to an OFF state and turns the second switch to an ON state to increase the current of the second variable current source; 7. The semiconductor device according to claim 6.

8. If the fifth voltage is equal to or greater than the reference voltage, The control circuit includes: repeatedly executing a first loop process including a process of turning on the first switch, turning off the second switch, and increasing the current of the first variable current source by a first trimming amount, and a process of determining whether or not a logic level of the result has transitioned; adjusting the current value of the first variable current source to a first current value at the time of the first loop processing one time before when the logic level of the result transitions; If the fifth voltage is less than the reference voltage, The control circuit includes: repeatedly executing a second loop process including a process of turning off the first switch, turning on the second switch, and increasing the current of the second variable current source by a second trimming amount, and a process of determining whether or not the logic level of the result has transitioned; adjusting the current value of the second variable current source to a second current value at the time of the second loop processing one time before when the logic level of the result transitions; 7. The semiconductor device according to claim 6.

9. The fourth circuit is A register for storing the result of the adjustment by the fourth circuit Including, The semiconductor device according to claim 1.

10. The second circuit is a fifth transistor having a gate to which a control signal is input, one end connected to the eighth node, and the other end connected to the fourth terminal; an operational amplifier having a first input terminal to which the first voltage is applied, a second input terminal to which the sixth voltage of the eighth node is applied, and an output terminal to which a seventh voltage is output based on the first voltage and the sixth voltage; a sixth transistor having a gate to which the seventh voltage is applied, one end connected to the ninth node, and the other end connected to the eighth node; Including, The third circuit is a seventh transistor having a gate connected to the ninth node, one end connected to the ninth node, and the other end connected to the fifth terminal; an eighth transistor having a gate connected to the ninth node, one end connected to a tenth node, and the other end connected to the fifth terminal; a ninth transistor having a gate connected to the tenth node, one end connected to the sixth terminal, and the other end connected to the tenth node; a tenth transistor having a gate connected to the tenth node, one end connected to the sixth terminal, and the other end connected to an eleventh node; a fifth switch, one end of which is connected to the ninth node and the other end of which is connected to a twelfth node; a sixth switch, one end of which is connected to the tenth node and the other end of which is connected to a thirteenth node; a third variable current source having one end connected to the twelfth node and the other end connected to the fifth terminal; a fourth variable current source having one end connected to the thirteenth node and the other end connected to the fifth terminal; Further comprising: The fourth circuit is a seventh switch having one end connected to the eleventh node and the other end connected to a fourteenth node; an eighth switch, one end of which is connected to the eleventh node and the other end of which is connected to a fifteenth node; a resistive element having one end connected to the fifteenth node and the other end connected to the fifth terminal; a comparator that compares the eighth voltage of the fifteenth node with a reference voltage and outputs the comparison result; a control circuit that adjusts the second current to approach zero based on the result; Including, The semiconductor device according to claim 1.

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