Power amplification device

Abstract

To realize a power amplification device capable of achieving a higher frequency and a higher output.SOLUTION: A power amplification device comprises: a substrate 2; and a chip device 3 mounted onto a main surface of the substrate 2. The chip device 3 comprises: a first difference amplifier containing a first carrier amplifier CA1 and a second carrier amplifier CA2; and a second difference amplifier containing a first peak amplifier PA1 and a second peak amplifier PA2. In the chip device 3, the first carrier amplifier CA1 and the second carrier amplifier CA2 are arranged in a first direction, and the first carrier amplifier CA1 and the first peak amplifier PA1 are arranged in a second direction that is different from the first direction. The first peak amplifier PA1 and the second peak amplifier PA2 are arranged in the first direction, and the second carrier amplifier CA2 and the second peak amplifier PA2 are arranged in the second direction.SELECTED DRAWING: Figure 2A

Description

[Technical field]

[0001] The present disclosure relates to a power amplifier device. [Background technology]

[0002] A Doherty amplifier circuit is known as a highly efficient power amplifier circuit. A Doherty amplifier circuit is generally configured in such a way that a carrier amplifier that operates regardless of the power level of a high-frequency input signal and a peak amplifier that is turned off when the power level of the high-frequency input signal is low and turned on when the power level of the high-frequency input signal is high are connected in parallel. In this configuration, when the power level of the high-frequency input signal is high, the carrier amplifier operates while maintaining saturation at the saturated output power level. This allows the Doherty amplifier circuit to have improved efficiency compared to a normal power amplifier circuit. A high-frequency module has been disclosed in which such a Doherty amplifier circuit is configured in a differential configuration, and an amplifier and a phase circuit that constitute a differential Doherty amplifier circuit, and a transformer for output matching are arranged on a module substrate (for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2022-90557 Summary of the Invention [Problem to be solved by the invention]

[0004] In recent years, increasing the frequency and output of power amplifiers has become an issue. In order to achieve higher frequencies and higher output in a differential Doherty amplifier, the impedance of the phase circuit must be low. In order to obtain good amplification characteristics, it is also desirable for the impedance of the phase circuit to be symmetric between differentials.

[0005] The present disclosure has been made in view of the above, and has an object to provide a power amplifier device capable of achieving higher frequencies and higher output. [Means for solving the problem]

[0006] A power amplification device according to one aspect of the present disclosure includes a substrate and a chip device mounted on a main surface of the substrate, the chip device including a first differential amplifier including a first carrier amplifier and a second carrier amplifier, and a second differential amplifier including a first peak amplifier and a second peak amplifier, and in the chip device, the first carrier amplifier and the second carrier amplifier are aligned in a first direction, the first carrier amplifier and the first peak amplifier are aligned in a second direction different from the first direction, the first peak amplifier and the second peak amplifier are aligned in the first direction, and the second carrier amplifier and the second peak amplifier are aligned in the second direction.

[0007] In this configuration, the impedance of the phase circuit provided between the first differential amplifier and the second differential amplifier can be reduced. This allows the power amplifier device to operate at higher frequencies and with higher output. In addition, the impedance of the phase circuit provided between the first carrier amplifier and the first peak amplifier and the phase circuit provided between the first carrier amplifier and the first peak amplifier can be made substantially symmetrical. This allows good amplification characteristics to be obtained. Effect of the Invention

[0008] According to the present disclosure, it is possible to realize a power amplifier device capable of achieving higher frequencies and higher output. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a diagram illustrating an example of a circuit configuration of a power amplifier device according to the present disclosure. [Figure 2A] FIG. 2A is a plan view showing an example of a conceptual layout of components of the power amplifier device according to the first embodiment. [Figure 2B] FIG. 2B is a plan view showing an example of a conceptual layout of the components of the power amplifier device according to the first embodiment. [Diagram 3]FIG. 3 is a plan view showing an example of a conceptual layout of components of a power amplifying device according to a first modification of the first embodiment. [Figure 4A] FIG. 4A is a diagram showing an example of the configuration of a first phase shift circuit and a second phase shift circuit according to a second modified example of the first embodiment. [Figure 4B] FIG. 4B is a diagram illustrating an example of the configuration of a first phase circuit and a second phase circuit according to a third modified example of the first embodiment. [Figure 4C] FIG. 4C is a diagram illustrating an example of the configuration of a first phase circuit and a second phase circuit according to a fourth modified example of the first embodiment. [Figure 4D] FIG. 4D is a diagram illustrating an example of the configuration of a first phase shift circuit and a second phase shift circuit according to a fifth modified example of the first embodiment. [Diagram 5] FIG. 5 is a plan view showing an example of a conceptual layout of components of a power amplifier device according to the second embodiment. [Figure 6A] FIG. 6A is a plan view showing an example of a conceptual layout of components of a power amplifying device according to the third embodiment. [Figure 6B] FIG. 6B is a plan view showing an example of a conceptual layout of components of the power amplifying device according to the third embodiment. [Figure 7A] FIG. 7A is a diagram illustrating a configuration example of a phase circuit according to a first modified example of the third embodiment. [Figure 7B] FIG. 7B is a diagram illustrating an example of the configuration of a phase circuit according to a second modification of the third embodiment. [Figure 8] FIG. 8 is a plan view showing an example of a conceptual layout of components of a power amplifying device according to a third modification of the third embodiment. [Figure 9] FIG. 9 is a plan view showing an example of a conceptual layout of components of a power amplifying device according to a fourth modification of the third embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] The power amplifier device according to the embodiment will be described in detail below with reference to the drawings. Note that the present disclosure is not limited to the embodiment. Each embodiment is an example, and it goes without saying that partial replacement or combination of the configurations shown in different embodiments is possible. In the second and subsequent embodiments, a description of matters common to the first embodiment will be omitted, and only the differences will be described. In particular, similar effects resulting from similar configurations will not be mentioned in each embodiment.

[0011] 1 is a diagram showing an example of a circuit configuration of a power amplifier according to the present disclosure. The power amplifier 1 amplifies a radio frequency input signal RFin and outputs a radio frequency output signal RFout. In the present disclosure, the power amplifier 1 is a differentiated Doherty type power amplifier circuit (hereinafter also referred to as a "differential Doherty amplifier circuit").

[0012] The differential Doherty amplifier circuit includes a first carrier amplifier CA1, a second carrier amplifier CA2, a first peaking amplifier PA1, a second peaking amplifier PA2, a first conversion circuit T1, a second conversion circuit T2, and a third conversion circuit T3.

[0013] The first carrier amplifier CA1 and the second carrier amplifier CA2 configure a first differential amplifier A1. The first conversion circuit T1 converts a high-frequency input signal RFin, which is an unbalanced input signal, into a differential signal and inputs it to the first differential amplifier A1. The first conversion circuit T1 is configured, for example, by a balun transformer.

[0014] The first peak amplifier PA1 and the second peak amplifier PA2 configure a second differential amplifier A2. The second conversion circuit T2 converts the unbalanced input signal input via the input phase shift circuit 4 and the drive stage amplifier DA into a differential signal and inputs it to the second differential amplifier A2. The second conversion circuit T2 is configured, for example, by a balun transformer.

[0015] The input phase shift circuit 4 is a circuit that delays the phase of the high frequency input signal RFin by 90 deg. The input phase shift circuit 4 is configured by, for example, a transmission line or a 90 deg hybrid coupler.

[0016] The drive stage amplifier DA includes a first drive stage amplifier DA1 and a second drive stage amplifier DA2. The first drive stage amplifier DA1 amplifies a high frequency input signal RFin, which is an unbalanced input signal, and inputs it to the first conversion circuit T1. The second drive stage amplifier DA2 amplifies an unbalanced input signal that is a 90 deg delay from the high frequency input signal RFin, and inputs it to the second conversion circuit T2.

[0017] A phase circuit 5 is provided between the output of the first differential amplifier A1 and the output of the second differential amplifier A2. The phase circuit 5 is a circuit that delays the phase of the differential output of the first differential amplifier A1 by 90 deg.

[0018] The phase shift circuit 5 includes a first phase shift circuit 51 having one end connected to the output of the first carrier amplifier CA1 and the other end connected to the output of the first peak amplifier PA1, and a second phase shift circuit 52 having one end connected to the output of the second carrier amplifier CA2 and the other end connected to the output of the second peak amplifier PA2. The first phase shift circuit 51 delays the output phase of the first carrier amplifier CA1 by 90 degrees. The second phase shift circuit 52 delays the output phase of the second carrier amplifier CA2 by 90 degrees. The first phase shift circuit 51 and the second phase shift circuit 52 are each formed of, for example, a transmission line or an LC circuit including an inductor and a capacitor.

[0019] The differential signal output from the connection point between the output of the second differential amplifier A2 and the phase shift circuit 5 is converted into an unbalanced output signal RFout by the third conversion circuit T3. The third conversion circuit T3 is formed of, for example, a balun transformer.

[0020] In the differential Doherty amplifier circuit shown in FIG. 1, the first differential amplifier A1 (the first carrier amplifier CA1 and the second carrier amplifier CA2) operates regardless of the power level of the high frequency input signal RFin. In addition, the second differential amplifier A2 (the first peak amplifier PA1 and the second peak amplifier PA2) is turned off when the power level of the high frequency input signal RFin is small, and is turned on when the power level is large. The first differential amplifier A1 and the second differential amplifier A2 are connected in parallel to configure the differential Doherty amplifier circuit. In this configuration, when the power level of the high frequency input signal RFin is large, the first differential amplifier A1 (the first carrier amplifier CA1 and the second carrier amplifier CA2) operates while maintaining saturation at the saturated output power level. This allows the differential Doherty amplifier circuit to have improved efficiency compared to a normal differential amplifier circuit.

[0021] (Embodiment 1) 2A and 2B are plan views showing conceptual layout examples of components of the power amplifier device according to the first embodiment.

[0022] 2A and 2B show an example of the power amplifier device 1 mounted on a front-end module. The front-end module is an ultra-compact integrated module in which a plurality of integrated circuits and various functional components are mounted on the main surface of a substrate 2 parallel to an XY plane including an X direction and a Y direction perpendicular to the X direction shown in FIGS. 2A and 2B. The substrate 2 includes a substrate that is approximately parallel to the XY plane, such as a substrate having a somewhat uneven surface. The substrate 2 is exemplified by a ceramic laminate substrate such as a low temperature co-fired ceramics (LTCC) substrate, a resin multilayer substrate, a film substrate, and the like. The X direction and the Y direction are not necessarily limited to being perpendicular to each other. The X direction and the Y direction may be approximately perpendicular to each other (approximately perpendicular to each other).

[0023] 2A and 2B are configured on a die of a chip device 3 that is flip-chip mounted in the Z direction on a substrate 2. Specifically, FIGs. 2A and 2B show an example in which at least a first carrier amplifier CA1, a second carrier amplifier CA2, a first peak amplifier PA1, a second peak amplifier PA2, a first conversion circuit T1, and a second conversion circuit T2 are configured on a die of the chip device 3.

[0024] In the present disclosure, the third conversion circuit T3 is provided on the substrate 2. Specifically, when the third conversion circuit T3 is configured with a balun transformer, the windings of the balun transformer are configured with wiring provided on the substrate 2. This contributes to miniaturization of the chip device 3. The third conversion circuit T3 may be configured with, for example, a 180 deg hybrid coupler. This makes it possible to suppress fluctuations in output characteristics with respect to fluctuations in load impedance of the power amplifier 1, compared to a configuration in which the third conversion circuit T3 is a balun transformer.

[0025] The chip device 3 is, for example, an HBT device (integrated circuit, IC) including a GaAs (gallium arsenide)-based heterojunction bipolar transistor (HBT), or a silicon device (integrated circuit, IC) including a Si (silicon)-based field effect transistor (FET). A first carrier amplifier CA1, a second carrier amplifier CA2, a first peak amplifier PA1, and a second peak amplifier PA2 are configured on a die of the chip device 3. The chip device 3 is bump-bonded to the main surface of the substrate 2 using, for example, a copper pillar.

[0026] 2A, in the layout of the power amplifier 1 according to the first embodiment, the chip device 3 has the first carrier amplifier CA1 and the second carrier amplifier CA2 arranged in the X direction (first direction), and the first carrier amplifier CA1 and the first peak amplifier PA1 arranged in the Y direction (second direction). Also, the first peak amplifier PA1 and the second peak amplifier PA2 arranged in the X direction (first direction), and the second carrier amplifier CA2 and the second peak amplifier PA2 arranged in the Y direction (second direction).

[0027] In the layout of the power amplifier 1 of embodiment 1 shown in FIG. 2B, the first carrier amplifier CA1, the second carrier amplifier CA2, the first peak amplifier PA1, and the second peak amplifier PA2 are respectively provided at positions shifted from the positions of the first carrier amplifier CA1, the second carrier amplifier CA2, the first peak amplifier PA1, and the second peak amplifier PA2 shown by solid lines in the layout shown in FIG. 2A (the positions shown by dashed dotted lines in FIG. 2B).

[0028] 2A illustrates an example in which the arrangement direction of the first carrier amplifier CA1 and the second carrier amplifier CA2 is parallel to the arrangement direction of the first peak amplifier PA1 and the second peak amplifier PA2, but as shown in FIG 2B, the arrangement direction of the first carrier amplifier CA1 and the second carrier amplifier CA2 is not necessarily limited to being parallel to the arrangement direction of the first peak amplifier PA1 and the second peak amplifier PA2. In other words, in the layout illustrated in FIG 2B, if the first carrier amplifier CA1 is arranged such that at least a part of the first carrier amplifier CA1 hits somewhere on the second carrier amplifier CA2 when the first carrier amplifier CA1 is moved in the X direction (first direction), the first carrier amplifier CA1 and the second carrier amplifier CA2 may be arranged in the X direction (first direction). Furthermore, if the first peak amplifier PA1 is positioned such that at least a part of the first peak amplifier PA1 comes into contact with somewhere on the second peak amplifier PA2 when the first peak amplifier PA1 is moved in the X direction (first direction), the first peak amplifier PA1 and the second peak amplifier PA2 may be said to be aligned in the X direction (first direction).

[0029] 2A illustrates an example in which the arrangement direction of the first carrier amplifier CA1 and the first peak amplifier PA1 is parallel to the arrangement direction of the second carrier amplifier CA2 and the second peak amplifier PA2, but as shown in FIG 2B, the arrangement direction of the first carrier amplifier CA1 and the first peak amplifier PA1 and the arrangement direction of the second carrier amplifier CA2 and the second peak amplifier PA2 are not necessarily limited to being parallel. In other words, in the present disclosure, in the layout illustrated in FIG 2B, if the first carrier amplifier CA1 is arranged such that at least a part of the first carrier amplifier CA1 hits somewhere on the first peak amplifier PA1 when the first carrier amplifier CA1 is moved in the Y direction (second direction), the first carrier amplifier CA1 and the first peak amplifier PA1 may be arranged in the Y direction (second direction). Furthermore, if the second carrier amplifier CA2 is positioned such that when the second carrier amplifier CA2 is moved in the Y direction (second direction), at least a part of the second carrier amplifier CA2 contacts somewhere on the second peak amplifier PA2, the second carrier amplifier CA2 and the second peak amplifier PA2 may be aligned in the Y direction (second direction).

[0030] The first conversion circuit T1 is provided between the first carrier amplifier CA1 and the second carrier amplifier CA2, and the second conversion circuit T2 is provided between the first peak amplifier PA1 and the second peak amplifier PA2.

[0031] In the layout shown in FIG. 2A and FIG. 2B, the first phase circuit 51 and the second phase circuit 52 are transmission lines provided on the die of the chip device 3. The input phase circuit 4 is composed of a 90 deg hybrid coupler provided on the die of the chip device 3. The input phase circuit 4 is provided between the first conversion circuit T1 and the second conversion circuit T2. The first drive stage amplifier DA1 is provided between the input phase circuit 4 and the first conversion circuit T1. The second drive stage amplifier DA2 is provided between the input phase circuit 4 and the second conversion circuit T2.

[0032] The layout of the power amplifier 1 according to the first embodiment shown in FIGS. 2A and 2B reduces the physical distance between the first differential amplifier A1 (the first carrier amplifier CA1 and the second carrier amplifier CA2) and the second differential amplifier A2 (the first peak amplifier PA1 and the second peak amplifier PA2), and the first phase circuit 51 and the second phase circuit 52 can have low impedance. This allows the power amplifier 1 to achieve higher frequency and higher output. In addition, the arrangement of the first carrier amplifier CA1 and the first peak amplifier PA1 and the arrangement of the second carrier amplifier CA2 and the second peak amplifier PA2 are approximately symmetrical, and the impedances of the first phase circuit 51 and the second phase circuit 52 can be approximately symmetrical. This allows good amplification characteristics to be obtained.

[0033] A modification of the power amplifying device according to the first embodiment will be described below.

[0034] Fig. 3 is a plan view showing a conceptual layout example of components of a power amplifier device according to a first modified example of embodiment 1. In the layout of a power amplifier device 1a shown in Fig. 3, a first phase circuit 51 and a second phase circuit 52 are transmission lines provided on a substrate 2.

[0035] Fig. 4A is a diagram showing a configuration example of a first phase circuit and a second phase circuit according to a second modified example of the first embodiment. Fig. 4B is a diagram showing a configuration example of a first phase circuit and a second phase circuit according to a third modified example of the first embodiment. Fig. 4C is a diagram showing a configuration example of a first phase circuit and a second phase circuit according to a fourth modified example of the first embodiment. Fig. 4D is a diagram showing a configuration example of a first phase circuit and a second phase circuit according to a fifth modified example of the first embodiment.

[0036] In the configuration examples shown in Figures 4A, 4B, 4C, and 4D, the first phase circuit 51 and the second phase circuit 52 are LC circuits composed of an inductor L and a capacitor C. This allows the first phase circuit 51 and the second phase circuit 52 to be smaller in size than a configuration in which the first phase circuit 51 and the second phase circuit 52 are transmission lines. In addition, in the configurations shown in Figures 4C and 4D, the LC circuits are made multi-staged, thereby allowing the bandwidth to be broadened compared to the configurations shown in Figures 4A and 4B.

[0037] (Embodiment 2) FIG. 5 is a plan view showing an example of a conceptual layout of components of a power amplifier device according to the second embodiment.

[0038] In the configuration of the power amplifier device 1b according to the second embodiment, the input phase circuit 4 includes a divider 4a and a transmission line 4b. The divider 4a is, for example, a Wilkinson type power divider configured on the die of the chip device 3. The transmission line 4b is provided on the substrate 2.

[0039] In the layout shown in FIG. 5, a first drive stage amplifier DA1, a first conversion circuit T1, a second drive stage amplifier DA2, and a second conversion circuit T2 are arranged in this order in the Y direction (second direction) on the die of the chip device 3.

[0040] The layout of the power amplifier 1b according to the second embodiment shown in FIG. 5 further shortens the physical distance between the first differential amplifier A1 (the first carrier amplifier CA1 and the second carrier amplifier CA2) and the second differential amplifier A2 (the first peak amplifier PA1 and the second peak amplifier PA2) compared to the first embodiment, and the first phase circuit 51 and the second phase circuit 52 can be made to have lower impedance. This allows the power amplifier 1b to achieve higher frequency and higher output. In addition, in the layout of the power amplifier 1b according to the second embodiment shown in FIG. 5, by making the first phase circuit 51 and the second phase circuit 52 into LC circuits composed of an inductor L and a capacitor C, it is possible to achieve a smaller size and a wider bandwidth, similar to the first embodiment.

[0041] (Embodiment 3) 6A and 6B are plan views showing conceptual layout examples of components of a power amplifying device according to the third embodiment.

[0042] 6A, in the layout of the power amplifier 1c according to the third embodiment, the chip device 3 has the first carrier amplifier CA1 and the second carrier amplifier CA2 arranged in the Y direction (first direction), and the first carrier amplifier CA1 and the first peak amplifier PA1 arranged in the X direction (second direction). Also, the first peak amplifier PA1 and the second peak amplifier PA2 arranged in the Y direction (first direction), and the second carrier amplifier CA2 and the second peak amplifier PA2 arranged in the X direction (second direction).

[0043] In the layout of the power amplifier 1c of embodiment 3 shown in FIG. 6B, the first carrier amplifier CA1, the second carrier amplifier CA2, the first peak amplifier PA1, and the second peak amplifier PA2 are respectively provided at positions shifted from the positions of the first carrier amplifier CA1, the second carrier amplifier CA2, the first peak amplifier PA1, and the second peak amplifier PA2 shown by solid lines in the layout shown in FIG. 6A (the positions shown by dashed lines in FIG. 6B).

[0044] 6A illustrates an example in which the arrangement direction of the first carrier amplifier CA1 and the second carrier amplifier CA2 is parallel to the arrangement direction of the first peak amplifier PA1 and the second peak amplifier PA2, but as shown in FIG 6B, the arrangement direction of the first carrier amplifier CA1 and the second carrier amplifier CA2 is not necessarily limited to being parallel to the arrangement direction of the first peak amplifier PA1 and the second peak amplifier PA2. In other words, in the layout shown in FIG 6B, if the first carrier amplifier CA1 is arranged such that at least a part of the first carrier amplifier CA1 hits somewhere on the second carrier amplifier CA2 when the first carrier amplifier CA1 is moved in the Y direction (first direction), the first carrier amplifier CA1 and the second carrier amplifier CA2 may be arranged in the Y direction (first direction). Furthermore, if the first peak amplifier PA1 is positioned such that at least a part of the first peak amplifier PA1 comes into contact with somewhere on the second peak amplifier PA2 when the first peak amplifier PA1 is moved in the Y direction (first direction), the first peak amplifier PA1 and the second peak amplifier PA2 may be said to be aligned in the Y direction (first direction).

[0045] 6A illustrates an example in which the arrangement direction of the first carrier amplifier CA1 and the first peak amplifier PA1 is parallel to the arrangement direction of the second carrier amplifier CA2 and the second peak amplifier PA2, but as shown in FIG 6B, the arrangement direction of the first carrier amplifier CA1 and the first peak amplifier PA1 and the arrangement direction of the second carrier amplifier CA2 and the second peak amplifier PA2 are not necessarily limited to being parallel. In other words, in the present disclosure, the first carrier amplifier CA1 and the first peak amplifier PA1 may be arranged in the X direction (second direction) if the first carrier amplifier CA1 is arranged so that at least a part of the first carrier amplifier CA1 hits somewhere on the first peak amplifier PA1 when the first carrier amplifier CA1 is moved in the X direction (second direction) in the layout shown in FIG 6B. Furthermore, if the second carrier amplifier CA2 is positioned such that at least a part of the second carrier amplifier CA2 comes into contact with somewhere on the second peak amplifier PA2 when the second carrier amplifier CA2 is moved in the X direction (second direction), the second carrier amplifier CA2 and the second peak amplifier PA2 may be aligned in the X direction (second direction).

[0046] The first differential amplifier A1 (first carrier amplifier CA1, second carrier amplifier CA2) and the second differential amplifier A2 (first peak amplifier PA1, second peak amplifier PA2) are provided between the first conversion circuit T1 and the second conversion circuit T2. The input phase circuit 4 is composed of a 90 deg hybrid coupler provided on the die of the chip device 3.

[0047] As in the first and second embodiments, the layout of the power amplifier 1c according to the third embodiment shown in FIG. 6A and FIG. 6B shortens the physical distance between the first differential amplifier A1 (the first carrier amplifier CA1 and the second carrier amplifier CA2) and the second differential amplifier A2 (the first peak amplifier PA1 and the second peak amplifier PA2), and the first phase circuit 51 and the second phase circuit 52 can have low impedance. This allows the power amplifier 1c to achieve higher frequency and higher output. Also, as in the first and second embodiments, the arrangement of the first carrier amplifier CA1 and the first peak amplifier PA1 and the arrangement of the second carrier amplifier CA2 and the second peak amplifier PA2 are approximately symmetrical, and the impedances of the first phase circuit 51 and the second phase circuit 52 can be approximately symmetrical. This allows good amplification characteristics to be obtained.

[0048] A modification of the power amplifying device according to the third embodiment will be described below.

[0049] Fig. 7A is a diagram showing a configuration example of a phase circuit according to a first modified example of embodiment 3. Fig. 7B is a diagram showing a configuration example of a phase circuit according to a second modified example of embodiment 3.

[0050] In the configuration examples shown in Figures 7A and 7B, the phase shift circuit 5 is an LC circuit composed of an inductor L and a capacitor C. This allows for a smaller size compared to a configuration in which the first phase shift circuit 51 and the second phase shift circuit 52 are transmission lines. In addition, in the configuration shown in Figure 7B, the LC circuit is made multi-staged, thereby enabling a wider bandwidth compared to the configuration shown in Figure 7A.

[0051] 8 is a plan view showing a conceptual layout example of components of a power amplifier device according to a third modification of the third embodiment. In the configuration of a power amplifier device 1d according to the third modification of the third embodiment, the input phase circuit 4 includes a divider 4a and a transmission line 4b. The divider 4a is, for example, a Wilkinson type power divider configured on the die of the chip device 3. The transmission line 4b is provided on the substrate 2.

[0052] 9 is a plan view showing a conceptual layout example of components of a power amplifier device according to a fourth modification of the embodiment 3. In the configuration of a power amplifier device 1e according to the fourth modification of the embodiment 3, the input phase circuit 4 includes a distributor 4a and a transmission line 4c. The transmission line 4c is provided on the die of the chip device 3.

[0053] The above-described embodiment is for facilitating understanding of the present disclosure, and is not intended to limit the present disclosure. The present disclosure may be modified or improved without departing from the spirit of the present disclosure, and equivalents thereof are also included in the present disclosure.

[0054] The present disclosure can have the following configuration as described above or instead of the above.

[0055] (1) A power amplification apparatus according to one aspect of the present disclosure includes a substrate and a chip device mounted on a main surface of the substrate, the chip device including a first differential amplifier including a first carrier amplifier and a second carrier amplifier, and a second differential amplifier including a first peak amplifier and a second peak amplifier, wherein in the chip device, the first carrier amplifier and the second carrier amplifier are aligned in a first direction, the first carrier amplifier and the first peak amplifier are aligned in a second direction different from the first direction, the first peak amplifier and the second peak amplifier are aligned in the first direction, and the second carrier amplifier and the second peak amplifier are aligned in the second direction.

[0056] In this configuration, the impedance of the phase circuit provided between the first differential amplifier and the second differential amplifier can be reduced. This allows the power amplifier device to operate at higher frequencies and with higher output. In addition, the impedance of the phase circuit provided between the first carrier amplifier and the first peak amplifier and the phase circuit provided between the first carrier amplifier and the first peak amplifier can be made substantially symmetrical. This allows good amplification characteristics to be obtained.

[0057] (2) The power amplifying device according to (1) above, further comprising a phase circuit that delays the phase of the differential output of the first differential amplifier by 90 deg.

[0058] (3) In the power amplifier device of (2) above, the phase circuit includes a first phase circuit having one end connected to the output of the first carrier amplifier and the other end connected to the output of the first peak amplifier, and a second phase circuit having one end connected to the output of the second carrier amplifier and the other end connected to the output of the second peak amplifier.

[0059] (4) In the power amplifier device of (3) above, the first phase circuit and the second phase circuit are configured by a transmission line provided on the chip device or the substrate.

[0060] (5) In the power amplifier device of (2) above, the phase circuit is composed of an LC circuit including an inductor and a capacitor.

[0061] With this configuration, it is possible to realize a power amplifier device that is compact and has a wide bandwidth.

[0062] (6) In the power amplification device of (2) to (5) above, the chip device includes a first conversion circuit that converts an unbalanced input signal into a differential signal and inputs it to the first differential amplifier, and a second conversion circuit that converts the unbalanced input signal into a differential signal and inputs it to the second differential amplifier, and the substrate includes a third conversion circuit that converts the differential signal output from the chip device into an unbalanced output signal.

[0063] (7) In the power amplifier device described above in (6), the first conversion circuit and the second conversion circuit are configured with a balun transformer.

[0064] (8) In the power amplifying device according to (6) or (7) above, the third conversion circuit is configured with a balun transformer.

[0065] (9) In the power amplifying device according to (6) or (7) above, the third conversion circuit is configured as a hybrid coupler.

[0066] With this configuration, it is possible to suppress fluctuations in the output characteristics of the power amplifier device due to fluctuations in the load impedance.

[0067] (10) The power amplifier device according to any one of (6) to (9) above, further comprising a first drive stage amplifier that amplifies an unbalanced input signal and inputs it to the first conversion circuit, a second drive stage amplifier that amplifies the unbalanced input signal and inputs it to the second conversion circuit, and an input phase circuit that delays the phase of the unbalanced input signal input to the second conversion circuit by 90 degrees relative to the unbalanced input signal input to the first conversion circuit.

[0068] (11) In the power amplification device of (10) above, the first conversion circuit is provided between the first carrier amplifier and the second carrier amplifier, and the second conversion circuit is provided between the first peak amplifier and the second peak amplifier.

[0069] (12) In the power amplifier device of (11) above, the input phase circuit is configured with a hybrid coupler.

[0070] (13) In the power amplifier device of (12) above, the input phase circuit is provided between the first conversion circuit and the second conversion circuit, the first drive stage amplifier is provided between the input phase circuit and the first conversion circuit, and the second drive stage amplifier is provided between the input phase circuit and the second conversion circuit.

[0071] (14) In the power amplifier device of (11) above, the input phase circuit includes a transmission line provided on the substrate, and in the chip device, the first drive stage amplifier, the first conversion circuit, the second drive stage amplifier, and the second conversion circuit are arranged in that order in the second direction.

[0072] In this configuration, the impedance of the first phase circuit and the second phase circuit can be further reduced, thereby enabling the power amplifier device to achieve higher frequencies and higher output.

[0073] (15) In the power amplifying device according to (10) above, the first differential amplifier and the second differential amplifier are provided between the first conversion circuit and the second conversion circuit.

[0074] In this configuration, the impedance of the first phase circuit and the second phase circuit can be further reduced, thereby enabling the power amplifier device to achieve higher frequencies and higher output.

[0075] (16) In the power amplifier device of (15) above, the input phase circuit is configured with a hybrid coupler.

[0076] (17) In the power amplifier device described above in (15), the input phase circuit includes a transmission line provided on the substrate.

[0077] (18) In the power amplifier device described above in (15), the input phase circuit includes a transmission line provided in the chip device.

[0078] According to the present disclosure, it is possible to realize a power amplifier device capable of achieving higher frequencies and higher output. [Explanation of symbols]

[0079] 1, 1a, 1b, 1c, 1d, 1e Power amplifier 2. Board 3 Chip Device 4 Input Phase Circuit 5 phase circuit 51 1st phase circuit 52 Second phase circuit A1 First differential amplifier A2 Second differential amplifier CA1 1st carrier amplifier CA2 2nd Carrier Amplifier DA drive stage amplifier DA1 1st drive stage amplifier DA2 2nd drive stage amplifier PA1 1st peak amplifier PA2 2nd peak amplifier T1 First conversion circuit T2 Second conversion circuit T3 3rd conversion circuit

Claims

1. A substrate; a chip device mounted on a main surface of the substrate; Equipped with The chip device comprises: a first differential amplifier including a first carrier amplifier and a second carrier amplifier; a second differential amplifier including a first peak amplifier and a second peak amplifier; Equipped with In the chip device, the first carrier amplifier and the second carrier amplifier are arranged in a first direction, the first carrier amplifier and the first peak amplifier are arranged in a second direction different from the first direction, the first peak amplifier and the second peak amplifier are aligned in the first direction, the second carrier amplifier and the second peak amplifier are aligned in the second direction; Power amplifier.

2. 2. The power amplifier according to claim 1, a phase circuit for delaying a phase of a differential output of the first differential amplifier by 90 deg; Power amplifier.

3. 3. The power amplifier according to claim 2, The phase circuit includes: a first phase circuit having one end connected to the output of the first carrier amplifier and the other end connected to the output of the first peak amplifier; a second phase circuit having one end connected to the output of the second carrier amplifier and the other end connected to the output of the second peak amplifier; Including, Power amplifier.

4. 4. The power amplifier according to claim 3, the first phase circuit and the second phase circuit are configured with a transmission line provided on the chip device or the substrate; Power amplifier.

5. 3. The power amplifier according to claim 2, The phase circuit is composed of an LC circuit including an inductor and a capacitor. Power amplifier.

6. 6. A power amplifier device according to claim 2, The chip device comprises: a first conversion circuit that converts an unbalanced input signal into a differential signal and inputs the differential signal to the first differential amplifier; a second conversion circuit that converts an unbalanced input signal into a differential signal and inputs the differential signal to the second differential amplifier; Equipped with The substrate is a third conversion circuit for converting a differential signal output from the chip device into an unbalanced output signal; Power amplifier.

7. 7. A power amplifier according to claim 6, The first conversion circuit and the second conversion circuit are configured with a balun transformer. Power amplifier.

8. 7. A power amplifier according to claim 6, The third conversion circuit is composed of a balun transformer. Power amplifier.

9. 7. A power amplifier according to claim 6, The third conversion circuit is composed of a hybrid coupler. Power amplifier.

10. 7. A power amplifier according to claim 6, a first drive stage amplifier that amplifies an unbalanced input signal and inputs the amplified signal to the first conversion circuit; a second drive stage amplifier that amplifies an unbalanced input signal and inputs the amplified signal to the second conversion circuit; an input phase circuit that delays the phase of an unbalanced input signal input to the second conversion circuit by 90 degrees relative to the phase of an unbalanced input signal input to the first conversion circuit; Equipped with Power amplifier.

11. 11. The power amplifier according to claim 10, the first conversion circuit is provided between the first carrier amplifier and the second carrier amplifier, the second conversion circuit is provided between the first peak amplifier and the second peak amplifier. Power amplifier.

12. 12. The power amplifier according to claim 11, The input phase circuit is composed of a hybrid coupler. Power amplifier.

13. 13. The power amplifier according to claim 12, the input phase circuit is provided between the first conversion circuit and the second conversion circuit, the first drive stage amplifier is provided between the input phase circuit and the first conversion circuit, the second drive stage amplifier is provided between the input phase circuit and the second conversion circuit; Power amplifier.

14. 12. The power amplifier according to claim 11, the input phase circuit includes a transmission line provided on the substrate; In the chip device, the first drive stage amplifier, the first conversion circuit, the second drive stage amplifier, and the second conversion circuit are arranged in this order in the second direction; Power amplifier.

15. 11. The power amplifier according to claim 10, the first differential amplifier and the second differential amplifier are provided between the first conversion circuit and the second conversion circuit; Power amplifier.

16. 16. The power amplifier according to claim 15, The input phase circuit is composed of a hybrid coupler. Power amplifier.

17. 16. The power amplifier according to claim 15, the input phase circuit includes a transmission line provided on the substrate; Power amplifier.

18. 16. The power amplifier according to claim 15, the input phase circuit includes a transmission line provided in the chip device; Power amplifier.

Images