Semiconductor device

Abstract

To provide technology that can reduce energy loss during transient on periods.SOLUTION: A semiconductor device comprises a first transistor, a second transistor and a control unit. The control unit applies a second off voltage lower than the first off voltage to a second gate before the first transistor enters the transient off state, and turns on the second transistor before the first transistor enters the transient on state, and after the first transistor is turned on, the second transistor is turned off by applying the first off voltage to the second gate.SELECTED DRAWING: Figure 9

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device. [Background technology]

[0002] In a power transistor with switching function, it is ideal for the steady-state on-state voltage and the energy loss during the off-state transition to be as small as possible. Since there is a trade-off between the steady-state on-state voltage and the energy loss during the off-state transition, various technologies have been proposed to reduce these.

[0003] For example, Patent Document 1 proposes a technique for reducing the steady-on state voltage and the energy loss during a transition to off by controlling the control timing of two gates in a double-gate structure.

[0004] In addition, a technology has been devised that uses a double gate structure to limit the saturation current for a certain period of time to prevent the element from being destroyed if the element is shorted to the power supply. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2004-319624 A Summary of the Invention [Problem to be solved by the invention]

[0006] However, in the conventional technology, there is room for improvement in gate control during the transient ON period and in reducing energy loss during the transient ON period.

[0007] Therefore, the present disclosure has been made in consideration of the above-mentioned problems, and has an object to provide a technique capable of reducing energy loss during the transient on-period. [Means for solving the problem]

[0008] A semiconductor device according to the present disclosure includes a first transistor including a first gate and a first emitter region provided along the first gate, a second transistor including a second gate and a second emitter region provided along the second gate and adjacent to the first transistor, and a control unit that controls on and off of the first transistor and the second transistor, wherein in a planar view, a length of a portion of the second emitter region facing the second gate is greater than a length of a portion of the first emitter region facing the first gate, and the control unit applies a second off voltage lower than a first off voltage to the second gate before the first transistor enters a transient off state, turns on the second transistor before the first transistor enters a transient on state, and applies the first off voltage to the second gate after the first transistor is turned on to turn off the second transistor. Effect of the Invention

[0009] According to the present disclosure, the control unit applies a second off voltage lower than the first off voltage to the second gate before the first transistor enters a transient off state, turns on the second transistor before the first transistor enters a transient on state, and applies the first off voltage to the second gate after the first transistor is on to turn off the second transistor. With this configuration, it is possible to reduce energy loss during the transient on period. [Brief description of the drawings]

[0010] [Figure 1] 1 is a diagram showing a configuration of a semiconductor device according to a first embodiment; [Diagram 2] 1 is a diagram showing a configuration of a portion of a semiconductor module according to a first embodiment. [Diagram 3] FIG. 2 is a plan view showing the configuration of a chip according to the first embodiment. [Figure 4] 1 is an enlarged plan view showing a configuration of a semiconductor device according to a first embodiment. [Diagram 5] 1 is a cross-sectional view showing a configuration of a semiconductor device according to a first embodiment. [Figure 6] 1 is an enlarged plan view showing a configuration of a semiconductor device according to a first embodiment. [Figure 7] 1 is a cross-sectional view showing a configuration of a semiconductor device according to a first embodiment. [Figure 8] 1 is a cross-sectional view showing a configuration of a semiconductor device according to a first embodiment. [Figure 9] 4 is a timing chart showing control by a control unit according to the first embodiment. [Figure 10] 4 is a timing chart showing control by a control unit according to the first embodiment. [Figure 11] FIG. 11 is an enlarged plan view showing the configuration of a semiconductor device according to a second embodiment. [Figure 12] FIG. 11 is an enlarged plan view showing the configuration of a semiconductor device according to a third embodiment. [Figure 13] FIG. 11 is an enlarged plan view showing the configuration of a semiconductor device according to a fourth embodiment. [Figure 14] 13 is a diagram showing impurity profiles of a first emitter region and a second emitter region according to the fourth embodiment. FIG. [Figure 15] 13 is a timing chart showing control by a control unit according to the fifth embodiment. [Figure 16] FIG. 13 is a diagram showing the relationship between Δt1 / tm and energy loss Eon. [Figure 17] 13 is a timing chart showing control by a control unit according to the sixth embodiment. [Figure 18] 13 is a timing chart showing control by a control unit according to the seventh embodiment. [Figure 19] 13 is a timing chart showing control by a control unit according to the seventh embodiment. [Figure 20] 20 is a timing chart showing control by a control unit according to the eighth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, the embodiments will be described with reference to the attached drawings. The features described in each of the following embodiments are illustrative, and not all features are necessarily required. In addition, in the following description, the same or similar symbols are used for similar components in multiple embodiments, and different components are mainly described. In addition, in the following description, specific positions and directions such as "upper", "lower", "left", "right", "front" or "back" do not necessarily have to match the positions and directions in actual implementation. In addition, a certain part having a higher density than another part means, for example, that the average density of a certain part is higher than the average density of another part. Conversely, a certain part having a lower density than another part means, for example, that the average density of a certain part is lower than the average density of another part.

[0012] <Embodiment 1> 1 is a diagram showing a configuration of a semiconductor device according to the present embodiment 1. The semiconductor device in FIG.

[0013] The first transistor 1 and the second transistor 2 are provided adjacent to each other on a chip 51. In the following, a configuration in which each of the first transistor 1 and the second transistor 2 is a trench-type IGBT (Insulated Gate Bipolar Transistor) will be mainly described, but the present invention is not limited thereto and may be, for example, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor).

[0014] The control unit 3 controls the voltage of the first gate 1a of the first transistor 1 and the voltage of the second gate 2a of the second transistor 2, thereby controlling the on and off of the first transistor 1 and the second transistor 2. The control unit 3 includes, for example, a CPU (Central Processing Unit).

[0015] Fig. 2 is a diagram showing the configuration of an IGBT module, which is a semiconductor module including the configuration of Fig. 1. Since the upper and lower parts of Fig. 2 have the same configuration, only one of these parts will be described here.

[0016] The collector of the first transistor 1 and the collector of the second transistor 2 are connected, and the emitter of the first transistor 1 and the emitter of the second transistor 2 are connected, so that the first transistor 1 and the second transistor 2 are connected in parallel to each other. A diode 6 is connected in parallel to the first transistor 1 and the second transistor 2. The diode 6 may be a diode using a PN junction or a Schottky barrier diode. In FIG. 2, the diode 6 is provided outside the chip 51, but it may be provided in the same chip 51 as the first transistor 1 and the second transistor 2, such as an RC-IGBT (Reverse Conducting - IGBT).

[0017] 3 is a plan view showing the configuration of a chip 51. The chip 51 includes a cell section 52 in which a first transistor 1 and a second transistor 2 are provided, and a peripheral section of the cell section 52. In the cell section 52, a first gate 1a of the first transistor 1 and a second gate 2a of the second transistor 2 are provided.

[0018] 3, pads 53 and 54 electrically connected to the first gate 1a and the second gate 2a, respectively, are provided on the outer periphery in order to input signals from a control unit 3 outside the chip 51 to the first gate 1a and the second gate 2a. Note that by providing a control unit 3 instead of the pads 53 and 54, the chip 51 and the control unit 3 may be configured monolithically (integrally).

[0019] Fig. 4 is an enlarged plan view showing the configuration of the semiconductor device according to the first embodiment, specifically, an enlarged plan view of the part enclosed by the dashed line in Fig. 3. In the example of Fig. 4, the first transistors 1 and the second transistors 2 are alternately provided one by one, but they may be alternately provided in units other than one, such as two by two. Fig. 5 is a cross-sectional view showing the configuration along the line AA and the configuration along the line BB in Fig. 4. Note that, for convenience of illustration, some of the components in Fig. 5 are omitted in Fig. 4.

[0020] The following describes the configurations of the first transistor 1 and the second transistor 2. In the following description, the n-type and p-type may be reversed.

[0021] As shown in FIG. 4 and FIG. 5, the first transistor 1 has a first gate 1a and + Type or n ++ a first emitter region 1b of n - A n-type drift layer 11, an n-type CS (charge storage) layer 12, a p-type base layer 13, and a p + The n-type contact layer 14, the gate insulating film 17, the interlayer insulating film 21, the emitter 22, the n-type buffer layer 23, and the p + The collector region 24 includes a collector 25 .

[0022] A CS layer 12 is provided on the drift layer 11, a base layer 13 is provided on the CS layer 12, and a first emitter region 1b and a contact layer 14 are selectively provided on the base layer 13.

[0023] The trench 16 is provided across the first emitter region 1b, the base layer 13, the CS layer 12, and an upper portion of the drift layer 11. The first gate 1a is an electrode provided on the inner wall of the trench 16 via a gate insulating film 17. The gate insulating film 17 is, for example, an oxide film, and the first gate 1a is made of, for example, doped polysilicon.

[0024] The interlayer insulating film 21 insulates the first gate 1a from the emitter 22. The interlayer insulating film 21 is, for example, an oxide film. The emitter 22 is an electrode electrically connected to the first emitter region 1b and the contact layer 14 through a contact hole in the interlayer insulating film 21. A buffer layer 23, a collector region 24, and a collector 25 are stacked in this order on the lower surface of the drift layer 11.

[0025] As shown in FIG. 4 and FIG. 5, the second transistor 2 has a second gate 2a and + Type or n ++ The second transistor 2 includes a second emitter region 2b of a type similar to the first transistor 1. The second transistor 2 also includes a drift layer 11, a CS layer 12, a base layer 13, a contact layer 14, a gate insulating film 17, an interlayer insulating film 21, an emitter 22, a buffer layer 23, a collector region 24, and a collector 25.

[0026] The configuration of the second transistor 2 is generally the same as that of the first transistor 1, except for the first emitter region 1b and the second emitter region 2b. The first emitter region 1b in FIG. 4 is provided intermittently (for example, periodically) along the first gate 1a, so the first emitter region 1b is provided in the cross-sectional configuration along the line AA in FIG. 5, but the first emitter region 1b is not provided in the cross-sectional configuration along the line BB in FIG. On the other hand, the second emitter region 2b in FIG. 4 is provided continuously along the second gate 2a, so the second emitter region 2b is provided in both the cross-sectional configuration along the line AA and the cross-sectional configuration along the line BB in FIG. 5. That is, in the plan view of FIG. 4, the length of the portion of the second emitter region 2b facing the second gate 2a is longer than the length of the portion of the first emitter region 1b facing the first gate 1a.

[0027] The first emitter region 1b, the second emitter region 2b, the drift layer 11, the CS layer 12, the base layer 13, the contact layer 14, the gate insulating film 17, the buffer layer 23, and the collector region 24 are included in a semiconductor layer, which is at least one of a semiconductor substrate and an epitaxial growth layer. In this specification, for example, at least one of A, B, C, ..., and Z means any one of all combinations of one or more types extracted from the group of A, B, C, ..., and Z. The semiconductor layer may be made of normal silicon (Si), or may be made of a wide band gap semiconductor such as silicon carbide (SiC), gallium nitride (GaN), or diamond. When the semiconductor layer is made of a wide band gap semiconductor, stable operation under high temperature and high voltage and high switching speed are possible.

[0028] 4 and 5, all of the mesa portions (i.e., the upper portions of the semiconductor layer sandwiched between the first gate 1a and the second gate 2a in FIG. 5) are in contact with the emitter 22, but this is not limited thereto. For example, as shown in FIGS. 6 and 7, only some of the mesa portions may be in contact with the emitter 22 by making the interlayer insulating film 21 larger than the interlayer insulating film 21 in FIG.

[0029] 7, the mesa portion covered with the interlayer insulating film 21 and the mesa portion not covered with the interlayer insulating film 21 have the same height in the vertical direction of the page. However, this is not limited to this, and the height of the mesa portion covered with the interlayer insulating film 21 and the height of the mesa portion not covered with the interlayer insulating film 21 may be different as shown in FIG.

[0030] In the above configuration, the control unit 3 in FIG. 1 or FIG. 2 controls the voltage of the first gate 1a of the first transistor 1 and the voltage of the second gate 2a of the second transistor 2. When a voltage higher than the threshold voltage VGE(th) is applied to the first gate 1a of the first transistor 1, a portion of the semiconductor layer near the gate insulating film 17 of the first gate 1a functions substantially as an n-type semiconductor layer to form a channel. On the other hand, when a negative bias, which is a negative voltage, is applied to the first gate 1a, a portion of the semiconductor layer near the gate insulating film 17 of the first gate 1a functions substantially as a p-type semiconductor layer. Similarly, when a voltage higher than the threshold voltage VGE(th) is applied to the second gate 2a of the second transistor 2, a portion of the semiconductor layer near the gate insulating film 17 of the second gate 2a functions substantially as an n-type semiconductor layer to form a channel. On the other hand, when a negative bias is applied to the second gate 2a, a portion of the semiconductor layer near the gate insulating film 17 of the second gate 2a functions substantially as a p-type semiconductor layer.

[0031] Fig. 9 is a timing chart showing the control of the control unit 3 according to the present embodiment 1. Fig. 9 shows the voltages of the pads 53 and 54 of the chip 51 in Fig. 3, that is, the voltages of the first gate 1a and the second gate 2a. The threshold voltages VGE(th) of the first transistor 1 and the second transistor 2 are greater than 0V.

[0032] Strictly speaking, the transient off state of the first transistor 1 is the state in which the first transistor 1 goes from on to off, and a transient off period including the transient off state is shown in Fig. 9. Similarly, the transient on state of the first transistor 1 is the state in which the first transistor 1 goes from off to on, and a transient on period including the transient on state is shown in Fig. 9.

[0033] The control unit 3 applies a second off voltage V2, which is lower than the first off voltage V1, to the second gate 2a before the first transistor 1 enters the transient off state. The control unit 3 turns on the second transistor 2 before the first transistor 1 enters the transient on state. Then, after the first transistor 1 passes through the transient on state and turns on, the control unit 3 applies the first off voltage V1 to the second gate 2a to turn off the second transistor 2.

[0034] 9, the first off voltage V1 is 0 V, and the second off voltage V2 is a negative bias. However, this is not limited to the above, as long as the first off voltage V1 and the second off voltage V2 are lower than the threshold voltage VGE(th) and the second off voltage V2 is lower than the first off voltage V1.

[0035] In the example of FIG. 9, in the steady-state off-period from the transient off-period to the transient on-period of the first transistor 1, the control unit 3 maintains application of the second off-voltage V2 (i.e., negative bias) to the second gate 2a. In the steady-state on-period from the transient on-period to the transient off-period of the first transistor 1, the control unit 3 maintains application of the first off-voltage V1 (i.e., 0V) to the second gate 2a. However, the voltage of the second gate 2a in the steady-state off-period and steady-state on-period is not limited to this. For example, as shown in FIG. 10, in the steady-state off-period, the control unit 3 may apply a third off-voltage V3, which is equal to or greater than 0 and less than the threshold voltage VGE(th), to the second gate 2a. According to the above control by the control unit 3, the first to third effects can be obtained.

[0036] <First effect> The control unit 3 applies a second off voltage V2 (i.e., a negative bias) to the second gate 2a before the first transistor 1 enters the transient off state. This causes the portion of the semiconductor layer near the gate insulating film 17 of the second gate 2a to function substantially as a p-type semiconductor layer. This has the effect of making it easier for holes remaining in the drift layer 11 to be discharged from the front surface via the p-type semiconductor layer. This reduces the total amount of holes contributing to the conductivity modulation of the entire first transistor 1 and the second transistor 2. As a result, fewer holes are discharged when the first transistor 1 is turned off after this operation, so the tail current becomes smaller, and the energy loss (Eoff) during the transient off period of the first transistor 1 can be reduced.

[0037] <Second effect> The control unit 3 turns on the second transistor 2 before the first transistor 1 enters the transient on state. As a result, energy loss during the transient on period occurs mainly in the second transistor 2, which is turned on first. Here, in the first embodiment, in plan view, the length of the portion of the second emitter region 2b facing the second gate 2a is longer than the length of the portion of the first emitter region 1b facing the first gate 1a. Therefore, when the first transistor 1 and the second transistor are turned on individually, the amount of electron injection at the moment the second transistor 2 is turned on is larger than the amount of electron injection in the first transistor 1, so that switching is completed earlier than in the first transistor.

[0038] As a result, the energy loss during the transient on-period when the second transistor 2 is turned on individually is smaller than the energy loss during the transient on-period when the first transistor 1 is turned on individually. As a result, it is possible to reduce the energy loss Eon during the transient on-period of the entire first transistor 1 and second transistor 2. In addition, by turning on the first transistor after turning on the second transistor, it is possible to turn on the first transistor 1 and the second transistor 2 with a smaller gate charge than when the first transistor 1 and the second transistor 2 are turned on simultaneously.

[0039] <Third Effect> After the first transistor 1 is turned on, the control unit 3 applies the first off voltage V1 to the second gate 2a to turn off the second transistor 2, thereby improving the behavior in the short circuit operation mode. The short circuit operation mode is a mode in which the main power supply is directly short-circuited to the collector 25 due to a failure in the peripheral circuit or the like, and in the short circuit operation mode, it is preferable that the steady on period after the completion of the transient on period lasts for a long time. This duration corresponds to the time until the time-integrated power determined by the voltage applied to the IGBT (i.e., the voltage of the main power supply) and the current (i.e., the saturation current of the IGBT) exceeds the energy allowable value of the IGBT. The current (the saturation current of the IGBT) depends on the size of the emitter area of ​​the on-transistor.

[0040] In the first embodiment, in plan view, the length of the portion of the second emitter region 2b facing the second gate 2a is greater than the length of the portion of the first emitter region 1b facing the first gate 1a. Since the above-mentioned length of the emitter region and the size of the emitter region correspond to each other, the saturation current of the first transistor 1 that is turned on is smaller than the saturation current of the second transistor 2 that is turned on. In the first embodiment, the second transistor 2 that is large in saturation current is turned off after the first transistor 1 that is small in saturation current is turned on, so that the duration of the short circuit operation mode can be extended when it occurs.

[0041] <Embodiment 2> Fig. 11 is an enlarged plan view showing the configuration of a semiconductor device according to the present embodiment 2. In the first embodiment, the second emitter region 2b is provided continuously along the second gate 2a in the plan view of Fig. 4. In the second embodiment, the second emitter region 2b is provided discontinuously (for example, periodically) along the second gate 2a in the plan view of Fig. 11, which is different from the first embodiment.

[0042] 11, the first emitter regions 1b and the second emitter regions 2b may be alternately arranged such that the lower and upper parts of the first emitter region 1b correspond to the upper and lower parts of the second emitter region 2b, respectively, in a plan view. Alternatively, the first emitter regions 1b and the second emitter regions 2b may be arranged according to a certain rule such that the upper part of the first emitter region 1b corresponds to the upper part of the second emitter region 2b, respectively, in a plan view.

[0043] According to such a configuration, the potential directly below the second emitter regions 2b can be lowered by thinning out the second emitter regions 2b, and therefore the latch-up resistance of the semiconductor device can be increased.

[0044] <Embodiment 3> 12 is an enlarged plan view showing the configuration of a semiconductor device according to the present embodiment 3. The present embodiment 3 differs from the embodiment 1 in that the first emitter region 1b and the second emitter region 2b are connected to each other in plan view.

[0045] Here, the first emitter region 1b and the second emitter region 2b need to be electrically connected to the emitter 22 via a contact hole in the interlayer insulating film 21. For this reason, in the first and second embodiments, the width of the contact hole in the interlayer insulating film 21 is limited by the arrangement of the first emitter region 1b and the second emitter region 2b. In contrast, in the third embodiment, the first emitter region 1b and the second emitter region 2b are connected to each other as shown in FIG. 12, and there is no such limitation on the width of the contact hole 21a in the interlayer insulating film 21, so that the degree of freedom in designing the contact hole can be increased.

[0046] <Fourth embodiment> Fig. 13 is an enlarged plan view showing the configuration of a semiconductor device according to the fourth embodiment, and Fig. 14 is a diagram showing the impurity profiles of the first emitter region 1b and the second emitter region 2b. The horizontal axis of Fig. 14 indicates the depth from the surface of the semiconductor layer (i.e., the surfaces of the first emitter region 1b and the second emitter region 2b), and the vertical axis of Fig. 14 indicates the impurity concentration.

[0047] As shown in FIG. 14, the peak of the n-type impurity concentration in the first emitter region 1b and the peak of the n-type impurity concentration in the second emitter region 2b are located on the upper surface side of the semiconductor layer. In the fourth embodiment, the difference from the first embodiment is that the peak of the n-type impurity concentration in the second emitter region 2b is larger than the peak of the n-type impurity concentration in the first emitter region 1b.

[0048] According to such a configuration, since the amount of electron injection at the moment when the second transistor 2 is turned on is large, switching is completed earlier than the first transistor. As a result, since the amount of electron injection at the moment when the second transistor 2 is turned on is larger than the amount of electron injection of the first transistor 1, the energy loss Eon during the transient on-period of the entire first transistor 1 and second transistor 2 can be reduced. Note that the fourth embodiment as described above is also applicable to the second and third embodiments.

[0049] <Embodiment 5> FIG. 15 is a timing chart showing the control of the control unit 3 according to the fifth embodiment, and specifically shows the control during the transient on-period of the first transistor 1. In the fifth embodiment, the difference from the first embodiment is that when the time from when the second transistor 2 is turned on until the first transistor 1 is turned on is Δt1 and the mirror section of the second transistor 2 is tm, 0 < Δt1 < tm holds. Note that the mirror section is a period during which the gate voltage becomes constant when the transistor is turned on due to the effective capacitance between the gate and the collector of the transistor.

[0050] FIG. 16 is a diagram showing the relationship between the ratio of tm to Δt1, that is, Δt1 / tm (horizontal axis), and the energy loss Eon (vertical axis) during the transient on-period of the entire first transistor 1 and second transistor 2. Note that the energy loss Eon shown on the vertical axis is normalized by the energy loss Eon when Δt1 / tm = -0.2 (that is, when the first transistor 1 rises before the mirror section of the second transistor).

[0051] In the portion where 0 < Δt1 < tm holds, that is, in the portion of the horizontal axis in FIG. 16 that is greater than 0 and less than 1, the energy loss Eon can be reduced compared to the case where Δt1 / tm = -0.2. In particular, among the results in FIG. 16, the energy loss Eon can be most reduced when Δt1 / tm = 0.3. Note that the fifth embodiment as described above is also applicable to the second to fourth embodiments.

[0052] <Embodiment 6> FIG. 17 is a timing chart showing the control of the control unit 3 according to the sixth embodiment, specifically, regarding the control during the transient on-period and the main voltage VCE and main current IC of the semiconductor device. In the sixth embodiment, the point where the voltage of the first gate 1a exceeds the mirror voltage before the voltage of the second gate 2a falls below the mirror voltage while the first transistor 1 is in the transient on state is different from the first embodiment.

[0053] The dashed-dotted line in FIG. 17 shows the waveform when the voltage of the first gate 1a exceeds the mirror voltage after the voltage of the second gate 2a has fallen below the mirror voltage. In this case, since the voltage VCE that once became 0 becomes greater than 0 between the time when the voltage of the first gate 1a rises and the time when the voltage of the second gate 2a falls below the mirror voltage, the energy loss Eon increases accordingly.

[0054] The solid line in FIG. 17 shows the waveform according to the control of the sixth embodiment of the present situation, that is, the waveform when the voltage of the first gate 1a exceeds the mirror voltage before the voltage of the second gate 2a falls below the mirror voltage. In this case, since the voltage VCE that once became 0 maintains 0, the energy loss Eon can be reduced compared to the above case. Note that the sixth embodiment as described above is also applicable to the second to fifth embodiments.

[0055] <Embodiment 7> Fig. 18 is a timing chart showing the control of the control unit 3 according to the seventh embodiment, specifically showing the control during the transient on period and the transient off period of the first transistor 1. The seventh embodiment is similar to the control shown in Fig. 10 described in the first embodiment, except that the control is changed so that the first transistor 1 transitions from the transient on period state to the transient off period state without passing through the steady on period state. That is, the seventh embodiment is different from the first embodiment in that the control unit 3 controls the voltage of the second gate 2a to the second off voltage V2 from the on voltage of the on level without maintaining it at the first off voltage V1 when the first transistor 1 enters the transient off state immediately after the transient on state.

[0056] Fig. 19 is an enlarged view of a part of Fig. 18. The dashed and dotted line in Fig. 19 indicates a waveform when the controller 3 controls the voltage of the second gate 2a from the on-voltage to the third off-voltage V3, and the solid line in Fig. 19 indicates a waveform under the control of the controller 3 according to the seventh embodiment.

[0057] In order to turn off the second transistor 2 earlier than the first transistor 1, the voltage of the second gate 2a needs to reach the threshold voltage VGE(th) earlier than the voltage of the first gate 1a. In contrast, according to the present embodiment 7, the second transistor 2 can be turned off earlier than the first transistor 1 by the time Δt(Vth) in FIG. 19 than when the control unit 3 controls the voltage of the second gate 2a from the on voltage to the third off voltage V3. As a result, the period in which the first transistor 1 is in the on state can be shortened. Note that the present embodiment 7 as described above can also be applied to FIG. 9 described in the embodiment 1, and in this case, the voltage of the second gate 2a is maintained at the second off voltage V2 in the steady off period after the transient off period. The present embodiment 7 can also be applied to the embodiments 2 to 6.

[0058] <Embodiment 8> 20 is a timing chart showing the control of the control unit 3 according to the present embodiment 8. The present embodiment 8 differs from the embodiment 1 in that the second off voltage V2 is 0 V or more, the first off voltage V1 is greater than the second off voltage V2, and the third off voltage V3 is greater than the second off voltage V2.

[0059] According to this configuration, the control unit 3 does not need to prepare a power supply for negatively biasing the second gate 2a, and therefore the configuration of the semiconductor device can be expected to be simplified. Note that the above-described eighth embodiment can be applied to FIG. 9 and also to the second to seventh embodiments.

[0060] It should be noted that the embodiments and modifications may be freely combined, and the embodiments and modifications may be modified or omitted as appropriate.

[0061] Various aspects of the present disclosure are summarized below as appendices.

[0062] (Appendix 1) a first transistor including a first gate and a first emitter region disposed along the first gate; a second transistor including a second gate and a second emitter region disposed along the second gate, the second transistor being adjacent to the first transistor; a control unit that controls on and off of the first transistor and the second transistor; Equipped with In a plan view, a length of a portion of the second emitter region facing the second gate is greater than a length of a portion of the first emitter region facing the first gate; The control unit is applying a second off voltage lower than the first off voltage to the second gate before the first transistor enters a transient off state; before the first transistor enters a transient on state, turning on the second transistor; after the first transistor is turned on, the first off voltage is applied to the second gate to turn off the second transistor.

[0063] (Appendix 2) The semiconductor device according to Appendix 1, In a plan view, the first emitter region is intermittently provided along the first gate, and the second emitter region is continuously provided along the second gate. A semiconductor device.

[0064] (Appendix 3) The semiconductor device according to Appendix 1, In a plan view, the first emitter region is intermittently provided along the first gate, and the second emitter region is intermittently provided along the second gate. A semiconductor device.

[0065] (Appendix 4) The semiconductor device according to any one of Appendices 1 to 3, In a plan view, the first emitter region and the second emitter region are connected to each other. A semiconductor device.

[0066] (Appendix 5) The semiconductor device according to any one of Appendices 1 to 4, The peak of the impurity concentration of the second emitter region is larger than the peak of the impurity concentration of the first emitter region. A semiconductor device.

[0067] (Appendix 6) The semiconductor device according to any one of Appendices 1 to 5, When the time from when the second transistor is turned on until the first transistor is turned on is Δt1 and the mirror section of the second transistor is tm, 0 < Δt1 < tm holds. A semiconductor device.

[0068] (Appendix 7) The semiconductor device according to any one of Appendices 1 to 6, A semiconductor device, wherein while the first transistor is in the transient on-state, the voltage of the first gate exceeds a mirror voltage before the voltage of the second gate falls below a mirror voltage.

[0069] (Appendix 8) A semiconductor device according to any one of claims 1 to 7, The control unit is a control circuit for controlling a voltage of the second gate to be changed from an on voltage to the second off voltage without maintaining the voltage at the first off voltage when the first transistor enters the transient off state immediately after the transient on state;

[0070] (Appendix 9) A semiconductor device according to any one of claims 1 to 8, The second off-voltage is 0V or higher. [Explanation of symbols]

[0071] 1 first transistor, 1a first gate, 1b first emitter region, 2 second transistor, 2a second gate, 2b second emitter region, 3 control section.

Claims

1. a first transistor including a first gate and a first emitter region disposed along the first gate; a second transistor including a second gate and a second emitter region disposed along the second gate, the second transistor being adjacent to the first transistor; a control unit that controls on and off of the first transistor and the second transistor; Equipped with a length of a portion of the second emitter region facing the second gate is greater than a length of a portion of the first emitter region facing the first gate in a plan view; The control unit is applying a second off-voltage lower than the first off-voltage to the second gate before the first transistor enters a transient off-state; before the first transistor enters a transient on state, turning on the second transistor; after the first transistor is turned on, the first off voltage is applied to the second gate to turn off the second transistor.

2. 2. The semiconductor device according to claim 1, A semiconductor device, wherein, in a plan view, the first emitter region is provided discontinuously along the first gate, and the second emitter region is provided continuously along the second gate.

3. 2. The semiconductor device according to claim 1, A semiconductor device, wherein, in a plan view, the first emitter region is provided discontinuously along the first gate, and the second emitter region is provided discontinuously along the second gate.

4. 4. The semiconductor device according to claim 1, In a plan view, the first emitter region and the second emitter region are connected to each other.

5. 4. The semiconductor device according to claim 1, a peak impurity concentration of the second emitter region is greater than a peak impurity concentration of the first emitter region.

6. 4. The semiconductor device according to claim 1, a time period from when the second transistor is turned on to when the first transistor is turned on is denoted by Δt1, and a mirror interval of the second transistor is denoted by tm, where 0<Δt1<tm holds.

7. 4. The semiconductor device according to claim 1, A semiconductor device, wherein while the first transistor is in the transient on-state, the voltage of the first gate exceeds a mirror voltage before the voltage of the second gate falls below a mirror voltage.

8. 4. The semiconductor device according to claim 1, The control unit is a control circuit for controlling a voltage of the second gate to be changed from an on voltage to the second off voltage without maintaining the voltage at the first off voltage when the first transistor enters the transient off state immediately after the transient on state;

9. 4. The semiconductor device according to claim 1, The second off-voltage is 0 V or higher.

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