Wiring board and mounting structure using the same

Abstract

To provide a wiring board that effectively excites an effect of an inductor contained in a semiconductor device mounted.SOLUTION: In a mounting structure 10 to which an electronic component S is mounted, a wiring board 11 contains: a build-up layer 1b that contains a first insulation layer 21 having a first surface f1 and a second surface f2 positioned at the side opposite to the first surface f1, and a first conductive layer 31 positioned on the first surface f1; and a solder resist 4 that covers one part of the first surface f1 and the first conductive layer 31. The build-up layer 1b includes a mounting region R onto which the electronic component S having an inductor is mounted on the first surface f1. The mounting region R contains a first region 1c at a position that faces the inductor at the time of mounting the electronic component S. The first conductive layer 31 and the solder resist 4 are not positioned in the first region 1c.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a wiring board and a mounting structure using the same. [Background technology]

[0002] An example of a semiconductor element mounted on a wiring board is a semiconductor element including an inductor, as described in Patent Document 1. In a wiring board on which a semiconductor element including an inductor is mounted, a conductor is not positioned in an area facing the inductor included in the semiconductor element. If a conductor is positioned therein, eddy currents and electrostatic capacitance are generated, reducing the effect of the inductor. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 4878502 DISCLOSURE OF THEINVENTION [Problem to be solved by the invention]

[0004] Simply ensuring that no conductor is located in the area facing the inductor may not be effective in reducing the adverse effects of capacitance, and the inductor may not be able to fully exert its effects.

[0005] An object of the present disclosure is to provide a wiring board that can efficiently exhibit the effect of an inductor included in a mounted semiconductor element. [Means for solving the problem]

[0006] The wiring board according to the present disclosure includes a build-up layer including a first insulating layer having a first surface and a second surface located opposite to the first surface, a first conductor layer located on the first surface, and a solder resist covering the first surface and a part of the first conductor layer. The build-up layer has a mounting area on the first surface in which an electronic component having an inductor is mounted. The mounting area includes a first area at a position facing the inductor when the electronic component is mounted. The first conductor layer and the solder resist are not located in the first area.

[0007] The mounting structure according to the present disclosure includes the above-mentioned wiring board and an electronic component located on a mounting area of ​​the wiring board. The electronic component includes an inductor, and the inductor faces the first area with a gap between the inductor and the wiring board. Effect of the Invention

[0008] The wiring board according to the present disclosure has a configuration as described in the section on Means for Solving the Problems, and thus can efficiently exhibit the effect of the inductor included in the mounted semiconductor element. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is an explanatory diagram for explaining a mounting structure in which an electronic component is mounted on a wiring board according to a first embodiment of the present disclosure. [Diagram 2] FIG. 11 is an explanatory diagram for explaining a mounting structure in which an electronic component is mounted on a wiring board according to a second embodiment of the present disclosure. [Diagram 3] FIG. 11 is an explanatory diagram for explaining a mounting structure in which an electronic component is mounted on a wiring board according to a third embodiment of the present disclosure. [Figure 4] FIG. 11 is an explanatory diagram for explaining a mounting structure in which an electronic component is mounted on a wiring board according to a fourth embodiment of the present disclosure. [Diagram 5] FIG. 13 is an explanatory diagram for explaining a mounting structure in which an electronic component is mounted on a wiring board according to a fifth embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] A wiring board according to a first embodiment of the present disclosure will be described with reference to Fig. 1. Fig. 1 is an explanatory diagram for explaining a mounting structure 10 in which an electronic component S is mounted on a wiring board 11 according to the first embodiment of the present disclosure. The wiring board 11 according to one embodiment includes a core layer 1a and a build-up layer 1b.

[0011] In the wiring board 11 shown in FIG. 1, the core layer 1a is located at approximately the center in the thickness direction of the wiring board 11. The core layer 1a is not particularly limited as long as it is made of an insulating material. Examples of insulating materials include resins such as epoxy resin, bismaleimide-triazine resin, polyimide resin, and polyphenylene ether resin. Two or more of these resins may be mixed and used. The thickness of the core layer 1a is not particularly limited, and may be, for example, 100 μm or more and 1500 μm or less.

[0012] The core layer 1a may contain a reinforcing material. Examples of the reinforcing material include insulating cloth materials such as glass fiber, glass nonwoven fabric, aramid nonwoven fabric, aramid fiber, and polyester fiber. Two or more types of reinforcing materials may be used in combination. Furthermore, the core layer 1a may have inorganic insulating fillers such as silica, barium sulfate, talc, clay, glass, calcium carbonate, and titanium oxide dispersed therein. Two or more types of inorganic insulating fillers may be used in combination.

[0013] In the core layer 1a, a through-hole conductor is located to electrically connect the upper and lower surfaces of the core layer 1a. The through-hole conductor is located in a through-hole penetrating the upper and lower surfaces of the core layer 1a. The through-hole conductor is formed of a metal such as copper, specifically, a metal plating such as copper plating. The through-hole conductor may be formed only on the inner wall surface, or may be filled in the through-hole.

[0014] Conductive layers 3 are located on the upper and lower surfaces of the core layer 1a. The conductive layers 3 are not limited as long as they are conductors such as metal. Specifically, the conductive layers 3 are formed of metal foil such as copper foil, or metal plating such as copper plating. The thickness of the conductive layers 3 is not particularly limited, and is, for example, 5 μm or more and 25 μm or less. At least a part of the conductive layers 3 located on the upper and lower surfaces of the core layer 1a is connected to a through-hole conductor. Therefore, the upper and lower surfaces of the core layer 1a are electrically connected.

[0015] Build-up layers 1b are located on the upper and lower surfaces of the core layer 1a. The build-up layer 1b has a structure in which an insulating layer 2 and a conductor layer 3 are laminated. The insulating layer 2 is not particularly limited as long as it is made of an insulating material, like the core layer 1a. Examples of insulating materials include resins such as epoxy resin, bismaleimide-triazine resin, polyimide resin, and polyphenylene ether resin. Two or more of these resins may be mixed and used. The insulating layers 2 may be made of the same resin or different resins. The insulating layer 2 and the core layer 1a may be made of the same resin or different resins. The thickness of the insulating layer 2 is not particularly limited, and may be, for example, 10 μm or more and 50 μm or less. The insulating layers 2 may have the same thickness or different thicknesses.

[0016] The insulating layer 2 may contain a reinforcing material. Examples of the reinforcing material include insulating cloth materials such as glass fiber, glass nonwoven fabric, aramid nonwoven fabric, aramid fiber, and polyester fiber. Two or more types of reinforcing materials may be used in combination. Furthermore, the insulating layer 2 may have inorganic insulating fillers such as silica, barium sulfate, talc, clay, glass, calcium carbonate, and titanium oxide dispersed therein. Two or more types of inorganic insulating fillers may be used in combination.

[0017] In the insulating layer 2, via-hole conductors are located to electrically connect the upper and lower surfaces of the insulating layer 2. The via-hole conductors are located in via holes that penetrate the upper and lower surfaces of the insulating layer 2. The via-hole conductors are formed by metal plating such as copper plating. The via-hole conductors are connected to conductor layers 3 located on both sides of the insulating layer 2. The via-hole conductors may fill the via holes, or may be located only on the inner surfaces of the via holes.

[0018] The conductor layer 3 is located on the first surface f1 of the insulating layer 2. In this specification, the "first surface f1 of the insulating layer 2" refers to the surface of the insulating layer 2 that is farther from the core layer 1a. The "second surface f2 of the insulating layer 2" refers to the surface opposite to the first surface f1, i.e., the surface closer to the core layer 1a. As described above, the conductor layer 3 is not limited as long as it is a conductor such as a metal.

[0019] As shown in Fig. 1, a solder resist 4 is located on the surface of the build-up layer 1b. The solder resist 4 is made of a resin, such as an acrylic modified epoxy resin. The solder resist 4 has a plurality of openings for electrically connecting the conductor layer 3 to electrodes of an electronic component S, which will be described later, via solder 5. In other words, the conductor layer 3 exposed in the openings of the solder resist 4 functions as a plurality of electrodes of the wiring board 11.

[0020] Of the conductor layers 3 included in the buildup layer 1b, a first conductor layer 31 located in the outermost layer of the buildup layer 1b is partially covered with a solder resist 4. Of the insulating layers 2 included in the buildup layer 1b, the first conductor layer 31 is located on a first surface f1 of a first insulating layer 21 located in the outermost layer of the buildup layer 1b.

[0021] The build-up layer 1b has a mounting area R on the first surface f1 of the first insulating layer 21. The mounting area R is defined as an area including, for example, a plurality of electrodes of the wiring board 11. An electronic component S having an inductor S1 is mounted in the mounting area R. As shown in FIG. 1, the mounting area R includes a first area 1c at a position facing the inductor S1 when the electronic component S is mounted. The area of ​​the first area 1c may be the same size as the inductor S1 so that it overlaps with the inductor S1 in a planar perspective view, or may be larger than the area of ​​the inductor S1 so that the periphery of the inductor S1 fits within the periphery of the first area 1c. The inductor S1 has a function of converting, for example, electric energy into magnetic energy and storing it.

[0022] 1, in the wiring board 11, the first region 1c is not provided with the first conductor layer 31 or the solder resist 4. The absence of both the first conductor layer 31 and the solder resist 4 in the first region 1c enhances the effect of reducing the adverse effects of capacitance. As a result, the effect of the inductor S1 included in the mounted electronic component S is efficiently exerted.

[0023] The method for forming the first region 1c is not limited as long as it can eliminate both the first conductor layer 31 and the solder resist 4. Specifically, there may be mentioned a method in which the first conductor layer 31 and the solder resist 4 are not provided in the portion corresponding to the first region 1c when the first conductor layer 31 and the solder resist 4 are formed, or a method in which the first conductor layer 31 and the solder resist 4 are removed from the portion corresponding to the first region 1c by laser processing, drilling, or the like.

[0024] Next, a wiring board according to a second embodiment of the present disclosure will be described with reference to Fig. 2. Fig. 2 is an explanatory diagram for explaining a mounting structure 20 in which an electronic component S is mounted on a wiring board 12 according to the second embodiment of the present disclosure. In the wiring board 12, the same members as those in the wiring board 11 are given the same reference numerals, and detailed description thereof is omitted as described above.

[0025] In the wiring board 11, the first region 1c is not provided with the first conductor layer 31 and the solder resist 4, whereas in the wiring board 12, the first region 1c further includes a recess 1d in the first insulating layer 21 that opens into the first region 1c. Specifically, the recess 1d corresponds to a portion at the bottom of the first region 1c that is recessed from the first surface f1 of the first insulating layer 21 toward the core layer 1a side. That is, in the wiring board 12, the first conductor layer 31 and the solder resist 4 are not provided in the first region 1c, and the recess 1d that is recessed from the first surface f1 of the first insulating layer 21 toward the core layer 1a side and opens into the first region 1c is provided.

[0026] In a planar perspective, the area of ​​the opening of the recess 1d may be the same size as the inductor S1 so that it overlaps with the inductor S1, or may be larger than the area of ​​the inductor S1 so that the periphery of the inductor S1 is located within the periphery of the opening. If the area of ​​the opening is larger than the area of ​​the inductor S1 in a planar perspective, this is advantageous in that even if misalignment occurs when mounting the electronic component S on the wiring board 12, it is easier to make the inductor S1 face the opening.

[0027] Since the first region 1c further has such a recess 1d, a wider gap (air layer) is provided between the inductor S1 and the wiring board 12 (the bottom of the recess 1d). Therefore, the adverse effect of the capacitance formed between the inductor S1 and the conductor layer 3 located on the core layer 1a side is also reduced. As a result, the effect of the inductor S1 included in the mounted electronic component S is more efficiently exhibited. The method of forming the recess 1d is not limited, and it may be formed by laser processing or drilling, for example. In the wiring board 12 according to the embodiment shown in FIG. 2, the bottom of the recess 1d is located in the first insulating layer 21. That is, the recess 1d does not penetrate the first insulating layer 21.

[0028] Next, a wiring board according to a third embodiment of the present disclosure will be described with reference to Fig. 3. Fig. 3 is an explanatory diagram for explaining a mounting structure 30 in which an electronic component S is mounted on a wiring board 13 according to the third embodiment of the present disclosure. In the wiring board 13, the same members as those in the wiring board 11 are given the same reference numerals, and detailed description thereof will be omitted as described above.

[0029] 3, in wiring board 13, buildup layer 1b has second insulating layer 22 in contact with second surface f2 of first insulating layer 21, and second conductor layer 32 located between first insulating layer 21 and second insulating layer 22. Wiring board 13 has recess 1d in first insulating layer 21 that opens to first region 1c, and the bottom of recess 1d is second conductor layer 32. This allows a wide gap (air layer) to be provided between inductor S1 and wiring board 13 (bottom of recess 1d).

[0030] Furthermore, as shown in Fig. 4, in the wiring board 14 according to the fourth embodiment of the present disclosure, the bottom of the recess 1d penetrates the second conductor layer 32 and is located in the conductor layer 3 closer to the core layer 1a. Fig. 4 is an explanatory diagram for explaining a mounting structure 40 in which an electronic component S is mounted on the wiring board 14 according to the fourth embodiment of the present disclosure. In the wiring board 14, the same members as those in the wiring board 11 are denoted by the same reference numerals, and detailed description thereof will be omitted as it has been described above.

[0031] As shown in Fig. 4, the recess 1d may be recessed deeper, penetrating the second conductor layer 32. The recess 1d shown in Fig. 4 is located in the conductor layer 3, which is one core layer 1a closer than the second conductor layer 32. However, the bottom of the recess 1d may be located further toward the core layer 1a than the recess 1d shown in Fig. 4, or may be located in the second insulating layer 22. As described above, the depth of the recess 1d is not limited. The depth of the recess 1d may be adjusted appropriately so that the effect of the inductor S1 is easily exerted.

[0032] Next, a wiring board according to a fifth embodiment of the present disclosure will be described with reference to Fig. 5. Fig. 5 is an explanatory diagram for explaining a mounting structure 50 in which an electronic component S is mounted on a wiring board 15 according to the fifth embodiment of the present disclosure. In the wiring board 15, the same members as those in the wiring board 11 are denoted by the same reference numerals, and detailed description thereof will be omitted as described above.

[0033] In the wiring board 15, the solder resist 4 has a wall portion 41 that protrudes in the opposite direction to the first surface f1 so as to surround the first region 1c. That is, the wall portion 41 protrudes from the first surface f1 side toward the electronic component S to be mounted. In the wiring board 11 according to the first embodiment, the wiring board 12 according to the second embodiment, the wiring board 13 according to the third embodiment, and the wiring board 14 according to the fourth embodiment described above, such a wall portion 41 is not located. Due to the presence of the wall portion 41, when filling the underfill 6 described below between the electronic component S and the mounting region R, the underfill 6 is less likely to flow into the first region 1c.

[0034] When the underfill 6 flows into the first region 1c, the gap (air layer) between the inductor S1 and the wiring board 15 is narrowed by the underfill 6. As a result, the effect of reducing the adverse effects of capacitance is less likely to be achieved. As described above, the presence of the wall portion 41 makes it difficult for the underfill 6 to flow into the first region 1c, and the effect of reducing the adverse effects of capacitance is fully achieved.

[0035] The height of the wall portion 41 is not limited, and in order to prevent the underfill 6 from flowing into the first region 1c, it is preferable that the wall portion 41 has a height that reaches the electronic component S to be mounted. If the wall portion 41 has a height that is 50% or more of the length from the solder resist 4 to the electronic component S, the inflow of the underfill 6 can be sufficiently reduced. If the angle between the wall surface of the wall portion 41 and the first face f1 is 45° or more and 90° or less, it is advantageous in that the underfill 6 is less likely to flow into the first region 1c. For example, if the angle is 60° or more, the inflow reduction effect is further improved.

[0036] Wiring board 15 is obtained by providing wall portions 41 on wiring board 13. Wiring board 15 merely illustrates one embodiment in which solder resist 4 has wall portions 41. Solder resist 4 may also have wall portions 41 in wiring board 11 according to the first embodiment, wiring board 12 according to the second embodiment, and wiring board 14 according to the fourth embodiment described above. Of course, as long as the wiring board falls within the scope of the present disclosure, the solder resist may have wall portions.

[0037] Next, a mounting structure according to the present disclosure will be described with reference to Fig. 1. As shown in Fig. 1, a mounting structure 10 according to one embodiment includes a wiring board 11 according to one embodiment and an electronic component S. The electronic component S is mounted in a mounting region R located on the surface of the buildup layer 1b (on the first surface of the first insulating layer 21). In the mounting region R, a conductor layer 3 exposed in an opening of a solder resist 4 located on the surface of the buildup layer 1b and an electrode of the electronic component S are connected via solder 5.

[0038] The electronic component S has an inductor S1. Examples of electronic components S having the inductor S1 include inductor-embedded semiconductor elements used in various electronic devices. In the mounting structure 10, the inductor S1 faces the first region 1c with a gap (air layer) between the inductor S1 and the wiring board 11, as shown in FIG. 1. In this way, the inductor S1 faces the first region 1c with a gap between them, which increases the effect of reducing the adverse effects of capacitance. As a result, the effect of the inductor S1 included in the mounted electronic component S is efficiently exerted.

[0039] 1, an underfill 6 may be located between the electronic component S and the wiring board 11 (mounting region R). By having the underfill 6 located between the electronic component S and the wiring board 11, the electronic component S and the wiring board 11 are firmly connected to each other. As the underfill 6, for example, a resin such as an epoxy resin can be used.

[0040] As shown in FIG. 1, a mounting structure 10 according to one embodiment may have an electronic component S located on one surface and, for example, a motherboard located on the other surface, or electronic components S may be located on both surfaces of a wiring board 1.

[0041] Mounting structures 20, 30, 40, and 50 shown in Figures 2 to 5 are obtained by mounting electronic components S on wiring board 12 according to the second embodiment, wiring board 13 according to the third embodiment, wiring board 14 according to the fourth embodiment, and wiring board 15 according to the fifth embodiment, respectively.

[0042] The embodiments of the present disclosure have been described above. However, the present disclosure is not limited to the above-described embodiments, and various modifications and improvements are possible within the scope of the present disclosure as shown in (1) and (6) below.

[0043] (1) A wiring board according to the present disclosure includes a build-up layer including a first insulating layer having a first surface and a second surface opposite to the first surface, a first conductor layer located on the first surface, and a solder resist covering the first surface and a part of the first conductor layer. The build-up layer has a mounting area on the first surface in which an electronic component having an inductor is mounted. The mounting area includes a first area at a position facing the inductor when the electronic component is mounted. The first conductor layer and the solder resist are not located in the first area.

[0044] The present disclosure further discloses the following embodiments (2) to (5).

[0045] (2) In the wiring board described above in (1), the build-up layer has a recess that opens to the first region. (3) In the wiring board according to (2) above, the bottom of the recess is located in the first insulating layer. (4) In the wiring board described in (2) or (3) above, the build-up layer further includes a second insulating layer in contact with the second surface and a second conductor layer located between the first insulating layer and the second insulating layer, and the bottom of the recess is the second conductor layer. (5) In the wiring board according to any one of (1) to (4) above, the solder resist has a wall portion that protrudes in the direction opposite to the first surface so as to surround the first region.

[0046] (6) A mounting structure according to the present disclosure includes the wiring board according to any one of (1) to (5) above, and an electronic component located on a mounting area of ​​the wiring board. The electronic component includes an inductor, and the inductor faces the first area with a gap between the inductor and the wiring board. (7) In the mounting structure described in (6) above, an underfill is located between the electronic component and the wiring board. [Explanation of symbols]

[0047] 11, 12, 13, 14, 15 Wiring board 1a Core layer 1b Build-up layer 1c 1st area 1d Recess 2. Insulation layer 21 First insulating layer 22 Second insulating layer 3 Conductor Layer 31 First conductor layer 32 Second conductor layer 4 Solder resist 41 Wall 5 Solder 6 Underfill 10, 20, 30, 40, 50 mounting structure f1 1st page f2 2nd side R Implementation area

Claims

1. a build-up layer including a first insulating layer having a first surface and a second surface opposite to the first surface, and a first conductor layer located on the first surface; a solder resist covering the first surface and a portion of the first conductor layer; Including, the build-up layer has a mounting area on the first surface in which an electronic component having an inductor is mounted; the mounting area includes a first area at a position facing the inductor when the electronic component is mounted; the first conductor layer and the solder resist are not located in the first region; Wiring board.

2. The wiring board according to claim 1 , wherein the build-up layer has a recess that opens to the first region.

3. The wiring board according to claim 2 , wherein a bottom of the recess is located in the first insulating layer.

4. the build-up layer further includes a second insulating layer in contact with the second surface, and a second conductor layer located between the first insulating layer and the second insulating layer, A bottom of the recess is the second conductor layer. The wiring board according to claim 2 .

5. The wiring board according to claim 1 , wherein the solder resist has a wall portion that protrudes in a direction opposite to the first surface so as to surround the first region.

6. A wiring board according to any one of claims 1 to 5, an electronic component located on the mounting area of ​​the wiring board; Including, The electronic component includes an inductor; the inductor faces the first region with a gap between the inductor and the wiring board; The implementation structure.

7. The mounting structure according to claim 6 , wherein an underfill is located between the electronic component and the wiring board.

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