Bias circuit

Abstract

To suppress a possibility that a start-up circuit stops supplying a current before charging of a capacitance element is completed in a bias circuit including a capacitance element in a circuit for outputting a bias voltage.SOLUTION: A bias circuit 10 comprises: a bias voltage output unit 20 that includes a first current mirror circuit 22 and a second current mirror circuit 24, which are connected to a high-potential-sided node VDD, and outputs a bias voltage; a start-up circuit unit 30; and a charge circuit unit 40 having a first switch SW1 that changes from a cutout state to a connection state when a resistor R1, a transistor N5, a capacitor C1, and the start-up circuit unit 30 stop supplying a current, and a second switch SW2 that is connected to a fourth node V4 and a third node V3 and changes from a connection state to a cutout state when the start-up circuit unit 30 stops supplying a current.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a bias circuit. [Background technology]

[0002] For example, Patent Document 1 discloses a semiconductor integrated circuit including a transistor having a control electrode to which a second voltage is supplied, a first electrode connected to a node, and a second electrode connected to a fourth node into which a current based on the potential of the second voltage supply node flows, the transistor having a predetermined threshold value representing the magnitude of the voltage supplied to the control electrode to pass a predetermined amount of current between the first electrode and the second electrode, the control electrode connected to the node, the first electrode to which a first voltage is supplied, and a second electrode connected to the node, and the transistor having a threshold value smaller than the predetermined value. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2009-140261 A Summary of the Invention [Problem to be solved by the invention]

[0004] The present disclosure reduces the possibility that, in a bias circuit having a capacitance element in a circuit that outputs a bias voltage, the supply of current by a startup circuit will stop before charging of the capacitance element is completed. [Means for solving the problem]

[0005] The bias circuit of the present disclosure includes a first current mirror circuit that supplies a current from a high potential side node to a first node and a second node, the first node being connected to a control electrode, and a second current mirror circuit that supplies a current from each of the first node and the second node to a low potential side node, the second node being connected to a control electrode, and includes a bias voltage output unit that outputs a bias voltage according to a combination of the high potential side node and the first node or a combination of the second node and the low potential side node, and a switch that is connected to the high potential side node and the second node, supplies a current from the high potential side node to the second node, and stops the supply of current from the high potential side node to the second node when the potential of the high potential side node exceeds a predetermined threshold. a start-up circuit unit, and a passive element that creates a potential difference between the high potential side node and a third node, equivalent to the high potential side node and the first node, between the high potential side node and a third node, a first transistor having a control electrode connected to the first node and another electrode connected to the third node and the low potential side node, a first capacitance element connected to one of the high potential side node or the low potential side node, which outputs the bias voltage, and a fourth node, a first switch connected to the fourth node and the other node combined with the one node, and changing from a disconnected state to a connected state when the start-up circuit unit stops supplying current, and a second switch connected to the fourth node and the third node, and changing from a connected state to a disconnected state when the start-up circuit unit stops supplying current.

[0006] In this bias circuit, while the startup circuit is supplying a current to the second node, the first capacitance element is connected to one of the high potential side node and the low potential side node, which outputs a bias voltage, and to the fourth node. Therefore, since the first capacitance element is disconnected from the bias voltage output unit during operation of the startup circuit, it can be charged without being affected by the bias voltage output unit. Therefore, according to this bias circuit, the possibility that the startup circuit will stop supplying a current from the high potential side node to the second node before charging of the first capacitance element is completed is suppressed, compared to a case in which both electrodes of the first capacitance element are connected to both electrodes of a combination of nodes that constitute a bias voltage output combination. Effect of the Invention

[0007] According to the present disclosure, there is provided a bias circuit having a capacitance element in a circuit that outputs a bias voltage, which reduces the possibility that the supply of current by a startup circuit will stop before charging of the capacitance element is completed. [Brief description of the drawings]

[0008] [Figure 1] FIG. 2 is a diagram illustrating a bias circuit according to the first embodiment. [Diagram 2] 4 is a time chart in the bias circuit according to the first embodiment. [Diagram 3] FIG. 13 is a diagram illustrating a bias circuit according to a comparative example. [Figure 4] 6 is a time chart in a bias circuit according to a comparative example. [Diagram 5] FIG. 11 is a diagram illustrating a bias circuit according to a second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, an example of an embodiment of the present disclosure will be described with reference to the drawings. In each drawing, the same or equivalent components and parts are given the same reference numerals. In addition, the dimensional ratios of the drawings are exaggerated for the convenience of explanation and may differ from the actual ratios.

[0010] In the following description of the present disclosure, the term "transistor" refers to a field effect transistor (FET). That is, in the following description, the term "gate" refers to a control electrode in the present disclosure.

[0011] In addition, in the following description, the threshold voltages of the transistors (the voltage applied between the gate and body when current is applied between the drain and source) are all assumed to be smaller than the potential difference between the high-potential node VDD and the low-potential node VSS.

[0012] [First embodiment] (composition) Fig. 1 is a diagram illustrating a bias circuit 10 according to this embodiment. As shown in Fig. 1, the bias circuit 10 according to this embodiment is an integrated circuit including a bias voltage output section 20, a start-up circuit section 30, and a charge circuit section 40, each of which is connected to a high-potential side node VDD and a low-potential side node VSS.

[0013] (Bias voltage output unit 20) The bias voltage output section 20 has a first current mirror circuit 22 and a second current mirror circuit 24 .

[0014] The first current mirror circuit 22 has a first P-type transistor (hereinafter referred to as transistor P1, and the same applies to other P-type transistors) and a transistor P2, and the gates (control electrodes) of the transistors are connected to a first node V1. The specifications (e.g., gate threshold, channel length, channel width) of the transistors P1 and P2 are equivalent. The sources and bodies of the transistors P1 and P2 are connected to a high potential node VDD. The drain of the transistor P1 is connected to the first node V1 so that the current flowing through the transistor P1 is equal to that of the transistor P2. The drain of the transistor P2 is connected to a second node V2.

[0015] The second current mirror circuit 24 has a first N-type transistor (hereinafter referred to as transistor N1, and the other N-type transistors are also referred to in the same manner), a transistor N2, and a resistor R1, and the gates of the transistors N1 and N2 are connected to a second node V2. The specifications (e.g., gate threshold, channel length, channel width) of the transistors N1 and N2 are the same. The drain of the transistor N1 is connected to the first node V1, and the source of the transistor N1 is connected to a low potential side node VSS via the resistor R1. The drain of the transistor N2 is connected to the second node V2, and the source of the transistor N2 is connected to the low potential side node VSS. The gates of the transistors N1 and N2 are both connected to the second node V2, so that the potential differences between the gates and sources of the transistors N1 and N2 are equal to each other.

[0016] Here, when a current flows between the drain and source of the transistor N2, the potential difference between the gate and source is equal, so that a current equivalent to that of the transistor N2 also flows between the drain and source of the transistor N1 (current mirror). Similarly, when a current flows between the drain and source of the transistor P1, the potential difference between the gate and source is equal, so that a current equivalent to that of the transistor P1 also flows between the drain and source of the transistor P2 (current mirror). Note that since the transistor N1 is connected to the low potential side node VSS via the resistor R1, the current flowing through the transistors N1 and P1 is limited according to the resistance value of the resistor R1. In other words, the current flowing through each node of the bias voltage output unit 20 is controlled by the resistance value of the resistor R1.

[0017] (Start-up circuit section 30) The startup circuit section 30 includes a transistor P3, a transistor P4, a transistor N3, and an inverter circuit 32. The inverter circuit 32 includes a transistor P5, a transistor N4, and a transistor P6. The startup circuit section 30 further includes a transistor P7.

[0018] The transistor P3 is an example of the second transistor in this embodiment, and has a gate connected to the first node V1, a source and a body connected to the high potential side node VDD, and a drain connected to the drain of the transistor P4. The specifications of the transistor P3 are the same as those of the transistors P1 and P2. That is, the current flowing between the drain and source of the transistor P3 is the same as the current flowing between the drain and source of each of the transistors P1 and P2.

[0019] The transistor P4 is an example of a fifth transistor in this embodiment, and has a drain connected to a fifth node V5 and a source connected to the transistor P3. The body of the transistor P4 is connected to the high potential node VDD. The gate of the transistor P4 is connected to the fifth node V5. The specifications of the transistor P4 are the same as those of the transistors P1 and P2.

[0020] The transistor N3 is an example of a fourth transistor in this embodiment and is a second capacitance element, and has a gate connected to the fifth node V5 and a source, a drain, and a body all connected to the low potential side node VSS. Therefore, the transistor N3 behaves as a capacitive element (capacitance) inserted between the fifth node V5 and the low potential side node VSS due to the parasitic capacitance between the gate and the body.

[0021] In the inverter circuit 32, the source and body of the transistor P5 are connected to the high potential node VDD, and the drain is connected to the sixth node V6. The drain of the transistor N4 is connected to the sixth node V6, and the source and body are connected to the low potential node VSS. The threshold voltages of the transistors P5 and N4 are equal to each other. The gates of the transistors P5 and N4 are both connected to the fifth node V5. That is, when the potential of the fifth node V5 applied to the gates of the transistors P5 and N4 falls below the threshold voltages of the transistors P5 and N4, the drain-source of the transistor P5 is energized. Then, the drain-source of the transistor P5 is energized, so that the potential of the sixth node V6 becomes equal to the high potential node VDD. On the other hand, when the potential of the fifth node V5 exceeds the threshold voltages of the transistors P5 and N4, the drain-source of the transistor N4 is energized, and the potential of the sixth node V6 becomes equal to the low potential node VSS. In the following description, a state in which the potential of the fifth node V5 falls below the threshold voltages of the transistors P5 and N4 and the potential of the sixth node V6 becomes equivalent to the high potential node VDD is referred to as a state in which the inverter circuit 32 is stopped. Also, a state in which the potential of the fifth node V5 exceeds the threshold voltages of the transistors P5 and N4 and the potential of the sixth node V6 becomes equivalent to the low potential node VSS is referred to as a state in which the inverter circuit 32 is operating.

[0022] The transistor P6 has a source and a body connected to the high potential node VDD, and a drain connected to a fifth node V5. The transistor P6 has a gate connected to a sixth node V6. The specifications of the transistor P6 are the same as those of the transistor P5. That is, when the inverter circuit 32 is in an operating state, the transistor P6 is energized between the drain and the source, and the potential of the fifth node V5 becomes the same as that of the high potential node VDD.

[0023] The source and body of the transistor P7 are connected to the high potential node VDD, and the drain is connected to the second node V2. The gate of the transistor P7 is connected to the fifth node V5. The specifications of the transistor P7 are the same as those of the transistor P6. That is, when the inverter circuit 32 is stopped, the drain-source of the transistor P7 is energized, and the potential of the second node V2 is equal to the high potential node VDD. On the other hand, when the inverter circuit 32 is operating, the drain-source of the transistor P7 is disconnected.

[0024] (Charge circuit section 40) As shown in FIG. 1, the charge circuit section 40 includes a transistor P8, a transistor N5, a capacitor C1, a first switch SW1, a second switch SW2, and a third switch SW3.

[0025] The transistor P8 is an example of a sixth transistor in this embodiment and an example of a passive element in this embodiment. The source and body of the transistor P8 are connected to the high potential side node VDD, and the drain and gate are connected to the seventh node V7. The specifications of the transistor P8 are the same as those of the transistors P1 and P2.

[0026] The transistor N5 is an example of a first transistor in this embodiment, and has a drain connected to the third node V3, a source connected to the low potential side node VSS, and a gate connected to the second node V2.

[0027] The capacitor C1 is an example of a first capacitance element in this embodiment, and has one terminal connected to the high potential side node VDD and the other terminal connected to the fourth node V4. The capacitance of the capacitor C1 is sufficiently larger than the parasitic capacitance of the transistor P1 in this embodiment.

[0028] The first switch SW1 connects and disconnects the first node V1 and the fourth node V4. The first switch SW1 may be made of any component, but as an example, it is made of a transistor with the same specifications as the transistor P7. The specific timing of the switching operation of the first switch SW1 will be described later.

[0029] The second switch SW2 connects and disconnects the seventh node V7 and the fourth node V4. The second switch SW2 may be made of any component, but as an example, it is made of a transistor with the same specifications as the transistor N4. The specific timing of the switching operation of the second switch SW2 will be described later.

[0030] The third switch SW3 connects and disconnects the third node V3 and the seventh node V7. The third switch SW3 may be made of any component, but as an example, it is made of a transistor with the same specifications as the transistor N4. The specific timing of the switching operation of the third switch SW3 will be described later.

[0031] In the following description, a state in which the first switch SW1, the second switch SW2, and the third switch SW3 connect the respective nodes is referred to as a connected state, and a state in which the respective nodes are disconnected is referred to as a disconnected state.

[0032] Here, the transistor P8 has a gate connected to the drain and a body and a source connected to the high potential node VDD, so that the seventh node V7 is electrically connected to the high potential node VDD via the transistor P8. In other words, the potential difference between the high potential node VDD and the seventh node V7 is created between the drain and source of the transistor P8. Since the specifications of the transistor P8 are the same as those of the transistor P1, the transistor P8 creates a potential difference between the high potential node VDD and the seventh node V7 that corresponds to the potential difference between the high potential node VDD and the first node V1.

[0033] In addition, when the third switch SW3 is in a connected state, if a current flows between the drain and source of transistor N2, since the potential difference between the gate and source is equal, a current equivalent to that of transistor N2 also flows between the drain and source of transistor N5 (current mirror).

[0034] In this embodiment, the first switch SW1, the second switch SW2, and the third switch SW3 all perform a switching operation together with the transistor P7. More specifically, when the drain-source of the transistor P7 is energized, the first switch SW1 is also energized, and when the drain-source of the transistor P7 is disconnected, the first switch SW1 is also disconnected. On the other hand, when the drain-source of the transistor P7 is energized, the second switch SW2 and the third switch SW3 are disconnected, and when the drain-source of the transistor P7 is disconnected, the second switch SW2 and the third switch SW3 are energized.

[0035] In the bias circuit 10 according to the present embodiment, in the initial state (when the bias circuit 10 is stopped), the potential of the high potential side node VDD is set to be equal to that of the low potential side node VSS. When the bias circuit 10 according to the present embodiment is started, power is supplied to the high potential side node VDD, and the potential rises.

[0036] In addition, although detailed operation will be described later, in the bias circuit 10 according to this embodiment, when the potential of the high potential side node VDD rises, the fifth node V5 also rises, and the transistor P7 disconnects the high potential side node VDD and the second node V2. In the following description, the period from when the potential of the high potential side node VDD starts to rise until the transistor P7 is disconnected is referred to as the start-up period.

[0037] Next, the operation of the bias circuit 10 of this embodiment will be described with reference to FIG.

[0038] (Operation of bias circuit 10) FIG. 2 is a diagram showing the potentials of the fifth node V5, the first node V1, and the fourth node V4, and the operating states of the first switch SW1, the second switch SW2, and the third switch SW3 in the bias circuit 10 according to the present embodiment.

[0039] 2, in the bias circuit 10 according to this embodiment, when the potential of the high potential side node VDD starts to rise, a current flows to the second node V2 of the bias voltage output unit 20 through the transistor P7. Then, the second current mirror circuit 24 causes a current to flow also through the transistor N1 and the transistor P1, so that charging of the first node V1 starts.

[0040] 1, in the bias circuit 10 according to the present embodiment, the potential of the second node V2 is also supplied to the gate of the transistor N5. Since the transistor P8 is also conductive, a current equivalent to that of the second node V2 flows through the seventh node V7 and the third node V3 via the transistor P8 and the transistor N5.

[0041] Furthermore, since the fourth node V4 is connected to the seventh node V7 via the second switch SW2, charge starts to accumulate in the capacitor C1 so that the high potential side node VDD becomes a high potential.

[0042] In the startup circuit section 30, a current flows to the fifth node V5 through the transistors P3 and P4. More specifically, since the gate of the transistor P3 is connected to the first node V1, the magnitude of the current flowing from the transistor P3 is equal to the magnitude of the current flowing to the transistor P1. The current flowing to the fifth node V5 charges the transistor N3, so the potential of the fifth node V5 rises. When a current is supplied to the first node V1 through the transistor P1, the potential of the fifth node V5 continues to rise.

[0043] Here, when the potential of the fifth node V5 rises to the operating potential of the inverter circuit 32, i.e., when the inverter circuit 32 operates, the drain-source of the transistor P6 is energized, so that the potential of the fifth node V5 rises rapidly to the high-potential node VDD. Also, the potential of the gate of the transistor P7 rises and exceeds the threshold, and the drain-source of the transistor P7 is disconnected, so that the supply of current to the second node V2 through the transistor P7 stops. In other words, when the potential of the fifth node V5 exceeds the potential at which the inverter circuit 32 operates, the startup circuit unit 30 stops operating.

[0044] Here, at the time when the startup circuit unit 30 stops operating, current flows through the first node V1 and the second node V2. Therefore, the bias voltage output unit 20 outputs a potential difference, that is, a bias voltage, between the high potential side node VDD and the electrode (electrode bh in FIG. 1) connected to the first node V1.

[0045] As described above, the first switch SW1 and the second switch SW2 perform a switching operation together with the transistor P7, so that the fourth node V4 is connected to the first node V1 and the fourth node V4 is disconnected from the seventh node V1. In other words, when the bias voltage is output, the capacitor C1 is connected to the first node V1, so that even if a voltage fluctuation such as a ripple occurs in the high potential node VDD, the bias voltage is less likely to fluctuate.

[0046] As described above, the third switch SW3 performs a switching operation together with the transistor P7, and therefore the seventh node V7 and the third node V3 are disconnected from each other. In other words, when the bias voltage is output, the supply of current to the seventh node V7 and the third node V3 is stopped.

[0047] (Operation of bias circuit 110 of comparison circuit) Here, the bias circuit 110 related to the comparison circuit of this embodiment will be described with reference to Figures 3 and 4. Note that, among the bias circuit 110 related to the comparison circuit, the same components as those of the bias circuit 10 according to the embodiment are denoted by the same reference numerals as those of the bias circuit 10 according to the embodiment, and detailed descriptions thereof will be omitted.

[0048] 3, the bias circuit 110 relating to the comparison circuit is different from the bias circuit 10 according to the embodiment in that it does not include a charge circuit unit 40. Also, a capacitor C1 is connected to a high potential side node VDD and a first node V1. The other configurations are the same as those of the bias circuit 10 according to the embodiment.

[0049] 4, in the bias circuit 110 associated with the comparator circuit, similarly to the bias circuit 10 of this embodiment, when the potential of the high potential side node VDD starts to rise, a current flows to the second node V2 of the bias voltage output unit 20 through the transistor P7. Then, the second current mirror circuit 24 causes a current to flow also through the transistors N1 and P1, and charging of the first node V1 starts.

[0050] Also, the charge starts to be stored in the capacitor C1 so that the high potential node VDD side becomes the high potential. However, as shown in FIG 3, the charge stored in the capacitor C1 depends on the difference between the potential of the high potential node VDD and the potential of the first node V1.

[0051] Here, the current flowing through the transistor P1 passes through the resistor R1 of the second current mirror circuit 24. That is, the potential difference between the high potential side node VDD and the first node V1 becomes smaller depending on the voltage drop due to the resistor R1. In other words, in the bias voltage output circuit according to the comparative example, the charging of the capacitor C1 becomes slower due to the resistor R1.

[0052] Furthermore, if the startup circuit section 30 stops operating before charging of the capacitor C1 is completed, the charge stored in the capacitor C1 will be insufficient, and if a voltage fluctuation occurs at the high-potential side node VDD, the effect of the voltage fluctuation will be easily reflected in the bias voltage.

[0053] In addition, when the startup circuit section 30 is stopped, the amount of current flowing into the first node V1 through the transistor P1 does not increase, so the charge stored in the capacitor C1 does not increase. Therefore, as shown in Fig. 4, in the bias circuit 110 according to the comparative example, it was necessary to extend the startup period in order to complete charging of the capacitor C1 before the startup circuit section 30 stops. More specifically, in the bias circuit 110 according to the comparative example, it was necessary to increase the operating potential of the inverter circuit 32.

[0054] 1, in the bias circuit 10 according to the present embodiment, the first capacitance element is connected to the high potential side node VDD and the fourth node V4 while the startup circuit section 30 is supplying a current to the second node V2. In other words, in the bias circuit 10 according to the present embodiment, while the startup circuit section 30 is operating, the charge stored in the capacitor C1 flows from the transistor P8, so that the capacitor C1 can be charged without being affected by the resistor R1. Therefore, the bias circuit 10 according to the present embodiment reduces the possibility that the supply of current from the high potential side node VDD to the second node V2 by the startup circuit 30 stops before the charging of the capacitor C1 is completed, compared to the bias circuit 110 according to the comparative example. In other words, the bias circuit 10 according to the present embodiment can shorten the startup period, compared to the bias circuit 110 according to the comparative example.

[0055] In the bias circuit 10 according to the present embodiment, the startup circuit section 30 includes a transistor P3 having a gate connected to the first node V1 and another electrode connected to a high potential node VDD and the source of the fourth transistor. The startup circuit section 30 also includes a transistor N3 connected to a fifth node V5 and a low potential node VSS. The startup circuit section 30 also includes an inverter circuit 32 that operates when the potential difference between the low potential node VSS and the fifth node V5 exceeds a predetermined threshold value to connect the high potential node VDD and the fifth node V5. The startup circuit section 30 also includes a transistor P7 that has a gate connected to the fifth node V5 and is connected to the high potential node VDD and the second node V2, and that cuts off the connection between the high potential node VDD and the second node V2 when the inverter circuit 32 operates.

[0056] In the bias circuit 10 according to the present embodiment, the transistor N3 has a gate connected to the fifth node V5 and another electrode connected to the low potential node VSS.

[0057] According to the bias circuit 10 of this embodiment, the capacitance relative to the area of ​​the transistor N3 can be made larger than when the transistor N3 is a capacitor.

[0058] Moreover, the bias circuit 10 according to this embodiment includes a transistor P4 that is connected between the transistor N5 and a fifth node V5 and has a gate connected to the fifth node V5.

[0059] According to the bias circuit 10 of this embodiment, since the transistor P4 is connected between the transistor P3 and the fifth node V5, the timing at which the current is supplied to the fifth node V5 is delayed compared to a configuration not including the transistor P4. Therefore, according to the bias circuit 10, the possibility that the startup circuit 30 stops supplying the current from the high potential side node VDD to the second node V2 before the charging of the capacitor C1 is completed is further suppressed compared to a configuration not including the transistor P4.

[0060] Moreover, the bias circuit 10 according to the present embodiment includes a third switch SW3 that cuts off the connection between the transistor P8 and the transistor N5 at the third node V3 when the startup circuit section 30 stops supplying current.

[0061] According to the bias circuit 10 of this embodiment, the current is not supplied from the transistor P8 to the transistor N5 after the startup circuit section 30 stops supplying the current. Therefore, according to the bias circuit 10, the power consumed after the startup circuit section 30 stops supplying the current can be reduced compared to a case where the transistor P8 and the transistor N5 are connected without the third switch SW3.

[0062] In the bias circuit 10 according to the present embodiment, the transistor P8 is connected to the high potential side node VDD and the third node V3, and has its gate connected to the third node V3.

[0063] According to the bias circuit 10 of this embodiment, it is easy to create a potential difference between the high potential side node VDD and the third node V3 equivalent to that between the high potential side node VDD and the first node V1.

[0064] Next, a bias circuit 210 according to a second embodiment of the present disclosure will be described with reference to Fig. 5. Note that, in the bias circuit 210 according to the second embodiment, the same components as those in the first embodiment are denoted by the same reference numerals as those in the first embodiment, and detailed descriptions thereof will be omitted.

[0065] [Second embodiment] 5 is a diagram of a bias circuit 210 according to a second embodiment of the present disclosure. The bias circuit 210 according to this embodiment differs from the bias circuit 10 according to the first embodiment in the following respects.

[0066] In this embodiment, the transistor N5 has a gate connected to the third node V3. Also, in this embodiment, the capacitor C1 connects the low potential side node VSS and the fourth node V4.

[0067] In this embodiment, the gate of the transistor P8 is connected to the first node V1.

[0068] In this embodiment, the first switch SW1 connects and disconnects the second node V2 and the fourth node V4. In this embodiment, the second switch SW2 connects and disconnects the third node V3 and the fourth node V4. In this embodiment, the third switch SW3 connects and disconnects the third node V3 and the seventh node V7. The operations of the first switch SW1, the second switch SW2, and the third switch SW3 in this embodiment are the same as those in the first embodiment.

[0069] In the bias circuit 210 according to this embodiment, even when the startup circuit section 30 stops operating, currents flow through the first node V1 and the second node V2. In the bias circuit 210 according to this embodiment, the capacitor C1 is connected to the low potential side node VSS and the second node V2. Therefore, in the bias circuit 210 according to this embodiment, the bias voltage output section 20 outputs a potential difference, that is, a bias voltage, between the low potential side node VSS and an electrode (electrode bl in FIG. 5) connected to the second node V2.

[0070] In the bias circuit 210 of this embodiment, the same functions and effects as those of the first embodiment can be obtained, except that the node that outputs the bias voltage is an electrode connected to the low potential side node VSS and the second node V2.

[0071] [Other embodiments] The bias circuit 10 according to the first embodiment and the bias circuit 210 according to the second embodiment may be combined. That is, the bias circuit 10 according to the first embodiment may have the first switch SW1, the second switch SW2, and the first capacitor of the bias circuit 210 according to the second embodiment, and the gate of the transistor N5 may be connected to the third node V3. In this case, the bias voltage is output from two locations: an electrode connected to the high potential node VDD and the first node V1, and an electrode connected to the low potential node VSS and the second node V2.

[0072] In the above description, the startup circuit section 30 has the transistor P3, the inverter circuit 32, and the transistor P7, but the technology according to the present embodiment is not limited to this. When the bias circuit 10 is started, the startup circuit section 30 may adopt another optimal configuration as appropriate as long as it can cause a current to flow to the second node V2 until the bias voltage is output from the bias voltage output section 20.

[0073] In the above description, the second capacitance element is the transistor N3 having a gate connected to the fifth node V5 and a source, a drain, and a body connected to the low potential node VSS, but the technology according to the present disclosure is not limited to this. That is, a capacitive element such as a capacitor may be used instead of the transistor N3.

[0074] In the above description, the bias circuit 10 includes the transistor P4 connected between the transistor N5 and the fifth node V5 and having a gate connected to the fifth node V5, but the technology according to the present disclosure is not limited to this. For example, instead of the transistor P4, a resistor may be inserted between the transistor P3 and the fifth node V5, or the transistor P3 may simply be directly connected to the fifth node V5.

[0075] In the above description, the charge circuit 40 has the third switch SW3 at the third node V3, but the technology according to the present disclosure is not limited to this. For example, the transistor P8 and the transistor N5 may be connected without the third switch SW3.

[0076] In the above description, the passive element of the charge circuit section 40 is the transistor P8 that connects the high potential node VDD and the third node V3, but the technology according to the present disclosure is not limited to this. That is, other elements such as resistors may be used as long as a potential difference equivalent to that between the high potential node VDD and the first node V1 can be created between the high potential node VDD and the third node V3.

[0077] In the above description of the present disclosure, all the transistors are field effect transistors, but the technology according to the present disclosure is not limited to this. That is, bipolar transistors may be used instead of field effect transistors. In the above description of the present disclosure, the bias circuit 10 is a so-called integrated circuit, but the technology according to the present disclosure is not limited to this. For example, the bias circuit 10 may be manufactured by bonding each element to a substrate.

[0078] The above describes an embodiment of the present disclosure with reference to the attached drawings. However, it is clear that a person with ordinary knowledge in the technical field to which the present disclosure pertains can conceive of various modifications or applications within the scope of the technical ideas described in the claims, and it is understood that these also naturally fall within the technical scope of the present disclosure.

[0079] Furthermore, preferred aspects of the present disclosure will be described below.

[0080] (Appendix 1) a bias voltage output section including a first current mirror circuit that supplies a current from a high potential side node to a first node and a second node, the first node being connected to a control electrode, and a second current mirror circuit that supplies a current from each of the first node and the second node to a low potential side node, the second node being connected to a control electrode, and which outputs a bias voltage according to a combination of the high potential side node and the first node or a combination of the second node and the low potential side node; a startup circuit section connected to a high potential side node and the second node, supplying a current from the high potential side node to the second node, and stopping the supply of the current from the high potential side node to the second node when the potential of the high potential side node exceeds a predetermined threshold value; a charge circuit section including: a passive element that creates a potential difference between the high potential side node and a third node, the potential difference corresponding to the high potential side node and the first node; a first transistor having a control electrode connected to the first node and another electrode connected to the third node and the low potential side node; a first capacitance element connected to one of the high potential side node and the low potential side node, the one node outputting the bias voltage, and a fourth node; a first switch connected to the fourth node and the other node combined with the one node, the first switch changing from a disconnected state to a connected state when the startup circuit section stops supplying current; and a second switch connected to the fourth node and the third node, the second switch changing from a connected state to a disconnected state when the startup circuit section stops supplying current; A bias circuit comprising:

[0081] (Appendix 2) the startup circuit unit includes a second transistor having a control electrode connected to the first node and another electrode connected to the high potential side node and a fifth node, a second capacitance element connected to the fifth node and the low potential side node, an inverter circuit that operates when a potential difference between the low potential side node and the fifth node exceeds a predetermined threshold value to connect the high potential side node and the fifth node, and a third transistor having a control electrode connected to the fifth node and another electrode connected to the high potential side node and the second node, and that cuts off the connection between the high potential side node and the second node when the inverter circuit operates. 2. The bias circuit of claim 1.

[0082] (Appendix 3) the second capacitance element is a fourth transistor having a control electrode connected to the fifth node and another electrode connected to the low potential side node; 3. The bias circuit according to claim 2.

[0083] (Appendix 4) a fifth transistor connected between the first transistor and the fifth node, the fifth transistor having a control electrode connected to the fifth node; 4. The bias circuit according to claim 2 or 3.

[0084] (Appendix 5) a third switch connected between the passive element at the third node and the first transistor, and cutting off between the passive element at the third node and the first transistor when the startup circuit section stops supplying current; 5. The bias circuit according to claim 1 ,

[0085] (Appendix 6) the passive element is a sixth transistor connected to the high potential side node and the third node, and having a control electrode connected to the third node; 6. The bias circuit according to claim 1, [Explanation of symbols]

[0086] 10, 210 Bias circuit 110 Comparative Example Bias Circuit 20 Bias voltage output section 22 First current mirror circuit 24 Second current mirror circuit 30 Start-up circuit section 32 Inverter circuit 40 Charge circuit section 42 Third current mirror circuit

Claims

1. a bias voltage output section including a first current mirror circuit that supplies a current from a high potential side node to a first node and a second node, the first node being connected to a control electrode, and a second current mirror circuit that supplies a current from each of the first node and the second node to a low potential side node, the second node being connected to a control electrode, and which outputs a bias voltage according to a combination of the high potential side node and the first node or a combination of the second node and the low potential side node; a startup circuit section connected to a high potential side node and the second node, supplying a current from the high potential side node to the second node, and stopping the supply of the current from the high potential side node to the second node when the potential of the high potential side node exceeds a predetermined threshold value; a charge circuit section including: a passive element that creates a potential difference between the high potential side node and a third node, the potential difference corresponding to the high potential side node and the first node; a first transistor having a control electrode connected to the first node and another electrode connected to the third node and the low potential side node; a first capacitance element connected to one of the high potential side node and the low potential side node, the one node outputting the bias voltage, and a fourth node; a first switch connected to the fourth node and the other node combined with the one node, the first switch changing from a disconnected state to a connected state when the startup circuit section stops supplying current; and a second switch connected to the fourth node and the third node, the second switch changing from a connected state to a disconnected state when the startup circuit section stops supplying current; A bias circuit comprising:

2. the startup circuit unit includes a second transistor having a control electrode connected to the first node and another electrode connected to the high potential side node and a fifth node, a second capacitance element connected to the fifth node and the low potential side node, an inverter circuit that operates when a potential difference between the low potential side node and the fifth node exceeds a predetermined threshold value to connect the high potential side node and the fifth node, and a third transistor having a control electrode connected to the fifth node and another electrode connected to the high potential side node and the second node, and that cuts off the connection between the high potential side node and the second node when the inverter circuit operates.

2. The bias circuit of claim 1.

3. the second capacitance element is a fourth transistor having a control electrode connected to the fifth node and another electrode connected to the low potential side node; 3. The bias circuit of claim 2.

4. a fifth transistor connected between the first transistor and the fifth node, the fifth transistor having a control electrode connected to the fifth node; 4. The bias circuit according to claim 2.

5. a third switch connected between the passive element at the third node and the first transistor, and cutting off between the passive element at the third node and the first transistor when the startup circuit section stops supplying current; 2. The bias circuit of claim 1.

6. the passive element is a sixth transistor connected to the high potential side node and the third node, and having a control electrode connected to the third node; 2. The bias circuit of claim 1.

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