Semiconductor device and manufacturing method of the semiconductor device

Abstract

To provide a semiconductor device capable of realizing a miniaturization while securing a proof pressure.SOLUTION: A semiconductor device comprises: a semiconductor substrate 11 having a first conductive type; a gate electrode 16 positioned on the semiconductor substrate 11; and a semiconductor part 30 embedded into the semiconductor substrate 11, and having the first conductive type. In the semiconductor substrate 11, at least a part of a drift region 19 adjacent to the semiconductor part 30, and having a second conductive type is provided, and both of a front surface 30a of the semiconductor part 30 and a first part included in a front surface of the drift region 19 are positioned above a second part positioned below the gate electrode 16 on a front surface of the semiconductor substrate 11.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing a semiconductor device. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device including a substrate, a first transistor provided on the substrate, and a second transistor provided on the substrate. The first transistor and the second transistor each have a well of a first conductivity type and a strip region provided on the well and extending in a first direction, the strip region having a backgate region of the first conductivity type and a source region of a second conductivity type, and the ratio of the length of the source region to the length of the backgate region along the first direction in the strip region of the first transistor is greater than the ratio in the strip region of the second transistor. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2016-27622 A

[0004] [overview] An object according to one aspect of the present disclosure is to provide a semiconductor device that can be miniaturized while ensuring a withstand voltage.

[0005] A semiconductor device according to one aspect of the present disclosure comprises a semiconductor substrate having a first conductivity type, a gate electrode located on the semiconductor substrate, and a semiconductor portion embedded in the semiconductor substrate and having the first conductivity type, wherein the semiconductor substrate has at least a portion of a drift region adjacent to the semiconductor portion and having a second conductivity type, and a surface of the semiconductor portion and a first portion included in the surface of the drift region are located above a second portion located below the gate electrode on the surface of the semiconductor substrate. [Brief description of the drawings]

[0006] [Figure 1]FIG. 1 is a plan view showing a chip of a semiconductor device according to an embodiment. [Diagram 2] FIG. 2 is a schematic cross-sectional view of a main part of the semiconductor device according to the embodiment. [Figure 3A] FIG. 3A is a schematic cross-sectional view for explaining a part of the manufacturing method of the semiconductor device according to the embodiment. [Figure 3B] FIG. 3B is a schematic cross-sectional view for explaining a part of the manufacturing method of the semiconductor device according to the embodiment. [Figure 3C] FIG. 3C is a schematic cross-sectional view for explaining a part of the manufacturing method of the semiconductor device according to the embodiment. [Figure 3D] FIG. 3D is a schematic cross-sectional view for explaining a part of the manufacturing method of the semiconductor device according to the embodiment. [Figure 4] FIG. 4 is a schematic cross-sectional view showing a configuration of a semiconductor device according to a modified example. [Figure 5A] FIG. 5A is a schematic cross-sectional view for explaining a part of a method for manufacturing a semiconductor device according to a modified example. [Figure 5B] FIG. 5B is a schematic cross-sectional view for explaining a part of a method for manufacturing a semiconductor device according to a modified example. [Figure 5C] FIG. 5C is a schematic cross-sectional view for explaining a part of a method for manufacturing a semiconductor device according to a modified example. [Figure 5D] FIG. 5D is a schematic cross-sectional view for explaining a part of a method for manufacturing a semiconductor device according to a modified example. [Figure 5E] FIG. 5E is a schematic cross-sectional view for explaining a part of a method for manufacturing a semiconductor device according to a modified example.

[0007] [Detailed Description] Hereinafter, the embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the following description, the same elements or elements having the same functions will be designated by the same reference numerals, and duplicated descriptions will be omitted. In this specification, the word "same" and similar words are not limited to "completely same". In addition, since the drawings are intended to conceptually explain the embodiments, the dimensions and ratios of each component shown may differ from the actual ones.

[0008] Fig. 1 is a schematic plan view showing a chip of a semiconductor device according to this embodiment. As shown in Fig. 1, the semiconductor device 1 includes a silicon chip 2 (semiconductor chip) having a rectangular parallelepiped shape. The chip 2 is one of a number of devices formed on a silicon wafer having a diameter of, for example, 300 mm (about 12 inches). Hereinafter, the direction along the thickness of the chip 2 will be simply referred to as the thickness direction, and the surface 2a of the chip 2 shown in Fig. 1 may be referred to as the top surface of the chip 2.

[0009] The surface 2a of the chip 2 is provided with device regions, such as a driver circuit 3, a pre-driver circuit 4, an analog circuit 5, a power supply circuit 6, a logic circuit 7, and an input / output circuit 8. At least one of the device regions includes a functional device formed by utilizing the internal and external regions of the chip 2. The functional device includes, for example, at least one of a semiconductor switching device, a semiconductor rectifying device, and a passive device. The functional device may include a circuit network in which at least two of a semiconductor switching device, a semiconductor rectifying device, and a passive device are combined. Although not shown, metal wiring and the like may be provided above the surface 2a of the chip 2.

[0010] The semiconductor switching device may include at least one of a metal insulator semiconductor field effect transistor (MISFET), a bipolar junction transistor (BJT), an insulated gate bipolar junction transistor (IGBT), and a JFET. The semiconductor rectifying device may include at least one of a pn junction diode, a pin junction diode, a Zener diode, a Schottky barrier diode, and a fast recovery diode. The passive device may include at least one of a resistor, a capacitor, an inductor, and a fuse.

[0011] At least one of the device regions includes at least one transistor region 10 (see FIG. 2 described later). The transistor region 10 includes a FET structure. In this embodiment, the FET structure has a so-called LDMISFET (Lateral Double Diffused MISFET) structure. An example of the FET structure included in the semiconductor device 1 will be described below.

[0012] 2 is a schematic cross-sectional view of a main part of the semiconductor device according to this embodiment. As shown in FIG. 2, the semiconductor substrate 11 is a high-resistance silicon substrate, which is the above-mentioned silicon wafer, and has a first conductivity type. In this embodiment, the first conductivity type is p-type, but may be n-type. The impurity concentration of the semiconductor substrate 11 is set to a relatively low value. In this embodiment, the impurity concentration of the semiconductor substrate 11 is, for example, 1.0×10 13 cm -3 Above 1.0×10 14 cm -3 The potential of the semiconductor substrate 11 is, for example, a reference potential, but is not limited to this. The semiconductor substrate 11 may be grounded. In FIG. 2, an element isolation region EIR and an active region AR in the semiconductor substrate 11 are shown.

[0013] The element isolation region EIR is a region where an STI (Shallow Trench Isolation) structure is provided as an element isolation structure. The STI structure has a groove G1 and an insulating layer 12 embedded in the groove G1. The groove G1 extends from the upper surface to the lower surface of the semiconductor substrate 11 along the thickness direction. The groove G1 is formed, for example, by removing a part of the semiconductor substrate 11 by etching. The insulating layer 12 is an insulator provided in the groove G1. The insulating layer 12 is, for example, an oxide film formed by a chemical vapor deposition method (CVD method).

[0014] The active region AR is a region in which a FET structure is provided, and is partitioned by, for example, an element isolation region EIR. One or more transistors T are provided in the active region AR. The portion of the semiconductor substrate 11 included in the active region AR has a first substrate portion 11a and a second substrate portion 11b that is thicker than the first substrate portion 11a. In the thickness direction, the thickness of the first substrate portion 11a is smaller than the thickness of the second substrate portion 11b, and the surface 11c of the first substrate portion 11a is located below the surface 11d of the second substrate portion 11b. Therefore, a part of the second substrate portion 11b can be regarded as a convex portion that protrudes upward in the thickness direction relative to the first substrate portion 11a. For example, the first substrate portion 11a and the second substrate portion 11b are provided by thinning a part of the semiconductor substrate 11 by etching or the like. In this embodiment, the first substrate portion 11a surrounds the second substrate portion 11b in a plan view, but this is not limited to this.

[0015] The transistor T has a source region 13 having a second conductivity type different from the first conductivity type, a drain region 14 having the second conductivity type, a gate insulating layer 15, and a gate electrode 16. The source region 13 and the drain region 14 are included in an active region AR. The source region 13 is provided in the first substrate portion 11a, and the drain region 14 is provided in the second substrate portion 11b. The gate insulating layer 15 and the gate electrode 16 are located on the semiconductor substrate 11.

[0016] The source region 13 is a region that functions as the source of the transistor T. The source region 13 constitutes a part of the surface 11c of the first substrate portion 11a. In this embodiment, the source region 13 is an n-type region and is fixed at a source potential. For example, a source potential is applied to the source region 13 from outside the chip 2. The impurity concentration of the source region 13 is, for example, 1.0×10 18 cm -3 Above 1.0×10 21 cm -3 The body region 17 and the contact region 18 in contact with the source region 13 are provided around the source region 13.

[0017] The body region 17 is, for example, a region (well region) that covers the bottom of the source region 13 and has the first conductivity type, and extends along the periphery of the active region AR. The body region 17 has, for example, a circular ring shape, an elliptical ring shape, or the like in a plan view. The body region 17 constitutes a part of the surface 11c of the first substrate portion 11a. The first region of the body region 17 is located closer to the drain region 14 than the source region 13 in a plan view. The second region of the body region 17 is located below the source region 13. The third region of the body region 17 is located closer to the element isolation region EIR than the source region 13 in a plan view. The third region is in contact with the element isolation region EIR, but is not limited to this. The depth of the body region 17 is, for example, approximately the same as the groove G1. The difference between the depth of the body region 17 and the depth of the groove G1 is, for example, 20% or less. From the viewpoint of element isolation, the depth of the body region 17 may be shallower than the depth of the groove G1. In this embodiment, the body region 17 is fixed to the potential of the semiconductor substrate 11 (for example, the back gate potential), but is not limited to this. The impurity concentration of the body region 17 is higher than the impurity concentration of the semiconductor substrate 11, and is, for example, 1.0×10 15 cm -3 Above 1.0×10 18 cm -3 The following is the result.

[0018] The contact region 18 is a region fixed to a potential different from that of the source region 13, and has a first conductivity type. The contact region 18 is located in the body region 17, contacts the source region 13, and is located outside the source region 13. The first region 18a of the contact region 18 is provided in the first substrate portion 11a of the semiconductor substrate 11, and the second region 18b of the contact region 18 is provided in the second substrate portion 11b of the semiconductor substrate 11. Therefore, the first region 18a constitutes a part of the surface 11c of the first substrate portion 11a, and the second region 18b constitutes a part of the surface 11d of the second substrate portion 11b. The second region 18b of the contact region 18 overlaps the third region of the body region 17. Therefore, the second region 18b contacts the element isolation region EIR, but is not limited to this. The impurity concentration of the contact region 18 is higher than the impurity concentration of the body region 17. For example, the impurity concentration of the contact region 18 is, for example, 1.0×10 18 cm -3 Above 1.0×10 21 cm -3 The following is the result.

[0019] The drain region 14 functions as the drain of the transistor T, and a drain potential is applied to the drain region 14. The drain region 14 has, for example, a ring shape or an elliptical ring shape in a plan view. The drain region 14 constitutes a part of the surface 11d of the second substrate portion 11b. Therefore, the drain region 14 constitutes a part of the uppermost part of the second substrate portion 11b, and is located above the source region 13. The impurity region of the drain region 14 has a dopant concentration of, for example, 1.0×10 18 cm -3 Above 1.0×10 21 cm -3 The drift region 19 is provided below the drain region 14 in the active region AR. The drift region 19 is in contact with the drain region 14 and is spaced apart from the body region 17.

[0020] The drift region 19 is a region (well region) covering the bottom of the drain region 14, and has the second conductivity type. As a result, the drift region 19 forms a pn junction with the semiconductor substrate 11. The drift region 19 and the semiconductor substrate 11 form a pn junction, thereby increasing the breakdown voltage of the transistor T. The drift region 19 has a shape surrounding the drain region 14 in a plan view, for example. The impurity concentration of the drift region 19 is higher than the impurity concentration of the semiconductor substrate 11, and is, for example, 1.0×10 15 cm -3 Above 1.0×10 18 cm -3 The following is the result.

[0021] In this embodiment, the entire drift region 19 is provided in the semiconductor substrate 11. The drift region 19 includes a first region 19a and a second region 19b located above the first region 19a. The first region 19a is provided in the first substrate portion 11a and the second substrate portion 11b of the semiconductor substrate 11. A part of the first region 19a is located closer to the source region 13 than the second region 19b. The second region 19b is in contact with the drain region 14 and provided in the second substrate portion 11b of the semiconductor substrate 11. The second region 19b is located between the drain region 14 and the first region 19a in the thickness direction. A part of the second region 19b is covered by the drain region 14. Therefore, a part of the first region 19a constitutes a part of the surface 11c of the first substrate portion 11a, and a part of the second region 19b constitutes a part of the surface 11d of the second substrate portion 11b. Therefore, the part (first portion) of the second region 19b is located above the surface 11c of the first substrate portion 11a. The part of the second region 19b includes, but is not limited to, an inclined surface that extends closer to the surface 11c of the first substrate portion 11a as it moves away from the drain region 14.

[0022] The gate insulating layer 15 is an insulator that selectively covers the semiconductor substrate 11. In this embodiment, the gate insulating layer 15 covers at least the first substrate portion 11a of the semiconductor substrate 11. The gate insulating layer 15 includes, for example, a LOCOS film (Local oxidation of silicon film) formed by selectively oxidizing the surface of the semiconductor substrate 11, an oxide film, a nitride film, an oxynitride film, or the like selectively formed on the semiconductor substrate 11. The gate insulating layer 15 may have a single layer structure or a laminated structure.

[0023] The gate electrode 16 is an electrode located on the semiconductor substrate 11 via the gate insulating layer 15. The gate electrode 16 overlaps at least a channel region 20 formed between the body region 17 and the drift region 19. A current path passing through the body region 17, the drift region 19, and the channel region 20 between the source region 13 and the drain region 14 is formed according to a potential applied to the gate electrode 16. In this embodiment, the gate electrode 16 overlaps the first region of the body region 17 and the first region 19a of the drift region 19. Therefore, a portion (second portion) located below the gate electrode 16 on the surface of the semiconductor substrate 11 is located below the second region 19b of the drift region 19. The gate electrode 16 is, for example, polycrystalline silicon into which an impurity is introduced.

[0024] The active region AR is provided with a semiconductor portion 30 that is embedded in the semiconductor substrate 11 and has a first conductivity type. The semiconductor portion 30 is a portion that forms a pn junction with the drift region 19, and is, for example, polycrystalline silicon into which an impurity is introduced. The semiconductor portion 30 is embedded in a groove G2 provided in the second substrate portion 11b of the semiconductor substrate 11. The groove G2 is formed, for example, at a different timing from the groove G1, but is not limited to this. The depth of the groove G2 is, for example, approximately the same as the depth of the groove G1, but is not limited to this. In this embodiment, the depth of the semiconductor portion 30 embedded in the groove G2 is approximately the same as the depth of the drift region 19. The groove G2 is provided so as to be adjacent to the drain region 14 and the drift region 19. Therefore, the semiconductor portion 30 embedded in the groove G2 is adjacent to at least the drift region 19. In this embodiment, the semiconductor portion 30 is adjacent to both the first region 19a and the second region 19b of the drift region 19. This satisfactorily exhibits the resurf effect provided by the semiconductor portion 30. Moreover, the surface 30a of the semiconductor portion 30 constitutes a part of the surface of the second substrate portion 11b, and substantially coincides with the surface of the drain region 14. Therefore, the surface 30a is located above the surface 11c of the first substrate portion 11a.

[0025] Although not shown, the shape of the semiconductor portion 30 in plan view has a substantially rectangular or elliptical shape, for example. The width of the semiconductor portion 30 along the direction in which the source region 13 and the contact region 18 are aligned in FIG. 2 is, for example, 0.5 μm or more and 1 μm or less. This direction corresponds to the short width direction of the semiconductor portion 30 in plan view. Therefore, the short width W of the semiconductor portion 30 is, for example, 0.5 μm or more and 1 μm or less.

[0026] From the viewpoint of exerting a good resurf effect, the difference between the depth of the semiconductor portion 30 and the depth of the drift region 19 is, for example, 10% or less. The semiconductor portion 30 is fixed to, for example, the potential of the semiconductor substrate 11. The impurity concentration of the semiconductor portion 30 is higher than the impurity concentration of the semiconductor substrate 11, and is, for example, 1.0×10 15 cm -3 Above 1.0×10 18 cm-3 In order to satisfactorily exert the RESURF effect, the difference between the impurity concentration of the semiconductor portion 30 and the impurity concentration of the drift region 19 is, for example, 10% or less.

[0027] Next, an example of a method for manufacturing a semiconductor device according to this embodiment will be described with reference to Figures 3A to 3D. Each of Figures 3A to 3D is a schematic cross-sectional view for explaining a part of the method for manufacturing a semiconductor device according to this embodiment. Below, an example of a method for manufacturing a transistor region 10 according to this embodiment will be described with reference to Figures 3A to 3D.

[0028] First, as shown in FIG. 3A, a groove G1 is formed in a semiconductor substrate 11 having a first conductivity type, and then an insulating layer 12 is embedded in the groove G1 (first step). In the first step, the groove G1 having a desired planar shape is formed in the semiconductor substrate 11, for example, by dry etching using a mask (not shown). Then, an insulator is embedded in the groove G1 by a CVD method or the like. This forms the insulating layer 12 embedded in the groove G1. The insulator provided outside the groove G1 is removed, for example, by CMP (chemical mechanical polishing), wet etching, or the like.

[0029] 3B, an impurity region IR1 having a first conductivity type and an impurity region IR2 having a second conductivity type are formed in the semiconductor substrate 11 (second step). In the second step, for example, the impurity region IR1 is formed in a part of the semiconductor substrate 11 by ion implantation using a mask not shown, and then the impurity region IR2 is formed in another part of the semiconductor substrate 11 by ion implantation using a mask different from the above mask. In the second step, the impurity region IR2 may be formed in one part of the semiconductor substrate 11, and then the impurity region IR1 may be formed in another part of the semiconductor substrate 11. The impurity concentration of each of the impurity regions IR1 and IR2 is higher than the impurity concentration of the semiconductor substrate 11, and may be, for example, 1.0×10 18 cm -3 Above 1.0×10 21 cm -33B and subsequent figures, a part of the impurity region IR2 is referred to as a first impurity region IR2a, and another part of the impurity region IR2 is referred to as a second impurity region IR2b.

[0030] Next, as shown in FIG. 3C, a groove G2 is formed in a region adjacent to the impurity region IR2 in the semiconductor substrate 11, and then a semiconductor portion 30 having a first conductivity type is embedded in the groove G2 (third step). In the third step, the groove G2 is formed in the semiconductor substrate 11 by, for example, dry etching using a mask not shown. In this embodiment, a region surrounded by the impurity region IR2 in the semiconductor substrate 11 in a planar view is thinned by etching or the like. Then, impurities and semiconductor are embedded in the groove G2 by a CVD method or the like. This forms the semiconductor portion 30 that is embedded in the groove G2 and adjacent to the impurity region IR2. In this embodiment, the semiconductor portion 30 surrounded by the impurity region IR2 in a planar view is formed. In FIG. 3C, the short width W of the semiconductor portion 30, which corresponds to the interval between the first impurity region IR2a and the second impurity region IR2b, is, for example, about 0.5 μm to 1 μm.

[0031] Next, as shown in FIG. 3D, a mask M is formed to cover at least a part of the impurity region IR2 and the semiconductor portion 30, and then the part of the semiconductor substrate 11 exposed from the mask M is thinned by etching (fourth step). In the fourth step, first, a mask M is formed on the semiconductor substrate 11. The mask M may be a resist mask or a silicon oxide film. In this embodiment, a mask M is formed to cover the entire insulating layer 12, the entire semiconductor portion 30, and a part of the impurity region IR2. The part of the impurity region IR2 includes at least a part of the impurity region IR2 adjacent to the semiconductor portion 30. On the other hand, the impurity region IR1 in the semiconductor portion 30 is exposed from the mask M. Next, the part of the semiconductor substrate 11 not covered by the mask M is thinned by etching using the mask M. As a result, the entire impurity region IR1 and a part of the impurity region IR2 are thinned to form the body region 17 and the drift region 19, respectively, and the first substrate portion 11a and the second substrate portion 11b of the semiconductor substrate 11 are formed. In this embodiment, the thickness of the portion of the semiconductor substrate 11 exposed from the mask M may be greater the closer to the mask M. In this way, the second region 18b of the contact region 18 and the like are formed.

[0032] Next, the transistor T shown in FIG. 2 is manufactured through the steps described below. As a specific example, first, the mask M is removed, and then ion implantation is performed multiple times. As a result, the source region 13 and the contact region 18 are formed in the body region 17, and the drain region 14 is formed in the drift region 19. The contact region 18 may be formed after the source region 13 and the drain region 14 are formed, or the source region 13 and the drain region 14 may be formed after the contact region 18 is formed. Next, after forming the gate insulating layer 15 on the semiconductor substrate 11, the gate electrode 16 is formed on the thinned first substrate portion 11a of the semiconductor substrate 11 (more specifically, on the gate insulating layer 15 overlapping the first substrate portion 11a). For example, the gate insulating layer 15 is formed by oxidizing the exposed surface of the semiconductor substrate 11. Then, the gate electrode 16 is formed by patterning, for example, a polycrystalline silicon layer formed on the gate insulating layer 15. The transistor T is formed in the above manner. After the transistor T is formed, wiring and the like may be appropriately formed on the transistor T. The ion implantation may be performed after the formation of the gate insulating layer 15 and the gate electrode 16. In other words, in forming the transistor T, the source region 13, the drain region 14, and the contact region 18 may be formed after the gate insulating layer 15 and the gate electrode 16 are formed.

[0033] The effects and advantages achieved by the semiconductor device 1 according to the present embodiment described above will be described with reference to transistors according to the following two reference examples.

[0034] The transistor according to the first reference example has a configuration similar to that of the transistor T, except that the groove G2 and the semiconductor portion 30 are not provided. That is, in the transistor according to the first reference example, a part of the semiconductor substrate 11 is located between the first impurity region IR2a and the second impurity region IR2b. Also, the transistor according to the second reference example has a configuration similar to that of the transistor T, except that an impurity region having a first conductivity type is formed in a region of the semiconductor substrate 11 located between the first impurity region IR2a and the second impurity region IR2b. The impurity concentration of the impurity region in the second reference example is higher than the impurity concentration of the semiconductor substrate 11, and is, for example, similar to the impurity concentrations of the first impurity region IR2a and the second impurity region IR2b.

[0035] In the first reference example, from the viewpoint of the impurity concentration of the semiconductor substrate 11 and the spread of the depletion layer, it is necessary to secure a certain size of the region located between the first impurity region IR2a and the second impurity region IR2b in the semiconductor substrate 11. For example, the width of the region corresponding to the distance between the first impurity region IR2a and the second impurity region IR2b needs to be at least 5 μm or more. In addition, in order to form an impurity region having a first conductivity type between the first impurity region IR2a and the second impurity region IR2b in the second reference example, the distance between the first impurity region IR2a and the second impurity region IR2b needs to be at least several μm or more (for example, 3 μm or more).

[0036] In contrast, in the manufacturing method of the semiconductor device 1 according to the present embodiment, a groove G2 is formed between the first impurity region IR2a and the second impurity region IR2b, and a semiconductor portion 30 having a first conductivity type is formed and embedded in the groove G2. In this case, even if the distance between the first impurity region IR2a and the second impurity region IR2b is, for example, 1 μm or less, the semiconductor portion 30 can be formed. Therefore, in this embodiment, the transistor T can be made smaller than the first and second reference examples. In addition, in this embodiment, the surface 30a of the semiconductor portion 30 and a part of the second region 19b of the drift region 19 are located above the surface 11c of the first substrate portion 11a of the semiconductor substrate 11. This allows the drift region 19 and the semiconductor portion 30 to protrude upward from the surface 11c. In this case, compared to when the surface of the semiconductor substrate is simply a smooth surface, the area where the drift region 19 and the semiconductor portion 30 contact each other can be made larger, and the resurf effect can be more effectively exhibited. Therefore, the withstand voltage of the transistor T can be ensured.

[0037] In one example, the entire drift region 19 and the drain region 14 having the second conductivity type and located on the second region 19b of the drift region 19 are provided in the semiconductor substrate 11. In this case, the length of the current path between the source region 13 and the drain region 14 can be made longer than when the surface of the semiconductor substrate is simply a smooth surface, thereby improving the breakdown voltage of the transistor T.

[0038] In one example, the difference between the depth of the drift region 19 and the depth of the semiconductor portion 30 is 10% or less. In this case, the balance of charges between the drift region 19 and the semiconductor portion 30 is less likely to be lost, so that the RESURF effect can be stably exerted.

[0039] In one example, the impurity concentration of the semiconductor portion 30 and the impurity concentration of the drift region 19 are higher than the impurity concentration of the semiconductor substrate 11. In this case, the RESURF effect can be stably exhibited.

[0040] In one example, the difference between the impurity concentration of the semiconductor portion 30 and the impurity concentration of the drift region 19 is 10% or less. In this case, the charge balance between the drift region 19 and the semiconductor portion 30 is less likely to be lost, so that the RESURF effect can be stably exerted.

[0041] In one example, the short width W of the semiconductor portion 30 in a plan view is 0.5 μm or more and 1 μm or less. Even in this case, the semiconductor portion 30 can be formed well, so that the semiconductor device 1 can be provided that can be miniaturized while ensuring the withstand voltage.

[0042] In the following, modified examples of the above-described embodiment will be described. In the description of the modified examples, descriptions that overlap with the above-described embodiment will be omitted, and differences will be described. In other words, to the extent technically possible, the description of the above-described embodiment may be used appropriately in the modified examples.

[0043] FIG. 4 is an enlarged cross-sectional view of a main part of a semiconductor device according to a modified example of the embodiment. As shown in FIG. 4, the transistor region 10A according to the modified example is different from the transistor region 10 of the embodiment in that it mainly includes a semiconductor substrate 11 and semiconductor layers 41 and 42. Each of the semiconductor layers 41 and 42 is formed, for example, by removing a part of an epitaxial semiconductor layer grown on the semiconductor substrate 11. The semiconductor layer 41 constitutes the second region 19b of the drift region 19A and has a second conductivity type. Therefore, in this modified example, the drift region 19A is provided in the semiconductor substrate 11 and the semiconductor layer 41. The semiconductor portion 30A is embedded in the groove G2 provided in the semiconductor substrate 11 and the opening 41a provided in the semiconductor layer 41 and overlapping with the groove G2. Therefore, the semiconductor portion 30A contacts not only the semiconductor substrate 11 but also the semiconductor layer 41. In this modified example, the surface 30a of the semiconductor portion 30 and the top surface 41b of the semiconductor layer 41 are continuously connected to each other, but this is not limited thereto. The top surface 41b of the semiconductor layer 41 is a portion (first portion) located above the surface 11c of the semiconductor substrate 11. The semiconductor layer 42 forms the second region 18b of the contact region 18, and has the first conductivity type.

[0044] In the element isolation region EIR of this modification, a groove G1A is formed in the semiconductor substrate 11 and the semiconductor layer 42, and an insulating layer 12A is embedded in the groove G1A.

[0045] Next, an example of a method for manufacturing a semiconductor device according to this modification will be described with reference to Figures 5A to 5E. Each of Figures 5A to 5E is a schematic cross-sectional view for explaining a part of the method for manufacturing a semiconductor device according to this modification. Hereinafter, an example of a method for manufacturing a transistor region 10A according to this modification will be described with reference to Figures 5A to 5E.

[0046] 5A, an impurity region IR2 having a second conductivity type is formed in a semiconductor substrate 11 (step 1A). In step 1A, the impurity region IR2 is formed in a part of the semiconductor substrate 11 by, for example, ion implantation using a mask (not shown).

[0047] 5B, a semiconductor layer 40 having a second conductivity type is formed on the semiconductor substrate 11 (step 2A). In step 2A, the semiconductor layer 40 is formed on the surface of the semiconductor substrate 11 by, for example, an epitaxial growth method. The thickness of the semiconductor layer 40 is, for example, 200 nm or more and 400 nm or less.

[0048] 5C, a groove G1A is formed in the semiconductor substrate 11 and the semiconductor layer 40, and then an insulating layer 12A is embedded in the groove G1A (step 3A). In step 3A, the groove G1A and the insulating layer 12A are formed in the same manner as in step 1 of the above embodiment, except that a mask (not shown) is formed on the semiconductor layer 40 and that a part of the semiconductor layer 40 in addition to the semiconductor substrate 11 is etched.

[0049] Next, as shown in FIG. 5D, a groove G2A is formed in a region adjacent to the impurity region IR2 in the semiconductor substrate 11, and an opening 40a is formed in a portion of the semiconductor layer 40 overlapping the groove G2 (step 4A). In step 4A, for example, the opening 40a is formed in the semiconductor layer 40 and the groove G2 is formed in the semiconductor substrate 11 by dry etching using a mask (not shown) provided on the semiconductor layer 40. Then, impurities and semiconductor are embedded in the groove G2 and the opening 40a by CVD or the like. This forms a semiconductor portion 30A that is embedded in the groove G2 and adjacent to the impurity region IR2 and the semiconductor layer 40. The short width of the semiconductor portion 30A is approximately the same as the short width W of the semiconductor portion 30 in the above embodiment.

[0050] 5E, a mask M2 is formed to cover at least a part of the semiconductor layer 40 that overlaps with the impurity region IR2, and then the part of the semiconductor layer 40 that is not covered by the mask M2 is removed (step 5A). In step 5A, first, a mask M2 is formed on the semiconductor layer 40 and the insulating layer 12. The shape of the mask M2 is, for example, the same as the shape of the mask M in the above embodiment. Then, the part of the semiconductor layer 40 that is not covered by the mask M2 is removed or thinned by etching using the mask M2. This forms the semiconductor layers 41 and 42 and also forms the drift region 19A.

[0051] Next, the transistor region 10A shown in FIG. 4 is manufactured through the steps described below. As a specific example, first, the mask M is removed, and then ion implantation is performed multiple times to form the source region 13 and the body region 17 in the semiconductor substrate 11, the contact region 18 in the semiconductor substrate 11 and the semiconductor layer 42, and the drain region 14 in the drift region 19A. In this modification, the order of forming the source region 13, the drain region 14, the body region 17, and the contact region 18 is not particularly limited. Then, as in the above embodiment, the gate insulating layer 15 and the gate electrode 16 are formed in order to form the transistor region 10A. In this modification, the gate electrode 16 is formed on a portion of the semiconductor substrate 11 exposed from the semiconductor layer 40. In other words, the gate electrode 16 is formed on a portion of the semiconductor substrate 11 that does not overlap the semiconductor layers 41 and 42.

[0052] The above-described modified example also provides the same advantageous effects as those of the above-described embodiment.

[0053] In the above embodiment and the above modified example, the semiconductor device can be applied to a power module used in an inverter circuit that drives an electric motor used as a power source for, for example, automobiles (including electric automobiles), trains, industrial robots, air conditioners, air compressors, electric fans, vacuum cleaners, dryers, refrigerators, etc. The semiconductor device can also be applied to a power module used in an inverter circuit for solar cells, wind power generators, and other power generation devices, etc. Alternatively, the semiconductor device can be applied to a circuit module that constitutes an analog control power supply, a digital control power supply, etc.

[0054] Although the embodiments and variants relating to one aspect of the present disclosure have been described in detail above, these are merely specific examples used to clarify the technical content of the present disclosure, and the present disclosure should not be interpreted as being limited to these specific examples, and the scope of the present disclosure is limited only by the appended claims.

[0055] Below, examples of features extracted from the description of this specification and the drawings are presented.

[0056] [A1] a semiconductor substrate having a first conductivity type; a gate electrode located on the semiconductor substrate; a semiconductor portion embedded in the semiconductor substrate and having the first conductivity type; the semiconductor substrate is provided with at least a portion of a drift region adjacent to the semiconductor portion and having a second conductivity type; a surface of the semiconductor portion and a first portion included in a surface of the drift region are located above a second portion located below the gate electrode on the surface of the semiconductor substrate; Semiconductor device.

[0057] [A2] The semiconductor device according to [A1], wherein the semiconductor substrate is provided with the entire drift region and a drain region located on the first portion and having the second conductivity type.

[0058] [A3] a semiconductor layer located on the semiconductor substrate and having the second conductivity type; the drift region is provided in the semiconductor substrate and the semiconductor layer, The semiconductor device according to [A1], wherein a surface of the semiconductor layer corresponds to the first portion.

[0059] [A4] The semiconductor device according to [A3], wherein the semiconductor portion is embedded in an opening in the semiconductor layer.

[0060] [A5] The semiconductor device according to any one of [A1] to [A4], wherein a difference between a depth of the drift region and a depth of the semiconductor portion is 10% or less.

[0061] [A6] The semiconductor device according to any one of [A1] to [A5], wherein an impurity concentration of the semiconductor portion and an impurity concentration of the drift region are higher than an impurity concentration of the semiconductor substrate.

[0062] [A7] The semiconductor device according to any one of [A1] to [A6], wherein a difference between an impurity concentration of the semiconductor portion and an impurity concentration of the drift region is 10% or less.

[0063] [A8] The semiconductor device according to any one of [A1] to [A7], wherein the semiconductor portion is grounded.

[0064] [A9] The semiconductor device according to any one of [A1] to [A8], wherein the short width of the semiconductor portion in a plan view is not less than 0.5 μm and not more than 1 μm.

[0065] [A10] forming an impurity region having a second conductivity type in a semiconductor substrate having a first conductivity type; forming a trench in a region of the semiconductor substrate adjacent to the impurity region; embedding a semiconductor portion having the first conductivity type in the trench; forming a mask covering at least a portion of the impurity region and the semiconductor portion; thinning the semiconductor substrate by etching a portion exposed under the mask; forming a gate electrode on the thinned portion of the semiconductor substrate; The impurity region corresponds to a drift region of a transistor including the gate electrode.

[0066] [A11] forming an impurity region having a second conductivity type in a semiconductor substrate having a first conductivity type; forming a semiconductor layer having the second conductivity type on the semiconductor substrate; forming a trench in a region of the semiconductor substrate adjacent to the impurity region and forming an opening in the semiconductor layer overlapping the trench; embedding a semiconductor portion having the first conductivity type in the groove and the opening; forming a mask covering at least a portion of the semiconductor layer that overlaps with the impurity region; removing a portion of the semiconductor layer exposed under the mask; forming a gate electrode on a portion of the semiconductor substrate exposed from the semiconductor layer; The impurity region corresponds to a drift region of a transistor including the gate electrode.

[0067] [A12] The method for manufacturing a semiconductor device according to [A10] or [A11], wherein a difference between a depth of the drift region and a depth of the semiconductor portion is 10% or less.

[0068] [A13] The method for manufacturing a semiconductor device according to any one of [A10] to [A12], wherein an impurity concentration of the semiconductor portion and an impurity concentration of the drift region are higher than an impurity concentration of the semiconductor substrate.

[0069] [A14] The method for manufacturing a semiconductor device according to any one of [A10] to [A13], wherein a difference between an impurity concentration of the semiconductor portion and an impurity concentration of the drift region is 10% or less.

[0070] [A15] The method for manufacturing a semiconductor device according to any one of [A10] to [A14], wherein the short width of the semiconductor portion in a plan view is 0.5 μm or more and 1 μm or less. [Explanation of symbols]

[0071] 1...semiconductor device, 2...chip, 2a...surface, 3...driver circuit, 4...pre-driver circuit, 5...analog circuit, 6...power supply circuit, 7...logic circuit, 8...input / output circuit, 10, 10A...transistor region, 11...semiconductor substrate, 11a...first substrate portion, 11b...second substrate portion, 11c...surface, 11d...surface, 12, 12A...insulating layer, 13...source region, 14...drain region, 15...gate insulating layer, 16...gate electrode, 17...body region, 18...contact region, 18a...first region area, 18b...second region, 19,19A...drift region, 19a...first region, 19b...second region, 20...channel region, 30,30A...semiconductor portion, 30a...surface, 40,41,42...semiconductor layer, 40a...opening, 41a...opening, 41b... Top surface, AR...active region, EIR...element isolation region, G1, G1A...trench, G2...trench, IR1...impurity region, IR2...impurity region, IR2a...first impurity region, IR2b...second impurity region, M, M2...mask, T...transistor, W...short width.

Claims

1. a semiconductor substrate having a first conductivity type; a gate electrode located on the semiconductor substrate; a semiconductor portion embedded in the semiconductor substrate and having the first conductivity type; the semiconductor substrate is provided with at least a portion of a drift region adjacent to the semiconductor portion and having a second conductivity type; a surface of the semiconductor portion and a first portion included in a surface of the drift region are located above a second portion located below the gate electrode on the surface of the semiconductor substrate; Semiconductor device.

2. The semiconductor device according to claim 1 , wherein the semiconductor substrate is provided with the entire drift region and a drain region located on the first portion and having the second conductivity type.

3. a semiconductor layer located on the semiconductor substrate and having the second conductivity type; the drift region is provided in the semiconductor substrate and the semiconductor layer, The semiconductor device according to claim 1 , wherein the surface of the semiconductor layer corresponds to the first portion.

4. The semiconductor device according to claim 3 , wherein the semiconductor portion is embedded in an opening in the semiconductor layer.

5. 5. The semiconductor device according to claim 1, wherein a difference between a depth of said drift region and a depth of said semiconductor portion is 10% or less.

6. 5. The semiconductor device according to claim 1, wherein an impurity concentration of said semiconductor portion and an impurity concentration of said drift region are higher than an impurity concentration of said semiconductor substrate.

7. 5. The semiconductor device according to claim 1, wherein a difference between an impurity concentration of said semiconductor portion and an impurity concentration of said drift region is 10% or less.

8. 5. The semiconductor device according to claim 1, wherein the semiconductor portion is grounded.

9. 5. The semiconductor device according to claim 1, wherein a width of the semiconductor portion in a plan view is 0.5 μm or more and 1 μm or less.

10. forming an impurity region having a second conductivity type in a semiconductor substrate having a first conductivity type; forming a trench in a region of the semiconductor substrate adjacent to the impurity region; embedding a semiconductor portion having the first conductivity type in the trench; forming a mask covering at least a portion of the impurity region and the semiconductor portion; thinning the semiconductor substrate by etching a portion exposed under the mask; forming a gate electrode on the thinned portion of the semiconductor substrate; The impurity region corresponds to a drift region of a transistor including the gate electrode.

11. forming an impurity region having a second conductivity type in a semiconductor substrate having a first conductivity type; forming a semiconductor layer having the second conductivity type on the semiconductor substrate; forming a trench in a region of the semiconductor substrate adjacent to the impurity region and forming an opening in the semiconductor layer overlapping the trench; embedding a semiconductor portion having the first conductivity type in the groove and the opening; forming a mask covering at least a portion of the semiconductor layer that overlaps with the impurity region; removing a portion of the semiconductor layer exposed under the mask; forming a gate electrode on a portion of the semiconductor substrate exposed from the semiconductor layer; The impurity region corresponds to a drift region of a transistor including the gate electrode.

12. 12. The method for manufacturing a semiconductor device according to claim 10, wherein a difference between a depth of the drift region and a depth of the semiconductor portion is 10% or less.

13. 12. The method for manufacturing a semiconductor device according to claim 10, wherein an impurity concentration of the semiconductor portion and an impurity concentration of the drift region are higher than an impurity concentration of the semiconductor substrate.

14. 12. The method for manufacturing a semiconductor device according to claim 10, wherein a difference between an impurity concentration of the semiconductor portion and an impurity concentration of the drift region is 10% or less.

15. The method for manufacturing a semiconductor device according to claim 10 or 11, wherein a short width of the semiconductor portion in a plan view is not less than 0.5 μm and not more than 1 μm.

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