Semiconductor device

Abstract

To provide a semiconductor device that integrates an IC chip and passive components such as coils, etc., and can appropriately dissipate heat from the IC chip and from the passive components, thereby contributing to downsizing of the device.SOLUTION: It is configured to direct the heat generated by a coil 15 to a motherboard II via first land 3, first via hole 5, second land 4, third land 6, second via hole 12, and sixth land 9 and to direct the heat generated by an IC chip 16 to the motherboard II via IMC 17, fifth land, fourth via hole, and eighth land.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device, and is particularly useful when applied to a semiconductor device integrally equipped with passive elements such as coils. [Background technology]

[0002] For example, a coil-integrated semiconductor element has been proposed, which is a passive element that is integrated with an IC chip. In addition, WL CSP (Wafer level Chip Size Package) has been proposed as a technology to realize miniaturization of semiconductor devices. This CSP is a type of package format for semiconductor components, and is the smallest semiconductor package possible, with no internal wiring using bonding wires and with part of the semiconductor exposed. It has the advantage of being able to occupy a small area when mounting a single highly integrated semiconductor on the surface of a printed circuit board.

[0003] 11 is a schematic diagram showing a vertical cross section of an example of a WL CSP according to the prior art. As shown in the figure, in this semiconductor device (WL CSP), a chip 01, which is an IC circuit molded with a specified built-in electronic circuit, is joined to lands 04 formed on the surface of a mounting substrate 05 by solder balls 03 via copper wiring 02 exposed to the outside on its bottom surface. Thus, electrical continuity between the chip 01 and the mounting substrate 05 is ensured.

[0004] In the semiconductor device according to the above-mentioned conventional technology, heat generated in the chip 01 is transferred to the mounting substrate 05 via the copper wiring 02, the solder balls 03, and the lands 04, and is mainly dissipated to the surroundings by the mounting substrate 05. Thus, in the semiconductor device, the heat generated in the chip 01 has only one heat transfer path 06 (indicated by a thick arrow in the figure) that passes through the copper wiring 02, the solder balls 03, and the lands 04 to the mounting substrate 05. For this reason, the only way to improve the efficiency of heat dissipation is to increase the heat dissipation area, for example by increasing the number of joints between the copper wiring 02 and the solder balls 03. This is an obstacle to further miniaturization of the semiconductor device.

[0005] On the other hand, a coil-integrated DC-DC converter has also been proposed, which integrates a coil, which is a passive component, with an electronic circuit formed by an IC chip such as a DC-DC converter.

[0006] In such a DC-DC converter with an integrated coil, in addition to the IC chip, the coil, which is a passive element, also generates heat and radiates heat, so finding a way to efficiently dissipate heat from these two heat sources is essential to miniaturizing this type of semiconductor device.

[0007] Although the same problems as those described above remain, Patent Document 1 is a known document disclosing a semiconductor device that is a WL CSP, and Patent Document 2 is a known document disclosing a coil-integrated DC-DC converter. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] JP 2020-10016 A [Patent Document 2] Utility Model Registration No. 3147172 Summary of the Invention [Problem to be solved by the invention]

[0009] In view of the above-mentioned conventional technology, the present invention aims to provide a semiconductor device that integrates an IC chip that constitutes the main part of an electronic circuit with passive components such as coils, and that can appropriately dissipate heat from the IC chip and the passive elements, thereby contributing to the miniaturization of the device. [Means for solving the problem]

[0010] The first aspect of the present invention for achieving the above object is as follows: The package substrate has a PKG substrate formed by stacking a first package substrate made of a flat insulator and having a recessed space formed from the bottom surface of the center of the first package substrate and a second package substrate made of the same insulator; A first land formed on the upper surface of the first PKG substrate and a second land formed on the lower surface of the first PKG substrate are connected to each other through a first via hole, a third land formed on the upper surface of the second PKG substrate and a sixth land formed on the lower surface of the second PKG substrate are connected to each other through a second via hole; a fourth land formed on the upper surface of the second PKG substrate and a seventh land formed on the lower surface of the second PKG substrate are connected to each other through a third via hole; a fourth via hole is formed between a fifth land formed on the upper surface of the second PKG substrate and an eighth land formed on the lower surface of the second PKG substrate; Furthermore, a passive element is mounted on the first land via an electrode, a thermal conductive member having a flat portion and a leg portion extending downward from an end of the flat portion toward the fifth land and having a recess portion opening to the lower surface side is placed in the recess portion of the first PKG substrate; an upper surface of an IC chip is bonded to a lower surface of the flat portion, and the IC chip is connected to the fourth land via an electrode disposed on the lower surface; The heat generated in the passive element is conducted to a motherboard via the first land, the first via hole, the second land, the third land, the second via hole, and the sixth land, The heat generated by the IC chip is configured to pass from the flat portion of the thermal conductive member through the legs to the fifth land, and then be conducted to the motherboard through the fourth via hole and the eighth land.

[0011] A second aspect of the present invention is The package substrate has a PKG substrate formed by stacking a first package substrate made of a flat insulator and having a recessed space formed from the bottom surface of the center of the first package substrate and a second package substrate made of the same insulator; a first land formed on the upper surface of the first PKG substrate and a second land formed on the lower surface of the first PKG substrate are connected to each other through a first via hole; a third land formed from a bottom of the recess of the first PKG substrate to the inside of the first PKG substrate and a fourth land formed on the lower surface of the first PKG substrate are connected to each other through a second via hole; a third via hole is formed between a fifth land formed on the upper surface of the second PKG substrate and a sixth land formed on the lower surface of the second PKG substrate; a seventh land formed on the upper surface of the second PKG substrate and an eighth land formed on the lower surface of the second PKG substrate are connected to each other through a fourth via hole; a ninth land formed on the upper surface of the second PKG substrate and a tenth land formed on the lower surface of the second PKG substrate are connected to each other through a fifth via hole; Furthermore, a passive element is mounted on the first land via an electrode, an upper surface of a flat heat conductive member is joined to a lower surface of the third land inside the first recess; an upper surface of an IC chip is joined to a lower surface of the thermal conductive member, and the IC chip is connected to the seventh land via an electrode disposed on the lower surface; The heat generated in the passive element is conducted to a motherboard via the first land, the first via hole, the second land, the fifth land, the third via hole, and the sixth land, The heat generated in the IC chip is configured to pass from the thermal conductive member to the third land, through the second via hole to the fourth land, further through the ninth land to the fifth via hole, and then to be conducted to the motherboard via the tenth land.

[0012] A third aspect of the present invention is In the semiconductor device according to the second aspect, The first via holes formed at the ends of the first lands arranged opposite each other in the plane of the first PKG substrate and the second via holes formed at the ends of the third lands are formed so as to be located diagonally opposite each other at the four corners of the first PKG substrate when viewed in a plane.

[0013] A fourth aspect of the present invention is In the semiconductor device according to any one of the first to third aspects, The first land to which the electrode of the passive element is joined is characterized in that it has a positive electrode formed by arranging multiple linear conductive members in parallel and shorting both ends of each conductive member, and a negative electrode formed in the same manner as the positive electrode and arranged opposite the positive electrode. Effect of the Invention

[0014] According to the present invention, the heat generated in the IC chip and the heat generated in the passive components can be guided to the motherboard on which the semiconductor device is mounted via two separate heat dissipation paths, which allows the heat generated in the IC chip and the heat generated in the passive components to be efficiently dissipated, contributing to the miniaturization of the semiconductor device. [Brief description of the drawings]

[0015] [Figure 1] FIG. 4 is a diagram showing the semiconductor device according to the first embodiment of the present invention, and is a schematic diagram showing a state cut along line AA in FIG. 3 with each portion disassembled. [Diagram 2] FIG. 5 is a diagram showing the semiconductor device according to the first embodiment of the present invention, and is a schematic diagram showing a state cut along line BB in FIG. 4 with each portion disassembled. [Diagram 3] 1 is a schematic diagram showing a semiconductor device according to a first embodiment of the present invention as viewed from above; [Figure 4] 1 is a schematic diagram showing a semiconductor device according to a first embodiment of the present invention as viewed from the back surface. [Diagram 5]FIG. 8 is a diagram showing a semiconductor device according to a second embodiment of the present invention, and is a schematic diagram showing a state cut along line CC in FIG. 7 with each portion disassembled. [Figure 6] FIG. 9 is a diagram showing a semiconductor device according to a second embodiment of the present invention, and is a schematic diagram showing a state cut along line DD in FIG. 8 with each component disassembled. [Figure 7] FIG. 11 is a schematic diagram showing a semiconductor device according to a second embodiment of the present invention as viewed from above. [Figure 8] FIG. 11 is a schematic diagram showing a semiconductor device according to a second embodiment of the present invention as viewed from the back surface. [Figure 9] FIG. 13 is a schematic diagram showing the relationship between a coil and electrodes in a third embodiment of the present invention. [Figure 10] FIG. 2 is a schematic diagram showing the relationship between a coil and electrodes in the first embodiment of the present invention. [Figure 11] FIG. 1 is a schematic diagram showing a vertical cross section of an example of a WL CSP according to a conventional technique. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

[0017] <First embodiment> Figures 1 to 4 show a semiconductor device according to a first embodiment of the present invention, where Figure 1 is a schematic diagram showing a state cut along line AA in Figure 3 with each part disassembled, Figure 2 is a schematic diagram showing a state cut along line BB in Figure 4 with each part disassembled, Figure 3 is a schematic diagram showing the state as viewed from above, and Figure 4 is a schematic diagram showing the state as viewed from the back.

[0018] As shown in Figures 1 to 4, a semiconductor device A according to this embodiment has a PKG substrate I formed by stacking a first package (PKG) substrate 1 on an upper layer and a second package (PKG) substrate 2 on a lower layer. Here, the first PKG substrate 1 is made of a flat insulator (e.g., epoxy resin) and has a recess 1A, which is a space formed from the lower surface side of the center. The second PKG substrate 2 is made of a similar insulator.

[0019] A first land 3 is formed on the upper surface of the first PKG substrate 1, and a second land 4 is formed on the lower surface of the first PKG substrate 1. The first land 3 and the second land 4 are connected to each other by a first via hole 5.

[0020] 1, a third land 6 is formed on the upper surface of the second PKG substrate 2, and a sixth land 9 is formed on the lower surface, with the third land 6 and the sixth land 9 communicating with each other through a second via hole 12. At the same time, a fifth land 8 is formed on the upper surface of the second PKG substrate 2, and an eighth land 11 is formed on the lower surface, with the fifth land 8 and the eighth land 11 communicating with each other through a fourth via hole 14. Furthermore, a fourth land 7 is formed on the upper surface of the second PKG substrate 2, and a seventh land 10 is formed on the lower surface, with the two communicating with each other through a third via hole 13.

[0021] A coil 15, which is a passive element, is mounted via an electrode 15A on the first land 3 of the first PKG substrate 1. Also, an IMC 17, which is a thermally conductive material, is housed in the recess 1A of the first PKG substrate 1. Here, IMC (Inter Metallic Compound) is a material based on Sn-Cu, manufactured by a manufacturing technique called the nanomize method, and is useful as a bonding agent with good electrical conductivity and a uniform, homogeneous fine grain structure.

[0022] In this embodiment, the IMC 17 is a member having a flat portion 17A, a leg portion 17B extending vertically downward from the end of the flat portion 17A, and a recess 17C that opens to the bottom side, and the upper surface of the flat portion 17A is joined to the bottom surface of the recess 1A of the first PKG substrate 1 via a joining land 18.

[0023] An IC chip 16 having an IC circuit molded therein, for example a DC-DC converter, has its upper surface fixed to the lower surface of flat portion 17A of IMC 17 and is connected to fourth land 7 via electrode 16A arranged on the lower surface.

[0024] In this embodiment, an electric path is formed that is connected from electrode 15A of coil 15, which is a passive element, to a predetermined circuit formed on motherboard II via first land 3, first via hole 5, second land 4, third land 6, second via hole 12, and fourth land 9. Heat generated in coil 15 is conducted to motherboard II via the same heat dissipation path as the electric path, i.e., first land 3, first via hole 5, second land 4, third land 6, second via hole 12, and sixth land 9, and dissipated via motherboard II, which has a large heat capacity.

[0025] From the electrode 16A of the IC chip 16, the fourth land 7, the third via hole 13, An electric path is formed that is connected to a predetermined circuit formed on the motherboard II via the seventh land 10. Heat generated by the IC chip 16 travels from the flat portion 17A of the IMC 17 through the leg portion 17B to the fifth land 8, and is conducted to the motherboard II via the fourth via hole 14 and the eighth land 11, and is dissipated via the motherboard II that has a large thermal capacity.

[0026] In this embodiment, the electrode 15A is joined to the first land 3 via IMC 19, the electrode 16A is joined to the fourth land 7 via IMC 20, and the second land 4 is joined to the third land 6 via IMC 21, and the space between the electrode 16A of the IC chip 16 and the fourth land 7 is filled with underfill material 22.

[0027] <Second embodiment> Figures 5 to 8 are diagrams showing a semiconductor device according to a second embodiment of the present invention, where Figure 5 is a schematic diagram showing the state cut along line CC in Figure 7 with each part disassembled, Figure 6 is a schematic diagram showing the state cut along line DD in Figure 8 with each component disassembled, Figure 7 is a schematic diagram showing the state as viewed from above, and Figure 8 is a schematic diagram showing the state as viewed from the back.

[0028] 5 to 8, the semiconductor device B according to this embodiment has a PKG substrate III formed by stacking a first package (PKG) substrate 31 on an upper layer and a second package (PKG) substrate 32 on a lower layer. Here, the first PKG substrate 31 is made of a flat insulator (e.g., epoxy resin) and has a recess 31A, which is a space formed from the lower surface side of the center. The second PKG substrate 32 is made of a similar insulator.

[0029] A first land 33 is formed on the upper surface of the first PKG substrate 31, and a second land 34 is formed on the lower surface, and the two are connected by a first via hole 35. A third land 36 is formed in the recess 31A of the first PKG substrate 31 so as to extend horizontally from the bottom thereof to reach the inside of the first PKG substrate 31, and a second via hole 38 connects the third land 36 to a fourth land 37 formed on the lower surface of the first PKG substrate 31.

[0030] 5, a fifth land 39 is formed on the upper surface of the second PKG substrate 32, and a sixth land 40 is formed on the lower surface thereof, with the two being connected to each other by a third via hole 41. At the same time, as shown in FIG. 6, a ninth land 45 is formed on the upper surface of the second PKG substrate 32, and a tenth land 46 is formed on the lower surface thereof, with the two being connected to each other by a fifth via hole 47.

[0031] A coil 15, which is a passive element, is mounted on the first land 33 of the first PKG substrate 31 via an electrode 15A. A flat IMC 48, which is a good thermal conductive member, is housed in the recess 31A of the first PKG substrate 31 with its upper surface bonded to the third land 36. Meanwhile, an IC chip 16 is bonded to the lower surface of the IMC 48 via its upper surface. Furthermore, the IC chip 16 is connected to a seventh land 42 via an electrode 16A, and is connected to a predetermined circuit of the motherboard II via a fourth via hole 44 that communicates with the eighth land 43.

[0032] 7 and 8, in this embodiment, the first via holes 35 formed at the ends of the first lands 33 arranged to face each other in the plane of the first PKG substrate 31 and the second via holes 38 formed at the ends of the third lands 36 are formed to be diagonally positioned relative to each other at the four corners of the first PKG substrate 31 in a plan view, as shown in FIG. 7 and FIG. 8. Although it is not essential to form them to be diagonally positioned in this manner, forming them to be diagonally positioned as in this embodiment has the advantage that the area occupied by the IC chip 16 can be made large.

[0033] In the present embodiment as described above, an electric path is formed that is connected from electrode 15A of coil 15, which is a passive element, to a predetermined circuit formed on motherboard II via first land 33, first via hole 35, second land 34, fifth land 39, second via hole 41, and sixth land 40. At the same time, heat generated in coil 15 is conducted to motherboard II via the same heat dissipation path as the electric path, i.e., first land 33, first via hole 34, second land 34, fifth land 39, second via hole 41, and sixth land 40, and is dissipated via motherboard II, which has a large thermal capacity.

[0034] On the other hand, the electrodes 16A of the IC chip 16 are connected to a predetermined circuit formed on the motherboard II through the seventh land 42, the fourth via hole 44, and the eighth land 43. The heat generated in the IC chip 16 reaches the third land 36 through the IMC 48, is conducted to the motherboard II through the second via hole 38, the fourth land 37, the ninth land 45, the fifth via hole 47, and the tenth land 46, and is dissipated through the motherboard II having a large thermal capacity.

[0035] In this embodiment, the electrode 15A is joined to the first land 33 via IMC 49, the electrode 16A is joined to the seventh land 42 via IMC 50, and the second land 34 is joined to the fifth land 39 via IMC 51, and the space between the electrode 16A of the IC chip 16 and the seventh land 42 is filled with underfill material 52.

[0036] <Third embodiment> As shown in Fig. 9, this embodiment relates to the electrode portion of the coil. As shown in the figure, the land 52 formed on the first PKG substrate 51 for joining the electrodes of the coils 15A and 15B of different sizes is composed of a positive electrode 50A formed by arranging multiple linear conductive members 52A in parallel and shorting both ends of each conductive member 52A, and a negative electrode 50B formed by arranging multiple similar linear conductive members 52B in parallel and shorting both ends of each conductive member 52B.

[0037] If such lands 52 are used, it is possible to flexibly accommodate changes in the size of coils 15A, 15B, as shown in Fig. 9. In other words, one type of land 52 can accommodate mounting of coils 15A, 15B of a plurality of different sizes. On the other hand, as shown in Fig. 10, if lands similar to the conventional lands such as lands 3 and 33 are used, they can only be applied to coils 15 of one size. [Explanation of symbols]

[0038] A, B Semiconductor device I,III PKG board II Motherboard 1, 31 First PKG board 2, 32 Second PKG board 15 Coil 16 IC chip 7, 17 IMC

Claims

1. a PKG substrate formed by laminating a first package substrate made of a flat insulator and having a recessed space formed from the lower surface side of the center portion, and a second package substrate made of the same insulator; a first land formed on the upper surface of the first PKG substrate and a second land formed on the lower surface of the first PKG substrate are connected to each other through a first via hole; a third land formed on the upper surface of the second PKG substrate and a sixth land formed on the lower surface of the second PKG substrate are connected to each other through a second via hole; a fourth land formed on the upper surface of the second PKG substrate and a seventh land formed on the lower surface of the second PKG substrate are connected to each other through a third via hole; a fourth via hole is formed between a fifth land formed on the upper surface of the second PKG substrate and an eighth land formed on the lower surface of the second PKG substrate; Furthermore, a passive element is mounted on the first land via an electrode, a thermal conductive member including a flat portion and a leg portion extending downward from an end of the flat portion toward the fifth land and having a recess portion opening to the lower surface side is housed in the recess portion of the first PKG substrate; an upper surface of an IC chip is bonded to a lower surface of the flat portion, and the IC chip is connected to the fourth land via an electrode disposed on the lower surface; heat generated in the passive element is conducted to a motherboard via the first land, the first via hole, the second land, the third land, the second via hole and the sixth land; A semiconductor device characterized in that heat generated by the IC chip is configured to pass from the flat portion of the thermal conductive member through the leg portion to the fifth land, and then be conducted to the motherboard through the fourth via hole and the eighth land.

2. a PKG substrate formed by laminating a first package substrate made of a flat insulator and having a recessed space formed from the lower surface side of the center portion, and a second package substrate made of the same insulator; a first land formed on the upper surface of the first PKG substrate and a second land formed on the lower surface of the first PKG substrate are connected to each other through a first via hole; a third land formed from a bottom of the recess of the first PKG substrate to the inside of the first PKG substrate and a fourth land formed on a lower surface of the first PKG substrate are connected to each other through a second via hole; a fifth land formed on the upper surface of the second PKG substrate and a sixth land formed on the lower surface of the second PKG substrate are connected to each other through a third via hole; a seventh land formed on the upper surface of the second PKG substrate and an eighth land formed on the lower surface of the second PKG substrate are connected to each other through a fourth via hole; a ninth land formed on the upper surface of the second PKG substrate and a tenth land formed on the lower surface of the second PKG substrate are connected to each other through a fifth via hole; Furthermore, a passive element is mounted on the first land via an electrode, an upper surface of a flat heat conductive member is joined to a lower surface of the third land inside the first recess; an upper surface of an IC chip is joined to a lower surface of the thermal conductive member, and the IC chip is connected to the seventh land via an electrode disposed on the lower surface; heat generated in the passive element is conducted to a motherboard via the first land, the first via hole, the second land, the fifth land, the third via hole and the sixth land; A semiconductor device characterized in that heat generated by the IC chip is configured to travel from the thermal conductive member to the third land, through the second via hole to the fourth land, further through the ninth land to the fifth via hole, and then to the motherboard via the tenth land.

3. 3. The semiconductor device according to claim 2, a first via hole formed at an end of the first land arranged to face each other in a plane of the first PKG substrate, and a second via hole formed at an end of the third land arranged to face each other in a plane of the first PKG substrate, the first via hole formed at an end of the third land being formed to be located diagonally opposite each other at four corners of the first PKG substrate in a planar view.

4. In the semiconductor device according to any one of claims 1 to 3, a first land to which an electrode of the passive element is joined, the first land having a positive electrode formed by arranging a plurality of linear conductive members in parallel and shorting both ends of each conductive member, and a negative electrode formed in the same manner as the positive electrode and disposed opposite the positive electrode.

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