Circuit device and measurement system

Abstract

To provide a circuit device capable of measuring an ohmic value of a measuring object resistor while switching the polarity of applied voltage.SOLUTION: A circuit device 20 comprises: a first terminal TSE and a second terminal TRF respectively connected to one ends a measuring object resistor RSE and a reference resistor RRF; a third terminal TIN connected to the other end of the measuring object resistor, the other end of the reference resistor and one end of a capacitor CA; an oscillation control part 50 controlling CR oscillation based on a detection signal DT according to an input signal IN from the third terminal TIN; a first drive circuit 30 and a second drive circuit 40 that output a first drive signal DS1 and a second drive signal DS2 to be at high level or low level according to the detection signal DT to the first terminal TSE and the second terminal TRF, respectively; and a measurement part 60 that measures an ohmic value of the measuring object resistor based on the detection signal DT.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a circuit device, a measurement system, and the like. [Background technology]

[0002] Conventionally, circuits that measure resistance by using CR oscillation have been known. This circuit is also called an R / F conversion circuit because it converts resistance value into frequency. A circuit device disclosed in Patent Document 1 is known as a conventional technique for such an R / F conversion circuit. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2007-078440 A Summary of the Invention [Problem to be solved by the invention]

[0004] In the circuit device of Patent Document 1, the bias of the terminal connected to the resistor is fixed, so it is not possible to measure the resistance of, for example, an aqueous solution, etc. In this case, if the bias is changed, a problem occurs in that the number of terminals of the circuit device increases. [Means for solving the problem]

[0005] One aspect of the present disclosure relates to a circuit device including a first terminal for connecting to one end of a resistor to be measured, a second terminal for connecting to one end of a reference resistor, a third terminal for connecting to the other end of the resistor to be measured, the other end of the reference resistor, and one end of a capacitor, an oscillation control unit that controls CR oscillation by the resistor to be measured and the capacitor and the CR oscillation by the reference resistor and the capacitor based on a detection signal corresponding to an input signal from the third terminal, a first drive circuit that outputs a first drive signal to the first terminal based on a signal from the oscillation control unit, the first drive signal being at a high level or a low level depending on the detection signal, a second drive circuit that outputs a second drive signal to the second terminal based on a signal from the oscillation control unit, the second drive signal being at a high level or a low level depending on the detection signal, and a measurement unit that measures a resistance value of the resistor to be measured based on the detection signal.

[0006] Another aspect of the present disclosure relates to a measurement system including the above circuit device, the reference resistor, and the capacitor. [Brief description of the drawings]

[0007] [Figure 1] 3 shows an example of the configuration of a circuit device and a measurement system according to the present embodiment. [Diagram 2] 3 shows a specific example of the configuration of the circuit device and the measurement system according to the present embodiment. [Diagram 3] 1 shows an example of a drive circuit configuration. [Figure 4] FIG. 4 is a signal waveform diagram illustrating the operation of the present embodiment. [Diagram 5] 13 is a configuration example of a comparative example in which driving is performed using a DC bias method. [Figure 6] FIG. 11 is a signal waveform diagram illustrating the operation of a comparative example. [Figure 7] 13 is a configuration example of a comparative example in which driving is performed using an AC bias method. [Figure 8] FIG. 13 is an explanatory diagram of a problem in the comparative example. [Figure 9] FIG. 13 is an explanatory diagram of a problem in the comparative example. [Figure 10] FIG. 4 is an explanatory diagram of the circuit device according to the present embodiment during inspection. [Figure 11] 3 shows a detailed configuration example of the circuit device of the present embodiment. [Figure 12] FIG. 4 is a signal waveform diagram illustrating the operation of the present embodiment. [Figure 13] An explanatory diagram of a CR circuit. [Figure 14] An explanatory diagram of charging in a CR circuit. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] The present embodiment will be described below. Note that the present embodiment described below does not unduly limit the contents of the claims. Furthermore, not all of the configurations described in the present embodiment are necessarily essential configurations.

[0009] 1. Circuit device, measuring system 1 shows an example of the configuration of a circuit device 20 according to this embodiment and a measurement system 200 including the circuit device 20. The circuit device 20 realizes R / F conversion that converts a resistance value into a frequency using, for example, CR oscillation.

[0010] As shown in FIG. 1, the circuit device 20 of this embodiment includes a first terminal TSE, a second terminal TRF, a third terminal TIN, a first driving circuit 30, a second driving circuit 40, an oscillation control unit 50, and a measurement unit 60. The circuit device 20 can also include a waveform shaping circuit 70. The measurement system 200 of this embodiment also includes the circuit device 20, a reference resistor RRF, and a capacitor CA. The reference resistor RRF and the capacitor CA are, for example, external components of the circuit device 20. For example, the reference resistor RRF and the capacitor CA are mounted on a circuit board of an electronic device in which the circuit device 20 of this embodiment is incorporated. The circuit device 20 then measures the resistance value of the resistance RSE to be measured. For example, the circuit device 20 measures the resistance value by converting the resistance value of the resistance RSE to be measured into a frequency using CR oscillation. The circuit device 20 is, for example, an IC manufactured by a semiconductor process, and is a semiconductor chip in which circuit elements are formed on a semiconductor substrate. The circuit device 20 can also be said to be a semiconductor device in which a semiconductor chip is mounted in a package. The circuit device 20 and the measurement system 200 are not limited to the configuration shown in FIG. 1, and various modifications are possible, such as omitting some of the components, adding other components, or replacing some of the components with other components.

[0011] The first terminal TSE is a terminal for connecting to one end of the resistance RSE to be measured. The second terminal TRF is a terminal for connecting to one end of the reference resistance RRF. For example, the first terminal TSE is a terminal for connecting the resistance RSE to be measured, and the second terminal TRF is a terminal for connecting the reference resistance RRF. The third terminal TIN is a terminal for connecting to the other end of the resistance RSE to be measured, the other end of the reference resistance RRF, and one end of the capacitor CA. For example, the third terminal TIN is a terminal for connecting the capacitor CA. Specifically, the resistance RSE to be measured has one end connected to the first terminal TSE and the other end connected to the third terminal TIN. The reference resistance RRF has one end connected to the second terminal TRF and the other end connected to the third terminal TIN. The capacitor CA has one end connected to the third terminal TIN. The other end of the capacitor CA is connected to, for example, a VSS node. The VSS node is a power supply node on the low potential side, for example, a ground GND node. For example, a node NC, which is one end of the capacitor CA, is a charging node, and is commonly connected to the other end of the resistance to be measured RSE, the other end of the reference resistor RRF, one end of the capacitor CA, and the third terminal TIN. For example, the measurement system 200 of this embodiment has a first electrode and a second electrode for measuring the resistance to be measured RSE, the first electrode being connected to the first terminal TSE, and the second electrode being connected to the third terminal TIN. Then, the measurement system 200 measures the resistance between the first electrode and the second electrode as the resistance to be measured RSE.

[0012] The first terminal TSE, the second terminal TRF, and the third terminal TIN are, for example, pads of the circuit device 20, or terminals of a package on which a semiconductor chip of the circuit device 20 is mounted. For example, in the pad region, a metal layer is exposed from a passivation film, which is an insulating layer, and this exposed metal layer forms a pad, which is a terminal of the circuit device 20. The connection in this embodiment is an electrical connection. An electrical connection is a connection that allows an electrical signal to be transmitted, and is a connection that allows information to be transmitted by an electrical signal. The electrical connection may be a connection via a passive element, etc.

[0013] The oscillation control unit 50 controls the CR oscillation based on a detection signal DT corresponding to an input signal IN from the third terminal TIN. For example, the oscillation control unit 50 controls the CR oscillation by the measurement target resistor RSE and the capacitor CA based on the detection signal DT. The oscillation control unit 50 also controls the CR oscillation by the reference resistor RRF and the capacitor CA based on the detection signal DT. The input signal IN is a signal of the voltage of a node NC which is a charging node of the capacitor CA, and is a signal indicating the level of the charging voltage of the capacitor CA. The detection signal DT is, for example, a square wave signal whose voltage level changes with the oscillation period of the CR oscillation by the measurement target resistor RSE or the reference resistor RRF and the capacitor CA. Specifically, the waveform shaping circuit 70 outputs a square wave detection signal DT based on the input signal IN from the third terminal TIN. The detection signal DT is, for example, a square wave signal obtained by shaping the input signal IN. For example, the waveform shaping circuit 70 outputs a detection signal DT that becomes a first voltage level when the capacitor CA is determined to be in a charging state based on the input signal IN, and becomes a second voltage level when the capacitor CA is determined to be in a discharging state. The first voltage level is either a low level or a high level, and the second voltage level is the other voltage level, either a low level or a high level. Specifically, the waveform shaping circuit 70 changes the detection signal DT from the first voltage level to the second voltage level when the voltage of the input signal IN indicating the charging voltage of the capacitor CA exceeds, for example, a threshold voltage for detecting the charging state. In addition, the waveform shaping circuit 70 changes the detection signal DT from the second voltage level to the first voltage level when the voltage of the input signal IN falls below, for example, a threshold voltage for detecting discharging.

[0014] The oscillation control unit 50 controls the CR oscillation based on the detection signal DT that changes according to the input signal IN. For example, in a measurement mode in which CR oscillation is performed by the measurement target resistor RSE and the capacitor CA, the oscillation control unit 50 controls the CR oscillation by outputting a signal CS1 having a voltage corresponding to the voltage of the detection signal DT to the first drive circuit 30. Also, in a reference mode in which CR oscillation is performed by the reference resistor RRF and the capacitor CA, the oscillation control unit 50 controls the CR oscillation by outputting a signal CS2 having a voltage corresponding to the voltage of the detection signal DT to the second drive circuit 40. The measurement mode can also be referred to as a mode in which the resistance value of the measurement target resistor RSE is measured by, for example, R / F conversion, and the reference mode can also be referred to as a mode in which the resistance value of the reference resistor RRF is measured by, for example, R / F conversion.

[0015] The first drive circuit 30 and the second drive circuit 40 are controlled by the oscillation control unit 50 to output a first drive signal DS1 and a second drive signal DS2, respectively. For example, the first drive circuit 30 outputs a first drive signal DS1 that becomes high or low depending on the detection signal DT based on a signal CS1 from the oscillation control unit 50 to a first terminal TSE. The second drive circuit 40 outputs a second drive signal DS2 that becomes high or low depending on the detection signal DT based on a signal CS2 from the oscillation control unit 50 to a second terminal TRF. For example, a signal obtained by buffering the detection signal DT is input from the oscillation control unit 50 as a signal CS1 to the first drive circuit 30. Then, the first drive circuit 30 outputs a first drive signal DS1 that becomes high or low depending on whether the detection signal DT is at a first voltage level or a second voltage level. Also, a signal obtained by buffering the detection signal DT is input from the oscillation control unit 50 to the second drive circuit 40 as a signal CS2. The second drive circuit 40 outputs a second drive signal DS2 that goes to a high level or a low level depending on whether the detection signal DT is at the first voltage level or the second voltage level.

[0016] The measurement unit 60 measures the resistance value of the resistor RSE to be measured based on the detection signal DT. For example, the measurement unit 60 measures the resistance value of the resistor RSE to be measured based on the detection signal DT in the reference mode in which CR oscillation is performed by the reference resistor RRF and the capacitor CA, and the detection signal DT in the measurement mode in which CR oscillation is performed by the resistor RSE to be measured and the capacitor CA. For example, the input signal IN is a signal of CR oscillation in the reference resistor RRF or the resistor RSE to be measured and the capacitor CA, and the detection signal DT based on the input signal IN is, for example, a square wave signal whose voltage level changes according to the oscillation period of the CR oscillation. Therefore, the measurement unit 60 can measure the oscillation frequency information of the CR oscillation in the reference mode based on the detection signal DT in the reference mode. Also, the measurement unit 60 can measure the oscillation frequency information of the CR oscillation in the measurement mode based on the detection signal DT in the measurement mode. The measurement unit 60 can measure the resistance value of the resistor RSE to be measured based on the oscillation frequency information in the reference mode and the oscillation frequency information in the measurement mode. Here, the oscillation frequency information is, for example, the oscillation count number of the CR oscillation, but is not limited to this, and various information can be used. The circuit device 20 of the present embodiment can also be realized by, for example, a microcomputer IC. In this case, the processing of the circuit device 20 can be realized by the processor of the microcomputer and peripheral circuits.

[0017] Fig. 2 shows a specific example of the configuration of the circuit device 20 and the measurement system 200 of this embodiment. In Fig. 2, the first drive circuit 30 and the second drive circuit 40 are configured with clocked inverter circuits. As a result, the first drive circuit 30 is enabled and disabled by an enable signal XOE1 from the oscillation control unit 50, and the second drive circuit 40 is enabled and disabled by an enable signal XOE2 from the oscillation control unit 50. Note that "X" indicates negative logic.

[0018] Figure 3 shows an example of the configuration of a clocked inverter circuit. The clocked inverter circuit includes transistors TA3, TA1, TA2, and TA4 that are connected in series between the VDD node and the VSS node. The transistors TA3 and TA1 are P-type transistors, and the transistors TA2 and TA4 are N-type transistors. The VDD node is the high-potential power supply node, and the VSS node is the low-potential power supply node. The transistors TA1 and TA2 form an inverter circuit, which receives a signal I at its gate and outputs an inverted signal Q of the signal I. The signals CS1 and CS2 in Figure 2 correspond to the signal I, and the first drive signal DS1 and the second drive signal DS2 correspond to the signal Q. The enable signal XOE is input to the gate of the transistor TA3, and a signal obtained by inverting the enable signal XOE by the inverter circuit IVA is input to the gate of the transistor TA4. The enable signal XOE corresponds to the enable signals XOE1 and XOE2 in Figure 2. As a result, the clocked inverter circuits constituting the first driving circuit 30 and the second driving circuit 40 are enabled when the enable signal XOE (XOE1, XOE2) becomes a low level, which is an active level of negative logic, and are disabled when the enable signal XOE becomes a high level, which is an inactive level of negative logic.

[0019] 2, the waveform shaping circuit 70 in FIG. 1 is realized by a Schmitt trigger circuit 72. As a result, when the voltage of the input signal IN from the third terminal TIN exceeds the upper threshold voltage VTH of the Schmitt trigger circuit 72, the detection signal DT goes from low level to high level, for example, and when the voltage of the input signal IN falls below the lower threshold voltage VTL of the Schmitt trigger circuit 72, the detection signal DT goes from high level to low level, for example. Here, the relationship VTH>VTL is established. Then, the oscillation control unit 50 outputs, for example, a signal CS1 obtained by buffering the detection signal DT to the first drive circuit 30. Also, the oscillation control unit 50 outputs, for example, a signal CS2 obtained by buffering the detection signal DT to the second drive circuit 40.

[0020] For example, in the measurement mode, the enable signal XOE1 goes to an active level and the enable signal XOE2 goes to an inactive level, thereby enabling the first drive circuit 30 and disabling the second drive circuit 40. The oscillation control unit 50 then outputs a signal CS1, which is a buffered version of the detection signal DT, to the first drive circuit 30, and the first drive circuit 30 is driven based on the signal CS1, causing CR oscillation to occur between the measurement target resistor RSE and the capacitor CA.

[0021] In the reference mode, the enable signal XOE2 goes to an active level and the enable signal XOE1 goes to an inactive level, thereby enabling the second drive circuit 40 and disabling the first drive circuit 30. The oscillation control unit 50 outputs a signal CS2, which is a buffered version of the detection signal DT, to the second drive circuit 40, and the second drive circuit 40 is driven based on the signal CS2, causing CR oscillation to occur between the reference resistor RRF and the capacitor CA.

[0022] FIG. 4 is a signal waveform diagram for explaining the operation of this embodiment. When the first driving circuit 30 outputs a high-level first driving signal DS1, the capacitor CA is charged via the measurement target resistor RSE, the voltage of the node NC rises due to charging, and the voltage of the input signal IN rises. When the voltage of the input signal IN is lower than the upper threshold voltage VTH of the Schmitt trigger circuit 72, the detection signal DT is at a low level, but when it exceeds the threshold voltage VTH, the detection signal DT becomes at a high level. Therefore, when the signal CS1 obtained by buffering the detection signal DT goes from a low level to a high level, the first driving circuit 30, which is a clocked inverter circuit, outputs a low-level first driving signal DS1. As a result, the capacitor CA is discharged via the measurement target resistor RSE, the voltage of the node NC drops due to discharging, and the voltage of the input signal IN drops. When the voltage of the input signal IN is higher than the lower threshold voltage VTL of the Schmitt trigger circuit 72, the detection signal DT is at a high level, but when it falls below the threshold voltage VTL, the detection signal DT becomes at a low level. Therefore, when the signal CS1 obtained by buffering the detection signal DT goes from high to low, the first drive circuit 30, which is a clocked inverter circuit, outputs a high-level first drive signal DS1. In this way, CR oscillation is performed by the measurement target resistor RSE and the capacitor CA.

[0023] CR oscillation is also achieved by the reference resistor RRF and the capacitor CA. For example, when the second drive circuit 40 outputs a high-level second drive signal DS2, the capacitor CA is charged via the reference resistor RRF, and the voltage of the input signal IN rises. When the voltage of the input signal IN exceeds the threshold voltage VTH of the Schmitt trigger circuit 72, the detection signal DT goes from low to high. Therefore, the signal CS2 obtained by buffering the detection signal DT goes from low to high, and the second drive circuit 40 outputs a low-level second drive signal DS2. This causes the capacitor CA to be discharged via the reference resistor RRF, and the voltage of the input signal IN drops. When the voltage of the input signal IN falls below the threshold voltage VTL of the Schmitt trigger circuit 72, the detection signal DT goes to low. Therefore, the signal CS2 obtained by buffering the detection signal DT goes from high to low, and the second drive circuit 40 outputs a high-level second drive signal DS2. In this way, CR oscillation is achieved by the reference resistor RRF and the capacitor CA.

[0024] Next, the configuration of a comparative example of this embodiment will be described. FIG. 5 is a diagram showing the configuration of a comparative example that is driven by a DC bias method. In FIG. 5, signals GC1, GC2, and GC3 from the oscillation control unit 150 are input to the gates of transistors TB1, TB2, and TB3. The transistors TB1 and TB2 are, for example, N-type transistors, and the drains are connected to, for example, a VDD node. The source of the transistor TB1 is connected to the first terminal TSE, and the source of the transistor TB2 is connected to the second terminal TRF. The source of the transistor TB3 is connected to a VSS node, and the drain is connected to a node of an input signal IN. The Schmitt trigger circuit 172 receives the input signal IN from the third terminal TIN, and outputs a detection signal DT to the oscillation control unit 150 and the measurement unit 160. The oscillation control unit 150 outputs signals GC1 and GC2 based on the detection signal DT, and the measurement unit 160 measures the resistance value of the measurement target resistor RSE based on the detection signal DT. The connection configuration of the measurement target resistor RSE, the reference resistor RRF, and the capacitor CA is the same as that in FIG. 1 and FIG. 2, and therefore the description will be omitted.

[0025] FIG. 6 is a signal waveform diagram for explaining the operation of the comparative example of FIG. 5. In the measurement mode, the oscillation control unit 150 outputs signals GC1 and GC3 as shown in FIG. 6 to the gates of the transistors TB1 and TB3, respectively. When the signal GC1 is at a high level, the transistor TB1 is turned on, and when the signal GC3 is at a low level, the transistor TB3 is turned off. As a result, a current flows from the node of VDD through the transistor TB1 and the first terminal TSE to the resistance RSE to be measured, so that the capacitor CA is charged, the voltage of the node NC increases, and the voltage of the input signal IN also increases. When the voltage of the input signal IN exceeds the upper threshold voltage VTH, the voltage of the detection signal DT output by the Schmitt trigger circuit 172 changes from a low level to a high level. As a result, when the signal GC3 becomes a high level, the transistor TB3 is turned on, and when the signal GC1 becomes a low level, the transistor TB1 is turned off. When the transistor TB3 is turned on, the capacitor CA is discharged, the voltage of the node NC decreases, and the voltage of the input signal IN decreases. When the voltage of the input signal IN falls below the lower threshold voltage VTL, the voltage of the detection signal DT output by the Schmitt trigger circuit 172 changes from high to low. This causes the signal GC1 to go high, turning on the transistor TB1, and the signal GC3 to go low, turning off the transistor TB3. In this way, in the measurement mode, CR oscillation is performed by the measurement target resistor RSE and the capacitor CA.

[0026] On the other hand, in the reference mode, the voltage level of the signal GC2 changes in the same manner as the signal GC1 in the measurement mode, and CR oscillation is performed by the reference resistor RRF and the capacitor CA. Then, the measurement unit 160 measures the resistance value of the resistor RSE to be measured based on the detection signal DT in the reference mode and the detection signal DT in the measurement mode. In this way, in the comparative example of the DC bias method of FIG. 5, the bias of the first terminal TSE and the third terminal TIN connected to the resistor RSE to be measured is fixed, and a current flows through the resistor RSE to be measured only in the direction from the first terminal TSE to the node NC. Therefore, for example, if the resistor RSE to be measured is a resistance of an aqueous solution, there is a problem that electrolysis or the like occurs in the aqueous solution.

[0027] FIG. 7 is a diagram showing the configuration of a comparative example in which driving is performed by the AC bias method. In FIG. 7, transistors TB11 and TB12 are provided instead of the transistor TB1 in FIG. 5, and switches SW11, SW12, and SW2 are provided. In FIG. 7, signals GC11, GC12, GC2, and GC3 from the oscillation control unit 150 are input to the gates of the transistors TB11, TB12, TB2, and TB3. The transistors TB11 and TB12 are, for example, N-type transistors, and their drains are connected to the node of VDD. The source of the transistor TB11 is connected to the terminal TSEA, and the source of the transistor TB12 is connected to the terminal TSEB. One end of the measurement target resistor RSE is connected to the terminal TSEA, and the other end is connected to the terminal TSEB. The switches SW11, SW12, and SW2 are provided between the node of the drains of the transistors TB11, TB12, and TB2 and the node of the input signal IN. The connection configuration of the transistors TB2 and TB3, the Schmitt trigger circuit 172, etc. is the same as that in FIG. 5, so a detailed description thereof will be omitted.

[0028] In the comparative example of FIG. 7, in the first charging period in the measurement mode, the signal GC11 goes high to turn on the transistor TB11, and the signals GC12 and GC3 go low to turn off the transistors TB12 and TB3. At this time, the switch SW12 is on, and the switches SW11 and SW2 are off. As a result, a current flows from the VDD node to the measurement target resistor RSE via the transistor TB11, and this current flows to the node NC via the switch SW12, thereby charging the capacitor CA. Then, when the voltage of the input signal IN exceeds the threshold voltage VTH of the Schmitt trigger circuit 172, the voltage of the detection signal DT goes high. As a result, in the first discharging period following the first charging period, the signal GC11 goes low to turn off the transistor TB11, and the signal GC3 goes high to turn on the transistor TB3, thereby discharging the capacitor CA.

[0029] When the voltage of the input signal IN falls below the threshold voltage VTL of the Schmitt trigger circuit 172, the voltage of the detection signal DT becomes low level. As a result, in the second charging period following the first discharging period, the signal GC12 becomes high level, turning on the transistor TB12, and the signals GC11 and GC3 become low level, turning off the transistors TB11 and TB3. At this time, the switch SW11 is turned on, and the switches SW12 and SW2 are turned off. As a result, a current flows from the VDD node to the resistance RSE to be measured via the transistor TB12, and this current flows to the node NC via the switch SW11, thereby charging the capacitor CA. When the voltage of the input signal IN exceeds the threshold voltage VTH of the Schmitt trigger circuit 172, the voltage of the detection signal DT becomes high level. Then, in the second discharging period following the second charging period, the signal GC12 becomes low level, turning off the transistor TB12, and the signal GC3 becomes high level, turning on the transistor TB3, thereby discharging the capacitor CA.

[0030] In this way, in the comparative example of the AC bias method in Fig. 7, in the first charging period, a current flows from the terminal TSEA to the terminal TSEB via the resistance RSE to be measured, and in the second charging period, a current flows from the terminal TSEB to the terminal TSEA via the resistance RSE to be measured. Therefore, the polarity of the voltage applied to the resistance RSE to be measured alternates, and the direction of the current flow alternates, so that there is an advantage that problems such as electrolysis do not occur even when the resistance RSE to be measured is a resistance such as an aqueous solution. However, in the comparative example of the AC bias method in Fig. 7, four terminals such as TRF, TSEA, TSEB, and TIN are required, and there is a disadvantage that the number of terminals is larger than that of this embodiment and the comparative example of the DC bias method in Fig. 6.

[0031] The method of the comparative example also has the problem explained in Fig. 8. For example, when testing a circuit device, the tester probe or the test circuit board causes parasitic resistances RP1, RP2, RP3 and parasitic capacitances CP1, CP2, CP3 as shown at A1, A2, and A3 in Fig. 8. For example, when a tester probe or the like is applied to node NC of capacitor CA to test whether the oscillation frequency is being measured properly, a problem occurs in that parasitic resistance RP1 and parasitic capacitance CP1 due to the tester are added at A1. Fig. 9 is a signal waveform diagram explaining the problem of this comparative example.

[0032] For example, in the charging period during the inspection, the signal GC2 goes high to turn on the transistor TB2, and the capacitor CA is charged by the charging current ICH, and the voltage of the input signal IN rises as shown in FIG. 9. Then, when the voltage of the input signal IN exceeds the threshold voltage VTH of the Schmitt trigger circuit 172 and the detection signal DT goes high, the signal GC3 goes high to turn on the transistor TB3, and the discharge period begins. In this discharge period, the capacitor CA is discharged by the discharge current IDS. In this case, since the parasitic resistor RP1 shown as A1 exists in the discharge path, the voltage of the node of the input signal IN drops faster than the voltage drop of the node NC. This is because the parasitic resistor RP1 and the parasitic capacitance CP1 act like a low-pass filter. Therefore, even though the voltage of the node NC at one end of the capacitor CA does not fall below the threshold voltage VTL of the Schmitt trigger circuit 172, the voltage of the input signal IN falls below the threshold voltage VTL, and the detection signal DT changes from high to low at a timing faster than that during normal operation. As a result, as shown in FIG. 9, even though the voltage of the node NC is not below the threshold voltage VTL, the signal GC2 becomes high level, the transistor TB2 turns on, and the charging period begins. This causes CR oscillation at a higher oscillation frequency than the expected oscillation frequency, which causes a problem that the test cannot be performed correctly. As an example, when the parasitic resistance RP1 is 40 Ω and the parasitic capacitance CP1 is 100 pF, the oscillation period is about 80 μs when there are no parasitic RP1 and CP1, whereas the oscillation period is about 55 μs when there are parasitic RP1 and CP1. This causes a problem that a product that should be judged as a good product is judged as a defective product.

[0033] FIG. 10 is a diagram for explaining the operation of the circuit device 20 of this embodiment during inspection. In FIG. 10, parasitic resistances RP1, RP2, RP3 and parasitic capacitances CP1, CP2, CP3 are added by the probes of a tester or the like, as shown in B1, B2, B3. For example, when inspection is performed along the path of the reference resistance RRF, in this embodiment, the second driving circuit 40 is driven to cause a charging current ICH to flow from the node VDD of the second driving circuit 40 to the node NC via the second terminal TRF, the parasitic resistance RP2, and the reference resistance RRF, thereby charging the capacitor CA during the charging period during inspection. When the voltage of the input signal IN exceeds the threshold voltage VTH of the Schmitt trigger circuit 72 and the detection signal DT becomes high level, the charging period is switched to the discharging period. During the discharging period, a discharge current IDS flows from the node NC of the capacitor CA to the node VSS of the second driving circuit 40 via the reference resistance RRF, the parasitic resistance RP2, and the second terminal TRF, thereby discharging the capacitor CA.

[0034] In this case, the resistance value of the reference resistor RRF is several kΩ to several tens of kΩ, while the resistance value of the parasitic resistor RP2 is several tens of Ω, which is sufficiently small. Therefore, even if the parasitic resistor RP2 exists in the charging path of the charging current ICH or the discharging path of the discharging current IDS, the oscillation frequency of the CR oscillation is hardly affected. Therefore, it is possible to prevent a situation in which an inaccurate test is performed, as in the comparative example.

[0035] As described above, the circuit device 20 of the present embodiment includes the first terminal TSE, the second terminal TRF, the third terminal TIN, the oscillation control unit 50, the first driving circuit 30, the second driving circuit 40, and the measurement unit 60, as shown in FIG. 1 and FIG. 2. The first terminal TSE is connected to one end of the resistance RSE to be measured, and the second terminal TRF is connected to one end of the reference resistance RRF. The third terminal TIN is connected to the other end of the reference resistance RRF, the other end of the resistance RSE to be measured, and one end of the capacitor CA. The oscillation control unit 50 controls the CR oscillation by the resistance RSE to be measured and the CR oscillation by the reference resistance RRF and the capacitor CA based on the detection signal DT corresponding to the input signal IN from the third terminal TIN. For example, in the reference mode, the CR oscillation is performed by the reference resistance RRF and the capacitor CA, and in the subsequent measurement mode, the CR oscillation is performed by the resistance RSE to be measured and the capacitor CA. Also, the first driving circuit 30 outputs to the first terminal TSE a first driving signal DS1 that becomes high or low depending on the detection signal DT based on the signal CS1 from the oscillation control unit 50. For example, in the measurement mode, the first driving circuit 30 outputs the first driving signal DS1 at a high level during the charging period of the capacitor CA, and outputs the first driving signal DS1 at a low level during the discharging period of the capacitor CA. Also, the second driving circuit 40 outputs to the second terminal TRF a second driving signal DS2 that becomes high or low depending on the detection signal DT based on the signal CS2 from the oscillation control unit 50. For example, in the reference mode, the second driving circuit 40 outputs the second driving signal DS2 at a high level during the charging period of the capacitor CA, and outputs the second driving signal DS2 at a low level during the discharging period of the capacitor CA. Then, the measurement unit 60 measures the resistance value of the measurement target resistor RSE based on the detection signal DT. For example, the measurement unit 60 measures the resistance value of the measurement target resistor RSE based on the detection signal DT in the reference mode and the detection signal DT in the measurement mode.For example, the measurement unit 60 measures oscillation frequency information of CR oscillation by the reference resistor RRF and the capacitor CA in the reference mode, and measures oscillation frequency information of CR oscillation by the measurement target resistor RSE and the capacitor CA in the measurement mode, and measures the resistance value of the measurement target resistor RSE from these oscillation frequency information. In this way, when the first drive signal DS1 is at a high level, a charging current flows from the first terminal TSE to the node NC at one end of the capacitor CA via the measurement target resistor RSE. Also, when the first drive signal DS1 is at a low level, a discharging current flows from the node NC at one end of the capacitor CA to the first drive circuit 30 via the measurement target resistor RSE and the first terminal TSE. Therefore, it is possible to alternately switch the polarity of the voltage applied to the measurement target resistor RSE to perform CR oscillation. This makes it possible to measure an appropriate resistance value even when the measurement target resistor RSE is, for example, the resistance of an aqueous solution. In addition, since the CR oscillation by the reference resistor RRF and the capacitor CA is also used, it is possible to more accurately measure the resistance value of the measurement target resistor RSE.

[0036] The circuit device 20 can also include a waveform shaping circuit 70 that outputs a detection signal DT of a square wave based on an input signal IN from the third terminal TIN. In this way, the measurement section 60 can measure the resistance RSE to be measured based on the detection signal DT of a square wave having a frequency corresponding to the oscillation frequency of the CR oscillation of the resistance RSE to be measured or the reference resistance RRF and the capacitor CA.

[0037] 2, the waveform shaping circuit 70 is, for example, a Schmitt trigger circuit 72. By using such a Schmitt trigger circuit 72, for example, during the charging period of the capacitor CA, when the voltage of the input signal IN exceeds the upper threshold voltage VTH of the Schmitt trigger circuit 72, it is possible to change the voltage level of the detection signal DT and transition to the discharging period. During the discharging period of the capacitor CA, when the voltage of the input signal IN falls below the lower threshold voltage VTL of the Schmitt trigger circuit 72, it is possible to change the voltage level of the detection signal DT and transition to the charging period.

[0038] In this embodiment, in the reference mode in which CR oscillation is performed by the reference resistor RRF and the capacitor, the second drive circuit 40 is enabled and the first drive circuit 30 is disabled. For example, the enable signal XOE2 in FIG. 2 becomes active level, and the second drive circuit 40 is enabled, and the enable signal XOE1 becomes inactive level, and the second drive circuit 40 is disabled. In the measurement mode in which CR oscillation is performed by the measurement target resistor RSE and the capacitor CA, the first drive circuit 30 is enabled and the second drive circuit 40 is disabled. For example, the enable signal XOE1 becomes active level, and the first drive circuit 30 is enabled, and the enable signal XOE2 becomes inactive level, and the second drive circuit 40 is disabled. In this manner, in the reference mode, CR oscillation is performed by the reference resistor RRF and capacitor CA, driven by the enabled second drive circuit 40, and in the measurement mode, CR oscillation is performed by the measurement target resistor RSE and capacitor CA, driven by the enabled first drive circuit 30.

[0039] The resistance to be measured RSE is, for example, the resistance of an aqueous solution, a thermistor, or food. In this way, the resistance value of the aqueous solution, thermistor, or food can be properly measured by the circuit device 20. For example, when the resistance to be measured RSE is an aqueous solution or a food containing moisture, in this embodiment, the polarity of the voltage applied to the resistance to be measured RSE is switched between the charging period and the discharging period, making it possible to prevent problems such as electrolysis from occurring.

[0040] 2. Detailed example Next, a detailed example of the circuit device 20 of this embodiment will be described.

[0041] In FIG. 11, the oscillation control unit 50 includes a buffer circuit BF. The buffer circuit BF outputs signals obtained by buffering the detection signal DT as signals CS1 and CS2. The first driving circuit 30 outputs a signal obtained by inverting the signal CS1 as the first driving signal DS1. The second driving circuit 40 outputs a signal obtained by inverting the signal CS2 as the second driving signal DS2. As a result, a CR oscillation driving circuit using an odd number of inversion circuits is realized by the Schmitt trigger circuit 72, the buffer circuit BF, and the first driving circuit 30 or the second driving circuit 40. The oscillation control unit 50 can also include an inverter circuit IV. The selection signal SEL of the driving circuit is input to the first driving circuit 30 as the enable signal XOE1, and a signal obtained by inverting the selection signal SEL by the inverter circuit IV is input to the second driving circuit 40 as the enable signal XOE2. When the selection signal SEL becomes low level, for example, the first driving circuit 30 is enabled and the second driving circuit 40 is disabled. Moreover, when the selection signal SEL becomes, for example, high level, the first drive circuit 30 is disabled and the second drive circuit 40 is enabled.

[0042] The measurement unit 60 also includes an oscillation measurement counter 62, a measurement time management counter 64, and a calculation unit 66. The oscillation measurement counter 62 counts the number of pulses (number of clocks) of a detection signal DT having a frequency (clock frequency) corresponding to the oscillation frequency of the CR oscillation. For example, in the reference mode, the oscillation measurement counter 62 counts the number of pulses of the detection signal DT having a frequency corresponding to the oscillation frequency of the CR oscillation caused by the reference resistor RRF and the capacitor CA, and outputs the oscillation count number Nrf of the CR oscillation. In the measurement mode, the oscillation measurement counter 62 counts the number of pulses of the detection signal DT having a frequency corresponding to the oscillation frequency of the CR oscillation caused by the measurement target resistor RSE and the capacitor CA, and outputs the oscillation count number Nse of the CR oscillation. The measurement time management counter 64 is a counter for managing the measurement time of the count number of the oscillation measurement counter 62. For example, the measurement time management counter 64 performs count processing of a clock signal (e.g., a master clock signal) not shown, and sets a period corresponding to a predetermined number of clocks of the clock signal as the measurement time. The oscillation measurement counter 62 counts the number of pulses of the detection signal DT during the set measurement time, and outputs the count value as an oscillation count number Nrf or an oscillation count number Nse. The calculation unit 66 then calculates the resistance value Rse of the resistance RSE to be measured based on the oscillation count numbers Nrf and Nse. If the circuit device 20 is, for example, a microcomputer, the calculation unit 66 can be realized by, for example, a processor of the microcomputer.

[0043] FIG. 12 is a signal waveform diagram for explaining the operation of the circuit device 20. When the first drive signal DS1 or the second drive signal DS2 becomes high level, the capacitor CA is charged, and tr in FIG. 12 indicates the charging time of CR. When the first drive signal DS1 or the second drive signal DS2 becomes low level, the capacitor CA is discharged, and tf in FIG. 12 indicates the discharging time of CR. For example, in the CR circuit of FIG. 13, the switch SW is turned on to charge the capacitor C. The charging time tr and discharging time tf in such a CR circuit are expressed by the following equations (1) and (2) when the voltage at the capacitor C is VC(t), as shown in FIG. 14.

[0044]

number

[0045] In addition, if the CR oscillation period corresponding to the CR charge / discharge time in the reference mode is Trf, and the CR oscillation period corresponding to the CR charge / discharge time in the measurement mode is Tse, in this embodiment, control is performed so that the following equation (3) holds.

[0046]

number

[0047] Here, TMA=Nrf·Trf=Nse·Tse is the measurement time set by the measurement time management counter 64 in Fig. 11. The oscillation measurement counter 62 outputs the number of pulses of the detection signal DT during the measurement time TMA as the oscillation count number Nrf in the reference mode, and outputs the number of pulses of the detection signal DT during the measurement time TMA as the oscillation count number Nse in the measurement mode, so the above formula (3) holds.

[0048] Since each of Trf and Tse is the sum of the charge time tr and the discharge time tf, the following equations (4) and (5) hold from the above equations (1), (2), and (3), and the following equations (6) and (7) hold from the below equations (4) and (5).

[0049]

number

[0050] Here, Rrf is the resistance value of the reference resistor RRF, Rse is the resistance value of the measurement target resistor RSE, and C is the capacitance value of the capacitor CA.

[0051] And since the parts in brackets in equations (6) and (7) above can be deleted as common terms, equation (8) below holds, and from equation (8) below, equation (9) holds.

[0052]

number

[0053] In this way, the calculation unit 66 of the measurement unit 60 calculates the resistance value Rse of the resistor to be measured RSE from the oscillation count number Nrf in the reference mode from the oscillation measurement counter 62, the oscillation count number Nse in the measurement mode, and the resistance value Rrf of the reference resistor RRF, which is a known resistance value.

[0054] As described above, in this embodiment, the oscillation control unit 50 outputs the signals CS1 and CS2 obtained by buffering the detection signal DT to the first driving circuit 30 and the second driving circuit 40. For example, the oscillation control unit 50 is provided with a buffer circuit BF, which outputs the signal CS1 obtained by buffering the detection signal DT to the first driving circuit 30 and outputs the signal CS2 obtained by buffering the detection signal DT to the second driving circuit 40. For example, in the measurement mode, the first driving circuit 30 is enabled by the enable signal XOE1. The enabled first driving circuit 30 receives the signal CS1 obtained by buffering the detection signal DT, and outputs the inverted signal of the signal CS1 as the first driving signal DS1. In the reference mode, the second driving circuit 40 is enabled by the enable signal XOE2. The enabled second driving circuit 40 receives the signal CS2 obtained by buffering the detection signal DT, and outputs the inverted signal of the signal CS2 as the second driving signal DS2. In this way, the first drive circuit 30 outputs a high or low level first drive signal DS1 based on the signal CS1 obtained by buffering the detection signal DT, thereby causing CR oscillation between the measurement target resistor RSE and the capacitor CA. Also, the second drive circuit 40 outputs a high or low level second drive signal DS2 based on the signal CS2 obtained by buffering the detection signal DT, thereby causing CR oscillation between the reference resistor RRF and the capacitor CA.

[0055] In this embodiment, the measurement unit 60 measures the resistance value of the resistance RSE to be measured based on the oscillation count number Nrf and the oscillation count number Nse. The oscillation count number Nrf is the count number of CR oscillation in the reference mode in which CR oscillation is performed by the reference resistance RRF and the capacitor CA. For example, the oscillation measurement counter 62 performs count processing based on the detection signal DT in the reference mode, and outputs the oscillation count number Nrf. The oscillation count number Nse is the count number of CR oscillation in the measurement mode in which CR oscillation is performed by the resistance RSE to be measured and the capacitor CA. For example, the oscillation measurement counter 62 performs count processing based on the detection signal DT in the measurement mode, and outputs the oscillation count number Nse. Then, the calculation unit 66 performs calculation processing of the above formula (9) based on the oscillation count number Nrf in the reference mode, the oscillation count number Nse in the measurement mode, and the resistance value Rrf of the reference resistance RRF, and thereby obtains the resistance value Rse of the resistance RSE to be measured. In this way, the resistance value Rse of the resistor RSE to be measured can be measured by simple calculation processing using the oscillation count number Nrf of the CR oscillation in the reference mode and the oscillation count number Nse of the CR oscillation in the measurement mode.

[0056] As described above, the circuit device of this embodiment includes a first terminal for connecting to one end of the resistor to be measured, a second terminal for connecting to one end of the reference resistor, and a third terminal for connecting to the other end of the resistor to be measured, the other end of the reference resistor, and one end of the capacitor. The circuit device also includes an oscillation control unit that controls the CR oscillation by the resistor to be measured and the capacitor and the CR oscillation by the reference resistor and the capacitor based on a detection signal corresponding to an input signal from the third terminal. The circuit device also includes a first drive circuit that outputs a first drive signal to the first terminal based on a signal from the oscillation control unit, the first drive signal being set to a high level or a low level according to the detection signal, a second drive circuit that outputs a second drive signal to the second terminal based on a signal from the oscillation control unit, the second drive signal being set to a high level or a low level according to the detection signal, and a measurement unit that measures the resistance value of the resistor to be measured based on the detection signal.

[0057] According to this embodiment, for example, when the first drive signal is at a high level, a charging current flows from the first terminal to a node at one end of the capacitor via the resistance to be measured. Also, for example, when the first drive signal is at a low level, a discharging current flows from the node at one end of the capacitor to the first drive circuit via the resistance to be measured and the first terminal. Therefore, it is possible to suppress an increase in the number of terminals, and to perform CR oscillation while switching the polarity of the voltage applied to the resistance to be measured, thereby making it possible to measure the resistance value of the resistance to be measured.

[0058] In this embodiment, a waveform shaping circuit may be included that outputs a detection signal with a rectangular wave based on an input signal from the third terminal.

[0059] In this way, the measurement section can measure the resistance value of the resistor to be measured based on a detection signal of a square wave having a frequency corresponding to the oscillation frequency of the CR oscillation.

[0060] In this embodiment, the waveform shaping circuit may be a Schmitt trigger circuit.

[0061] In this way, when the voltage of the input signal exceeds the upper threshold voltage of the Schmitt trigger circuit during the charging period of the capacitor, the voltage level of the detection signal can be changed to transition to the discharging period, and when the voltage of the input signal falls below the lower threshold voltage, the voltage level of the detection signal can be changed to transition to the charging period.

[0062] In addition, in this embodiment, in a reference mode in which CR oscillation is performed by a reference resistor and a capacitor, the second drive circuit may be enabled and the first drive circuit may be disabled, and in a measurement mode in which CR oscillation is performed by a resistor to be measured and a capacitor, the first drive circuit may be enabled and the second drive circuit may be disabled.

[0063] In this manner, in the reference mode, CR oscillation is performed by the reference resistor and capacitor, driven by the enabled second drive circuit, and in the measurement mode, CR oscillation is performed by the measurement target resistor and capacitor, driven by the enabled first drive circuit.

[0064] In this embodiment, the oscillation control section may buffer the detection signal and output the buffered signal to the first drive circuit and the second drive circuit.

[0065] In this way, the first drive circuit outputs a first drive signal based on a buffered detection signal, thereby causing CR oscillation between the resistor to be measured and the capacitor, and the second drive circuit outputs a second drive signal based on a buffered detection signal, thereby causing CR oscillation between the reference resistor and the capacitor.

[0066] In addition, in this embodiment, the measurement unit may measure the resistance value of the resistor to be measured based on the oscillation count number of CR oscillation in a reference mode in which CR oscillation is performed by a reference resistor and a capacitor, and the oscillation count number of CR oscillation in a measurement mode in which CR oscillation is performed by the resistor to be measured and a capacitor.

[0067] In this way, the resistance value of the resistor to be measured can be measured by simple calculation using the CR oscillation count number in the reference mode and the CR oscillation count number in the measurement mode.

[0068] In this embodiment, the resistance to be measured may be the resistance of an aqueous solution, a thermistor, or a food.

[0069] In this way, the resistance value of the aqueous solution, thermistor, or food can be properly measured by the circuit device.

[0070] The measurement system of this embodiment also includes the circuit device described above, a reference resistor, and a capacitor.

[0071] Although the present embodiment has been described in detail as above, it will be easily understood by those skilled in the art that many modifications are possible without substantially departing from the novel matters and effects of the present disclosure. Therefore, all such modifications are intended to be included in the scope of the present disclosure. For example, a term described at least once in the specification or drawings together with a different term having a broader meaning or synonymy can be replaced with that different term anywhere in the specification or drawings. In addition, all combinations of the present embodiment and modifications are also included in the scope of the present disclosure. In addition, the configurations and operations of the circuit device and the measurement system are not limited to those described in the present embodiment, and various modifications are possible. [Explanation of symbols]

[0072] 20...circuit device, 30...first drive circuit, 40...second drive circuit, 50...oscillation control unit, 60...measurement unit, 62...oscillation measurement counter, 64...measurement time management counter, 66...calculation unit, 70...wave shaping circuit, 72...Schmitt trigger circuit, 150...oscillation control unit, 160...measurement unit, 172...Schmitt trigger circuit, 200...measurement system, BF...buffer circuit, CA...capacitor, CS1, CS2...signal, DS1...first drive signal, DS2...second drive signal, DT...detection signal, IN...input signal, NC...node, Nrf, Nse...oscillation count number, RRF...reference resistor, RSE...resistance to be measured, Rrf, Rse...resistance value, TSE...first terminal, TRF...second terminal, TIN...third terminal, XOE1, XOE2...enable signal

Claims

1. a first terminal for connecting to one end of a resistor to be measured; a second terminal for connecting to one end of a reference resistor; a third terminal for connecting to the other end of the measurement target resistor, the other end of the reference resistor, and one end of a capacitor; an oscillation control unit that controls a CR oscillation by the measurement target resistor and the capacitor and the CR oscillation by the reference resistor and the capacitor based on a detection signal corresponding to an input signal from the third terminal; a first drive circuit that outputs a first drive signal to the first terminal, the first drive signal being set to a high level or a low level in response to the detection signal, based on a signal from the oscillation control unit; a second drive circuit that outputs a second drive signal to the second terminal, the second drive signal being set to a high level or a low level in response to the detection signal, based on a signal from the oscillation control unit; a measurement unit that measures a resistance value of the resistor to be measured based on the detection signal; A circuit device comprising:

2. 2. The circuit device according to claim 1, a waveform shaping circuit that outputs the detection signal having a rectangular wave based on the input signal from the third terminal.

3. 3. The circuit device according to claim 2, The circuit device is characterized in that the waveform shaping circuit is a Schmitt trigger circuit.

4. 2. The circuit device according to claim 1, In a reference mode in which the CR oscillation is performed by the reference resistor and the capacitor, the second drive circuit is enabled and the first drive circuit is disabled; A circuit device, characterized in that in a measurement mode in which the CR oscillation is performed by the resistance to be measured and the capacitor, the first drive circuit is enabled and the second drive circuit is disabled.

5. 2. The circuit device according to claim 1, The oscillation control unit is a detection signal buffered by the detection circuit and outputted to the first drive circuit and the second drive circuit;

6. 2. The circuit device according to claim 1, The measurement unit includes: A circuit device characterized in that it measures the resistance value of the resistor to be measured based on the oscillation count number of the CR oscillation in a reference mode in which the CR oscillation is performed by the reference resistor and the capacitor, and the oscillation count number of the CR oscillation in a measurement mode in which the CR oscillation is performed by the resistor to be measured and the capacitor.

7. 2. The circuit device according to claim 1, The circuit device according to claim 1, wherein the resistance to be measured is the resistance of an aqueous solution, a thermistor, or a food.

8. A circuit arrangement according to any one of claims 1 to 7; the reference resistor; The capacitor; A measurement system comprising:

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