Wiring board and manufacturing method for the same, and semiconductor device

Abstract

To suppress resistance loss in a wiring board incorporating an electronic component.SOLUTION: The present wiring board includes a first wiring structure including a first wiring layer and a first insulating layer, a second wiring structure including a second wiring layer and a second insulating layer and stacked on one side of the first wiring structure, and a third wiring structure including a third wiring layer and a third insulating layer and stacked on the other side of the first wiring structure. The second wiring layer has higher wiring density than the first wiring layer and the third wiring layer. The first insulating layer includes a penetration hole penetrating the first insulating layer. In the penetration hole, an electronic component electrically connected to the second wiring layer is disposed. In the penetration hole, an embedded resin to cover the electronic component is provided. The embedded resin extends from the penetration hole, covers the first insulating layer and fills a space between the first insulating layer and the second insulating layer.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a wiring board, a manufacturing method thereof, and a semiconductor device. [Background technology]

[0002] When mounting a semiconductor chip on a wiring board, for example, the chip is mounted via a wiring structure that serves as an interposer having fine wiring. Interposers include silicon substrates, glass substrates, and organic substrates. A technique for incorporating a capacitor in such a wiring board has been proposed (for example, see Patent Document 1). It is preferable that such a wiring board has as small a resistance loss as possible. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2021 / 084750 Summary of the Invention [Problem to be solved by the invention]

[0004] The present invention has been made in view of the above-mentioned points, and has an object to suppress resistance loss in a wiring board having an electronic component built therein. [Means for solving the problem]

[0005] This wiring board has a first wiring structure having a first wiring layer and a first insulating layer, a second wiring structure having a second wiring layer and a second insulating layer and stacked on one side of the first wiring structure, and a third wiring structure having a third wiring layer and a third insulating layer and stacked on the other side of the first wiring structure, wherein the second wiring layer has a higher wiring density than the first wiring layer and the third wiring layer, the first insulating layer has a through hole penetrating the first insulating layer, an electronic component electrically connected to the second wiring layer is disposed in the through hole, and an embedding resin covering the electronic component is provided in the through hole, and the embedding resin extends from within the through hole to cover the first insulating layer and fill the space between the first insulating layer and the second insulating layer. Effect of the Invention

[0006] According to the disclosed technique, it is possible to suppress resistance loss in a wiring board having an electronic component built therein. [Brief description of the drawings]

[0007] [Figure 1] 1 is a cross-sectional view illustrating a wiring board according to a first embodiment. [Diagram 2] 1A to 1C are diagrams illustrating a manufacturing process of the wiring board according to the first embodiment (part 1). [Diagram 3] 5A to 5C are diagrams illustrating the manufacturing process of the wiring board according to the first embodiment (part 2). [Figure 4] 5A to 5C are views (part 3) illustrating the manufacturing process of the wiring board according to the first embodiment; [Diagram 5] 1 is a cross-sectional view illustrating a wiring board according to a first modified example of the first embodiment. [Figure 6] 10A to 10C are diagrams illustrating a manufacturing process of a wiring board according to Modification 1 of the first embodiment. [Figure 7] 11 is a cross-sectional view illustrating a wiring board according to a second modified example of the first embodiment. FIG. [Figure 8] 11 is a cross-sectional view illustrating a wiring board according to a third modified example of the first embodiment. FIG. [Figure 9]10A to 10C are diagrams illustrating a manufacturing process of a wiring board according to a third modified example of the first embodiment. [Figure 10] 11 is a cross-sectional view illustrating a wiring board according to a fourth modified example of the first embodiment. FIG. [Figure 11] 13 is a cross-sectional view illustrating a wiring board according to a fifth modified example of the first embodiment. FIG. [Figure 12] 13A to 13C are diagrams illustrating a manufacturing process of a wiring board according to a fifth modified example of the first embodiment. [Figure 13] 1 is a cross-sectional view illustrating a semiconductor device according to an application example of the first embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the drawings, the same components are denoted by the same reference numerals, and duplicated explanations may be omitted.

[0009] First embodiment [Wiring board structure] Fig. 1 is a cross-sectional view illustrating a wiring board according to a first embodiment. Referring to Fig. 1, a wiring board 5 has a first wiring structure 1, a second wiring structure 2, and a third wiring structure 3. The second wiring structure 2 is laminated on one side in the thickness direction of the first wiring structure 1. The third wiring structure 3 is laminated on the other side in the thickness direction of the first wiring structure 1. In other words, the third wiring structure 3 is disposed on the opposite side of the second wiring structure 2 across the first wiring structure 1.

[0010] In this embodiment, for convenience, the side of the insulating layer 23 (described later) of the wiring board 5 in FIG. 1 is referred to as the upper side or one side, and the side of the insulating layer 32 (described later) is referred to as the lower side or the other side. In addition, the surface of each part facing the insulating layer 23 is referred to as one side or upper side, and the surface facing the insulating layer 32 is referred to as the other side or lower side. However, the wiring board 5 can be used upside down or placed at any angle. In addition, a planar view refers to a view of an object from the normal direction of one side of the insulating layer 23, and a planar shape refers to a shape of an object viewed from the normal direction of one side of the insulating layer 23.

[0011] The first wiring structure 1 is a wiring structure in which a wiring layer and an insulating layer are laminated. The wiring layer of the first wiring structure 1 may be referred to as a first wiring layer, the insulating layer of the first wiring structure 1 may be referred to as a first insulating layer, and the via wiring of the first wiring structure 1 may be referred to as a first via wiring. In the example of FIG. 1, the first wiring structure 1 has a wiring layer 11 and a wiring layer 14 as the first wiring layer, and an insulating layer 12 as the first insulating layer. In the first wiring structure 1, the number of layers of the first wiring layer and the first insulating layer is not limited to the example of FIG. 1.

[0012] In the first wiring structure 1, the wiring layer 11 is embedded in the lower surface side of the insulating layer 12. The lower surface of the wiring layer 11 is exposed from the lower surface of the insulating layer 12, and the upper surface and side surfaces of the wiring layer 11 are covered by the insulating layer 12. In the example of Fig. 1, the lower surface of the wiring layer 11 is recessed toward the wiring layer 14 side with respect to the lower surface of the insulating layer 12. However, the lower surface of the wiring layer 11 may be flush with the lower surface of the insulating layer 12.

[0013] The lower surface of the wiring layer 11 exposed from the lower surface of the insulating layer 12 is formed, for example, in a circular planar shape, and can be used as a pad to be connected to the third wiring structure 3. The wiring layer 11 may have a wiring pattern in addition to the pad. The material of the wiring layer 11 may be, for example, copper (Cu) or the like. The wiring layer 11 may have a laminated structure of multiple metal layers. The thickness of the wiring layer 11 may be, for example, about 10 to 35 μm. The line / space of the wiring layer 11 may be, for example, about 10 μm / 10 μm to 50 μm / 50 μm.

[0014] In the line / space definition, the line refers to the wiring width, and the space refers to the distance between adjacent wirings (wiring distance). For example, if the line / space is described as 10 μm / 10 μm to 50 μm / 50 μm, this means that the wiring width is 10 μm to 50 μm, and the wiring distance between adjacent wirings is 10 μm to 50 μm. The wiring width and wiring distance do not necessarily have to be the same.

[0015] The insulating layer 12 is formed so as to cover the upper surface and side surfaces of the wiring layer 11. The insulating layer 12 is an insulating layer mainly composed of, for example, a non-photosensitive resin. The insulating layer 12 may mainly comprise, for example, a thermosetting non-photosensitive resin such as an epoxy resin, an imide resin, a phenol resin, or a cyanate resin. The thickness of the insulating layer 12 may be, for example, about 20 to 150 μm. The insulating layer 12 may contain a filler such as silica (SiO2).

[0016] The insulating layer 12 has a through hole 12z penetrating the insulating layer 12. An electronic component 60 is disposed in the through hole 12z. The electronic component 60 may be a passive component or an active component, or a mixture of both. The electronic component 60 is, for example, an IPD (Intelligent Power Device), a semiconductor chip, a capacitor, an inductor, a resistor, or the like. The planar shape of the through hole 12z is, for example, similar to the planar shape of the electronic component 60, and is larger than the electronic component 60. The electronic component 60 has, for example, an electrode 61 on the lower side and an electrode 62 on the upper side.

[0017] The embedding resin 13 is provided in the through hole 12z to cover the electronic component 60, and extends upward from the through hole 12z to cover the upper surface of the insulating layer 12, filling between the insulating layer 12, which is the first insulating layer, and the insulating layer 21, which is the second insulating layer. The lower surface of the electrode 61 of the electronic component 60 is exposed from the embedding resin 13. The lower surface of the electrode 61 of the electronic component 60 can be flush with the lower surface of the embedding resin 13, for example. The lower surface of the embedding resin 13 can be flush with the lower surface of the insulating layer 12. The material of the embedding resin 13 can be the same as that of the insulating layer 12, for example. The embedding resin 13 may be formed from a material different from that of the insulating layer 12. The thickness of the embedding resin 13 at the portion laminated on the upper surface of the insulating layer 12 can be, for example, about 20 to 50 μm. The embedding resin 13 may contain a filler such as silica (SiO2).

[0018] The insulating layer 12 and the embedded resin 13 are interlayer insulating layers located between the wiring layer 11 and the wiring layer 14. The insulating layer 12 and the embedded resin 13 are provided with a via hole 13x that penetrates the insulating layer 12 and the embedded resin 13 and exposes the upper surface of the wiring layer 11. The embedded resin 13 is also provided with a via hole 13y that penetrates the embedded resin 13 and exposes the upper surface of the electrode 62 of the electronic component 60. The via holes 13x and 13y can be inverted truncated cone-shaped recesses in which the diameter of the opening that opens on the second wiring structure 2 side is larger than the diameter of the bottom of the opening formed by the upper surface of the wiring layer 11 and the upper surface of the electrode 62.

[0019] The wiring layer 14 is formed on the upper side of the insulating layer 12 and the embedding resin 13, and inside the insulating layer 12 and the embedding resin 13. The wiring layer 14 is configured to include via wiring filled in the via holes 13x and the via holes 13y, and a wiring pattern formed on the upper surface of the embedding resin 13. The wiring pattern includes a portion electrically connected to the wiring layer 11 through the via wiring filling the via holes 13x. The wiring pattern also includes a portion electrically connected to the electrode 62 of the electronic component 60 through the via wiring filling the via holes 13y. The material of the wiring layer 14 and the thickness of the wiring pattern can be, for example, the same as those of the wiring layer 11. The lines / spaces of the wiring pattern of the wiring layer 14 can be, for example, the same as those of the wiring layer 11.

[0020] The second wiring structure 2 is a wiring structure in which a wiring layer and an insulating layer are laminated. The wiring layer of the second wiring structure 2 may be referred to as a second wiring layer, the insulating layer of the second wiring structure 2 may be referred to as a second insulating layer, and the via wiring of the second wiring structure 2 may be referred to as a second via wiring. In the example of FIG. 1, the second wiring structure 2 has a wiring layer 22 and a wiring layer 24 as the second wiring layer, and insulating layers 21 and 23 as the second insulating layer. In the second wiring structure 2, the number of layers of the second wiring layer and the second insulating layer is not limited to the example of FIG. 1.

[0021] The wiring width and wiring spacing of the second wiring layer constituting the second wiring structure 2 are smaller than the wiring width and wiring spacing of the first wiring layer constituting the first wiring structure 1. In other words, the second wiring layer is a fine wiring layer having a higher wiring density than the first wiring layer.

[0022] The insulating layer 21 is provided on the upper surface of the embedding resin 13, and covers the upper surface and side surface of the wiring pattern constituting the wiring layer 14. The insulating layer 21 is an insulating layer mainly composed of, for example, a non-photosensitive resin. The insulating layer 21 can be mainly composed of, for example, a thermosetting non-photosensitive resin such as an epoxy resin, an imide resin, a phenol resin, or a cyanate resin. The insulating layer 21 may contain a filler such as silica (SiO2). The insulating layer 21 is an insulating layer that is thinner than the total thickness of the insulating layer 12 and the embedding resin 13. The thickness of the insulating layer 21 can be, for example, about 3 to 20 μm. The insulating layer 21 is provided with a via hole 21x that penetrates the insulating layer 21 and reaches the upper surface of the wiring layer 14.

[0023] The wiring layer 22 is formed on one side of the insulating layer 21 and is electrically connected to the wiring layer 14 of the first wiring structure 1. The wiring layer 22 fills the via holes 21x and extends onto the upper surface of the insulating layer 21. The portion filling the via holes 21x is a via wiring, and the portion extending onto the upper surface of the insulating layer 21 is a wiring pattern. The material of the wiring layer 22 can be, for example, mainly copper or the like. The thickness of the wiring pattern constituting the wiring layer 22 can be, for example, about 1 to 10 μm. The line / space of the wiring pattern constituting the wiring layer 22 can be, for example, about 1 μm / 1 μm to 8 μm / 8 μm.

[0024] The insulating layer 23 is provided on one surface of the insulating layer 21, and covers the upper surface and side surfaces of the wiring layer 22. The material and thickness of the insulating layer 23 can be, for example, the same as those of the insulating layer 21. The insulating layer 23 may contain a filler such as silica (SiO2). The insulating layer 23 is provided with a via hole 23x that penetrates the insulating layer 23 and reaches the upper surface of the wiring layer 22.

[0025] The wiring layer 24 is formed on one side of the insulating layer 23 and is electrically connected to the wiring layer 22. The wiring layer 24 fills the via holes 23x and extends to the upper surface of the insulating layer 23. The portion filling the via holes 23x is a via wiring, and the portion extending to the upper surface of the insulating layer 23 is a wiring pattern and an electrode. The material of the wiring layer 24, the thickness of the wiring pattern constituting the wiring layer 24, and the line / space of the wiring pattern constituting the wiring layer 24 can be, for example, the same as the wiring layer 22. The electrodes constituting the wiring layer 24 can be used to electrically connect to electronic components such as semiconductor chips. The wiring layer 24 is electrically connected to the electronic component 60 via the wiring layer 22 and the wiring layer 14.

[0026] The third wiring structure 3 is a wiring structure in which a wiring layer and an insulating layer are laminated. The wiring layer of the third wiring structure 3 may be referred to as a third wiring layer, and the insulating layer of the third wiring structure 3 may be referred to as a third insulating layer. In the example of FIG. 1, the third wiring structure 3 has a wiring layer 31 as the third wiring layer and an insulating layer 32 as the third insulating layer. In the third wiring structure 3, the number of layers of the third wiring layer and the third insulating layer is not limited to the example of FIG. 1.

[0027] The wiring width and wiring spacing of the second wiring layer constituting the second wiring structure 2 are smaller than the wiring width and wiring spacing of the third wiring layer constituting the third wiring structure 3. In other words, the second wiring layer is a fine wiring layer having a higher wiring density than the third wiring layer.

[0028] The third wiring structure 3 may be, for example, a well-known build-up wiring board, as long as it has a pad or the like connected to the first wiring structure 1. Therefore, in Fig. 1, only a portion of the third wiring structure 3 close to the first wiring structure 1 is shown, and the underlying insulating layer and wiring layer are not shown.

[0029] The wiring layer 31 is a wiring layer that is the uppermost layer of the third wiring structure 3. The wiring layer 31 includes at least a pad. The wiring layer 31 may include a wiring pattern in addition to the pad. The planar shape of the pad constituting the wiring layer 31 may be, for example, circular. The material of the wiring layer 31 may be, for example, copper (Cu) or the like.

[0030] The insulating layer 32 is an insulating layer that is the uppermost layer of the third wiring structure 3, and is a so-called solder resist layer or build-up resin layer. When the insulating layer 32 is a solder resist layer, the material of the insulating layer 32 can be, for example, a photosensitive insulating resin mainly composed of a phenolic resin or a polyimide resin. When the insulating layer 32 is a build-up resin layer, the material of the insulating layer 32 can be, for example, the same as the insulating layer 12 of the first wiring structure 1. The insulating layer 32 may contain a filler such as silica (SiO2). The insulating layer 32 has openings 32x, and the upper surfaces of the pads that constitute the wiring layer 31 are exposed in the openings 32x.

[0031] The metal layers 33 and 34 are provided as necessary. The metal layer 33 is laminated on the upper surface of the wiring layer 31 exposed in the opening 32x. The metal layer 34 is laminated on the upper surface of the metal layer 33 exposed in the opening 32x. An example of the metal layer 33 is a Ni layer. An example of the metal layer 34 is an Au layer or a Pd / Au layer (a metal layer formed by laminating a Pd layer and an Au layer in this order).

[0032] The metal layer 34 of the third wiring structure 3 and the wiring layer 11 of the first wiring structure 1 are electrically connected via a bonding member 70. For example, solder can be used as the bonding member 70. Examples of solder materials include an alloy containing Pb, an alloy of Sn and Cu, an alloy of Sn and Ag, and an alloy of Sn, Ag, and Cu. An underfill resin 80 may be provided between the upper surface of the insulating layer 32 of the third wiring structure 3 and the lower surfaces of the insulating layer 12 and the embedded resin 13 of the first wiring structure 1.

[0033] Thus, in wiring board 5, electronic component 60 is embedded in first wiring structure 1. Since second wiring structure 2 having fine wiring has a thin overall thickness, it is difficult to embed electronic component 60. In contrast, first wiring structure 1 has a thicker overall thickness than the second wiring structure, so electronic component 60 can be embedded therein.

[0034] The electronic component 60 is electrically connected to a semiconductor chip or the like mounted on the second wiring structure 2. At this time, since the second wiring structure 2 has a thin overall thickness, it is possible to shorten the distance in the thickness direction between the electronic component 60 and the semiconductor chip or the like. This also shortens the electrical path between the electronic component 60 and the semiconductor chip or the like, making it possible to reduce resistance loss. As a result, it is possible to improve power supply efficiency and stabilize the power supply.

[0035] Furthermore, many electronic components 60 can be built into wiring board 5 without increasing the size of the planar shape. If there is sufficient space, other electronic components can also be mounted on the upper surface of wiring board 5.

[0036] [Method of manufacturing wiring board] Next, a method for manufacturing the wiring board according to the first embodiment will be described. Figures 2 to 4 are diagrams illustrating the manufacturing process of the wiring board according to the first embodiment. Note that, although an example of the process for manufacturing one wiring board is shown here, the process may be such that a plurality of parts that will become the wiring board are manufactured and then diced into individual wiring boards.

[0037] First, in the step shown in FIG. 2(a), a patterned sacrificial layer 52 and wiring layer 11 are formed on a support 51. For example, a copper foil having a thickness of about 20 to 70 μm can be used as the support 51. To form the sacrificial layer 52 and wiring layer 11, for example, a dry film resist is placed on the upper surface of the support 51, and the dry film resist is exposed and developed to form a resist layer having openings in the portions where the sacrificial layer 52 and wiring layer 11 are to be formed. Next, the sacrificial layer 52 and wiring layer 11 are sequentially formed on the upper surface of the support 51 exposed in the openings of the resist layer by electrolytic plating method in which power is supplied from the support 51. The sacrificial layer 52 is a layer that is finally removed, and is formed from a material different from the wiring layer 11. The sacrificial layer 52 can be formed from, for example, nickel. The wiring layer 11 can be formed from, for example, copper. Thereafter, the resist layer is removed. The resist layer can be removed by, for example, a resist stripper.

[0038] 2(b), an insulating layer 12 is formed on the upper surface of the support 51 to cover the sacrificial layer 52 and the wiring layer 11. Specifically, for example, a film-like insulating resin in a semi-cured state containing a thermosetting resin as a main component is prepared. Then, this insulating resin is laminated on the upper surface of the support 51 and cured under heat and pressure to form the insulating layer 12. Alternatively, instead of laminating a film-like insulating resin, a liquid or paste-like insulating resin may be applied and then cured to form the insulating layer 12. The material and thickness of the insulating layer 12 are as described above.

[0039] 2(c), a through hole 12z is formed in the insulating layer 12, penetrating the insulating layer 12 and exposing the upper surface of the support 51. The through hole 12z can be formed by laser processing using, for example, a CO2 laser. A cavity for mounting an electronic component is formed by the upper surface of the support 51 and the inner side surface of the through hole 12z.

[0040] 2(d), an electronic component 60 having electrodes 61 and 62 is prepared. Then, the electronic component 60 is placed on the upper surface of the support 51 exposed inside the through hole 12z, with the electrode 61 facing the support 51. The electronic component 60 may be temporarily fixed to the upper surface of the support 51 using an adhesive.

[0041] 2(e), embedding resin 13 is formed, which is filled in through hole 12z to cover electronic component 60 and extends upward from through hole 12z to cover the upper surface of insulating layer 12. Specifically, for example, a film-like epoxy resin in a semi-cured state is laminated to cover electronic component 60 and cured to form embedding resin 13. Alternatively, instead of laminating a film-like epoxy resin, liquid or paste-like epoxy resin may be applied and cured to form embedding resin 13. The material and thickness of embedding resin 13 are as described above.

[0042] Next, in the step shown in FIG. 3(a), a via hole 13x is formed in the insulating layer 12 and the embedding resin 13, penetrating the insulating layer 12 and the embedding resin 13 to expose the upper surface of the wiring layer 11. Also, a via hole 13y is formed in the embedding resin 13, penetrating the embedding resin 13 to expose the upper surface of the electrode 62 of the electronic component 60. The via holes 13x and 13y can be inverted truncated cone-shaped recesses in which the diameter of the opening on the upper surface side of the embedding resin 13 is larger than the diameter of the bottom surface of the opening formed by the upper surface of the wiring layer 11 and the upper surface of the electrode 62. The via holes 13x and 13y can be formed by a laser processing method using, for example, a CO2 laser. After the via holes 13x and 13y are formed, it is preferable to perform a desmear process to remove resin residue attached to the surfaces of the wiring layer 11 and the electrode 62 exposed at the bottom of the via holes 13x and 13y.

[0043] 3(b), the wiring layer 14 is formed. The wiring layer 14 includes via wirings filled in the via holes 13x and 13y, and a wiring pattern formed on the upper surface of the embedding resin 13. The wiring pattern includes a portion electrically connected to the wiring layer 11 through the via wirings filling the via holes 13x. The wiring pattern also includes a portion electrically connected to an electrode 62 of the electronic component 60 through the via wirings filling the via holes 13y.

[0044] The wiring layer 14 can be formed using various wiring forming methods such as a semi-additive method or a subtractive method. For example, when the wiring layer 14 is formed by a semi-additive method, a seed layer is formed by electroless plating of copper, for example, on the upper surface of the embedded resin 13, the inner side surfaces of the via holes 13x and 13y, the upper surface of the wiring layer 11 exposed in the via hole 13x, and the upper surface of the electrode 62 exposed in the via hole 13y. Next, a plating resist pattern having an opening corresponding to the shape of the wiring pattern of the wiring layer 14 is formed on the seed layer, and then an electrolytic plating layer is deposited on the seed layer exposed in the opening of the plating resist pattern by electrolytic plating of copper or the like supplied from the seed layer. Next, the plating resist pattern is removed, and then etching is performed using the electrolytic plating layer as a mask to remove the seed layer exposed from the electrolytic plating layer, and the wiring layer 14 having the via wiring and the wiring pattern can be obtained. Through the above steps, the first wiring structure 1 is completed.

[0045] Next, in the step shown in FIG. 3(c), for example, an uncured insulating resin film that covers the upper and side surfaces of the wiring pattern of the wiring layer 14 is laminated on the embedding resin 13. Then, this insulating resin film is pressed against the embedding resin 13 while being heated to harden it, forming the insulating layer 21. At this time, in order to suppress the skin effect, it is preferable to select an insulating resin film with a low roughness of the upper surface Ra of 30 nm or less. It is more preferable to select an insulating resin film with a low roughness of Ra of 20 nm or less, and even more preferable to select an insulating resin film with a low roughness of Ra of 10 nm or less. Note that instead of laminating the insulating resin film, a liquid or paste insulating resin may be applied and then hardened to form the insulating layer 21. At this time, if the roughness of the upper surface of the insulating layer 21 is high, it is preferable to smooth it by chemical mechanical polishing (CMP method) or the like to suppress the skin effect, and to make the roughness of the upper surface of the insulating layer 21 as described above. The material and thickness of the insulating layer 21 are as described above.

[0046] 3(d), a via hole 21x is formed penetrating the insulating layer 21 to expose the upper surface of the wiring layer 14, and then the wiring layer 22 is formed. The via hole 21x can be formed by, for example, a laser processing method using a CO2 laser or the like. The wiring layer 22 can be formed by, for example, a semi-additive method similar to the wiring layer 14.

[0047] 4(a), the same steps as those shown in Fig. 3(c) and Fig. 3(d) are repeated to sequentially form an insulating layer 23 and a wiring layer 24. In this way, the second wiring structure 2 is completed.

[0048] Next, in the step shown in FIG. 4(b), the support 51 and the sacrificial layer 52 shown in FIG. 4(a) are removed. For example, when the support 51 is made of copper and the sacrificial layer 52 is made of nickel, the support 51 is first removed by an etching solution that can etch copper but cannot etch nickel. Next, the sacrificial layer 52 is removed by an etching solution that can etch nickel but cannot etch copper. At this time, if the wiring layer 11 is made of copper, the wiring layer 11 will not be removed even if the sacrificial layer 52 is removed. The lower surface of the wiring layer 11 is exposed at a position recessed toward the wiring layer 14 side from the lower surface of the insulating layer 12. The lower surface of the electrode 62 of the electronic component 60 is exposed to be substantially flush with the lower surface of the insulating layer 12.

[0049] Next, in the step shown in FIG. 4(c), the third wiring structure 3 is prepared, and the third wiring structure 3 and the first wiring structure 1 are electrically connected. Here, the third wiring structure 3 having the wiring layer 31, the insulating layer 32, and the metal layers 33 and 34 is prepared. The third wiring structure 3 can be fabricated, for example, by a well-known build-up method. After the third wiring structure 3 is prepared, the metal layer 34 of the third wiring structure 3 and the wiring layer 11 of the first wiring structure 1 are electrically connected via a bonding member 70 such as solder. If necessary, an underfill resin 80 is provided between the upper surface of the insulating layer 32 of the third wiring structure 3 and the lower surfaces of the insulating layer 12 and the embedded resin 13 of the first wiring structure 1. This completes the wiring board 5.

[0050] Modification of the First Embodiment In the modified example of the first embodiment, an example of a wiring board having a structure different from that of the first embodiment is shown. Note that in the modified example of the first embodiment, the description of the same components as those in the already described embodiment may be omitted.

[0051] Fig. 5 is a cross-sectional view illustrating a wiring board according to Modification 1 of the first embodiment. Wiring board 5A shown in Fig. 5 differs from wiring board 5 in that wiring layer 11 includes electronic component mounting pads 11p.

[0052] In the wiring board 5A, at least a part of the upper surface of the electronic component mounting pad 11p is exposed inside the through hole 12z, and a cavity is formed by the upper surface of the electronic component mounting pad 11p exposed inside the through hole 12z and the inner side surface of the through hole 12z. The electronic component 60 is disposed in this cavity. That is, the electronic component 60 is disposed on the upper surface of the electronic component mounting pad 11p exposed inside the through hole 12z. The electrode 62 of the electronic component 60 is electrically and mechanically connected to the electronic component mounting pad 11p via a conductive material such as solder. The electronic component mounting pad 11p constitutes a part of the electrical path connecting the electronic component 60 and the wiring layer 31.

[0053] 6A and 6B are diagrams illustrating a manufacturing process of a wiring board according to the first modified example of the first embodiment. The process shown in FIG. 6A is similar to the process shown in FIG. 2A, but differs in that a wiring layer 11 including an electronic component mounting pad 11p is formed on a support 51. Next, after forming an insulating layer in the same manner as in FIG. 2B, in the process shown in FIG. 6B, a through hole 12z is formed that penetrates the insulating layer 12 and exposes at least a part of the upper surface of the electronic component mounting pad 11p. A cavity for mounting an electronic component is formed by the upper surface of the electronic component mounting pad 11p and the inner side surface of the through hole 12z.

[0054] Next, in the step shown in Fig. 6(c), an electronic component 60 having electrodes 61 and 62 is prepared. Then, the electronic component 60 is placed on the upper surface of the electronic component mounting pad 11p exposed inside the through hole 12z, with the electrode 61 facing the electronic component mounting pad 11p. The electrode 62 of the electronic component 60 is electrically and mechanically connected to the electronic component mounting pad 11p via a conductive material such as solder. Next, in the step shown in Fig. 6(d), the same steps as those shown in Figs. 2(d) to 4(c) are performed to complete the wiring board 5A.

[0055] In this manner, electronic component mounting pads 11p may be provided, and electronic component 60 may be disposed on the upper surface of electronic component mounting pad 11p. In such a structure, bonding members 70 do not need to be directly connected to electrodes 61 of electronic component 60, and can be connected to the lower surface of electronic component mounting pad 11p. This provides a good connection between electronic component mounting pad 11p and bonding members 70. That is, a good connection between electronic component 60 and bonding members 70 is provided.

[0056] Fig. 7 is a cross-sectional view illustrating a wiring board according to Modification 2 of the first embodiment. Wiring board 5B shown in Fig. 7 differs from wiring board 5 in that first wiring structure 1 is replaced with first wiring structure 1B. First wiring structure 1B does not have embedding resin 13. Note that wiring board 5B may or may not have electronic component mounting pads 11p.

[0057] In the wiring board 5B, the embedding resin is formed integrally with the insulating layer 21 in contact with the insulating layer 12. That is, the insulating layer 21 also serves as the embedding resin, covers the upper surface of the insulating layer 12, and extends into the through hole 12z to cover the electronic component 60. The insulating layer 21 also serves as the embedding resin, extends from the through hole 12z to cover the upper surface of the insulating layer 12, and is filled between the insulating layer 12, which is the first insulating layer, and the insulating layer 23, which is the second insulating layer. The electrodes 61 of the electronic component 60 are directly connected to the wiring layer 22. The upper side of the electronic component 60 may or may not protrude above the upper surface of the insulating layer 12.

[0058] In the manufacturing method of the wiring board 5B, the step shown in Fig. 2(e) is not performed. In addition, in the step shown in Fig. 3(c), an insulating layer 21 is formed, which is filled in the through hole 12z to cover the electronic component 60 and extends upward from the inside of the through hole 12z to cover the upper surface of the insulating layer 12 and the upper surface of the wiring layer 14. The other steps can be the same as those in the manufacturing method of the wiring board 5.

[0059] In this way, the second insulating layer constituting the second wiring structure 2 may also serve as the embedding resin. In this case, the distance in the thickness direction from the wiring layer 24 to the electronic component 60 can be made shorter than in the case of the wiring board 5. This makes it possible to further shorten the electrical path between the electronic component 60 and the semiconductor chip or the like when a semiconductor chip or the like is mounted on the second wiring structure 2, thereby further reducing the resistance loss. In addition, since the process shown in FIG. 2(e) can be omitted, the manufacturing cost of the wiring board 5B can be reduced.

[0060] Fig. 8 is a cross-sectional view illustrating a wiring board according to Modification 3 of the first embodiment. Wiring board 5C shown in Fig. 8 differs from wiring board 5 in that first wiring structure 1 is replaced with a first wiring structure 1C.

[0061] The first wiring structure 1C is different from the first wiring structure 1 in that it has a wiring layer 15 and an insulating layer 16. In the wiring board 5C, the insulating layer 12 is a first interlayer insulating layer, and the insulating layer 16 and the embedding resin 13 are a second interlayer insulating layer. The insulating layer 16 is provided with a through hole 16z that exposes at least a part of the upper surface of the electronic component mounting pad 15p, and an electronic component 60 is disposed on the upper surface of the electronic component mounting pad 15p exposed inside the through hole 16z. The embedding resin 13 fills the through hole 16z to cover the electronic component 60, and extends upward from the through hole 16z to cover the upper surface of the insulating layer 16, and is filled between the insulating layer 16, which is the first insulating layer, and the insulating layer 21, which is the second insulating layer. The wiring board 5C may or may not have the electronic component mounting pad 15p.

[0062] 9A and 9B are diagrams illustrating a manufacturing process of a wiring board according to Modification 3 of the first embodiment. To manufacture a wiring board 5C, first, in the process shown in Fig. 9A, a sacrificial layer 52, a wiring layer 11, an insulating layer 12, a wiring layer 15, and an insulating layer 16 are sequentially formed on a support 51 by the same method as in the first embodiment. Then, a through hole 16z is formed in the insulating layer 16, and an electronic component 60 is disposed in the through hole 16z.

[0063] Next, in the step shown in Fig. 9(b), an embedding resin 13 is formed by a method similar to that of the first embodiment, filling the through hole 16z to cover the electronic component 60 and extending upward from the through hole 16z to cover the upper surface of the insulating layer 16. Thereafter, via holes 13x and 13y are formed, and further a wiring layer 14 is formed. Thereafter, in the step shown in Fig. 9(c), a second wiring structure 2 is formed on the first wiring structure 1 by a method similar to that of the first embodiment. Furthermore, the first wiring structure 1 and the third wiring structure 3 are joined by a method similar to that of the first embodiment, thereby completing a wiring board 5C.

[0064] In this way, the first wiring structure may have multiple insulating layers, in which case the electronic component 60 can be embedded in any of the insulating layers. The first wiring structure 1C may have three or more insulating layers. From the viewpoint of shortening the electrical path with a semiconductor chip or the like mounted on the second wiring structure 2 and suppressing resistance loss, when the first wiring structure 1C has multiple insulating layers, it is preferable that the electronic component 60 is disposed in a through hole penetrating the uppermost insulating layer.

[0065] Fig. 10 is a cross-sectional view illustrating a wiring board according to Modification 4 of the first embodiment. The wiring board 5D shown in Fig. 10 differs from the wiring board 5C in that the electronic component mounting pad 15p is not electrically connected to the wiring layer 11. That is, in the wiring board 5D, the electronic component 60 is electrically connected only to the wiring layer located above the wiring layer 15. In this case, an electronic component that does not have an electrode 61 may be disposed on the electronic component mounting pad 15p. In that case, the lower surface of the electronic component and the upper surface of the electronic component mounting pad 15p may be fixed with an insulating adhesive.

[0066] Fig. 11 is a cross-sectional view illustrating a wiring board according to Modification 5 of the first embodiment. Wiring board 5E shown in Fig. 11 differs from wiring board 5C in that first wiring structure 1C is replaced with first wiring structure 1E and second wiring structure 2 is replaced with second wiring structure 2E.

[0067] The first wiring structure 1E differs from the first wiring structure 1C in that the wiring layer 14 is replaced with via wiring 14E. The second wiring structure 2E differs from the second wiring structure 2 in that a wiring layer 25 is added. The via wiring 14E is an example of a first wiring layer. The wiring layer 25 is an example of a second wiring layer. The wiring board 5E may or may not have an electronic component mounting pad 15p.

[0068] The via wiring 14E fills the via holes 13x and 13y. The via wiring 14E does not have a portion extending onto the embedding resin 13. The upper surface of the via wiring 14E is exposed from the upper surface of the embedding resin 13 in contact with the insulating layer 21. The upper surface of the via wiring 14E is, for example, flush with the upper surface of the embedding resin 13 in contact with the insulating layer 21. The upper surfaces of the via wiring 14E and the embedding resin 13 are polished surfaces. Therefore, the upper surfaces of the via wiring 14E and the embedding resin 13 are smooth surfaces (low roughness surfaces) with few irregularities. The roughness of the upper surfaces of the via wiring 14E and the embedding resin 13 can be about 15 to 40 nm in terms of surface roughness Ra.

[0069] The wiring layer 25 is formed on the upper surface of the embedding resin 13 and the upper surface of the via wiring 14E. A part of the lower surface of the wiring layer 25 is in contact with the upper surface of the via wiring 14E, and the two are electrically connected. That is, the via wiring 14E is directly connected to the wiring layer 25, which is the lowermost second wiring layer. The wiring layer 25 includes a portion electrically connected to the wiring layer 15 through the via wiring 14E. Also, the wiring layer 25 includes a portion electrically connected to the electrode 62 of the electronic component 60 through the via wiring 14E. Also, the wiring layer 25 is electrically connected to the via wiring of the wiring layer 22. The material of the wiring layer 25 can be, for example, the same as that of the wiring layer 22. The thickness of the wiring layer 25 can be, for example, the same as that of the wiring pattern constituting the wiring layer 22. The line / space of the wiring layer 25 can be, for example, the same as the line / space of the wiring pattern constituting the wiring layer 22.

[0070] FIG. 12 is a diagram illustrating a manufacturing process of a wiring board according to the fifth modified example of the first embodiment. To manufacture a wiring board 5E, first, in the process shown in FIG. 12(a), a process similar to that shown in FIG. 9(b) is performed. Next, in the process shown in FIG. 12(b), the upper surface of the wiring layer 14 and the upper surface of the embedding resin 13 are polished to form a via wiring 14E. This completes the first wiring structure 1E. For example, a chemical mechanical polishing (CMP) method can be used for polishing. After polishing, the upper surface of the via wiring 14E and the upper surface of the embedding resin 13 can be made flush with each other, for example. The roughness of the upper surface of the via wiring 14E and the upper surface of the embedding resin 13 after polishing can be about 15 to 40 nm in terms of surface roughness Ra. The roughness of the lower surface of the embedding resin 13 is, for example, about 180 to 280 nm in terms of surface roughness Ra.

[0071] 12(c), a wiring layer 25 is formed on the upper surface of the via wiring 14E and the upper surface of the embedding resin 13. A part of the lower surface of the wiring layer 25 contacts the upper surface of the via wiring 14E, and the two are electrically connected. The wiring layer 25 can be formed by, for example, a semi-additive method similar to the wiring layer 14.

[0072] In the step shown in FIG. 12(a), the upper surface of the embedding resin 13 covering the electronic component 60 may have a concave shape. In this case, the upper surface of the wiring layer 14 located on the electronic component 60 is lower than the upper surface of the wiring layer 14 not located on the electronic component 60, so that the insulating layer 21 formed thereafter also has irregularities, making it difficult to form a fine wiring layer 22. Therefore, the step shown in FIG. 12(b) is provided to smooth the upper surface of the via wiring 14E and the upper surface of the embedding resin 13 and to make the roughness low. Then, the step shown in FIG. 12(c) is further provided to form a wiring layer 25 on the upper surface of the via wiring 14E and the upper surface of the embedding resin 13. This makes it possible to form a fine wiring layer 25. In addition, the height variation of the upper surface of the wiring layer 24 that becomes the external connection terminal is reduced, so that the connection reliability when connecting with the electrodes of the semiconductor chip can be improved.

[0073] The wiring boards 5, 5A, 5B, and 5D may also have a structure having the via wiring 14E. For example, when the wiring board 5 has the via wiring 14E, the upper surface of the via wiring 14E is exposed from the upper surface of the insulating layer 12 in contact with the insulating layer 21. The upper surface of the via wiring 14E is flush with the upper surface of the insulating layer 12 in contact with the insulating layer 21. The via wiring 14E is directly connected to the wiring layer 25, which is the lowermost second wiring layer. The manufacturing method of the wiring board 5B includes a step of forming the via wiring 14E having an upper surface flush with the upper surface of the insulating layer 12 in the insulating layer 12 in contact with the insulating layer 21.

[0074] Application Example of the First Embodiment In the application example of the first embodiment, an example of a semiconductor device in which a semiconductor chip is mounted on a wiring substrate is shown. Note that in the application example of the first embodiment, the description of the same components as those in the already described embodiment may be omitted.

[0075] Fig. 13 is a cross-sectional view illustrating a semiconductor device according to an application example of the first embodiment. Referring to Fig. 13, a semiconductor device 8 has the wiring substrate 5 shown in Fig. 1, a semiconductor chip 91, and bumps 95. The semiconductor chip 91 is mounted on the second wiring structure 2 of the wiring substrate 5.

[0076] The semiconductor chip 91 is, for example, a semiconductor integrated circuit (not shown) formed on a thinned semiconductor substrate (not shown) made of silicon or the like. Electrodes electrically connected to the semiconductor integrated circuit (not shown) are formed on the semiconductor substrate (not shown). The electrodes are connection terminals connected to the wiring substrate 5, and are, for example, copper posts. The semiconductor chip 91 may be, for example, a processor such as a CPU (Central Processing Unit) or a GPU (Graphics Processing Unit). The semiconductor chip 91 may be, for example, a memory such as an HBM (High Bandwidth Memory).

[0077] The electrodes of the semiconductor chip 91 are electrically connected to the wiring layer 24 of the wiring board 5 via bumps 95. The bumps 95 are, for example, solder bumps. Examples of the solder material that can be used include an alloy containing Pb, an alloy of Sn and Cu, an alloy of Sn and Ag, and an alloy of Sn, Ag, and Cu. An underfill resin may be filled between the semiconductor chip 91 and the upper surface of the wiring board 5.

[0078] In this way, by mounting a semiconductor chip on the wiring board 5 according to the first embodiment, a semiconductor device 8 can be realized. The wiring board 5 can be suitably used as an interposer substrate for high-speed data communication, for example, between a processor and a memory. Furthermore, by using the wiring board 5, the electrical path between the electronic component 60 and the semiconductor chip 91 is shortened and resistance loss is reduced, thereby improving power efficiency and stabilizing the power supply.

[0079] Although the preferred embodiments have been described in detail above, the present invention is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope of the claims. [Explanation of symbols]

[0080] 1, 1B, 1C, 1E First wiring structure 2,2E 2nd wiring structure 3 Third wiring structure 5,5A,5B,5C,5D,5E Wiring board 8 Semiconductor Devices 11,14,22,24,25,31 wiring layer 11p,15p Pads for mounting electronic components 12, 21, 23, 32 Insulating layer 12x, 13x, 13y, 21x, 21y, 23x Via Hole 12z through hole 13 Embedding resin 14E Via wiring 32x opening 33,34 Metal layer 60 Electronic Components 61,62 electrode 70 Joint materials 80 Underfill resin 91 Semiconductor Chips 95 Bump

Claims

1. a first wiring structure having a first wiring layer and a first insulating layer; a second wiring structure having a second wiring layer and a second insulating layer and laminated on one side of the first wiring structure; a third wiring structure having a third wiring layer and a third insulating layer and laminated on the other side of the first wiring structure; the second wiring layer has a higher wiring density than the first wiring layer and the third wiring layer; the first insulating layer includes a through hole penetrating the first insulating layer; an electronic component electrically connected to the second wiring layer is disposed in the through hole; An embedding resin that covers the electronic component is provided in the through hole, The embedding resin extends from within the through hole to cover the first insulating layer and fills a space between the first insulating layer and the second insulating layer.

2. the first wiring layer includes an electronic component mounting pad, At least a part of an upper surface of the electronic component mounting pad is exposed to the inside of the through hole, The wiring board according to claim 1 , wherein the electronic component is disposed on an upper surface of the electronic component mounting pad exposed to the inside of the through hole.

3. The wiring board according to claim 2 , wherein the electronic component mounting pad constitutes a part of an electrical path connecting the electronic component and the third wiring layer.

4. the embedding resin is formed integrally with the second insulating layer in contact with the first insulating layer, The wiring board according to claim 1 , wherein an electrode of the electronic component is directly connected to the second wiring layer.

5. the first wiring layer includes a first via wiring, an upper surface of the first via wiring is exposed from an upper surface of the first insulating layer that is in contact with the second insulating layer; an upper surface of the first via wiring is flush with an upper surface of the first insulating layer that is in contact with the second insulating layer; The wiring board according to claim 4 , wherein the first via wiring is directly connected to the lowermost second wiring layer.

6. the first wiring layer includes a first via wiring, an upper surface of the first via wiring is exposed from an upper surface of the embedding resin that is in contact with the second insulating layer; an upper surface of the first via wiring is flush with an upper surface of the embedding resin that is in contact with the second insulating layer; The wiring board according to claim 1 , wherein the first via wiring is directly connected to the lowermost second wiring layer.

7. the first wiring structure includes a plurality of the first insulating layers; The wiring board according to claim 1 , wherein the electronic component is disposed in the through hole penetrating the uppermost first insulating layer.

8. The wiring board according to claim 1 , a semiconductor chip mounted on the second wiring structure.

9. a first wiring structure including a first wiring layer and a first insulating layer; a second wiring structure including a second wiring layer and a second insulating layer, the second wiring structure being laminated on one side of the first wiring structure; a third wiring structure including a third wiring layer and a third insulating layer and laminated on the other side of the first wiring structure, forming the first insulating layer; forming the first wiring layer; forming a through hole penetrating the first insulating layer in the first insulating layer; placing an electronic component in the through hole; forming the second insulating layer, the second insulating layer being filled in the through hole to cover the electronic component and extending upward from the through hole to cover an upper surface of the first insulating layer; forming, on the second insulating layer, the second wiring layer electrically connected to the first wiring layer and the electronic component.

10. 10. The method for manufacturing a wiring board according to claim 9, wherein the step of forming the first wiring layer includes a step of forming a first via wiring in the first insulating layer in contact with the second insulating layer, the first via wiring having an upper surface flush with an upper surface of the first insulating layer.

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