Output amplifier circuit, display driver and display device

Abstract

PURPOSE: To provide an output amplifier circuit capable of suppressing display nonuniformity, a display driver including the output amplifier circuit, and a display device.CONSTITUTION: An output amplifier circuit comprises: first to n-th amplifiers receiving first to n-th input voltages and generating first to n-th output voltages respectively amplifying the input voltages; first to K-th bias circuits provided correspondingly to first to K-th amplifier groups, which are obtained by dividing the first to n-th amplifiers into K groups, and generating bias voltages for setting current values of operation currents of the amplifiers; first to K-th wires individually supplying the bias voltages generated by the first to K-th bias circuits to the first to K-th amplifier groups; and a switch circuit connecting one of the first to K-th wires with the other wire different from the one wire in an ON state.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to an output amplifier circuit including a plurality of amplifiers, and a display driver and a display device including the output amplifier circuit. [Background technology]

[0002] A display driver that drives a display panel, such as a liquid crystal display panel or an organic EL panel, includes a number of output amplifiers that amplify gradation voltages corresponding to the brightness levels represented by a video signal and supply them to source lines of the display panel.

[0003] In addition, with the recent trend toward larger screens and higher definition display panels, there is a demand for output amplifiers with shorter rise or fall times of the output voltage, i.e., higher slew rates. The output amplifier is, for example, an operational amplifier, and the slew rate can be increased by increasing the operating current flowing through its own differential stage, but this increases the power consumption accordingly.

[0004] Therefore, it is conceivable to control the magnitude of the operating current flowing through the differential stage of the output amplifier by using a bias voltage from outside the output amplifier so that it is large in the first half of one data period and small in the second half.For example, a bias circuit that generates a bias voltage is provided in the center of a semiconductor IC chip serving as a display driver, and the bias voltage is supplied from this bias circuit via a bias line to each of the output amplifiers arranged along the long side of the semiconductor IC chip.

[0005] However, due to large impedance caused by the resistance of the bias lines and the gate capacitance of the transistors contained in each output amplifier, there was a risk that a large discrepancy would occur in the timing of changing the bias voltage between the center and ends of the chip, resulting in uneven display.

[0006] Therefore, as a method of shortening the timing difference between the bias voltage changes at the center and ends of the chip, a display driver has been proposed in which output amplifiers are grouped and a sub-bias circuit that generates a bias voltage is provided for each group (see, for example, Patent Document 1).

[0007] In the display driver disclosed in Patent Document 1, output amplifiers are grouped, and a sub-bias circuit that generates a bias voltage for each group is provided. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] JP 2019-95545 A Summary of the Invention [Problem to be solved by the invention]

[0009] Incidentally, in the display driver disclosed in Patent Document 1, if variations in the bias voltages generated by each sub-bias circuit occur due to manufacturing variations or the like, this can lead to variations in the characteristics of the output amplifiers between groups, causing display unevenness.

[0010] Therefore, an object of the present invention is to provide an output amplifier circuit capable of suppressing display unevenness, and a display driver and a display device including the output amplifier circuit. [Means for solving the problem]

[0011] The output amplifier circuit of the present invention includes first to nth amplifiers receiving first to nth (n is an integer of 2 or more) input voltages for each data period of a predetermined cycle and generating first to nth output voltages by amplifying each of the input voltages, first to Kth bias circuits provided corresponding to first to Kth amplifier groups obtained by dividing the first to nth amplifiers into K (K is an integer of 2 or more) groups, each of which generates a bias voltage for setting a current value of an operating current of the amplifier, first to Kth wirings that are independent of each other and supply the bias voltages generated in the first to Kth bias circuits to the first to Kth amplifier groups, respectively, and a switch circuit that, when in an on state, connects one of the first to Kth wirings to another wiring different from the one wiring.

[0012] A display driver according to the present invention includes: a grayscale voltage generating circuit that generates first to nth (n is an integer of 2 or more) grayscale voltages, each having a voltage value corresponding to a luminance level of each pixel based on a video signal; first to nth amplifiers that receive the first to nth grayscale voltages and amplify them to supply first to nth output voltages to first to nth data lines of a display panel; first to Kth bias circuits that are provided corresponding to first to Kth amplifier groups obtained by dividing the first to nth amplifiers into K (K is an integer of 2 or more) groups, each of which generates a bias voltage for setting a current value of an operating current of the amplifier; first to Kth wirings that are independent of each other and supply the bias voltages generated in the first to Kth bias circuits to the first to Kth amplifier groups, respectively; and a switch circuit that, in an on state, connects one of the first to Kth wirings to another wiring different from the one wiring.

[0013] A display device according to the present invention includes a display panel having 1st to nth (n is an integer of 2 or more) data lines extending along the horizontal direction of a display screen, a grayscale voltage generating circuit generating 1st to nth grayscale voltages each having a voltage value corresponding to a luminance level of each pixel based on a video signal, 1st to nth amplifiers receiving the 1st to nth grayscale voltages and amplifying them to supply 1st to nth output voltages to the 1st to nth data lines of the display panel, 1st to Kth bias circuits provided corresponding to each of 1st to Kth amplifier groups obtained by dividing the 1st to nth amplifiers into K (K is an integer of 2 or more) groups, each of which generates a bias voltage for setting a current value of an operating current of the amplifier, 1st to Kth wirings independent of each other and supplying the bias voltages generated in the 1st to Kth bias circuits to the 1st to Kth amplifier groups, respectively, and a switch circuit for connecting one of the 1st to Kth wirings to another wiring different from the one wiring when in an on state. Effect of the Invention

[0014] In the present invention, 1st to nth amplifiers that receive 1st to nth input voltages for each data period of a predetermined cycle and generate 1st to nth output voltages by amplifying the input voltages are divided into K groups of 1st to Kth amplifiers, and 1st to Kth bias circuits that generate bias voltages for setting the current values ​​of the amplifiers' operating currents are provided corresponding to the groups. Furthermore, when the bias voltages generated by the 1st to Kth bias circuits are supplied to the 1st to Kth amplifier groups via the 1st to Kth wirings, a switch circuit is provided that connects one of the 1st to Kth wirings to another wiring different from the one wiring.

[0015] As a result, even if there is variation in the bias voltages generated by each of the first to Kth bias circuits, the difference in voltage value between the bias voltages generated by each bias circuit will disappear just before the end of each data period, thereby reducing display unevenness on the display screen. [Brief description of the drawings]

[0016] [Figure 1]1 is a block diagram showing a configuration of an output amplifier circuit 100_1 as a first embodiment of the output amplifier circuit according to the present invention. [Diagram 2] 1 is a circuit diagram showing the internal configuration of an amplifier AP1 selected from amplifiers AP1 to APn. [Diagram 3] 4 is a circuit diagram showing the internal configuration of each of the sub-bias circuits SB1 to SB3. FIG. [Figure 4] 11 is a time chart showing an example of an internal operation of the output amplifier circuit 100_1. [Diagram 5] 13 is a time chart showing another example of the internal operation of the output amplifier circuit 100_1. [Figure 6] FIG. 1 is a block diagram showing a configuration of an output amplifier circuit 100_2 as a second embodiment of the output amplifier circuit according to the present invention. [Figure 7] 1 is a block diagram showing a configuration of a display device having a display driver including an output amplifier circuit 100_1 or 100_2. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. EXAMPLES

[0018] FIG. 1 is a block diagram showing a configuration of an output amplifier circuit 100_1 as a first embodiment of the output amplifier circuit according to the present invention.

[0019] The output amplifier circuit 100_1 is provided, for example, in a display driver that drives a display panel, and receives n (n is an integer equal to or greater than 2) input voltages V1 to Vn as gradation voltages corresponding to the luminance levels represented by a video signal, and outputs the amplified voltages to the display panel as output voltages G1 to Gn that drive the display panel.

[0020] The output amplifier circuit 100_1 is formed on a semiconductor IC chip, and includes a main bias circuit MB_1, sub-bias circuits SB1 to SB3, a control unit CN_1, and an output amplifier unit OBLK_1.

[0021] The main bias circuit MB_1 includes a current mirror circuit CM_1 and a reference current source IG_1.

[0022] The reference current source IG_1 generates a reference current Io having a predetermined constant current value.

[0023] The current mirror circuit CM_1 generates three systems of bias control currents I1 to I3, each of which is a copy of a reference current Io. The current mirror circuit CM_1 supplies the bias control current I1 to the sub-bias circuit SB1 via a wiring BL1, supplies the bias control current I2 to the sub-bias circuit SB2 via a wiring BL2, and supplies the bias control current I3 to the sub-bias circuit SB3 via a wiring BL3.

[0024] The control unit CN_1 receives a clock signal CLK as a clock signal with a predetermined period, and supplies a bias control signal PWRC that specifies the voltage value of the bias voltage to the sub-bias circuits SB1 to SB3 at the timing of the clock signal CLK. Furthermore, the control unit CN_1 supplies a switch control signal SWC that sets a switch to an on or off state to the output amplifier unit OBLK_1.

[0025] The output amplifier section OBLK_1 includes amplifiers AP1 to APn and switch circuits SW12 and SW23.

[0026] The amplifiers AP1 to APn receive input voltages V1 to Vn for each data period of a predetermined cycle separated by the rising edge (or falling edge) of the clock signal CLK. The amplifiers AP1 to APn then amplify the input voltages V1 to Vn individually to generate n voltages obtained as output voltages G1 to Gn, and output the voltages via output terminals T1 to Tn of the semiconductor IC chip. Each of the amplifiers AP1 to APn is, for example, an operational amplifier having the same configuration. Note that the data period of the predetermined cycle may be set such that the start timing of the data period of each of the amplifiers AP1 to APn is shifted little by little for each of a predetermined number of the amplifiers AP1 to APn, in order to suppress the influence of noise due to the simultaneous operation of the amplifiers AP1 to APn.

[0027] In the amplifiers AP1 to APn, the operating currents flowing through their own differential stages and current mirror stages are set by the bias voltages VB1N to VB3N and VB1P to VB3P supplied from the sub-bias circuits SB1 to SB3. As a result, each of the amplifiers AP1 to APn adjusts its own output slew rate based on the above-mentioned bias voltage group (VB1N to VB3, VB1P to VB3P).

[0028] The amplifiers AP1 to APn are divided into a first group including amplifiers AP1 to APr (r is an integer less than n), a second group including amplifiers AP(r+1) to APg (g is an integer greater than r and less than n), and a third group including amplifiers AP(g+1) to APn.

[0029] In this case, the amplifiers AP1 to APr belonging to the first group receive the bias voltages VB1N to VB3N and VB1P to VB3P generated by the sub-bias circuit SB1 via a first wiring group L1 consisting of six wirings. The amplifiers AP(r+1) to APg belonging to the second group receive the bias voltages VB1N to VB3N and VB1P to VB3P generated by the sub-bias circuit SB2 via a second wiring group L2 consisting of six wirings. The amplifiers AP(g+1) to APn belonging to the third group receive the bias voltages VB1N to VB3N and VB1P to VB3P generated by the sub-bias circuit SB3 via a third wiring group L3 consisting of six wirings.

[0030] The switch circuit SW12 is composed of six switch elements that, when in the on state, electrically connect the first wiring group L1 and the second wiring group L2 so that the wiring groups supply the same bias voltage, and, when in the off state, cut off the connection between the first wiring group L1 and the second wiring group L2.

[0031] The switch circuit SW23 is composed of six switch elements that, when in an on state, electrically connect the second wiring group L2 and the third wiring group L3 to each other so that the same bias voltage is supplied thereto, and, when in an off state, cuts off the connection between the second wiring group L2 and the third wiring group L3.

[0032] The switch circuits SW12 and SW23 are set to the above-mentioned on or off state in response to a switch control signal SWC supplied from the control unit CN_1.

[0033] Each of the sub-bias circuits SB1 to SB3 has the same internal configuration, and is provided corresponding to each of the first to third groups into which the amplifiers AP1 to APn are divided, as described above.

[0034] The sub-bias circuit SB1 receives the bias control current I1 sent from the main bias circuit MB_1 via a wiring BL1. The sub-bias circuit SB1 generates bias voltages VB1N-VB3N and VB1P-VB3P having voltage values ​​corresponding to the current value of the bias control current I1, and supplies them to the amplifiers AP1-APr belonging to the first group via a first wiring group L1.

[0035] The sub-bias circuit SB2 receives the bias control current I2 sent from the main bias circuit MB_1 via a wiring BL2. The sub-bias circuit SB2 generates bias voltages VB1N-VB3N and VB1P-VB3P having voltage values ​​corresponding to the current value of the bias control current I2, and supplies each of them to the amplifiers AP(r+1)-APg belonging to the second group via a second wiring group L2.

[0036] The sub-bias circuit SB3 receives the bias control current I3 sent from the main bias circuit MB_1 via a wiring BL3. The sub-bias circuit SB3 generates bias voltages VB1N-VB3N and VB1P-VB3P having voltage values ​​corresponding to the current value of the bias control current I3, and supplies each of them to the amplifiers AP(g+1)-APn belonging to the third group via a second wiring group L2.

[0037] The sub-bias circuits SB1 to SB3 have a function of adjusting the voltage values ​​of the bias voltages (VB1N to VB3N, VB1P to VB3P) in response to the bias control signal PWRC.

[0038] The detailed configurations of the amplifiers AP1 to APn and the sub-bias circuits SB1 to SB3 shown in FIG. 1 will be described below.

[0039] FIG. 2 is a circuit diagram showing the internal configuration of the amplifier AP1 selected from the amplifiers AP1 to APn.

[0040] The amplifier AP1 has a differential stage including P-channel transistors U2 to U4 and N-channel transistors J2 to J4, an output stage including a P-channel transistor U11 and an N-channel transistor J11, cascode current mirror circuits 30 and 40, and floating current sources 50 and 60.

[0041] A power supply voltage VDD is applied to the source of the transistor U2 of the differential stage, and a bias voltage VB1P is supplied to the gate. The transistor U2 generates an operating current Iu1 having a current value corresponding to the bias voltage VB1P, and supplies this to the sources of the transistors U3 and U4. The transistor U3 receives the input voltage V1 at its gate. The transistor U4 receives the output voltage G1, which is the output of the amplifier AP1, at its gate. The transistors U3 and U4 generate currents NCM1 and NCM2 by dividing the operating current Iu1 supplied from the transistor U2 by two in accordance with the voltage ratio between the input voltage V1 and the output voltage G1. The transistors U3 and U4 supply the currents NCM1 and NCM2 to the nodes n3 and n4 of the cascode current mirror circuit 40 via their respective drains. That is, the transistor U3 supplies the current NCM2 corresponding to the voltage value of the input voltage V1 to the node n4 of the cascode current mirror circuit 40. The transistor U4 supplies a current NCM1 corresponding to the voltage value of the output voltage G1 to the node n3 of the cascode current mirror circuit 40.

[0042] A ground voltage VSS is applied to the source of the transistor J2 of the differential stage, and a bias voltage VB1N is supplied to the gate. The drain of the transistor J2 is connected to the sources of the transistors J3 and J4. The transistor J2 generates an operating current Ij1 having a current value corresponding to the bias voltage VB1N, and draws it from the sources of the transistors J3 and J4. The transistor J3 receives an input voltage V1 at its gate. The transistor J4 receives an output voltage G1 at its gate. The transistors J3 and J4 generate currents PCM1 and PCM2 by dividing the operating current Ij1 by two based on the voltage ratio between the input voltage V1 and the output voltage G1 received at their respective gates. The transistor J3 draws a current PCM2 corresponding to the input voltage V1 from the node n2 of the cascode current mirror circuit 30, and supplies it to the drain of the transistor J2. The transistor J4 draws a current PCM1 corresponding to the output voltage G1 from the node n1 of the cascode current mirror circuit 30, and supplies it to the drain of the transistor J2.

[0043] In the above-mentioned differential stage, the current value of the operating current Iu1 is adjusted by the bias voltage VB1P, and further, the current value of the above-mentioned operating current Ij1 is adjusted by the bias voltage VB1N. As a result, for example, the lower the voltage value of the bias voltage VB1P, the larger the current is supplied to the nodes n3 and n4 of the cascode current mirror circuit 40. Also, the higher the voltage value of the bias voltage VB1N, the larger the current is drawn from the nodes n1 and n2 of the cascode current mirror circuit 30.

[0044] The cascode current mirror circuit 30 includes P-channel transistors U5 to U8, and the cascode current mirror circuit 40 includes N-channel transistors J7 to J10. The floating current source 50 includes a P-channel transistor U9 and an N-channel transistor J5, and the floating current source 60 includes a P-channel transistor U10 and an N-channel transistor J6.

[0045] The power supply voltage VDD is applied to the sources of the transistors U5 and U6 of the cascode current mirror circuit 30, and the gates of the transistors are connected to each other. The drain of the transistor U5 is connected to the source of the transistor U7 via a node n1. The drain of the transistor U6 is connected to the source of the transistor U8 via a node n2. The bias voltage VB2P is applied to both the gates of the transistors U7 and U8. The drain of the transistor U7 is connected to the gates of the transistors U5 and U6, the source of the transistor U9 of the floating current source 50, and the drain of the transistor J5 via a node n5.

[0046] The drain of transistor U8 is connected to the source of transistor U10 and the drain of transistor J6 of floating current source 60 via node n6 as a high-potential drive node. A bias voltage VB3P is applied to each of the gates of transistors U9 and U10, and a bias voltage VB3N is applied to each of the gates of transistors J5 and J6. The drain of transistor U9 and the source of transistor J5 are connected to the drain of transistor J7 of cascode current mirror circuit 40 via node n7. The drain of transistor U10 and the source of transistor J6 are connected to the drain of transistor J8 of cascode current mirror circuit 40 via node n8 as a low-potential drive node.

[0047] A bias voltage VB2N is applied to the gates of the transistors J7 and J8. The source of the transistor J7 is connected to the drain of the transistor J9 via a node n3. The source of the transistor J8 is connected to the drain of the transistor J10 via a node n4. The ground voltage VSS is applied to the sources of the transistors J9 and J10, and the gates of the transistors J9 and J10 are connected to the drain of the transistor J7.

[0048] In the above-mentioned cascode current mirror circuits 30 and 40 and floating current sources 50 and 60, an operating current Iu2 having a current value corresponding to the difference between the currents PCM1 and PCM2 supplied from the differential stage flows to node n6, and an operating current Ij2 having a current value corresponding to the difference between the currents NCM1 and NCM2 supplied from the differential stage flows to node n8.

[0049] As a result, in the cascode current mirror circuits 30 and 40 and the floating current sources 50 and 60, an operating current Iu2 corresponding to the difference between the currents PCM1 and PCM2 is supplied to or drawn from the node n6, thereby generating a high-potential output drive voltage PG at the node n6. The output drive voltage PG is supplied to the gate of the transistor U11 in the output stage. Also, in the cascode current mirror circuits 30 and 40 and the floating current sources 50 and 60, an operating current Ij2 corresponding to the difference between the currents NCM1 and NCM2 is supplied to or drawn from the node n8, thereby generating a low-potential output drive voltage NG at the node n8. The output drive voltage NG is supplied to the gate of the transistor J11 in the output stage.

[0050] The power supply voltage VDD is applied to the source of transistor U11 in the output stage, and a current corresponding to the output drive voltage PG received at its gate is generated and supplied to output node nZ, thereby increasing the voltage at output node nZ. The ground voltage VSS is applied to the source of transistor J11, and a current corresponding to the output drive voltage NG received at its gate is drawn from output node nZ, thereby lowering the voltage at output node nZ.

[0051] The above-mentioned operation of the transistors U11 and J11 generates an output voltage G1 at the output node nZ, which is then output via the output terminal. At this time, the output voltage G1 is fed back to the gate of the high-potential side transistor U4 of the differential stage and the gate of the low-potential side transistor J4.

[0052] 2, the current values ​​of the operating currents Iu2 and Ij2 flowing through the nodes n6 and n8, which serve as drive nodes for driving the transistors U11 and J11 in the output stage, are adjusted by the magnitudes of the bias voltages VB1N-VB3N and VB1P-VB3P. This changes the magnitude of the current sent to and drawn from the output node nZ, adjusting the slew rate of the amplifier AP1.

[0053] FIG. 3 is a circuit diagram showing the internal configuration of the sub-bias circuit SB1 selected from the sub-bias circuits SB1 to SB3.

[0054] The sub-bias circuit SB1 has a voltage adjustment unit VCN including P-channel MOS transistors Q1 to Q5 and switch circuits SW1 to SW3, P-channel MOS transistors Q6 to Q12, and N-channel MOS transistors R1 to R10.

[0055] The transistor R1 receives at its drain a bias control current I1 supplied from the main bias circuit MB_1 via a line BL1. The drain and gate of the transistor R1 are connected to the gate of the transistor R2, and a ground voltage VSS is applied to the sources of the transistors R1 and R2. The drain of the transistor R2 is connected to the voltage adjustment unit VCN via a node w2.

[0056] With this configuration, the transistor R2 generates a current I1a corresponding to the bias control current I1 and causes this current to flow to the node w2.

[0057] The gates of the transistors Q1 and Q2 of the voltage adjustment unit VCN are connected to a node w2. A power supply voltage VDD is applied to the sources of the transistors Q1 and Q2. The drain of the transistor Q2 is connected to the drain and gate of the transistor R3 via a node w3. A ground voltage VSS is applied to the source of the transistor R3.

[0058] With this configuration, the transistor Q2 generates the reference bias voltage VQ at the node w3 by sending a current I1b corresponding to the above-mentioned current I1a to the node w3.

[0059] A power supply voltage VDD is applied to the source of each of the transistors Q3 to Q5 of the voltage adjustment unit VCN, and each of the drains is connected to a node w3.

[0060] The switch circuit SW1 is set to a state in which the power supply voltage VDD is supplied to the gate of the transistor Q3 (referred to as an off state) or a state in which the node w2 is connected to the gate of the transistor Q3 (referred to as an on state) in response to the bias control signal PWRC. The switch circuit SW2 is set to a state in which the power supply voltage VDD is supplied to the gate of the transistor Q4 (referred to as an off state) or a state in which the node w2 is connected to the gate of the transistor Q3 (referred to as an on state) in response to the bias control signal PWRC. The switch circuit SW3 is set to a state in which the power supply voltage VDD is supplied to the gate of the transistor Q5 (referred to as an off state) or a state in which the node w2 is connected to the gate of the transistor Q5 (referred to as an on state) in response to the bias control signal PWRC.

[0061] The transistor Q3 is turned on only when the switch circuit SW1 is turned on, and sends a current Ic corresponding to the current I1a to the node w3. The transistor Q4 is turned on only when the switch circuit SW2 is turned on, and sends a current Ic corresponding to the current I1a to the node w3. The transistor Q5 is turned on only when the switch circuit SW3 is turned on, and sends a current Ic corresponding to the current I1a to the node w3.

[0062] With the above-mentioned configuration, the voltage adjustment unit VCN outputs to a node w3 a composite current It obtained by combining a current I1b corresponding to the bias control current I1 and a current Ic output from the transistors Q3 to Q5 that are set to an on-state in response to the bias control signal PWRC. The voltage value of the reference bias voltage VQ generated by outputting the composite current It to the node w3 is adjusted.

[0063] For example, when voltage adjustment unit VCN receives bias control signal PWRC indicating that the number of transistors Q3 to Q5 to be set to the on state is zero, the combined current It flowing through node w3 becomes current I1b.

[0064] In addition, when the voltage adjustment unit VCN receives a bias control signal PWRC indicating that the number of transistors Q3 to Q5 to be set to the on state is "2", for example, only Q3 and Q4 of the transistors Q3 to Q5 are set to the on state. As a result, the composite current It becomes a current (I1b+2·Ic) obtained by adding the current I1b to the current Ic sent from each of the transistors Q3 and Q4.

[0065] That is, the voltage adjustment unit VCN shown in FIG. 3 adjusts the voltage value of the reference bias voltage VQ in four stages in response to the bias control signal PWRC.

[0066] In Fig. 3, the gates of the transistors R4 to R7 are connected to the gate of the transistor R3 and to a node w3, and the ground voltage VSS is applied to the sources of the transistors R4 to R7. The drain of the transistor R4 is connected to the gate and drain of the transistor Q6 via a node w4. The drain of the transistor R5 is connected to the gate and drain of the transistor Q7 via a node w5. The drain of the transistor R6 is connected to the gate and drain of the transistor Q8 via a node w6. The power supply voltage VDD is applied to the sources of the transistors Q6 to Q8.

[0067] The drain of transistor R7 is connected to the drain of transistor Q9 and the gates of transistors Q9 to Q12. A power supply voltage VDD is applied to the sources of transistors Q9 to Q12. The drain of transistor Q10 is connected to the gate and drain of transistor R8 via node w7. The drain of transistor Q11 is connected to the gate and drain of transistor R9 via node w8. The drain of transistor Q12 is connected to the gate and drain of transistor R9 via node w9. A ground voltage VSS is applied to the sources of transistors R8 to R10.

[0068] In the circuit consisting of the above-mentioned transistors R4 and Q6, the transistor R4 passes a current corresponding to the reference bias voltage VQ supplied to its gate through the node w4. The voltage generated at the node w4 is supplied to the amplifiers AP1 to APr as the bias voltage VB1P.

[0069] In the circuit consisting of the transistors R5 and Q7, the transistor R5 passes a current corresponding to the reference bias voltage VQ supplied to its gate through the node w5. The voltage generated at the node w5 is supplied to the amplifiers AP1 to APr as the bias voltage VB2P.

[0070] In the circuit consisting of the transistors R6 and Q8, the transistor R6 passes a current corresponding to the reference bias voltage VQ supplied to its gate through the node w6. The voltage generated at the node w6 is supplied to the amplifiers AP1 to APr as the bias voltage VB3P.

[0071] The transistor R7 passes a current corresponding to the reference bias voltage VQ supplied to its gate through the transistor Q9, whereby the current corresponding to the reference bias voltage VQ is sent from the drains of the transistors Q10 to Q12 to the nodes w7 to w9, respectively.

[0072] At this time, the transistor Q10 sends a current corresponding to the reference bias voltage VQ to the node w7, and the voltage generated at the node w7 is supplied to the amplifiers AP1 to APr as the bias voltage VB1N. Also, the transistor Q11 sends a current corresponding to the reference bias voltage VQ to the node w8, and the voltage generated at the node w8 is supplied to the amplifiers AP1 to APr as the bias voltage VB2N. Also, the transistor Q12 sends a current corresponding to the reference bias voltage VQ to the node w9, and the voltage generated at the node w9 is supplied to the amplifiers AP1 to APr as the bias voltage VB3N.

[0073] In this way, the sub-bias circuit SB1 generates the bias voltages VB1N-VB3N and VB1P-VB3P by performing current-voltage conversion processing on the bias control current I1. Furthermore, the sub-bias circuit SB1 adjusts the voltage values ​​of each of the six bias voltages VB1N-VB3N and VB1P-VB3P in response to the bias control signal PWRC.

[0074] In addition, by adopting a configuration similar to that shown in Figure 3 in the sub-bias circuits SB2 and SB3, similar to the sub-bias circuit SB1, bias voltages VB1N-VB3N and VB1P-VB3P are generated based on the bias control currents I2 and I3 received by each of them, and the voltage values ​​of each bias voltage are adjusted based on the bias control signal PWRC.

[0075] Next, the internal operation of the output amplifier circuit 100_1 will be described in detail.

[0076] Fig. 4 is a time chart showing an example of the internal operation (CLK, PWRC, SWC, VBx, V1, G1) of the output amplifier circuit 100_1. In Fig. 4, VBx collectively represents the bias voltages VB1N to VB3N, VB1P to VB3P generated in each of the sub-bias circuits SB1 to SB3.

[0077] The control unit CN_1 generates a bias control signal PWRC of logic level 1 that specifies a predetermined first voltage value that makes the amplifier have a high slew rate as the voltage value of the bias voltage over a predetermined first period PE1 from time t0 of the rising edge of the clock signal CLK, and supplies this to the sub-bias circuits SB1 to SB3. Thus, over the first period PE1 shown in FIG. 4, the sub-bias circuits SB1 to SB3 supply bias voltages VBx (VB1N to VB3N, VB1P to VB3P) having a high voltage value Vbxb to the amplifier groups belonging to the respective groups in accordance with the bias control signal PWRC.

[0078] Then, during a second period PE2 from time t1 when the first period PE1 has elapsed to time t2 of the rising edge of the next clock signal CLK, the control unit CN_1 supplies the sub-bias circuits SB1 to SB3 with a bias control signal PWRC of logic level 0 that specifies a predetermined second voltage value that reduces the slew rate of the amplifier as the voltage value of the bias voltage. Thus, during the second period PE2 shown in FIG. 4, the sub-bias circuits SB1 to SB3 supply bias voltage groups VBx (VB1N to VB3N, VB1P to VB3P) having a low voltage value Vbxa lower than the above-mentioned high voltage value Vbxb to the amplifier groups belonging to the respective groups in accordance with the bias control signal PWRC.

[0079] According to the series of operations described above, as shown in FIG. 4, the operating current flowing in each amplifier AP from the rising edge t0 of the clock signal CLK to the first period PE1 is greater than the operating current flowing in each amplifier AP in the second period PE2 following the first period PE1.

[0080] As a result, during the rise or fall interval of the output voltage (for example, the output voltage G1 shown in Figure 4) where a high-speed response is required, the slew rate of the amplifier AP becomes high, and the rise or fall time of the output voltage output from the amplifier AP also becomes short.

[0081] On the other hand, in a second period PE2 from the end time t1 of the first period PE1 to the rising edge time t2 of the next clock signal CLK, the operating current flowing in each amplifier AP is smaller than the operating current flowing in each amplifier AP in the first period PE1.

[0082] As a result, during the constant voltage value section (PE2) of the output voltage where high-speed response is not required, the power consumed by the amplifier AP is reduced.

[0083] In this way, in the output amplifier circuit 100_1, the bias voltage that determines the operating current in each of the amplifiers AP1 to APn is adjusted in accordance with the bias control signal PWRC, thereby controlling (changing) the slew rate of each amplifier, thereby making it possible to achieve both high-speed response and low power consumption.

[0084] Furthermore, in the output amplifier circuit 100_1, as shown in FIG. 4, the control unit CN_1 sets the switch circuits SW12 and SW23 to the on state for a predetermined period (ts to t2) in the latter half of the second period PE2 for each data period.

[0085] This makes it possible to reduce the voltage difference in the bias voltages between groups even when bias voltages (VB1N-VB3N and VB1P-VB3P) are supplied to the amplifiers AP1-APn individually for each of the first to third groups into which the amplifiers AP1-APn are divided. Therefore, even if there is variation in the voltage values ​​of the bias voltages (VB1N-VB3N and VB1P-VB3P) between the sub-bias circuits SB1-SB3, the difference in voltage values ​​disappears immediately before the end of each data period, reducing display unevenness on the display screen.

[0086] When the six switch elements included in each of the switch circuits SW12 and SW23 have an on-resistance higher than a predetermined value, the control unit CN_1 may set the switch circuits SW12 and SW23 to the on state throughout the first period PE1 and the second period PE2. In this case, six high-resistance elements may be used instead of the six switch elements included in each of the switch circuits SW12 and SW23.

[0087] FIG. 5 is a time chart showing another example of the internal operations (CLK, PWRC, SWC, VBx, V1, G1) of the output amplifier circuit 100_1.

[0088] 5, at time tP, which is a predetermined time before the start time t0 of each data period, the control unit CN_1 switches the bias control signal PWRC from logic level 0, which causes the amplifier to have a low slew rate, to logic level 1, which causes the amplifier to have a high slew rate. The on / off switching timing of the switch circuits SW12 and SW23 by the switch control signal SWC is the same as that shown in FIG.

[0089] According to the operation shown in FIG. 5, even if the output voltage of each amplifier fluctuates slightly due to external noise (e.g., coupling noise due to changes in the gate voltage) during the second period PE2 when the bias voltage is low, it is possible to restore the output voltage to the desired voltage value.

[0090] In addition, since each amplifier is set to a high slew rate state by the bias control signal PWRC before the start of each data period, each amplifier operates at a high slew rate without causing a delay in response to the change in output voltage immediately after the start of one data period. This makes it possible to eliminate the effect of a response delay from the start of the adjustment process to change the slew rate of the amplifier in response to the bias control signal PWRC until the bias voltage actually changes. EXAMPLES

[0091] FIG. 6 is a block diagram showing a configuration of an output amplifier circuit 100_2 as a second embodiment of the output amplifier circuit according to the present invention.

[0092] The output amplifier circuit 100_2 employs sub-bias circuits SB1a to SB3a instead of the sub-bias circuits SB1 to SB3, employs a current mirror circuit CM_2 instead of the current mirror circuit CM_1, and is identical to the configuration (IG_1, CN_1, OBLK_1) shown in FIG. 1 except for the addition of a new common bias voltage generating circuit VG.

[0093] The current mirror circuit CM_2 supplies a bias control current I1, which is a copy of the reference current Io generated by the reference current source IG_1, to the sub-bias circuit SB1, supplies a bias control current I2, which is a copy of the reference current Io, to the sub-bias circuit SB2, and supplies a bias control current I3, which is a copy of the reference current Io, to the sub-bias circuit SB3.

[0094] Furthermore, the current mirror circuit CM_2 supplies a bias control current I_C, which is a copy of the reference current Io, to the common bias voltage generating circuit VG.

[0095] The common bias voltage generation circuit VG performs current-voltage conversion on the bias control current I_C to generate bias voltages VB2N, VB3N, VB2P, and VB3P that have little effect on the slew rate of the amplifiers, and supplies these to all of the amplifiers AP1 to APn.

[0096] The sub-bias circuit SB1a performs current-voltage conversion on the bias control current I1 to generate bias voltages VB1N and VB1P that have a large effect on the slew rate of the amplifiers, and supplies these to the amplifiers AP1 to APr belonging to the first group.

[0097] The sub-bias circuit SB2a performs current-voltage conversion on the bias control current I2 to generate bias voltages VB1N and VB1P that have a large effect on the slew rate of the amplifiers, and supplies these to the amplifiers AP(r+1) to APg belonging to the second group.

[0098] The sub-bias circuit SB3a performs current-voltage conversion on the bias control current I3 to generate bias voltages VB1N and VB1P that have a large effect on the slew rate of the amplifiers, and supplies these to the amplifiers AP(g+1) to APn belonging to the third group.

[0099] In this manner, in the output amplifier circuit 100_2, of the six bias voltage groups, the bias voltages VB1N and VB1P, which have a large effect on the slew rate of the amplifier, are generated by each of the sub-bias circuits SB1a to SB3a, and the other bias voltage groups (VB2N, VB3N, VB2P, VB3P) are generated by the common bias voltage generation circuit VG as common to all the amplifiers.

[0100] Therefore, each of the sub-bias circuits SB1a to SB3a has a configuration in which the transistor groups involved in generating the bias voltages VB2N, VB3N, VB2P, and VB3P are omitted from the configuration shown in Fig. 3. This makes it possible to reduce the number of elements constituting the sub-bias circuits and thus save area. EXAMPLES

[0101] FIG. 7 is a block diagram showing the configuration of a display device 200 having a display driver including an output driver circuit according to the present invention.

[0102] As shown in FIG. 7, the display device 200 includes a drive control unit 10, a scan driver 120, a data driver 13, and a display panel 20.

[0103] The display panel 20 is, for example, an organic EL panel or a liquid crystal display panel. Horizontal scanning lines S1 to Sm (m is an integer of 2 or more) extending in the horizontal direction of the two-dimensional screen, and data lines D1 to Dn (n is an integer of 2 or more) extending in the vertical direction of the two-dimensional screen are formed on the display panel 20. Display cells are formed in the areas (areas surrounded by dashed lines) of the intersections between the horizontal scanning lines and the data lines.

[0104] The horizontal scanning lines S1 to Sm are connected to a scanning driver 120, and the data lines D1 to Dn are connected to a data driver 13.

[0105] The drive control unit 10 receives the video signal VD, detects a horizontal synchronization signal from the video signal VD, and supplies it to the scan driver 120. The drive control unit 10 also generates an image data signal PD including various control signals such as a clock signal and a data capture signal together with a string of pixel data pieces that represents the luminance level of a pixel in, for example, an 8-bit luminance gradation based on the video signal VD, and supplies this to the data driver 13.

[0106] The scan driver 120 sequentially applies horizontal scan pulses to each of the horizontal scan lines S1 to Sm of the display panel 20 in accordance with a timing signal synchronized with the horizontal sync signal supplied from the drive control unit .

[0107] The data driver 13 is formed on, for example, a semiconductor IC (integrated circuit) chip, and includes a data acquisition section 131, a grayscale voltage generation section 132, and an output section 133.

[0108] The data acquisition unit 131 acquires pixel data pieces one horizontal scanning line at a time, that is, n pieces at a time, in response to a data acquisition signal included in the image data signal PD. The data acquisition unit 131 sets the acquired n pixel data pieces as pixel data P1 to Pn, and supplies the pixel data P1 to Pn to the grayscale voltage generation unit 132 at the timing of, for example, the rising edge of the clock signal CLK. The clock signal CLK is generated within the data driver 13 based on the clock signal included in the image data signal PD.

[0109] The grayscale voltage generating section 132 converts the pixel data P1 to Pn supplied from the data acquiring section 131 into grayscale voltages V1 to Vn having voltage values ​​corresponding to the respective luminance levels, and supplies the voltages to the output section 133.

[0110] The output section 133 includes the output amplifier circuit 100_1 or 100_2 described above, receives the grayscale voltages V1 to Vn as input voltages V1 to Vn, amplifies the input voltages V1 to Vn individually using amplifiers AP1 to APn, and supplies the resulting output voltages G1 to Gn to the data lines D1 to Dn of the display panel 20.

[0111] In the above embodiment, the output amplifier circuit 100_1 or 100_2 is used as the output section 133 of the data driver 13, but such an output amplifier circuit may be used as a circuit included in the drive control section 10 for outputting the above-mentioned timing signal.

[0112] 1 or 6, three sub-bias circuits (SB1 to SB3, or SB1a to SB3) are provided for one main bias circuit MB_1, but the number of sub-bias circuits may be two or more. Also, the main bias circuit MB_1 may be eliminated, and a current mirror circuit that generates a bias control current that is a copy of the reference current Io may be provided in each sub-bias circuit.

[0113] Furthermore, in the output amplifier circuit 100_1 or 100_2 shown in FIG. 1, each sub-bias circuit generates six bias voltages (VB1N to VB3N, VB1P to VB3P), but it is sufficient that the sub-bias circuit generates at least one bias voltage.

[0114] In short, the output amplifier circuit of the present invention may include the following 1st to nth (n is an integer of 2 or more) amplifiers, 1st to Kth (K is an integer of 2 or more) bias circuits, 1st to Kth wirings, and a switch circuit.

[0115] The first to n-th amplifiers (AP1 to APn) receive first to n-th input voltages (V1 to Vn) for each data period of a predetermined cycle and generate first to n-th output voltages (G1 to Gn) by amplifying the input voltages. The first to K-th bias circuits (e.g., SB1 to SB3) are provided corresponding to the first to K-th amplifier groups obtained by dividing the first to n-th amplifiers into K (e.g., 3) groups, and each generates a bias voltage for setting the current value of the amplifier's operating current. The first to K-th wirings (e.g., L1 to L3) are independent wirings that supply the bias voltages generated by the first to K-th bias circuits to the first to K-th amplifier groups, respectively. The switch circuits (SW12, SW23), when in an on state, connect one of the first to K-th wirings to another wiring different from the one wiring. [Explanation of symbols]

[0116] 13 Data Driver 133 Output section 200 Display device AP1~APn Amplifiers CM_1 Current mirror circuit CN_1 control section MB_1 Main bias circuit SB1~SB3 Sub-bias circuit

Claims

1. first to n-th amplifiers each receiving first to n-th (n is an integer of 2 or more) input voltages for each data period of a predetermined cycle and amplifying the input voltages to generate first to n-th output voltages; first to K-th bias circuits, which are provided corresponding to first to K-th amplifier groups obtained by dividing the first to n-th amplifiers into K (K is an integer of 2 or more) groups, and each of which generates a bias voltage for setting a current value of an operating current of the amplifier; first to K-th wirings that are independent of one another and supply the bias voltages generated in the first to K-th bias circuits to the first to K-th amplifier groups, respectively; a switch circuit that, when in an on state, connects one of the first to Kth wirings to another wiring different from the one wiring.

2. a control unit that sets the switch circuit to an on state or an off state; 2. The output amplifier circuit according to claim 1, wherein the control unit includes, for each data period, a first period immediately after the start of the data period and a second period following the first period, and sets the switch circuit to an on state for at least the second period.

3. 3. The output amplifier circuit according to claim 2, wherein the control unit sets the switch circuit to an off state during the first period, thereby cutting off the connection between the one wiring and the other wiring.

4. The switch circuit has an on-resistance higher than a predetermined value, 3. The output amplifier circuit according to claim 2, wherein the control section sets the switch circuit to an on state throughout the data period.

5. 2. The output amplifier circuit according to claim 1, wherein the data period is set so that a start timing of the data period is shifted for each of a predetermined number of the first to n-th amplifiers.

6. The output amplifier circuit according to any one of claims 1 to 5, characterized in that the first to Kth bias circuits each include a voltage adjustment unit that receives a bias control signal that specifies a voltage value of the bias voltage and adjusts the voltage value of each of the bias voltages to the voltage value specified by the bias control signal.

7. 7. The output amplifier circuit according to claim 6, further comprising: a common bias voltage generating circuit that generates a bias voltage having a fixed voltage value different from the bias voltage and supplies the bias voltage to the first to nth amplifiers.

8. a grayscale voltage generating circuit for generating first to n-th (n is an integer of 2 or more) grayscale voltages each having a voltage value corresponding to a luminance level of each pixel based on a video signal; first to n-th amplifiers for receiving the first to n-th grayscale voltages and amplifying the first to n-th output voltages, respectively, and supplying the first to n-th output voltages to first to n-th data lines of a display panel; first to K-th bias circuits, which are provided corresponding to first to K-th amplifier groups obtained by dividing the first to n-th amplifiers into K (K is an integer of 2 or more) groups, and each of which generates a bias voltage for setting a current value of an operating current of the amplifier; first to K-th wirings that are independent of one another and supply the bias voltages generated in the first to K-th bias circuits to the first to K-th amplifier groups, respectively; a switch circuit that, when in an on state, connects one of the first to Kth wirings to another wiring different from the one wiring.

9. a display panel having first to n-th (n is an integer of 2 or more) data lines extending along a horizontal direction of a display screen; a grayscale voltage generating circuit for generating first to n-th grayscale voltages each having a voltage value corresponding to a luminance level of each pixel based on a video signal; first to n-th amplifiers for receiving the first to n-th grayscale voltages, amplifying the first to n-th grayscale voltages, and supplying the first to n-th output voltages to the first to n-th data lines of the display panel; first to K-th bias circuits, which are provided corresponding to first to K-th amplifier groups obtained by dividing the first to n-th amplifiers into K (K is an integer of 2 or more) groups, and each of which generates a bias voltage for setting a current value of an operating current of the amplifier; first to K-th wirings that are independent of one another and supply the bias voltages generated in the first to K-th bias circuits to the first to K-th amplifier groups, respectively; a switch circuit that, when in an on state, connects one of the first to Kth wirings to another wiring different from the one wiring.

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