Display device and manufacturing method for display device

Abstract

To provide a high-definition display device.SOLUTION: A display device includes an oxide semiconductor layer including a polycrystal structure, a gate insulating layer provided on the oxide semiconductor layer, a gate electrode facing the oxide semiconductor layer on the gate insulating layer, a first silicon nitride layer provided in contact with the gate electrode, a source wire provided in contact with the first silicon nitride layer and electrically connected to the oxide semiconductor layer, a second silicon nitride layer provided in contact with the source wire and the first silicon nitride layer, a first transparent conductive layer provided in contact with the second silicon nitride layer and electrically connected to the oxide semiconductor layer, and a third silicon nitride layer provided in contact with the first transparent conductive layer and the second silicon nitride layer. The gate electrode has a channel length of 2.0 μm or less.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] One embodiment of the present invention relates to a display device and a method for manufacturing the display device. In particular, one embodiment of the present invention relates to a display device and a method for manufacturing the display device in which a transistor having an oxide semiconductor is used.

Background Art

[0002] Recently, instead of amorphous silicon, low-temperature polysilicon, and single-crystalline silicon, the development of a transistor using an oxide semiconductor as a channel has been advanced (for example, Patent Document 1 and Patent Document 2). A transistor using an oxide semiconductor as a channel is formed with a simple structure and a low-temperature process, similarly to a transistor using amorphous silicon as a channel. A transistor using an oxide semiconductor as a channel is known to have higher mobility and a very low off-current than a transistor using amorphous silicon as a channel.

[0003] In recent years, display devices have been required to have higher definition, and the pixel size has been reduced. Along with the reduction of the pixel size, the reduction of the wiring width and the transistor size has been studied. However, there are limits to these reductions, and the aperture ratio has been reduced due to the arrangement of the metal layer and the semiconductor layer constituting the pixel circuit. Therefore, even if the transistor size is small, the development of using a transistor using an oxide semiconductor layer as a channel, which can obtain sufficient characteristics for driving the pixel circuit, for the transistor of the pixel circuit has been advanced.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0005] It has been found that a transistor using an oxide semiconductor is greatly affected by hydrogen contained in an insulating film provided around the oxide semiconductor. As the pixel size of a display device is reduced, it is necessary to also reduce the size (channel length L) of the transistor. When the channel length L is 2.0 μm or less, hydrogen easily penetrates not only into the source region and the drain region but also into the channel region, and thus there is a risk that the transistor will not operate.

[0006] One of the objectives of one embodiment of the present invention is to provide a high-definition display device.

Means for Solving the Problems

[0007] A display device according to an embodiment of the present invention , acid has an oxide semiconductor layer, a gate insulating layer provided on the oxide semiconductor layer, a gate electrode provided on the gate insulating layer and facing the oxide semiconductor layer, a first silicon nitride layer provided in contact with the gate electrode, a source wiring provided in contact with the first silicon nitride layer and electrically connected to the oxide semiconductor layer, a second silicon nitride layer provided in contact with the source wiring and the first silicon nitride layer, a first transparent conductive layer provided in contact with the second silicon nitride layer and electrically connected to the oxide semiconductor layer, and a third silicon nitride layer provided in contact with the first transparent conductive layer and the second silicon nitride layer, and the channel length of the gate electrode is 2.0 μm or less.

[0008] A display device according to an embodiment of the present invention , acidAn oxide semiconductor layer, a gate insulating layer provided on the oxide semiconductor layer, a gate electrode facing the oxide semiconductor layer on the gate insulating layer, a first silicon nitride layer provided in contact with the gate electrode, a silicon oxide layer provided in contact with the first silicon nitride layer, a source wiring provided in contact with the silicon oxide layer and electrically connected to the oxide semiconductor layer, a second silicon nitride layer provided in contact with the source wiring and the silicon oxide layer, a first transparent conductive layer provided in contact with the second silicon nitride layer and electrically connected to the oxide semiconductor layer, and a third silicon nitride layer provided in contact with the first transparent conductive layer and the second silicon nitride layer. The channel length of the gate electrode is 2.0 μm or less, and the film thickness of the silicon oxide layer is smaller than the film thicknesses of the first silicon nitride layer, the second silicon nitride layer, and the third silicon nitride layer. A display device.

[0009] A method for manufacturing a display device according to an embodiment of the present invention , acid Form an oxide semiconductor layer, form a gate insulating layer on the oxide semiconductor layer, form a gate electrode facing the oxide semiconductor layer on the gate insulating layer, form a first silicon nitride layer in contact with the gate electrode, form a source wiring electrically connected to the oxide semiconductor layer in contact with the first silicon nitride layer, form a second silicon nitride layer in contact with the source wiring and the first silicon nitride layer, form a first transparent conductive layer electrically connected to the oxide semiconductor layer in contact with the second silicon nitride layer, and form a third silicon nitride layer in contact with the first transparent conductive layer and the second silicon nitride layer. In the oxide semiconductor layer, the channel length of the channel region overlapping the gate electrode is 2.0 μm or less, and the film formation temperature of each of the first silicon nitride layer, the second silicon nitride layer, and the third silicon nitride layer is 150°C or higher and 250°C or lower.

Brief Description of the Drawings

[0010] [[Fig. 1]] It is a schematic plan view showing the configuration of a display device according to an embodiment of the present invention. [[Fig. 2]] It is a schematic plan view showing the circuit configuration of a display device according to an embodiment of the present invention. [[Fig. 3]]It is a circuit diagram showing a pixel circuit of a pixel of a display device according to an embodiment of the present invention. [[Fig. 4]] It is a cross-sectional view showing an overview of a display device according to an embodiment of the present invention. [[Fig. 5]] It is a plan view showing the configuration of a pixel of a display device according to an embodiment of the present invention. [[Fig. 6]] It is a plan view showing the configuration of a pixel of a display device according to an embodiment of the present invention. [[Fig. 7]] It is a sequence diagram for explaining a manufacturing method of a display device according to an embodiment of the present invention. [[Fig. 8]] It is a sequence diagram for explaining a manufacturing method of a display device according to an embodiment of the present invention. [[Fig. 9]] It is a cross-sectional view for explaining a manufacturing method of a display device according to an embodiment of the present invention. [[Fig. 10]] It is a cross-sectional view for explaining a manufacturing method of a display device according to an embodiment of the present invention. [[Fig. 11]] It is a cross-sectional view for explaining a manufacturing method of a display device according to an embodiment of the present invention. [[Fig. 12]] It is a cross-sectional view for explaining a manufacturing method of a display device according to an embodiment of the present invention. [[Fig. 13]] It is a cross-sectional view for explaining a manufacturing method of a display device according to an embodiment of the present invention. [[Fig. 14]] It is a cross-sectional view for explaining a manufacturing method of a display device according to an embodiment of the present invention. [[Fig. 15]] It is a cross-sectional view for explaining a manufacturing method of a display device according to an embodiment of the present invention. [[Fig. 16]] It is a cross-sectional view for explaining a manufacturing method of a display device according to an embodiment of the present invention. [[Fig. 17]] It is a cross-sectional view for explaining a manufacturing method of a display device according to an embodiment of the present invention. [[Fig. 18]] It is a cross-sectional view showing an overview of a display device according to an embodiment of the present invention. [[Fig. 19]] It is a sequence diagram for explaining a manufacturing method of a display device according to an embodiment of the present invention. [[Fig. 20]]It is a cross-sectional view for explaining a method of manufacturing a display device according to an embodiment of the present invention. [[Fig. 21]] It is a cross-sectional view for explaining a method of manufacturing a display device according to an embodiment of the present invention. [[Fig. 22]] It is a cross-sectional view showing an outline of a display device according to an embodiment of the present invention. [[Fig. 23]] It is a cross-sectional view for explaining a method of manufacturing a display device according to an embodiment of the present invention. [[Fig. 24]] It is a cross-sectional view showing an outline of a display device according to an embodiment of the present invention. [[Fig. 25]] It is a sequence diagram for explaining a method of manufacturing a display device according to an embodiment of the present invention. [[Fig. 26]] It is a sequence diagram for explaining a method of manufacturing a display device according to an embodiment of the present invention.

Embodiments for Carrying Out the Invention

[0011] Hereinafter, each embodiment of the present invention will be described with reference to the drawings. The following disclosure is merely an example. Configurations that can be easily conceived by those skilled in the art by appropriately changing the configuration of the embodiment while maintaining the gist of the invention are naturally included in the scope of the present invention. For the sake of clearer explanation, the drawings may be schematically represented in terms of the width, film thickness, shape, etc. of each part compared to the actual aspect. However, the illustrated shape is merely an example and does not limit the interpretation of the present invention. In this specification and each drawing, the same reference numerals may be given to configurations similar to those described above with respect to the previously shown drawings, and detailed descriptions may be appropriately omitted.

[0012] The “semiconductor device” generally refers to all devices that can function by utilizing semiconductor characteristics. Transistors and semiconductor circuits are one form of semiconductor devices. The semiconductor devices in the embodiments shown below may be, for example, transistors used in display devices, integrated circuits (ICs) such as microprocessors (MPUs), or memory circuits.

[0013] The "display device" refers to a structure that displays an image using an electro-optical layer. For example, the term "display device" may refer to a display panel including an electro-optical layer, or may refer to a structure in which other optical members (e.g., a polarizing member, a backlight, a touch panel, etc.) are attached to a display cell. The "electro-optical layer" may include a liquid crystal layer, an electroluminescence (EL) layer, an electrochromic (EC) layer, and an electrophoretic layer as long as no technical contradiction occurs. Therefore, in the embodiments described below, as display devices, a liquid crystal display device including a liquid crystal layer and an organic EL display device including an organic EL layer will be exemplified and described, but the structure in the present embodiment can be applied to a display device including other electro-optical layers described above.

[0014] In each embodiment of the present invention, the direction from the substrate toward the oxide semiconductor layer is referred to as up or upward. Conversely, the direction from the oxide semiconductor layer toward the substrate is referred to as down or downward. Thus, for the sake of convenience of explanation, the terms up or downward are used for explanation, but for example, the substrate and the oxide semiconductor layer may be arranged such that their vertical relationship is different from that shown in the drawing. In the following description, for example, the expression an oxide semiconductor layer on a substrate merely explains the vertical relationship between the substrate and the oxide semiconductor layer as described above, and other members may be arranged between the substrate and the oxide semiconductor layer. Up or downward means the stacking order in a structure in which a plurality of layers are stacked. When expressing a pixel electrode above a transistor, in a plan view, the positional relationship may be such that the transistor and the pixel electrode do not overlap. On the other hand, when expressing a pixel electrode directly above the transistor in a vertical direction, in a plan view, it means the positional relationship in which the transistor and the pixel electrode overlap.

[0015] In this specification, expressions such as "α includes A, B, or C", "α includes any one of A, B, and C", "α includes one selected from the group consisting of A, B, and C" do not exclude the case where α includes a plurality of combinations of A to C unless otherwise specified. Furthermore, these expressions do not exclude the case where α includes other elements.

[0016] Note that the following embodiments can be combined with each other as long as no technical contradiction occurs.

[0017] <First Embodiment> A display device 10 according to an embodiment of the present invention will be described with reference to FIGS. 1 to 26.

[0018] <1. Overview of the Display Device> The overview of the display device 10 will be described with reference to FIGS. 1 and 2. FIG. 1 is a schematic plan view showing the configuration of the display device 10. FIG. 2 is a schematic plan view showing the circuit configuration of the display device 10. The display device 10 is, for example, a liquid crystal display device.

[0019] As shown in FIG. 1 or FIG. 2, the display device 10 includes an array substrate 100, a seal portion 200, a counter substrate 190, a flexible printed circuit board (FPC) 300, and an IC chip 400. The array substrate 100 and the counter substrate 190 are bonded together by the seal portion 200.

[0020] Further, the display device 10 includes a display area 122 and a peripheral area 121 surrounding the display area 122. The peripheral area 121 includes a seal area 124 and the outside of the seal area 124 surrounding the seal area 124. The outside of the seal area 124 includes an exposed area 126.

[0021] In the display area 122, a plurality of pixels 180 arranged in a matrix in the first direction D1 and the second direction D2 are arranged. The display area 122 is an area that overlaps with a liquid crystal layer (not shown) containing liquid crystal molecules in a plan view.

[0022] In the peripheral area 121, a light-shielding portion 192 overlapping the array substrate 100 and the counter substrate 190 is arranged. In the seal area 124, the seal portion 200 is arranged. The seal area 124 is an area that overlaps with the seal portion 200 in a plan view.

[0023] The exposed area 126 is the area where the array substrate 100 is exposed from the counter substrate 190. The FPC terminal portion 150 is disposed in the exposed area 126. Further, the FPC 300, the IC chip 400, and a part of the routing wiring portion 115 are disposed in the exposed area 126.

[0024] In the display device 10, the seal area 124, the outside of the seal area 124, and the exposed area 126 may be collectively referred to as a frame area.

[0025] The FPC terminal portion 150 includes a plurality of FPC terminals. The routing wiring portion 115 includes a plurality of data signal supply lines 116. The light shielding portion 192 overlaps with the seal portion 200, the first drive circuit 110, the second drive circuit 120, a part of the routing wiring portion 115, and the common wiring 145, and has a function of hiding the seal portion 200, the first drive circuit 110, the second drive circuit 120, a part of the routing wiring portion 115, the common wiring 145, and the like.

[0026] The shape of the array substrate 100 and the shape of the display area 122 of the display device 10 will be described for the case where they are octagonal. Note that the shape of the array substrate 100 and the shape of the display area 122 of the display device 10 are not limited to octagonal, and may be rectangular or circular.

[0027] <2. Circuit Configuration of Display Device 10> Next, the circuit configuration of the display device 10 will be described with reference to FIG. 2. Configurations that are the same as or similar to those in FIG. 1 will be described as necessary.

[0028] As shown in FIG. 2, the FPC terminal portion 150 connected to the FPC 300 is connected to the IC chip 400 and the second drive circuit 120 by a connection wiring 141. The IC chip 400 is connected to the first drive circuit 110 using a plurality of data signal supply lines 116.

[0029] The first driving circuit 110 is provided in parallel with the first direction D1 of the display area 122. Also, the second driving circuit 120 is provided in parallel with the second direction D2 of the display area 122. The first driving circuit 110 and the second driving circuit 120 overlap with the seal area 124 (FIG. 1) in a plan view. The area where the seal area 124 overlaps with the first driving circuit 110 and the second driving circuit 120 is an example and is not limited to the seal area 124 shown in FIG. 1. The area where the seal area 124 overlaps with the first driving circuit 110 and the second driving circuit 120 may be an area outside the area where the pixel circuits 182 (see FIG. 3) of the plurality of pixels 180 are provided.

[0030] The first driving circuit 110 is, for example, a source driver and includes a plurality of multiplexer circuits 111 that select data signals. The multiplexer circuit 111 includes a plurality of analog switches (ASW) 112. The plurality of ASW 112 are electrically connected between the plurality of data signal lines 131 and the plurality of data signal supply lines 116 and have a function of electrically connecting the corresponding data signal line 131 and data signal supply line 116. The ASW 112 in the multiplexer circuit 111 shown in FIG. 2 are, for the sake of convenience of explanation, two as an example. The number of ASW 112 included in the multiplexer circuit 111 may be greater than two.

[0031] The second driving circuit 120 is, for example, a gate driver circuit. Also, the IC chip 400 supplies, for example, a control signal for driving the pixel circuit 182 to at least one of the first driving circuit 110 and the second driving circuit 120.

[0032] Each of the plurality of pixels 180 may correspond to, for example, a sub-pixel R, a sub-pixel G, and a sub-pixel B. The pixel 180 is the minimum unit that constitutes a part of the image reproduced in the display area 122. Each pixel 180 is provided with one display element. In the example shown in FIG. 1, the display element is a liquid crystal element 170 (see FIG. 3). The color corresponding to the sub-pixel is determined by the characteristics of the liquid crystal element 170 or a color filter (not shown) provided in the sub-pixel. The color filter may be provided on the counter substrate 190 or may be provided on the array substrate 100.

[0033] For example, the sub-pixel R may include a red color filter that emits red, the sub-pixel G may include a green color filter that emits green, and the sub-pixel B may include a blue color filter that emits blue.

[0034] A plurality of data signal lines including the data signal line 131 extend from the first driving circuit 110 in the second direction D2 and are connected to a plurality of pixels 180 arranged in the second direction D2. A plurality of scanning signal lines including the scanning signal line 129 extend from the second driving circuit 120 in the first direction D1 and are connected to a plurality of pixels 180 arranged in the first direction D1.

[0035] The common wiring 145 overlaps, for example, the peripheral area 121 and is provided inside the outer periphery of the peripheral area 121. A common voltage is supplied to the common wiring 145 from an external device. The common voltage may be, for example, a voltage between the voltage of the plus side of the data signal and the voltage of the minus side of the data signal, a reference voltage of the voltage amplitude, 0V, a ground voltage, or a ground voltage. The common wiring 145 may be electrically connected to a common electrode (not shown) formed on the counter substrate 190 via a plurality of connection portions 143, or may be electrically connected to the common electrode 146 (see FIG. 3) using various wiring layers.

[0036] When the FPC 300 is connected to the FPC terminal portion 150, the display device 10 is connected to an external device (not shown) connected to the FPC 300, and signals from the external device are supplied to, for example, the IC chip 400, the first drive circuit 110, the second drive circuit 120, and each pixel 180. The display device 10 drives each pixel circuit 182 provided in the display device 10 using signals from the external device and control signals generated by the IC chip 400, the first drive circuit 110, and the second drive circuit 120.

[0037] <3. Configuration of Pixel Circuit 182 of Pixel 180> Referring to FIG. 3, the configuration of the pixel circuit 182 will be described. FIG. 3 is a schematic circuit diagram showing the configuration of the pixel circuit 182 of the pixel 180 in the display device 10. Configurations identical or similar to those in FIGS. 1 and 2 will be described as necessary.

[0038] The pixel circuit 182 includes, for example, a transistor 160, a liquid crystal element 170, and a capacitive element 168. Although details will be described later, for example, the first electrode of the capacitive element 168 is the pixel electrode PTCO, and the second electrode of the capacitive element 168 is grounded. Similar to the capacitive element 168, the first electrode of the liquid crystal element 170 is the pixel electrode PTCO, and the second electrode of the liquid crystal element 170 is the common electrode CTCO. Note that the first and second electrodes of the capacitive element 168 are interchangeable. The first and second electrodes of the liquid crystal element 170 are interchangeable. The second electrode of the liquid crystal element 170 is the common electrode 146. Note that the second electrode of the capacitive element 168 may be the common electrode CTCO or the common electrode 146. The transistor 160 includes a first gate electrode 161, a first source electrode 163, and a first drain electrode 164. The first gate electrode 161 is connected to the scanning signal line 129. The first source electrode 163 is connected to the data signal line 131. The first drain electrode 164 is connected to the first electrode of the capacitive element 168 and the first electrode of the liquid crystal element 170. In this specification and the like, for convenience of explanation, the first source electrode 163 is referred to as the source electrode, and the first drain electrode 164 is referred to as the drain electrode. However, depending on the voltage supplied (applied) to the source electrode and the drain electrode of the transistor 160, the functions of each electrode as a source and a drain may be interchanged.

[0039] An arbitrary signal (voltage or current) is supplied to each pixel circuit 182 of the three sub-pixels of the display device 10, and the display device 10 can display an image. For example, the IC chip 400, the first driving circuit 110, the second driving circuit 120, and an external device can change the alignment state of the liquid crystal molecules included in the liquid crystal element 170 by supplying a current or a voltage to each of the pixel electrode and the common electrode 146 included in the pixel circuit 182. As a result, the display device 10 can display an image.

[0040] <4. Configuration of the display device 10> The outline of the display device 10 according to an embodiment of the present invention will be described with reference to FIGS. 4 to 6. FIG. 4 is a cross-sectional view showing the configuration of the display device 10 according to an embodiment of the present invention. The cross-sectional view shown in FIG. 4 shows the transistor Tr2 in the peripheral region 121 adjacent to each other and the transistor Tr1 in the pixel circuit 182. Actually, the pixel circuit 182 is included in the display region 122, and the peripheral circuit is included in the peripheral region 121. Therefore, in FIG. 4, it goes without saying that the pixel circuit and the peripheral circuit shown adjacent to each other are provided separately in the display device 10. Further, the cross-sectional view shown in FIG. 4 shows the periphery of the opening of the pixel 180 and a part of the transmission region (opening region) contributing to the display of the image. The transistor Tr2 and the transistor Tr1 are, for example, thin film transistors. Configurations the same as or similar to those in FIGS. 1 to 3 will be described as necessary.

[0041] Further, FIGS. 5 and 6 are plan views showing the configuration of the pixels of the display device 10 according to an embodiment of the present invention. FIG. 5 shows the layout from the light shielding layer LS to the passivation layer PAS3, and FIG. 6 shows the layout from the passivation layer PAS3 to the common electrode CTCO.

[0042] As shown in FIG. 4, each layer included in the display device 10 is provided above the substrate SUB1 (in the third direction D3). The display device 10 has the transistor Tr1, the transistor Tr2, a wiring group W including a plurality of wirings, a connection electrode ZTCO, a pixel electrode PTCO, a common auxiliary electrode CMTL, and a common electrode CTCO. TCO is an abbreviation for Transparent Conductive Oxide. The transistor Tr1 is a transistor included in the pixel circuit 182 of the pixel 180 of the display device 10. The transistor Tr2 is a transistor included in a peripheral circuit such as the first drive circuit 110 or the second drive circuit 120. The wiring group W includes, for example, a wiring W1, a wiring W2, and a wiring W3.

[0043] <4-1. Configuration of Transistor Tr1> As shown in FIG. 4, the transistor Tr1 is provided above the substrate SUB1. The transistor Tr1 includes at least an oxide semiconductor layer OS , a first gate insulating layer GI1, a gate wiring GL1 (also referred to as a gate electrode), a passivation layer PAS1, a wiring W3, a passivation layer PAS2, and a connection electrode ZTCO (also referred to as a connection electrode). The transistor Tr1 may further have a passivation layer PAS3 on the connection electrode ZTCO. The transistor Tr1 may further have a second insulating layer IL2 and a light-shielding layer LS between the oxide semiconductor layer OS and the substrate SUB1. Also, the transistor Tr1 may further have a metal oxide layer MO1 mainly composed of aluminum provided in contact with the oxide semiconductor layer OS between the oxide semiconductor layer OS and the second insulating layer IL2. In FIG. 4, an example of providing the metal oxide layer MO1 under the oxide semiconductor layer OS will be described, but an embodiment of the present invention is not limited thereto, and the oxide semiconductor layer OS may be in contact with the second insulating layer IL2 (see FIG. 24).

[0044] The gate wiring GL1 faces the oxide semiconductor layer OS . The first gate insulating layer GI1 is provided between the oxide semiconductor layer OS and the gate wiring GL1. In the present embodiment, as the transistor Tr1, a top-gate transistor in which the oxide semiconductor layer OS is provided on the substrate SUB1 side of the gate wiring GL1 is exemplified, but a bottom-gate transistor in which the positional relationship between the gate wiring GL1 and the oxide semiconductor layer OS is reversed may be used. Note that the structure from the substrate SUB1 to the passivation layer PAS3 may be referred to as a semiconductor device in some cases.

[0045] The oxide semiconductor layer OSIt includes a channel region OS1 and a low-resistance region OS2. The channel region OS1 is an oxide semiconductor layer in a region that overlaps with the gate wiring GL1 in plan view. The channel region OS1 can be switched between a conductive state and a non-conductive state according to the voltage supplied to the gate wiring GL1. The low-resistance region OS2 is a region with lower resistance than the channel region OS1. The low-resistance region OS2 functions as a source region or a drain region. For example, the low-resistance region OS2 is an oxide semiconductor layer OS whose resistance is reduced by ion-implanting impurities into it.

[0046] As shown in FIG. 5, the gate wiring GL1 is arranged along the first direction D1. The region of the gate wiring GL1 that overlaps with the oxide semiconductor layer OS is called the gate electrode. The oxide semiconductor layer is arranged so as to intersect the gate wiring GL1 OS . Also, in the oxide semiconductor layer OS , the region that overlaps with the gate wiring GL1 is the channel region OS1. In FIG. 5, in the channel region OS1, the width of the gate wiring GL1 (the length in the second direction D2) corresponds to the channel length L. Also, in the channel region OS1, the oxide semiconductor layer OS (the length in the first direction D1) corresponds to the channel width W. In this embodiment, the width of the gate wiring GL1 (the channel length L) is 2.0 μm or less, preferably 1.5 μm or less.

[0047] The oxide semiconductor layer OSA first gate insulating layer GI1 is provided on top of it. A passivation layer PAS1 is provided on top of the first gate insulating layer GI1. A wiring W3 is provided on top of the passivation layer PAS1. As shown in FIG. 5, in plan view, the wiring W3 is arranged along the second direction D2 and functions as a source wiring. The wiring W3 is connected to the low-resistance region OS2 through an opening SCON1 provided in the first gate insulating layer GI1 and the passivation layer PAS1. A passivation layer PAS2 is provided on top of the passivation layer PAS1 and the wiring W3. A connection electrode ZTCO is provided on top of the passivation layer PAS2. The connection electrode ZTCO is connected to the low-resistance region OS2 through an opening ZCON provided in the first gate insulating layer GI1 and the passivation layers PAS1 and PAS2. The connection electrode ZTCO is in contact with the low-resistance region OS2 at the bottom of the opening ZCON. The region where the connection electrode ZTCO and the low-resistance region OS2 are in contact is called a contact region CON1.

[0048] Oxide semiconductor layer OS A second insulating layer IL2 and a light-shielding layer LS are provided between the oxide semiconductor layer and the substrate SUB1. As shown in FIG. 5, in plan view, the light-shielding layer LS is arranged along the first direction D1 and is provided in a region overlapping with the gate wiring GL1. Also, the light-shielding layer LS is provided so as to intersect with the oxide semiconductor layer OS That is, in plan view, the light-shielding layer LS is provided in a region overlapping with the channel region OS1. The light-shielding layer LS suppresses light incident from the substrate SUB1 side from reaching the channel region OS1. When a conductive layer is used as the light-shielding layer LS, a voltage may be applied to the light-shielding layer LS to control the channel region OS1. When a voltage is applied to the light-shielding layer LS, the light-shielding layer LS and the gate wiring GL1 may be electrically connected. In plan view, the contact region CON1 is provided in a region that does not overlap with the light-shielding layer LS.

[0049] When high light transmittance is required for the display device 10, one of the source electrode and the drain electrode may be formed of a metal conductive layer, and the other may be formed of a transparent conductive layer. For example, when a transparent conductive layer such as ITO is formed in contact with the silicon layer, the surface of the silicon layer is oxidized by the process gas or oxygen ions during the film formation of ITO. Since the oxide layer formed on the surface of the silicon layer has high resistance, the contact resistance between the silicon layer and the transparent conductive layer increases. As a result, poor electrical contact occurs between the silicon layer and the transparent conductive layer. On the other hand, even if the above transparent conductive layer is formed in contact with the oxide semiconductor layer, the above high-resistance oxide layer is not formed on the surface of the oxide semiconductor layer. Therefore, poor electrical contact does not occur between the oxide semiconductor layer and the transparent conductive layer.

[0050] In order to realize a high-definition display device 10, it is necessary that the width (channel length L) of the gate electrode of the transistor using the oxide semiconductor layer be 2 μm or less. Considering the variation in the width of the gate electrode due to the photolithography process and etching in the manufacturing process of the display device 10, it is necessary to be able to drive as a transistor even at 1.5 μm or less.

[0051] It is known that oxygen defects are generated in the oxide semiconductor due to processing damage such as etching. When hydrogen is trapped in the oxygen defect, the resistance of the oxide semiconductor can be reduced to function as a conductor. On the other hand, by supplying oxygen to the oxygen defect and increasing the resistance of the oxide semiconductor, it can function as a semiconductor. That is, in order to operate well as a transistor, in the channel region, it is preferable to increase the resistance of the oxide semiconductor by supplying oxygen to the oxygen defect, and in the source region or the drain region, it is preferable to supply hydrogen to the oxygen defect to reduce the resistance of the oxide semiconductor.

[0052] The characteristics of a transistor using an oxide semiconductor are greatly affected by hydrogen and oxygen contained in an insulating film provided around the oxide semiconductor. When oxygen is excessively supplied to the oxide semiconductor, defect levels different from oxygen vacancies are formed by the excessive oxygen, resulting in a decrease in the reliability of the transistor or a decrease in the field-effect mobility. Further, when hydrogen is excessively supplied to the oxide semiconductor and hydrogen is supplied up to the channel region, there is a problem that the transistor is depressed and does not operate.

[0053] Therefore, in order to miniaturize a transistor using an oxide semiconductor, it is necessary to appropriately supply oxygen and hydrogen to a channel region OS1 having a channel length of 2.0 μm or less and a low-resistance region OS2.

[0054] In one embodiment of the present invention, an oxide semiconductor layer OS By appropriately supplying hydrogen to the oxide semiconductor layer, the resistance of the low-resistance region OS2 functioning as the source region and the drain region is reduced, and the diffusion of hydrogen into the channel region OS1 is suppressed.

[0055] In this embodiment, a silicon nitride layer is used as the passivation layers PAS1 to PAS3. The silicon nitride layer contains more hydrogen than silicon oxide. The hydrogen contained in the silicon nitride layer diffuses when heat exceeding 250°C is applied. Therefore, as the passivation layers PAS1 to PAS3, the silicon nitride layer is formed at 150°C or higher and 250°C or lower. Thereby, it is possible to suppress the diffusion of a large amount of hydrogen contained in the silicon nitride layer, and it is possible to suppress the excessive supply of hydrogen to the low-resistance region OS2. Thereby, it is possible to suppress the transistor Tr1 from being depressed. The configuration of the passivation layers PAS1 to PAS3 will be described in detail later.

[0056] <4-2. Configuration of Transistor Tr2> Transistor Tr2 includes a p-type transistor Tr2-1 and an n-type transistor Tr2-2. When transistor Tr2 is not distinguished, the transistors included in the peripheral region 121 are represented as transistor Tr2. When transistor Tr2 is distinguished, transistor Tr2 is represented as p-type transistor Tr2-1, n-type transistor Tr2-2, etc.

[0057] Both the p-type transistor Tr2-1 and the n-type transistor Tr2-2 have a gate electrode GL2, a second gate insulating layer GI2, and a semiconductor layer S. The gate electrode GL2 faces the semiconductor layer S. The second gate insulating layer GI2 is provided between the semiconductor layer S and the gate electrode GL2. As an example, the transistor Tr2 of the display device 10 is a top-gate transistor in which the gate electrode GL2 is provided above the semiconductor layer S. Transistor Tr2 may be a bottom-gate transistor in which the positional relationship between the semiconductor layer S and the gate electrode GL2 is reversed.

[0058] A first insulating layer IL1 is provided on the substrate SUB1. The first insulating layer IL1 functions as an underlying layer. By providing the first insulating layer IL1, it is possible to prevent impurities from entering the semiconductor layer S from the substrate SUB1.

[0059] The semiconductor layer S of the p-type transistor Tr2-1 includes semiconductor layers S1 and S2. The semiconductor layer S of the n-type transistor Tr2-2 includes semiconductor layers S1, S2, and S3. The semiconductor layer S1 is the semiconductor in the region that overlaps the gate electrode GL2 in plan view. The semiconductor layer S1 functions as the channel region of the transistor Tr2-1. The semiconductor layer S2 functions as a conductor. The semiconductor layer S3 functions as a conductor with a higher resistance than the semiconductor layer S2. The semiconductor layer S3 suppresses hot carrier degradation by attenuating the hot carriers that penetrate toward the semiconductor layer S1.

[0060] A second insulating layer IL2 and a first gate insulating layer GI1 are provided over the gate electrode GL2. A wiring W2 is provided over these insulating layers. The wiring W2 functions as the source electrode and the drain electrode of the transistor Tr2. The wiring W2 is connected to the semiconductor layer S through an opening SCON2 provided in the second insulating layer IL2, the first gate insulating layer GI1, and the second gate insulating layer GI2. Also, the wiring W2 is connected to the wiring W1 through an opening WC1 provided in the second insulating layer IL2 and the first gate insulating layer GI1. A passivation layer PAS1 is provided over the wiring W2. A wiring W3 is provided over the passivation layer PAS1. The wiring W3 is connected to the wiring W2 through an opening WC2 provided in the passivation layer PAS1.

[0061] The gate electrode GL2 is formed in the same layer as the wiring W1 and the light-shielding layer LS. The wiring W2 is formed in the same layer as the gate wiring GL1. The same layer means that a plurality of members are formed by patterning one layer.

[0062] <4-3. Other Configurations of the Display Device> Next, the layer structure provided over the transistors Tr1 and Tr2 will be described. In the display area 122, a color filter CF is provided over the passivation layer PAS3. By providing the color filter CF on the substrate SUB1 side, misalignment between the color filter CF and the pixel circuit can be suppressed. Also, a third insulating layer IL3 is provided over the color filter CF and the passivation layer PAS3. Since the color filter CF is not provided in the peripheral area 121, the third insulating layer IL3 is provided over the passivation layer PAS3. The third insulating layer IL3 functions as a planarization film.

[0063] In the display area 122, a pixel electrode PTCO is provided on the third insulating layer IL3. The pixel electrode PTCO is connected to the connection electrode ZTCO through an opening PCON provided in the third insulating layer IL3. As shown in FIGS. 5 and 6, the pixel electrode PTCO overlaps with two adjacent wirings W3 and the gate wiring GL1, the oxide semiconductor layer OS , and the connection electrode ZTCO. The pixel electrode PTCO contacts the connection electrode ZTCO at an opening PCON that overlaps with the gate wiring GL1.

[0064] A fourth insulating layer IL4 is provided in the display area 122 and the peripheral area 121. In the display area 122, the fourth insulating layer IL4 is provided so as to cover the pixel electrode PTCO and the third insulating layer IL3. In the peripheral area 121, the fourth insulating layer IL4 is provided on the third insulating layer IL3. Also, at the end of the peripheral area 121 (the end of the substrate SUB1), the fourth insulating layer IL4 is in contact with the third insulating layer IL3. Thereby, moisture contained in the third insulating layer IL3 can be sealed.

[0065] In the display area 122, a common auxiliary electrode CMTL and a common electrode CTCO are provided on the fourth insulating layer IL4. As shown in FIG. 6, the common auxiliary electrode CMTL and the common electrode CTCO are arranged in a grid pattern so as to overlap with the gate wiring GL and the wiring W3. That is, the common auxiliary electrode CMTL is provided in common for a plurality of pixels. In other words, the common auxiliary electrode CMTL has an opening OP. The opening OP is provided so as to expose the pixel electrode PTCO. The pattern of the opening OP is provided inside the pattern of the pixel electrode PTCO. Note that the area where the opening OP is provided corresponds to the opening of the pixel. That is, the opening ZCON (first contact area CON1) is included in the opening of the pixel. Note that the opening of the pixel means an area where a user can visually recognize light from the pixel. For example, an area shielded from light by a metal layer and not visible to the user is not included in the opening of the pixel. That is, the above-mentioned opening of the pixel may be referred to as a "light-transmitting area". Also, the area extending along the D1 direction of the common auxiliary electrode CMTL overlaps with the opening PCON. In the display area 122, the common auxiliary electrode CMTL also functions as a black matrix. Note that the common auxiliary electrode CMTL and the common electrode CTCO are also provided in the opening PCON. In FIG. 4, the case where the common electrode CTCO is provided on the common auxiliary electrode CMTL is described, but the common auxiliary electrode CMTL may be arranged on the common electrode CTCO. Here, as shown in FIG. 4, the pixel electrode PTCO overlaps with the common electrode CTCO via the fourth insulating layer IL4. The area where the pixel electrode PTCO overlaps with the common electrode CTCO via the fourth insulating layer IL4 functions as a storage capacitor.

[0066] On the common electrode CTCO, a spacer SP is provided so as to fill the opening PCON. The spacer SP protrudes toward the counter substrate SUB2. By the spacer SP, the spacer SP of the liquid crystal layer LC is provided not only in the display area 122 but also in the peripheral area 121. In the display area 122 and the peripheral area 121, an alignment film OF1 is provided on the third insulating layer IL3, the common electrode CTCO, and the spacer SP.

[0067] In the peripheral region 121, a black matrix BM is provided on the counter substrate SUB2. An overcoat layer OC is provided in the peripheral region 121 and the display region 122. An alignment film OF2 is provided so as to cover the overcoat layer OC. The substrate SUB1 and the counter substrate SUB2 are arranged such that the alignment film OF1 and the alignment film OF2 face each other, and are bonded together by a seal portion 200 provided in the peripheral region 121. A liquid crystal layer LC is provided in the region surrounded by the seal portion 200.

[0068] <5. Manufacturing method of the display device 10> A manufacturing method of the display device 10 according to an embodiment of the present invention will be described. FIGS. 7 and 8 are sequence diagrams for explaining the manufacturing method of the display device 10 according to an embodiment of the present invention. FIGS. 9 to 17 are cross-sectional views for explaining the manufacturing method in the display device 10 according to an embodiment of the present invention.

[0069] First, a first insulating layer IL1, a semiconductor layer S, and a second gate insulating layer GI2 are formed on the substrate SUB1 (see step S1001 shown in FIG. 7 and FIG. 9).

[0070] As the substrate SUB1, a rigid substrate having translucency, such as a glass substrate, a quartz substrate, and a sapphire substrate, is used. When the substrate SUB1 needs to have flexibility, as the substrate SUB1, a substrate containing an organic resin such as a polyimide substrate, an acrylic substrate, a siloxane substrate, and a fluororesin substrate is used. When a substrate containing an organic resin is used as the substrate SUB1, an impurity element may be introduced into the above organic resin in order to improve the heat resistance of the substrate SUB1.

[0071] The first insulating layer IL1 is formed by a CVD (Chemical Vapor Deposition) method or a sputtering method. As the first insulating layer IL1, for example, silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), silicon nitride (SiN x ), silicon oxynitride (SiN x Oy ) Inorganic insulating materials such as x N y is a silicon compound containing nitrogen (N) in a ratio less than that of oxygen (O) (x > y). SiN x O y is a silicon compound containing oxygen in a ratio less than that of nitrogen (x > y). The first insulating layer IL1 may have a single-layer structure using the above inorganic insulating material, or may have a laminated structure.

[0072] Also, polysilicon is used as the semiconductor layer S. Also, as the second gate insulating layer GI2, the same film formation method and inorganic insulating material as those of the first insulating layer IL1 are used.

[0073] Next, a light-shielding layer LS is formed on the gate insulating layer GI2 (see steps S1002 shown in FIG. 7 and FIG. 9).

[0074] The light-shielding layer LS is formed, for example, by processing a conductive layer formed by a sputtering method. As the light-shielding layer LS, a general metal material is used. As the light-shielding layer LS, for example, aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), silver (Ag), copper (Cu), and alloys or compounds thereof are used. Also, the light-shielding layer LS may have a single-layer structure using the above materials, or may have a laminated structure.

[0075] Next, a second insulating layer IL2 is formed on the light-shielding layer LS (see steps S1003 shown in FIG. 7 and FIG. 9). As the second insulating layer IL2, the same film formation method and inorganic insulating material as those of the first insulating layer IL1 are used.

[0076] Further, the second insulating layer IL2 may have a single-layer structure using the above inorganic insulating material, or may have a stacked structure. When the second insulating layer IL2 has a stacked structure, it is preferably formed in the order of an insulating material containing nitrogen and an insulating material containing oxygen from the substrate SUB1. By using an insulating material containing nitrogen, for example, impurities diffusing from the side of the substrate SUB1 toward the oxide semiconductor layer OS can be blocked. Further, by using an insulating material containing oxygen, oxygen can be released by heat treatment. The temperature of the heat treatment at which the insulating material containing oxygen releases oxygen is, for example, 600 °C or lower, 500 °C or lower, 450 °C or lower, or 400 °C or lower. That is, the insulating material containing oxygen releases oxygen at the heat treatment temperature performed in the manufacturing process of the display device when a glass substrate is used as the substrate SUB1. In the present embodiment, for example, silicon nitride is formed as the insulating material containing nitrogen. Further, for example, silicon oxide is formed as the insulating material containing oxygen.

[0077] Next, a metal oxide layer MO1 mainly composed of aluminum is formed on the second insulating layer IL2 (see steps S1004 shown in FIG. 7 and FIG. 10).

[0078] The metal oxide layer MO1 is formed by a sputtering method. The metal oxide layer MO1 mainly composed of aluminum uses, for example, inorganic insulating materials such as aluminum oxide (AlO x ), aluminum oxynitride (AlO x N y ), aluminum nitride oxide (AlN x O y ), aluminum nitride (AlN x ). The above AlO x N y is an aluminum compound containing nitrogen in a ratio (x>y) less than that of oxygen (O). AlN x O y is an aluminum compound containing oxygen in a ratio (x>y) less than that of nitrogen.

[0079] The "metal oxide layer mainly composed of aluminum" means that the ratio of aluminum contained in the metal oxide layer MO1 is 1% or more of the entire metal oxide layer MO1. The ratio of aluminum contained in the metal oxide layer MO1 may be 5% or more and 70% or less, 10% or more and 60% or less, or 30% or more and 50% or less of the entire metal oxide layer MO1. The above ratio may be a mass ratio or a weight ratio.

[0080] The film thickness of the metal oxide layer MO1 is, for example, 1 nm or more and 10 nm or less, 1 nm or more and 4 nm or less, or 1 nm or more and 3 nm or less. In this embodiment, aluminum oxide is used as the metal oxide layer MO1. Aluminum oxide has a high barrier property against gases.

[0081] Next, on the metal oxide layer MO1 with acid an oxide semiconductor layer AOS is formed (see steps S1005 shown in FIG. 7 and FIG. 10).

[0082] The oxide semiconductor layer AOS is formed by a sputtering method or an atomic layer deposition method (ALD: Atomic Layer Deposition). The film thickness of the oxide semiconductor layer AOS is, for example, 5 nm or more and 50 nm or less, preferably 10 nm or more and 40 nm or less, and more preferably 10 nm or more and 30 nm or less.

[0083] As the oxide semiconductor layer AOS, a metal oxide having semiconductor characteristics can be used 。

[0084] s When the oxide semiconductor layer AOS is formed by a sputtering method, the oxide semiconductor layer AOS is formed while controlling the temperature of the object to be film-formed (substrate SUB1 and the structure formed thereon).

[0085] When film formation is performed on the object to be film-formed by the sputtering method, ions generated in the plasma and atoms rebounded by the sputtering target collide with the object to be film-formed, so the temperature of the object to be film-formed rises with the film formation process. Above As described above, in order to control the temperature of the object to be coated, for example, film formation may be performed while cooling the object to be coated. For example, the object to be coated may be cooled from the surface opposite to the surface to be coated so that the temperature of the surface to be coated of the object to be coated (hereinafter referred to as "film formation temperature") becomes 100°C or lower, 70°C or lower, 50°C or lower, or 30°C or lower. 。

[0086] Next, a pattern of the oxide semiconductor layer AOS is formed (see step S1006 shown in FIG. 7). Although not shown, a resist mask is formed on the oxide semiconductor layer AOS, and the oxide semiconductor layer AOS is etched using the resist mask. As the etching of the oxide semiconductor layer AOS, wet etching may be used, or dry etching may be used. As the wet etching, etching may be performed using an acidic etchant. As the etchant, for example, oxalic acid or hydrofluoric acid may be used.

[0087] It is preferable that the pattern of the oxide semiconductor layer AOS is formed before the OS annealing treatment. . E Even if the oxide semiconductor layer AOS is damaged by etching, it is preferable because the damage can be repaired by the OS annealing treatment.

[0088] After the pattern formation of the oxide semiconductor layer AOS, heat treatment (OS annealing treatment) is performed on the oxide semiconductor layer AOS (see step S1007 shown in FIG. 7 and FIG. 11). In the OS annealing treatment, the oxide semiconductor layer AOS is held at a predetermined reaching temperature for a predetermined time. The predetermined reaching temperature is 300°C or higher and 500°C or lower, preferably 350°C or higher and 450°C or lower. Also, the holding time at the reaching temperature is 15 minutes or longer and 120 minutes or shorter, preferably 30 minutes or longer and 60 minutes or shorter. By performing the OS annealing treatment , acid oxide semiconductor layer OS is formed.

[0089] Next, OS a first gate insulating layer GI1 is formed on the oxide semiconductor layer (see step S1009 shown in FIG. 7 and FIG. 13).

[0090] For the method of forming the first gate insulating layer GI1 and the insulating material, reference may be made to the description of the second insulating layer IL2. Further, the film thickness of the first gate insulating layer GI1 is, for example, 50 nm or more and 300 nm or less, preferably 60 nm or more and 200 nm or less, and more preferably 70 nm or more and 150 nm or less.

[0091] As the first gate insulating layer GI1, it is preferable to use an insulating material containing oxygen. Further, as the first gate insulating layer GI1, it is preferable to use an insulating layer with few defects. For example, when comparing the oxygen composition ratio in the first gate insulating layer GI1 with the oxygen composition ratio in an insulating layer having the same composition as the second gate insulating layer GI2 (hereinafter referred to as "other insulating layer"), the oxygen composition ratio in the first gate insulating layer GI1 is closer to the stoichiometric ratio for the insulating layer than the oxygen composition ratio in the other insulating layer. For example, when silicon oxide (SiO x ) is used for each of the first gate insulating layer GI1 and the second gate insulating layer GI2, the oxygen composition ratio in the silicon oxide used as the first gate insulating layer GI1 is closer to the stoichiometric ratio of silicon oxide than the oxygen composition ratio in the silicon oxide used as the second gate insulating layer GI2. For example, as the first gate insulating layer GI1, a layer in which no defects are observed when evaluated by the electron spin resonance method (ESR) may be used.

[0092] In order to form an insulating layer with few defects as the first gate insulating layer GI1, the first gate insulating layer GI1 may be formed at a film formation temperature of 350 °C or higher. Further, after forming the first gate insulating layer GI1, a process of implanting oxygen into a part of the first gate insulating layer GI1 may be performed. In the present embodiment, in order to form an insulating layer with few defects as the first gate insulating layer GI1, silicon oxide is formed at a film formation temperature of 350 °C or higher.

[0093] Next, a metal oxide layer MO2 mainly composed of aluminum is formed on the first gate insulating layer GI1 (see step S1010 shown in FIG. 7 and FIG. 13).

[0094] For the method of forming the metal oxide layer MO2 and the insulating material, reference may be made to the description of the metal oxide layer MO1. By forming the metal oxide layer MO2, oxygen is implanted into the first gate insulating layer GI1. The film thickness of the metal oxide layer MO2 is, for example, 5 nm or more and 100 nm or less, 5 nm or more and 50 nm or less, 5 nm or more and 30 nm or less, or 7 nm or more and 15 nm or less. In the present embodiment, aluminum oxide is used as the metal oxide layer MO2. Aluminum oxide has a high barrier property against gases. In the present embodiment, the aluminum oxide used as the metal oxide layer MO2 suppresses the outward diffusion of the oxygen implanted into the first gate insulating layer GI1 during the formation of the metal oxide layer MO2.

[0095]

[0096] OS Oxide semiconductor layer OS With the first gate insulating layer GI1 formed on the oxide semiconductor layer and the metal oxide layer MO2 formed on the first gate insulating layer GI1, a heat treatment (oxidation annealing treatment) for supplying oxygen to the oxide semiconductor layer is performed (see step S1011 shown in FIG. 7).

[0097] OS OS Oxide semiconductor layer OS After the oxide semiconductor layer is formed and before the first gate insulating layer GI1 is formed on the oxide semiconductor layer, many oxygen defects are generated on the upper surface and side surfaces of the oxide semiconductor layer. Therefore, the oxygen defects formed near the upper surface of the oxide semiconductor layer are more than the oxygen defects formed near the lower surface of the oxide semiconductor layer. That is, the oxide semiconductor layer OS OS OS ​​​​​​The oxygen defects in it do not uniformly exist in the thickness direction of the oxide semiconductor layer OS but exist in a non-uniform distribution in the thickness direction of the oxide semiconductor layer OS Specifically, the oxygen defects in the oxide semiconductor layer OS are fewer on the lower surface side of the oxide semiconductor layer OS and more on the upper surface side of the oxide semiconductor layer OS .

[0098] When performing an oxygen supply process uniformly on the oxide semiconductor layer OS having the above oxygen defect distribution, when supplying an amount of oxygen necessary to repair the oxygen defects formed on the upper surface side of the oxide semiconductor layer OS , oxygen is excessively supplied to the lower surface side of the oxide semiconductor layer OS . As a result, on the lower surface side, defect levels different from oxygen defects are formed by the excessive oxygen. As a result, phenomena such as characteristic fluctuations in the reliability test or a decrease in the field-effect mobility occur. Therefore, in order to suppress such phenomena, it is necessary to supply oxygen to the upper surface side of the oxide semiconductor layer OS while suppressing the oxygen supply to the lower surface side of the oxide semiconductor layer OS .

[0099] An annealing oxidation is performed in a state where a metal oxide layer MO1 is provided under the oxide semiconductor layer OS and a metal oxide layer MO2 is provided above the oxide semiconductor layer OS . Thereby, in the above annealing oxidation treatment, the oxygen implanted into the first gate insulating layer GI1 is blocked by the metal oxide layer MO2, so that it is suppressed from being released into the atmosphere. Further, the oxygen released from the second insulating layer IL2 is supplied to the upper surface and side surfaces of the oxide semiconductor layer OS . Also, the metal oxide layer MO1 can suppress excessive oxygen supply below the oxide semiconductor layer OS . Thereby, the oxygen is efficiently supplied to the oxide semiconductor layer OS and the oxygen defects can be repaired.

[0100] Next, after the oxidation annealing treatment, the metal oxide layer MO2 is etched (removed) (see step S1012 shown in FIG. 7 and FIG. 14). As the etching of the metal oxide layer MO2, wet etching may be used, or dry etching may be used. As the wet etching, for example, diluted hydrofluoric acid (DHF) is used. By this etching, the metal oxide layer MO2 formed over the entire surface is removed. In other words, the removal of the metal oxide layer MO2 is performed without using a mask. Further in other words, by this etching, at least in plan view, all the metal oxide layers in the region overlapping with the oxide semiconductor layer OS formed in a certain pattern are removed.

[0101] Next, a gate wiring GL1 is formed over the first gate insulating layer GI1 (see step S1013 shown in FIG. 7 and FIG. 15). For the film formation method and conductive material of the gate wiring GL, reference may be made to the description of the light shielding layer LS.

[0102] Next, using the gate wiring GL1 as a mask, impurities are added to the oxide semiconductor layer OS (see step S1014 shown in FIG. 7 and FIG. 15). In this embodiment, the case where the addition of impurities is performed by ion implantation will be described, but it may also be performed by the ion doping method.

[0103] Specifically, by ion implantation, impurity elements are added to the oxide semiconductor layer OS through the first gate insulating layer GI1, whereby a low-resistance region OS2 is formed. Also, in the oxide semiconductor layer OS the region overlapping with the gate wiring GL1 becomes a channel region OS1. As the impurity element, for example, argon (Ar), phosphorus (P), or boron (B) may be used. Also, when boron (B) is added by the ion implantation method, the acceleration energy is set to 20 keV or more and 40 keV or less, and the implantation amount of boron (B) is set to 1×10 14 cm -2 or more and 1×10 16 cm -2 or less.

[0104] When the concentration of impurity elements contained in the low-resistance region OS2 is measured by SIMS analysis (secondary ion mass spectrometry), it is preferably 1×10 18 cm -3 or more and 1×10 21 cm -3 or less. Further, when the low-resistance region OS2 contains 1×10 18 cm -3 or more and 1×10 21 cm -3 or less, it is presumed that impurity elements have been intentionally added by ion implantation or doping method.

[0105] oxide semiconductor layer OS By ion-implanting impurity elements into the, oxygen defects are formed in the low-resistance region OS2, and defects are also formed in the metal oxide layer MO1 and the second insulating layer IL2 provided under the low-resistance region OS2. In a subsequent process, the resistance of the low-resistance region OS2 can be further reduced by supplying hydrogen to the oxygen defects. As a method of supplying hydrogen to the oxygen defects, for example, using a silicon nitride layer as a passivation layer can be mentioned. Since the silicon nitride layer contains a large amount of hydrogen during film formation, the hydrogen contained in the silicon nitride layer is trapped by the oxygen defects in the low-resistance region OS2, so that the low-resistance region OS2 can be made to have a lower resistance. Also, by trapping hydrogen in the defects formed by ion implantation in the metal oxide layer MO1 and the second insulating layer IL2, the supply of hydrogen to the channel region OS1 more than necessary is suppressed. However, if a large amount of hydrogen diffuses during the formation of the silicon nitride layer, the oxygen defects in the low-resistance region OS2 and the defects in the metal oxide layer MO1 and the second insulating layer IL2 cannot trap all the hydrogen. If too much hydrogen is supplied to the oxygen defects in the low-resistance region OS2, hydrogen will be supplied from the low-resistance region OS2 to the channel region OS1, and the transistor will be depressed.

[0106] In order to prevent an excessive supply of hydrogen to the low-resistance region OS2, silicon oxide can be used in combination as a passivation layer. However, when forming the silicon oxide film, film formation dust (particles) may be generated by the reaction gas. It is difficult to remove the film formation dust, which becomes an obstacle to the subsequent manufacturing process. Therefore, it is not very desirable to use a thick silicon oxide film as the passivation layer.

[0107] Therefore, in the present embodiment, a silicon nitride layer is used as the passivation layers PAS1 to PAS3 formed on the gate wiring GL1, and the silicon nitride layer is formed at a temperature of 150°C or higher and 250°C or lower. Thereby, it is possible to suppress a large amount of hydrogen from diffusing during the formation of the silicon nitride layer, and to suppress an excessive supply of hydrogen to the low-resistance region OS2. As a result, it is possible to suppress the transistor Tr1 from being depressed. Hereinafter, the method for forming the passivation layers PAS1 to PAS3 will be described in detail.

[0108] Next, a passivation layer PAS1 is formed on the first gate insulating layer GI1 and the gate wiring GL1 (see steps S1015 shown in FIG. 8 and FIG. 16). The passivation layer PAS1 is formed using a silicon nitride layer. The film thickness of the passivation layer PAS1 is 200 nm or more and 600 nm or less. Also, the film thickness of the passivation layer PAS1 is preferably thicker than the film thicknesses of the passivation layers PAS2 and PAS3. Thereby, the parasitic capacitance generated in the wiring W3 can be reduced. The source gas during the formation of the silicon nitride layer contains a large amount of hydrogen. Therefore, when the film formation temperature exceeds 250°C, hydrogen diffuses and OS enters the oxide semiconductor layer. Therefore, when forming the passivation layer PAS1 as a silicon nitride layer, it is preferable to form the film at a temperature of 150°C or higher and 250°C or lower.

[0109] Next, an opening SCON1 reaching the low-resistance region OS2 is formed in the passivation layer PAS1. Thereafter, a wiring W3 is formed on the passivation layer PAS1, and the wiring W3 is connected to the low-resistance region OS2 through the opening SCON1 (see step S1016 shown in FIG. 8 and FIG. 16). For the film formation method and conductive material of the wiring W3, reference may be made to the description of the light-shielding layer LS. The film formation temperature of the wiring W3 is preferably a temperature not exceeding the film formation temperature of the passivation layer PAS1. When the film is formed at a temperature significantly exceeding the film formation temperature of the wiring W3, hydrogen is released from the passivation layer PAS1, and hydrogen diffuses into the channel region OS1. Thus, the film formation temperatures of the wiring, electrode, and insulating layer formed on the passivation layer PAS1 are preferably not higher than the film formation temperature of the passivation layer PAS1.

[0110] Next, a passivation layer PAS2 is formed on the passivation layer PAS1 and the wiring W3 (see step S1017 shown in FIG. 8 and FIG. 16). The passivation layer PAS2 is formed using a silicon nitride layer. The film thickness of the passivation layer PAS2 is 50 nm or more and 350 nm or less. Similar to the passivation layer PAS1, the silicon nitride layer of the passivation layer PAS2 is preferably formed at a film formation temperature of 150°C or more and 250°C or less. Thereby, it is possible to suppress the diffusion of hydrogen contained in the source gas during the film formation of the passivation layer PAS2, and it is also possible to suppress the diffusion of hydrogen contained in the silicon nitride layer of the passivation layer PAS1.

[0111] Next, an opening ZCON reaching the low-resistance region OS2 is formed in the passivation layer PAS2. Thereafter, a connection electrode ZTCO is formed on the passivation layer PAS2, and the connection electrode ZTCO is connected to the low-resistance region OS2 through the opening ZCON (see step S1018 shown in FIG. 8 and FIG. 16).

[0112] The connection electrode ZTCO is formed by processing a light-transmissive oxide conductive layer formed by a sputtering method. As the connection electrode ZTCO, a transparent conductive material such as a mixture of indium oxide and tin oxide (ITO) or a mixture of indium oxide and zinc oxide (IZO) can be used. As the connection electrode ZTCO, a transparent conductive material other than the above may be used.

[0113] Next, a passivation layer PAS3 is formed in contact with the connection electrode ZTCO using a silicon nitride layer (see step S1019 shown in FIG. 8 and FIG. 17). The passivation layer PAS3 is formed using a silicon nitride layer. The film thickness of the passivation layer PAS3 is 50 nm or more and 300 nm or less. Similar to the passivation layer PAS1, the silicon nitride layer of the passivation layer PAS3 is preferably formed at a film formation temperature of 150°C or more and 250°C or less. Thereby, during the formation of the passivation layer PAS3, diffusion of hydrogen contained in the source gas can be suppressed, and moreover, diffusion of hydrogen contained in the silicon nitride layers of the passivation layers PAS1 and PAS2 can be suppressed.

[0114] Also, by forming the silicon nitride layer as the passivation layer PAS3 at 150°C or more and 250°C or less, reduction of the connection electrode ZTCO during film formation can be suppressed. Thereby, generation of unevenness on the surface of the connection electrode ZTCO can be suppressed. Short circuits of the connection electrode ZTCO and a decrease in the light transmittance due to the unevenness generated on the surface of the connection electrode ZTCO can be suppressed.

[0115] As described above, in the present embodiment, silicon nitride layers are used as the passivation layers PAS1 to PAS3 formed on the gate wiring GL1, and the film formation temperature of the silicon nitride layers is set to 150°C or higher and 250°C or lower. Thereby, excessive diffusion of hydrogen during the film formation of the passivation layers PAS1 to PAS3 can be suppressed, so that hydrogen can be appropriately supplied to the low resistance region OS2. Further, since silicon oxide is not used as the passivation layers PAS1 to PAS3, the influence of film formation dust can be reduced. Further, since the passivation layers PAS1 to PAS3 are formed only of silicon nitride layers, the adhesion between the passivation layers PAS1 to PAS3 can be improved. Furthermore, by forming the silicon nitride layers as the passivation layers PAS1 to PAS3 at 150°C or higher and 250°C or lower, the generation of compressive stress in the silicon nitride layers can be suppressed. Thereby, film peeling of the silicon nitride layers or the connection electrodes ZTCO, and warping of the substrate SUB1 can be suppressed.

[0116] Next, a color filter CF is formed on the passivation layer PAS3 (see step S1020 shown in FIG. 8 and FIG. 4). In the present embodiment, the color filter CF has red, green, and blue. The color filters CF of each color are arranged along the second direction D2.

[0117] Next, a third insulating layer IL3 is formed on the color filter CF (see step S1021 shown in FIG. 8 and FIG. 4). The third insulating layer IL3 is formed using an organic resin material. By forming the third insulating layer IL3 on the color filter CF, unevenness caused by the color filter CF and the transistor Tr1 formed thereunder can be reduced.

[0118] In a high-definition display device, it is difficult to align a color filter formed on a counter substrate with a pixel circuit on an array substrate. Therefore, it is preferable to provide the color filter on the array substrate side. Further, in order to flatten the surface on which the liquid crystal is driven, a planarization film is provided on the color filter. The color filter and the planarization film are made of an organic insulating material, but the organic insulating material contains a large amount of moisture. If this large amount of moisture penetrates into the oxide semiconductor layer, it will have a great influence on the operation of the transistor. Therefore, it is necessary to suppress the penetration of moisture into the oxide semiconductor layer.

[0119] In this embodiment, as the passivation layers PAS1 to PAS3, a silicon nitride layer formed at a temperature of 150°C or higher and 250°C or lower is used. The silicon nitride layer can suppress the moisture contained in the color filter CF and the third insulating layer IL3 from penetrating into the oxide semiconductor layer OS thereby.

[0120] Next, an opening PCON reaching the connection electrode ZTCO is formed in the third insulating layer IL3 and the color filter CF. Thereafter, a pixel electrode PTCO is formed on the third insulating layer IL3, and the pixel electrode PTCO is connected to the connection electrode ZTCO through the opening PCON (see steps S1022 shown in FIG. 8 and FIG. 4). The pixel electrode PTCO is formed by the inorganic insulating material and the film forming method described for the connection electrode ZTCO.

[0121] Next, a fourth insulating layer IL4 is formed on the third insulating layer IL3 and the pixel electrode PTCO (see steps S1023 shown in FIG. 8 and FIG. 4). The fourth insulating layer IL4 is formed by the inorganic insulating material and the film forming method described for the first insulating layer IL1. Since the fourth insulating layer IL4 functions as the capacitance of the capacitance element 168, for example, it is preferably formed using a silicon nitride layer.

[0122] Next, a common auxiliary electrode CMTL is formed on the fourth insulating layer IL4 (see step S1024 shown in FIG. 8 and FIG. 4). For the film formation method and conductive material of the common auxiliary electrode CMTL, reference may be made to the description of the light shielding layer LS. After forming a conductive film on the fourth insulating layer IL4, the conductive film is processed so as to cover the gate wiring GL1 and the wiring W3, whereby the common auxiliary electrode CMTL arranged in a lattice shape can be formed.

[0123] Next, a common electrode CTCO is formed on the common auxiliary electrode CMTL (see step S1025 shown in FIG. 8 and FIG. 4). For the film formation method and transparent conductive material of the common electrode CTCO, reference may be made to the description of the connection electrode ZTCO. After forming a transparent conductive film on the fourth insulating layer IL4 and the common auxiliary electrode CMTL, the transparent conductive film is processed so as to overlap with the common auxiliary electrode CMTL, whereby the common electrode CTCO arranged in a lattice shape can be formed. The common electrode CTCO and the common auxiliary electrode CMTL function as common wiring. Although the common electrode CTCO is formed of a transparent conductive material and has a high resistance, the resistance can be reduced by providing it in contact with the common auxiliary electrode CMTL. Further, since the common auxiliary electrode CMTL has light shielding properties, it also functions as a black matrix.

[0124] Next, a spacer SP is formed in the opening PCON (see step S1026 shown in FIG. 8 and FIG. 4). The spacer SP is formed using an organic resin so that the organic resin protrudes from the substrate surface. The spacer SP does not have to be formed in all the openings PCON. When the spacer SP is not formed, the opening PCON may be only filled with the organic resin and the organic resin may not protrude from the surface.

[0125] Next, an alignment film OF1 is formed on the substrate SUB1, a seal portion 200 is applied so as to surround the display region 122, and liquid crystal is dropped. The counter substrate SUB2 on which the black matrix BM and the like are formed is bonded to the substrate SUB1 so as to face each other, and the seal portion 200 is cured. Through the above steps, the display device 10 can be manufactured.

[0126] In this embodiment, silicon nitride layers are used as the passivation layers PAS1 to PAS3 formed over the gate wiring GL1. Therefore, the passivation layer PAS2 is in contact with the passivation layer PAS1 and the passivation layer PAS3. The wiring W3 is sandwiched between the passivation layer PAS1 and the passivation layer PAS2, and the connection electrode ZTCO is sandwiched between the passivation layer PAS2 and the passivation layer PAS3. Thereby, the adhesion of the passivation layers PAS1 to PAS3 is improved. Further, the passivation layers PAS1 to PAS3 are formed at a low temperature of 150°C or higher and 250°C or lower. Thereby, it is possible to prevent hydrogen contained in the source gas and hydrogen contained in the silicon nitride layer from diffusing due to the heat applied during the film formation of the passivation layers PAS1 to PAS3. Further, since silicon oxide is not used as the passivation layers PAS1 to PAS3, film formation dust during film formation can be suppressed.

[0127] In the transistor Tr1 including the oxide semiconductor layer formed by the above manufacturing method OS even if the channel length L of the channel region OS1 is set to 0.5 μm or more and 2.0 μm or less, good transistor characteristics can be obtained. Since a miniaturized transistor can be formed, the pixel circuit can also be miniaturized. Thereby, a high-definition display device 10 can be provided.

[0128] This The mobility in the embodiment is the field-effect mobility in the saturation region of the transistor, and means the maximum value of the field-effect mobility in a region where the potential difference (Vd) between the source electrode and the drain electrode is larger than the value (Vg-Vth) obtained by subtracting the threshold voltage (Vth) of the transistor from the voltage (Vg) supplied to the gate electrode.

[0129] <7. Modification Example 1> Next, a first modification example of the display device 10 will be described with reference to FIGS. 18 to 21. In the present embodiment, a configuration in which only a silicon nitride layer is used as the passivation layers PAS1 to PAS3 and silicon oxide is not used has been described. In this modification example, a case where a silicon oxide layer SO is formed on the passivation layer PAS1 will be described.

[0130] FIG. 18 is a cross-sectional view showing an outline of a display device 10A according to an embodiment of the present invention. The display device 10A shown in FIG. 18 is different from the configuration of the display device 10 shown in FIG. 4 in that a silicon oxide layer SO is provided between the passivation layer PAS1 and the wiring W3.

[0131] FIG. 19 is a sequence diagram for explaining a manufacturing method of the display device 10A according to an embodiment of the present invention. In this modification example, steps S1027 and S1016, which are different from the sequence diagrams shown in FIGS. 7 and 8, will be described in more detail.

[0132] A silicon oxide layer SO is formed on the passivation layer PAS1 (see steps S1027 shown in FIG. 19 and FIG. 20). As described above, since film deposition dust is generated when forming the silicon oxide layer, the film thickness T1 of the silicon oxide layer SO is preferably smaller than the film thicknesses of the passivation layers PAS1 to PAS3. For example, it is preferably formed with a film thickness of 10 nm or more and 50 nm, or 10 nm or more and 30 nm or less. Thereby, generation of film deposition dust during film formation can be suppressed. Further, by setting the temperature for forming the silicon oxide layer SO to 150° C. or higher and 250° C. or lower, diffusion of hydrogen contained in the passivation layer PAS1 can be suppressed.

[0133] Next, an opening SCON1 that reaches the low-resistance region OS2 is formed in the passivation layer PAS1. Thereafter, a wiring W3 is formed on the passivation layer PAS1, and the wiring W3 is connected to the low-resistance region OS2 through the opening SCON1 (see step S1016 shown in FIG. 8 and FIG. 21). For the film formation method and conductive material of the wiring W3, reference may be made to the description of the light-shielding layer LS. The wiring W3 can be formed by processing a conductive film, but the passivation layer PAS1 may also be etched when processing the conductive film. By forming a thin silicon oxide layer SO on the passivation layer PAS1, the silicon oxide layer SO can function as an etching stopper.

[0134] In this modification, all of the silicon oxide layer SO exposed from the wiring W3 is removed by etching. Therefore, as shown in FIG. 21, a silicon oxide layer SO is provided between the passivation layer PAS1 and the wiring W3. Since the silicon oxide layer SO is masked by the wiring W3, it remains at the film thickness when it is formed. Therefore, the film thickness T1 of the silicon oxide layer SO shown in FIG. 21 is 10 nm or more and 50 nm, or 10 nm or more and 30 nm or less. Thereafter, by forming a silicon nitride layer as the passivation layer PAS2 on the passivation layer PAS1, the adhesion between the passivation layer PAS1 and the passivation layer PAS2 can be improved. Therefore, in this modification, in addition to obtaining the effects described in the manufacturing process of FIGS. 7 to 8, it is possible to suppress the passivation layer PAS1 from being etched more than necessary during the processing of the wiring W3.

[0135] <8. Modification 2> Next, a second modification example of the display device 10 will be described with reference to FIGS. 22 and 23. In the first modification example, the case where the silicon oxide layer SO is formed on the passivation layer PAS1 and then all the silicon oxide layer SO exposed from the wiring W3 is removed during the formation of the wiring W3 was described. In this modification example, the case where the wiring W3 is processed so that the silicon oxide layer SO remains will be described. Therefore, the sequence diagram for explaining the manufacturing method of the display device 10B is substantially the same as FIG. 19.

[0136] FIG. 22 is a cross-sectional view showing an outline of a display device 10B according to an embodiment of the present invention. In this modification example, a configuration is provided in which a silicon oxide layer SO is provided between the passivation layer PAS1 and the passivation layer PAS2. In the silicon oxide layer SO, the thickness T1 of the first region overlapping the wiring W3 is larger than the thickness T2 in the second region not overlapping the wiring W3.

[0137] In this modification example, in the sequence diagram shown in FIG. 19, the process of step S1016 is different from that of the first modification example. Since the silicon oxide layer SO is formed with a film thickness of 10 nm or more and 50 nm or less, preferably 10 nm or more and 30 nm or less, the film thickness T1 is the film thickness in the state where the silicon oxide layer SO is formed. On the other hand, since the region exposed from the wiring W3 is removed by etching, the film thickness T2 becomes smaller than the film thickness T1. The film thickness T2 may be larger than 0 nm and less than 10 nm. The conductive film is etched to form the wiring W3 so that the silicon oxide layer SO remains.

[0138] By providing a thin silicon oxide layer SO between the passivation layer PAS1 and the passivation layer PAS2, the diffusion of hydrogen contained in the layer above the passivation layer PAS2 can be suppressed. In addition, since the film thickness of the silicon oxide layer SO is smaller than the film thicknesses of the passivation layers PAS1 to PAS3, the influence of film formation dust during film formation can also be reduced.

[0139] <9. Third Modification Example> Next, a third modification example of the display device 10 will be described with reference to FIGS. 24 and 25. In this modification example, a manufacturing method that is partially different from the manufacturing method of the display device 10 will be described.

[0140] FIG. 24 is a cross-sectional view showing an outline of a display device 10C according to an embodiment of the present invention. As shown in FIG. 24, the configuration of the transistor Tr1 is different from the configuration of the transistor Tr1 shown in FIG. 4. In FIG. 24, the metal oxide layer MO1 formed under the oxide semiconductor layer OS is omitted.

[0141] FIG. 25 is a sequence diagram for explaining a manufacturing method of the display device 10C according to an embodiment of the present invention. The sequence diagram shown in FIG. 25 is partially different from the sequence diagram shown in FIG. 7. As shown in FIG. 25, the step of forming the metal oxide layer MO1 on the second insulating layer IL2 (step S1004 shown in FIG. 7) and the step of patterning the metal oxide layer MO1 (step S1008 shown in FIG. 7) are omitted. Note that the steps after step S1014 shown in FIG. 25 are the same as the steps shown in FIG. 8, so detailed description thereof is omitted. In this modification example, although the metal oxide layer MO1 is omitted, the first gate insulating layer GI1 is capped by the metal oxide layer MO2. As a result, oxygen released from the second insulating layer IL2 and the first gate insulating layer GI1 by subsequent oxidation annealing is capped by the metal oxide layer MO2, so that OS it is supplied to the upper and lower surfaces of the oxide semiconductor layer, and oxygen defects are repaired. Therefore, it is possible to efficiently supply oxygen to the oxygen defects of the oxide semiconductor layer OS efficiently.

[0142] <10. Fourth Modification Example> Next, a fourth modification example of the display device 10 will be described with reference to FIG. 26. In this modification example, a manufacturing method that is partially different from the manufacturing method of the display device 10 will be described. Note that the cross-sectional structure of the display device according to this modification example is the same as the cross-sectional structure of the display device 10C shown in FIG. 24, so illustration thereof is omitted.

[0143] FIG. 26 is a sequence diagram for explaining a method of manufacturing a display device according to an embodiment of the present invention. The sequence diagram shown in FIG. 26 is partly different from the sequence diagram shown in FIG. 7. As shown in FIG. 26, the step of forming the metal oxide layer MO2 on the first gate insulating layer GI1 (step S1010 shown in FIG. 7) and the step of removing the metal oxide layer MO2 (step S1012 shown in FIG. 7) are omitted. Note that the steps after step S1014 shown in FIG. 26 are the same as those shown in FIG. 8, and thus detailed description thereof is omitted. In this modification, although the metal oxide layer MO2 is omitted, the metal oxide layer MO1 caps the lower side of the oxide semiconductor layer OS Thereby, oxygen released from the second insulating layer IL2 by subsequent thermal annealing is supplied to the upper and lower surfaces of the oxide semiconductor layer OS so that oxygen vacancies are repaired. Further, since oxygen released from the second insulating layer IL2 is blocked by the metal oxide layer MO1 and is suppressed from being supplied in a large amount to the lower surface of the oxide semiconductor layer OS it is possible to suppress the formation of defect levels. Therefore, oxygen can be efficiently supplied to the oxygen vacancies of the oxide semiconductor layer OS

[0144] As described in Modification 3 and Modification 4, by performing annealing in a state where the metal oxide layer MO1 or the metal oxide layer MO2 is formed on at least one of the lower surface and the upper surface of the oxide semiconductor layer OS oxygen can be supplied to the oxygen vacancies of the oxide semiconductor layer OS

[0145] Also in the method of manufacturing the display device 10 according to this Modification 3 and Modification 4, in the transistor Tr1 including the oxide semiconductor layer OS even if the channel length L of the channel region OS1 is set to 0.5 μm or more and 2 μm or less, good transistor characteristics can be obtained. Since a miniaturized transistor can be formed, the pixel circuit can also be miniaturized. Thereby, a high-definition display device 10 can be provided.

[0146] ​​Also in the method for manufacturing the display device 10C according to the third and fourth modified examples , acid Compound semiconductor layer OS can be formed 。

[0147] Each of the embodiments described above as embodiments of the present invention can be implemented in appropriate combination as long as they do not contradict each other. Further, based on the semiconductor device and the display device of each embodiment, those in which those skilled in the art have appropriately added, deleted, or changed the design of components, or added, omitted, or changed the conditions of the process are also included in the scope of the present invention as long as they have the gist of the present invention.

[0148] Even other effects different from the effects brought about by the aspects of each of the above-described embodiments, those that are obvious from the description of this specification or those that can be easily predicted by those skilled in the art are naturally understood to be brought about by the present invention.

Description of Reference Numerals

[0149] 10, 10A to 10C: indicating device, 100: array substrate, 110: first driving circuit, 111: multiplexer circuit, 112: analog switch, 115: wiring portion, 116: data signal supply line, 120: second driving circuit, 121: peripheral region, 122: display region, 124: seal region, 126: exposed region, 129: scanning signal line, 131: data signal line, 141: connection wiring, 143: connection portion, 145: common wiring, 146: common electrode, 150: terminal portion, 160: transistor, 161: first gate electrode, 163: first source electrode, 164: first drain electrode, 168: capacitor element, 170: liquid crystal element, 180: pixel, 182: pixel circuit, 190: counter substrate, 192: light shielding portion, 200: seal portion, 300: flexible printed circuit board, 400: IC chip, AOS: oxide semiconductor layer, B: sub-pixel, BM: black matrix, CF: color filter, CMTL: common auxiliary electrode, CON1: contact region, CTCO: common electrode, G: sub-pixel, GI1: first gate insulating layer, GI2: second gate insulating layer, GL1: gate wiring, GL2: gate electrode, IL1: first insulating layer, IL2: second insulating layer, IL3: third insulating layer, IL4: fourth insulating layer, LC: liquid crystal layer, LS: light shielding layer, MO1, MO2: metal oxide layer, OC: overcoat layer, OF1, OF2: alignment film, OS1: channel region, OS2: low resistance region, PAS1 to PAS3: passivation layer, PCON: opening, OS : oxide semiconductor layer, PTCO: pixel electrode, R: sub-pixel, S: semiconductor layer, S1: semiconductor layer, S2: semiconductor layer, S3: semiconductor layer, SCON1: opening, SCON2: opening, SO: silicon oxide layer, SP: spacer, SUB1: substrate, SUB2: counter substrate, Tr, Tr1, Tr2, Tr2-1, Tr2-2: transistor, W: wiring group, W1 to W3: wiring, WC1, WC2: opening, ZCON: opening, ZTCO: connection electrode

Claims

1. An oxide semiconductor layer, a gate insulating layer provided on the oxide semiconductor layer, a gate electrode provided on the gate insulating layer and facing the oxide semiconductor layer, a first silicon nitride layer provided in contact with the gate electrode, a source wiring provided in contact with the first silicon nitride layer and electrically connected to the oxide semiconductor layer, a second silicon nitride layer provided in contact with the source wiring and the first silicon nitride layer, a first transparent conductive layer provided in contact with the second silicon nitride layer and electrically connected to the oxide semiconductor layer, and a third silicon nitride layer provided in contact with the first transparent conductive layer and the second silicon nitride layer, and a display device, wherein a channel length of the gate electrode is 2.0 μm or less.

2. The display device according to claim 1, further comprising a silicon oxide layer between the source wiring and the first silicon nitride layer.

3. The display device according to claim 2, wherein a film thickness of the silicon oxide layer is 10 nm or more and 50 nm or less.

4. The display device according to claim 1, further comprising an aluminum oxide layer between the gate insulating layer and the oxide semiconductor layer.

5. An oxide semiconductor layer, a gate insulating layer provided on the oxide semiconductor layer, a gate electrode provided on the gate insulating layer and facing the oxide semiconductor layer, a first silicon nitride layer provided in contact with the gate electrode, a silicon oxide layer provided in contact with the first silicon nitride layer, a source wiring provided in contact with the silicon oxide layer and electrically connected to the oxide semiconductor layer, a second silicon nitride layer provided in contact with the source wiring and the silicon oxide layer, a first transparent conductive layer provided in contact with the second silicon nitride layer and electrically connected to the oxide semiconductor layer, and a third silicon nitride layer provided in contact with the first transparent conductive layer and the second silicon nitride layer, and a display device, wherein a channel length of the gate electrode is 2.0 μm or less, and a film thickness of the silicon oxide layer is smaller than film thicknesses of the first silicon nitride layer, the second silicon nitride layer, and the third silicon nitride layer.

6. The display device according to claim 5, wherein in the silicon oxide layer, a film thickness of a first region overlapping with the source wiring is larger than a film thickness of a second region not overlapping with the source wiring.

7. The display device according to claim 6, wherein the film thickness of the first region of the silicon oxide layer is 10 nm or more and 50 nm or less.

8. The display device according to claim 6, wherein the film thickness of the second region of the silicon oxide layer is greater than 0 nm and less than 10 nm.

9. The display device according to claim 5, further comprising an aluminum oxide layer between the gate insulating layer and the oxide semiconductor layer.

10. Form an oxide semiconductor layer, Form a gate insulating layer on the oxide semiconductor layer, Form a gate electrode facing the oxide semiconductor layer on the gate insulating layer, Form a first silicon nitride layer in contact with the gate electrode, Form a source wiring electrically connected to the oxide semiconductor layer in contact with the first silicon nitride layer, Form a second silicon nitride layer in contact with the source wiring and the first silicon nitride layer, Form a first transparent conductive layer electrically connected to the oxide semiconductor layer in contact with the second silicon nitride layer, Including forming a third silicon nitride layer in contact with the first transparent conductive layer and the second silicon nitride layer, In the oxide semiconductor layer, the channel length of the channel region overlapping the gate electrode is 2.0 μm or less, A method for manufacturing a display device, wherein the film formation temperature of each of the first silicon nitride layer, the second silicon nitride layer, and the third silicon nitride layer is 150° C. or more and 250° C. or less.

Images