Multilayer ceramic capacitor and method of manufacturing the same

Abstract

To provide a multilayer ceramic capacitor in which internal electrode connectivity is improved due to a reduction in sintering mismatching between a dielectric layer and an internal electrode layer and reliability such as a withstand voltage characteristic or the like is improved.SOLUTION: There are provided a multilayer ceramic capacitor and a method of manufacturing the same. The multilayer ceramic capacitor includes: a capacitor body that includes a dielectric layer and an internal electrode layer; and an external electrode that is disposed outside the capacitor body. The internal electrode layer includes nickel (Ni) and cerium (Ce). When, in the case where the internal electrode layer is divided into three equal portions in a thickness direction to be divided into an upper portion, a middle portion, and a lower portion, the middle portion is referred to as a central region and at least one of the upper and lower portions having an interface with the dielectric layer is referred to as an interface region, both the central region and the interface region include the cerium (Ce), and the interface region includes the cerium (Ce) in a content higher than a content of cerium (Ce) in the central region.SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] The present disclosure relates to a multilayer ceramic capacitor and a manufacturing method thereof. [Background technology]

[0002] Electronic components using ceramic materials include capacitors, inductors, piezoelectric elements, varistors, thermistors, etc. Among these ceramic electronic components, multilayer ceramic capacitors (MLCCs) have the advantages of being small, having high capacitance, and being easy to mount, and can be used in a variety of electronic devices.

[0003] For example, the multilayer ceramic capacitor can be used as a chip-type capacitor that is mounted on substrates of various electronic products such as imaging devices such as liquid crystal displays (LCDs), plasma display panels (PDPs), and organic light-emitting diodes (OLEDs), computers, personal portable terminals, and smartphones, and serves to charge and discharge electricity.

[0004] Recently, there is a strong demand for multilayer ceramic capacitors to be more compact and perform better. To achieve high-capacity, compact multilayer ceramic capacitors, the dielectric layers and internal electrode layers must be thinner, but the thinner the dielectric layers and internal electrode layers are, the more reliability problems arise, such as the occurrence of short circuits and deterioration of the breakdown voltage (BDV), which is a DC and voltage resistance characteristic. Meanwhile, multilayer ceramic capacitors used in autonomous vehicles or electric cars require not only thin layers but also high reliability. Summary of the Invention [Problem to be solved by the invention]

[0005] According to an embodiment, there is provided a multilayer ceramic capacitor having improved reliability such as withstand voltage characteristics, by improving the connectivity of the internal electrodes through a reduction in sintering mismatching between the dielectric layers and the internal electrode layers.

[0006] Another embodiment provides a method for manufacturing the multilayer ceramic capacitor. [Means for solving the problem]

[0007] One embodiment provides a multilayer ceramic capacitor including a capacitor body including a dielectric layer and an internal electrode layer, and an external electrode disposed on an outside of the capacitor body, the internal electrode layer including nickel (Ni) and cerium (Ce), and when the internal electrode layer is divided into three equal parts in a thickness direction into an upper part, a middle part, and a lower part, the middle part is defined as a central region, and at least one of the upper part and the lower part having an interface with the dielectric layer is defined as an interface region, the cerium (Ce) is contained in the central region and the interface region, and the cerium (Ce) is contained in a higher content in the interface region than in the central region.

[0008] The cerium (Ce) is contained at a content 1.5 to 3 times higher in the interface region than in the central region.

[0009] The cerium (Ce) is contained in the internal electrode layer in an amount of 0.01 parts by weight to 5 parts by weight relative to 100 parts by weight of the nickel (Ni).

[0010] The internal electrode layers may further include copper (Cu), silver (Ag), palladium (Pd), gold (Au), an alloy thereof, or a combination thereof.

[0011] The dielectric layer may include a barium titanate-based main component including barium (Ba) and titanium (Ti), and cerium (Ce).

[0012] When the dielectric layer is divided into three equal parts in the thickness direction into an upper part, a middle part and a lower part, the middle part is defined as a central region, and at least one of the upper part and the lower part having an interface with the internal electrode layer is defined as an interface region, the cerium (Ce) is contained in the interface region of the dielectric layer.

[0013] The cerium (Ce) is contained in an amount of 0.05 to 1 part by mol relative to 100 parts by mol of the barium (Ba) in the interface region of the dielectric layer.

[0014] The cerium (Ce) is contained in an amount of 0.05 to 1 part by mol relative to 100 parts by mol of the barium (Ba) in a region in the interface region of the dielectric layer to a depth of 10 to 100 nm from the interface with the internal electrode layer.

[0015] The interface region of the dielectric layer may include a plurality of dielectric crystal grains, and at least one of the dielectric crystal grains may have a structure including a core and a shell surrounding the core, and the shell may include the cerium (Ce).

[0016] The size (D50) of the dielectric crystal grains may be 50 nm to 250 nm.

[0017] The cerium (Ce) contained in the dielectric layers originates from cerium oxide (CeO2) used when forming the internal electrode layers, and may be a component that diffuses from the dielectric layers after sintering.

[0018] Another embodiment provides a method for manufacturing a multilayer ceramic capacitor, the method comprising the steps of: preparing a conductive paste by mixing raw materials including nickel (Ni) and cerium oxide (CeO2); preparing a dielectric green sheet using a dielectric slurry, and printing the conductive paste on a surface of the dielectric green sheet to form a conductive paste layer; laminating the dielectric green sheets on which the conductive paste layer is formed to prepare a dielectric green sheet laminate; sintering the dielectric green sheet laminate to prepare a capacitor body including a dielectric layer and an internal electrode layer; and forming an external electrode on one surface of the capacitor body, wherein the internal electrode layer includes nickel (Ni) and cerium (Ce), and when the internal electrode layer is divided into three equal parts in a thickness direction into an upper part, a middle part, and a lower part, the middle part is defined as a central region, and at least one of the upper part and the lower part having an interface with the dielectric layer is defined as an interface region, the cerium (Ce) is contained in the central region and the interface region, and the cerium (Ce) is contained in a higher content in the interface region than in the central region.

[0019] The cerium oxide (CeO2) is mixed in an amount of 0.01 to 5 parts by weight based on 100 parts by weight of the nickel (Ni).

[0020] The source material may further include copper (Cu), silver (Ag), palladium (Pd), gold (Au), alloys thereof, or combinations thereof.

[0021] The dielectric slurry is produced by mixing a barium titanate-based main component powder and, optionally, a subcomponent powder.

[0022] The sintering is carried out at a temperature of 1000°C to 1400°C. Effect of the Invention

[0023] In the multilayer ceramic capacitor according to an embodiment, sintering mismatching between the dielectric layers and the internal electrode layers is reduced, improving the connectivity of the internal electrodes, and improving reliability such as withstand voltage characteristics. [Brief description of the drawings]

[0024] [Figure 1] 1 is a perspective view illustrating a multilayer ceramic capacitor according to an embodiment; [Diagram 2] 2 is a cross-sectional view of the multilayer ceramic capacitor taken along line II' in FIG. [Diagram 3] 2 is a cross-sectional view of the multilayer ceramic capacitor taken along line II-II' in FIG. [Figure 4] FIG. 4 is a schematic diagram showing a part of the active area in FIG. [Diagram 5] This is a SEM-EDS analysis image of the active area of ​​a multilayer ceramic capacitor. [Figure 6] 1 is a SEM-EDS (Scanning Electron Microscope-Energy Dispersive Spectroscopy) analysis image of an active area of ​​the multilayer ceramic capacitor according to Example 1. [Figure 7] 1 is a thermomechanical analysis (TMA) graph for internal electrode layer materials according to Example 6 and Comparative Example 1. [Figure 8A] 4 is a scanning electron microscope (SEM) analysis image of an interface region of a dielectric layer according to Example 1. [Figure 8B] 1 is a scanning electron microscope (SEM) analysis image of an interface region of a dielectric layer according to Example 2. [Figure 8C] 11 is a scanning electron microscope (SEM) analysis image of an interface region of a dielectric layer according to Example 4. [Figure 8D] 11 is a scanning electron microscope (SEM) analysis image of an interface region of a dielectric layer according to Example 5. [Figure 8E] 13 is a scanning electron microscope (SEM) analysis image of an interface region of a dielectric layer according to Example 7. [Figure 9] 1 is a graph showing the dielectric constant of dielectrics according to Examples 1, 2, 4 and 5. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0025] Hereinafter, with reference to the accompanying drawings, an embodiment of the present invention will be described in detail so that a person having ordinary skill in the art to which the present invention pertains can easily carry out the present invention. In the drawings, parts that are unnecessary for the explanation are omitted in order to clearly explain the present invention, and the same reference numerals are used for the same or similar components throughout the specification. In addition, in the accompanying drawings, some components are exaggerated, omitted, or shown in a schematic manner, and the size of each component does not completely reflect the actual size.

[0026] It should be understood that the attached drawings are merely intended to facilitate understanding of the embodiments disclosed in this specification, and do not limit the technical ideas disclosed in this specification, but include all modifications, equivalents, or alternatives included in the idea and technical scope of the present invention.

[0027] Terms including ordinal numbers such as first, second, etc. may be used to describe various components, but the components are not limited by the terms. The terms are used only to distinguish one component from another.

[0028] In addition, when a part such as a layer, film, region, or plate is said to be "above" another part, this includes not only the case where it is "directly above" the other part, but also the case where there is another part in between. Conversely, when a part is said to be "directly above" another part, it means that there is no other part in between. Furthermore, being "above" a reference part means being located above or below the reference part, and does not necessarily mean being located "above" the opposite direction of gravity.

[0029] It should be understood that, throughout the specification, the terms "comprise" or "have" are intended to specify the presence of a feature, number, step, operation, component, part, or combination thereof described in the specification, but do not preclude the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof. Thus, when a part "comprises" a certain element, this means that it can further include other elements, but not to the exclusion of other elements, unless specifically stated to the contrary.

[0030] Also, throughout the specification, "on a plane" means when the subject part is viewed from above, and "on a cross section" means when the subject part is cut vertically and viewed from the side.

[0031] Furthermore, throughout the specification, when the term "connected" is used, this does not only mean that two or more components are directly connected, but also that two or more components are indirectly connected via other components, and can mean not only that they are physically connected but also that they are electrically connected, or that they are referred to by different names depending on their position or function.

[0032] Hereinafter, a multilayer ceramic capacitor according to an embodiment will be described with reference to FIGS.

[0033] FIG. 1 is a perspective view showing a multilayer ceramic capacitor according to one embodiment, FIG. 2 is a cross-sectional view of the multilayer ceramic capacitor taken along line II' in FIG. 1, FIG. 3 is a cross-sectional view of the multilayer ceramic capacitor taken along line II-II' in FIG. 1, and FIG. 4 is a schematic view showing a portion of the active area in FIG. 3.

[0034] The L axis, W axis, and T axis shown in Figs. 1 to 4 respectively indicate the longitudinal direction, width direction, and thickness direction of the capacitor body 110. Here, the thickness direction (T axis direction) may be a direction perpendicular to the wide surface (main surface) of the sheet-shaped component, and may be used in the same concept as the lamination direction in which the dielectric layers 111 are laminated, for example. The longitudinal direction (L axis direction) is a direction extending in parallel to the wide surface (main surface) of the sheet-shaped component and approximately perpendicular to the thickness direction (T axis direction), and may be, for example, a direction in which the first external electrode 131 and the second external electrode 132 are located on both sides. The width direction (W axis direction) may be a direction extending in parallel to the wide surface (main surface) of the sheet-shaped component and approximately perpendicular to the thickness direction (T axis direction) and the longitudinal direction (L axis direction), and the length of the longitudinal direction (L axis direction) of the sheet-shaped component is longer than the length of the width direction (W axis direction).

[0035] 1 to 4, a multilayer ceramic capacitor 100 according to an embodiment includes a capacitor body 110 and external electrodes 131, 132 disposed on the outer side of the capacitor body 110. The external electrodes 131, 132 may include a first external electrode 131 and a second external electrode 132 disposed on opposite ends of the capacitor body 110 in a longitudinal direction (L-axis direction).

[0036] For example, the capacitor body 110 may have a substantially hexahedral shape.

[0037] For the convenience of describing one embodiment, in capacitor body 110, the two surfaces that face each other in the thickness direction (T-axis direction) are defined as the first surface and the second surface, and the two surfaces that are connected to the first surface and the second surface, the two surfaces that face each other in the longitudinal direction (L-axis direction) are defined as the third surface and the fourth surface, and the two surfaces that are connected to the first surface and the second surface and the third surface and the fourth surface, and the two surfaces that face each other in the width direction (W-axis direction) are defined as the fifth surface and the sixth surface.

[0038] As an example, the first surface of the lower surface is the surface facing the mounting direction. The first to sixth surfaces may be flat, but the embodiment is not limited to this. For example, the first to sixth surfaces may be curved surfaces with a convex center, and the corners that are the boundaries between the surfaces may be rounded.

[0039] The shape and size of the capacitor body 110 and the number of laminated dielectric layers 111 are not limited to those shown in the figure of this embodiment.

[0040] The capacitor body 110 includes a plurality of dielectric layers 111 and internal electrode layers 121 and 122. Specifically, the capacitor body 110 includes a plurality of dielectric layers 111, and first internal electrodes 121 and second internal electrodes 122 that are alternately arranged in the thickness direction (T-axis direction) with the dielectric layers 111 sandwiched between them.

[0041] At this time, the boundaries between the adjacent dielectric layers 111 of the capacitor body 110 are integrated to such an extent that it is difficult to confirm them without using a scanning electron microscope (SEM).

[0042] Referring to FIG. 3, the capacitor body 110 may include an active area.

[0043] The active area is a portion that contributes to forming the capacitance of the multilayer capacitor 100. As an example, the active area may be an area where the first internal electrode 121 or the second internal electrode 122 stacked along the thickness direction (T-axis direction) overlaps.

[0044] Additionally, the capacitor body 110 may further include a cover region and a side margin region.

[0045] The cover region is a marginal portion in the thickness direction and may be located on the first and second sides of the active region in the thickness direction (T-axis direction). Such a cover region may be a single dielectric layer 111 or two or more dielectric layers 111 stacked on the upper and lower surfaces of the active region.

[0046] The side margin regions are widthwise margins and may be located on the fifth and sixth surfaces of the active region in the widthwise direction (W-axis direction). Such side margin regions are formed by applying a conductive paste layer for an internal electrode to only a part of the surface of the dielectric green sheet when applying the conductive paste layer to the surface of the dielectric green sheet, laminating dielectric green sheets on both sides of the surface of the dielectric green sheet without applying the conductive paste layer, and then firing the laminate.

[0047] The cover region and the side margin region serve to prevent the first internal electrode 121 and the second internal electrode 122 from being damaged by physical or chemical stress.

[0048] The first internal electrode 121 and the second internal electrode 122 are electrodes having different polarities and are alternately arranged so as to face each other along the T-axis direction across the dielectric layer 111, and one end can be exposed through the third and fourth surfaces of the capacitor body 110, respectively.

[0049] The first internal electrode 121 and the second internal electrode 122 can be electrically insulated from each other by a dielectric layer 111 disposed therebetween.

[0050] Ends of the first internal electrode 121 and the second internal electrode 122 alternately exposed through the third and fourth surfaces of the capacitor body 110 can be electrically connected to the first external electrode 131 and the second external electrode 132, respectively.

[0051] According to one embodiment, the internal electrode layers 121, 122, ie, the first internal electrode 121 and the second internal electrode 122, include nickel (Ni) and cerium (Ce).

[0052] To realize a thin internal electrode layer, the atomization of the material must be prioritized. When the material of the internal electrode layer is atomized to the nanoparticle level, the smaller the particle size, the lower the melting point tends to be. The phenomenon of lowering the melting point leads to a decrease in the thermal shrinkage start temperature, and in the case of metals, the degree of lowering of the melting point is even greater than that of ceramic materials, which results in further increase in sintering mismatching between the internal electrode layer and the dielectric layer during the firing process of the multilayer ceramic capacitor. For example, when sintering mismatching is maximized, there may be a difference of more than 500 degrees Celsius at the time of sintering the dielectric layer and the internal electrode layer. The internal electrode layer starts to sinter earlier than the dielectric layer, so nearby particles aggregate and balling occurs, and the thinly printed parts break first, causing deterioration of connectivity. To solve this problem, a method of adding a co-material to the internal electrode layer is used. However, if the amount of the common material added is large, the film density of the internal electrode layer may decrease, and the common material may be squeezed out toward the dielectric layer, resulting in a side effect of increasing the thickness of the dielectric layer.

[0053] According to one embodiment, it is possible to solve the deterioration of the connectivity of the internal electrodes due to sintering mismatch by applying cerium (Ce), which has better thermal stability and a higher melting point than barium titanate (BaTiO3) used as the common material, to the internal electrode layers 121 and 122. For reference, the melting point of nickel oxide (NiO) is 1,455°C, the melting point of barium titanate (BaTiO3) is 1,625°C, and the melting point of cerium oxide (CeO2) is 2,400°C. Cerium (Ce) is a non-reducing material and has a large sintering retarding effect.

[0054] In other words, the internal electrode layers 121 and 122 according to an embodiment include cerium (Ce), thereby increasing the thermal stability of the internal electrode layers during high-temperature firing, thereby reducing sintering mismatch between the dielectric layers and the internal electrode layers and improving the connectivity of the internal electrodes. Also, cerium (Ce) diffuses into the dielectric layer 111 during firing to improve degradation caused by oxygen vacancies, thereby improving reliability such as voltage resistance.

[0055] Specifically, cerium (Ce) is contained in an amount of 0.01 to 5 parts by weight, for example, 0.05 to 3 parts by weight, or 0.08 to 2.5 parts by weight, relative to 100 parts by weight of nickel (Ni) in the internal electrode layers 121 and 122. When cerium (Ce) is contained in the internal electrode layers 121 and 122 within the above content range, the thermal stability of the internal electrode layers during high-temperature firing can be increased, thereby reducing sintering mismatch between the dielectric layers and the internal electrode layers, and cerium (Ce) can diffuse into the dielectric layers during firing to improve deterioration due to oxygen vacancies.

[0056] The sintering mismatch between the dielectric layers and the internal electrode layers is reduced, improving the connectivity of the internal electrodes, and improving reliability such as voltage resistance characteristics.

[0057] Cerium (Ce) may be present in both the central region and the interface region of the internal electrode layers 121, 122. Here, the central region and the interface region are described with reference to Fig. 4. That is, when the internal electrode layers 121, 122 are divided into three equal parts in the thickness direction into an upper part, a middle part, and a lower part, the middle part is defined as a central region A, and at least one of the upper part and the lower part having the interface between the dielectric layer 111 and the internal electrode layers 121, 122 is defined as an interface region B.

[0058] Specifically, the cerium (Ce) in the internal electrode layers 121, 122 is contained at a higher content in the interface region B than in the central region A. For example, the cerium (Ce) is contained at a content 1.5 to 3 times higher in the interface region B than in the central region A, for example, 1.7 to 2.8 times, 2.0 to 2.5 times higher. When the cerium (Ce) is contained at a higher content within the above range in the interface region B than in the central region A, the sintering mismatch between the dielectric layer and the internal electrode layer is reduced to improve the connectivity of the internal electrodes, and the interface reliability and voltage resistance characteristics can be improved.

[0059] The cerium (Ce) content in the internal electrode layers 121, 122 and the cerium (Ce) content ratio in the interface region B to the central region A in the internal electrode layers 121, 122 can be measured by SEM-EDS (scanning electron microscope-energy dispersive spectroscopy).

[0060] Specifically, the multilayer ceramic capacitor 100 is placed in an epoxy mixture and hardened, and then the W-axis and T-axis directions (WT directions) of the capacitor body 110 are polished to the 1 / 2 point in the L-axis direction, fixed, and maintained in a vacuum atmosphere chamber to obtain a cross-sectional sample so that the active area where the dielectric layer 111 and the internal electrode layers 121 and 122 intersect can be observed.

[0061] Next, the active area of ​​the cross-sectional sample, for example, the central portion indicated by C in Fig. 3, can be measured with a scanning electron microscope (SEM). The scanning electron microscope can be, for example, a Verios G4 product from Thermofisher Scientific, with measurement conditions of 10 kV, 0.2 nA, and an analysis magnification of 50 k times, and can be measured so that at least one, three, five, or ten dielectric layers 111 and internal electrode layers 121, 122 are exposed.

[0062] Next, the content and composition of cerium (Ce) can be analyzed by point-EDS analysis in a scanning electron microscope (SEM) image of the measured cross-sectional sample. In the point-EDS analysis, at least one point, three points, five points, or ten points can be specified at intervals of 100 nm to 1000 nm, for example, at intervals of 300 nm to 700 nm, in each of the central region A and interface region B of the internal electrode layers 121 and 122, and the interface region B' of the dielectric layer 111, and the cerium (Ce) content at each point can be measured and the arithmetic average value thereof can be obtained. For example, FIG. 5 is an image showing the SEM-EDS analysis positions for the active region of the multilayer ceramic capacitor, and as shown in FIG. 5, the point-EDS analysis positions can be represented by five points.

[0063] The internal electrode layers 121, 122, i.e., the first internal electrode 121 and the second internal electrode 122, may further include a conductive metal in addition to nickel (Ni) and cerium (Ce). Examples of the conductive metal may be copper (Cu), silver (Ag), palladium (Pd), gold (Au), alloys thereof, such as Ag-Pd alloys, or combinations thereof.

[0064] Furthermore, the internal electrode layers 121 and 122 may contain dielectric particles having the same composition as the ceramic material contained in the dielectric layer 111 .

[0065] The cerium (Ce) contained in the internal electrode layers 121, 122 may be an element derived from cerium oxide (CeO2) used in manufacturing the internal electrode layers 121, 122 of the multilayer ceramic capacitor 100. Specifically, the internal electrode layers 121, 122 are formed using a conductive paste obtained by mixing raw materials containing nickel (Ni) and cerium oxide (CeO2). The conductive paste can be printed using a screen printing method or a gravure printing method.

[0066] The average thickness of the first internal electrode 121 and the second internal electrode 122 may be 0.1 μm to 2 μm. This is determined by taking the center point of the first internal electrode 121 or the second internal electrode 122 in the longitudinal direction (L-axis direction) or width direction (W-axis direction) as a reference point in a scanning electron microscope (SEM) image of the cross-sectional sample measured as described above, and calculating the arithmetic average value of the thicknesses of the first internal electrode 121 or the second internal electrode 122 at 10 points spaced apart by a predetermined distance from the reference point. The interval between the 10 points can be adjusted according to the scale of the scanning electron microscope (SEM) image, and may be, for example, 1 μm to 100 μm, 1 μm to 50 μm, or 1 μm to 10 μm. In this case, all 10 points must be located within the first internal electrode 121 or the second internal electrode 122, and if all 10 points are not located within the first internal electrode 121 or the second internal electrode 122, the position of the reference point can be changed or the interval between the 10 points can be adjusted.

[0067] The dielectric layer 111 according to one embodiment may include a barium titanate based main component including barium (Ba) and titanium (Ti), and cerium (Ce).

[0068] The main component of the barium titanate-based material is a dielectric base material having a high dielectric constant, and contributes to the formation of the dielectric constant of the multilayer ceramic capacitor 100 .

[0069] As an example, the main components of the barium titanate system can include BaTiO3, Ba(Ti,Zr)O3, Ba(Ti,Sn)O3, (Ba,Ca)TiO3, (Ba,Ca)(Ti,Zr)O3, (Ba,Ca)(Ti,Sn)O3, (Ba,Sr)TiO3, (Ba,Sr)(Ti,Zr)O3, (Ba,Sr)(Ti,Sn)O3, or combinations thereof.

[0070] The cerium (Ce) contained in the dielectric layer 111 may be an element derived from cerium oxide (CeO2) used in manufacturing the internal electrode layers 121, 122 of the multilayer ceramic capacitor 100. Specifically, during the sintering process for manufacturing the multilayer ceramic capacitor 100, the cerium (Ce) present in the interface region B of the internal electrode layers 121, 122 may partially diffuse into the dielectric layer 111 in contact with the interface region B. Therefore, the cerium (Ce) contained in the dielectric layer 111 is due to the diffusion of the cerium (Ce) present in the interface region B of the internal electrode layers 121, 122, and such diffusion can improve deterioration caused by oxygen vacancies.

[0071] Cerium (Ce) may be present in the interface region of the dielectric layer 111. Here, the interface region will be described with reference to Fig. 4. That is, when the dielectric layer 111 is divided into three equal parts in the thickness direction into an upper part, a middle part, and a lower part, the middle part is defined as a central region A', and at least one of the upper part and the lower part having an interface between the dielectric layer 111 and the internal electrode layers 121, 122 is defined as an interface region B'.

[0072] Specifically, cerium (Ce) is contained in an amount of 0.05 to 1 molar part, for example, 0.1 to 0.8 molar parts, relative to 100 molar parts of barium (Ba) in the interface region B' of the dielectric layer 111. When cerium (Ce) is contained within the above-mentioned content range in the interface region B' of the dielectric layer 111, it is possible to improve deterioration due to oxygen vacancies caused by the diffusion of cerium (Ce) in the internal electrode layers 121 and 122, specifically, cerium (Ce) present in the interface region B of the internal electrode layers 121 and 122, thereby improving reliability such as withstand voltage characteristics.

[0073] For example, cerium (Ce) is contained in an amount of 0.05 to 1 molar part, for example 0.1 to 0.8 molar parts, relative to 100 molar parts of barium (Ba) in region B″ of interface region B′ of dielectric layer 111, from the interface between dielectric layer 111 and internal electrode layers 121, 122 to a depth of 10 nm to 100 nm, for example 30 nm to 70 nm. When cerium (Ce) is contained within the above content range in region B″ of dielectric layer 111, it is possible to improve deterioration due to oxygen vacancies caused by diffusion of cerium (Ce) present in interface region B of internal electrode layers 121, 122, thereby improving reliability such as voltage resistance characteristics.

[0074] The content and composition of cerium (Ce) in the dielectric layer 111 can be measured by SEM-EDS (scanning electron microscope-energy dispersive spectroscopy). Specifically, the content and composition of cerium (Ce) can be analyzed by point-EDS analysis in a scanning electron microscope (SEM) image of the cross-sectional sample measured as described above. The point-EDS analysis can specify at least one point, three points, five points, or ten points at intervals of 100 nm to 1000 nm, for example, at intervals of 300 nm to 700 nm, in the interface region B' of the dielectric layer 111, and calculate the arithmetic average value of these points.

[0075] The dielectric layer 111 may further include a minor component, such as manganese (Mn), chromium (Cr), silicon (Si), aluminum (Al), magnesium (Mg), tin (Sn), antimony (Sb), germanium (Ge), gallium (Ga), indium (In), barium (Ba), lanthanum (La), yttrium (Y), actinium (Ac), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), ruthenium (Lu), hafnium (Hf), vanadium (V), or a combination thereof.

[0076] According to an embodiment, the interface region B' of the dielectric layer 111 may include a plurality of dielectric crystal grains. The dielectric crystal grains may include a barium titanate-based main component and cerium (Ce), and may optionally include a secondary component.

[0077] At least one of the plurality of dielectric crystal grains may have a core-shell structure including a core and a shell surrounding the core, and each of the core and shell may include a barium titanate-based main component, cerium (Ce), and optionally a secondary component.

[0078] Specifically, according to one embodiment, the shell may include cerium (Ce). Here, cerium (Ce) is due to the diffusion of cerium (Ce) present in the internal electrode layers 121 and 122 as described above, and the cerium (Ce) acts as a donor to the dielectric base material, thereby converting Ba at the A site of the dielectric to Ba. 2+ can be substituted to form a shell to enhance dielectric constant and reliability.

[0079] In addition, by containing cerium (Ce) in the internal electrode layers 121 and 122, the size of the dielectric crystal grains present in the interface region B' of the dielectric layer 111 in contact with the internal electrode layers 121 and 122 can be increased. Specifically, the size (D50) of the dielectric crystal grains may be 50 nm to 250 nm, for example, 70 nm to 230 nm. When the size (D50) of the dielectric crystal grains is within the above range, the dielectric constant and reliability can be improved. The size (D50) of the dielectric crystal grains can be calculated by measuring the maximum long axis of at least 100 dielectric crystal grains in a scanning electron microscope image of the interface region of the dielectric layer in the center part of the active region of the cross-sectional sample, creating a size distribution cumulative curve, and calculating D50. D50 is the size at the 50% point in the cumulative curve of the size distribution.

[0080] The average thickness (average length in the T-axis direction) of the dielectric layer 111 may be 2.0 μm to 8.0 μm, for example, 2.4 μm to 7.8 μm. When the average thickness of the dielectric layer 111 is within the above range, the reliability of the multilayer ceramic capacitor is excellent. This is determined by taking the center point of the dielectric layer 111 in the longitudinal direction (L-axis direction) or width direction (W-axis direction) as a reference point in a scanning electron microscope (SEM) image of the cross-sectional sample measured as described above, and calculating the arithmetic average value of the thickness of the dielectric layer 111 at 10 points spaced apart from the reference point by a predetermined distance. The interval between the 10 points can be adjusted according to the scale of the scanning electron microscope (SEM) image, and may be, for example, 1 μm to 100 μm, 1 μm to 50 μm, or 1 μm to 10 μm. In this case, all of the 10 points must be located within the dielectric layer 111, and if all of the 10 points are not located within the dielectric layer 111, the position of the reference point can be changed or the interval between the 10 points can be adjusted.

[0081] The first external electrode 131 and the second external electrode 132 are provided with voltages of different polarities and are electrically connected to exposed portions of the first internal electrode 121 and the second internal electrode 122, respectively.

[0082] With this configuration, when a predetermined voltage is applied to the first external electrode 131 and the second external electrode 132, charges are stored between the opposing first internal electrode 121 and second internal electrode 122. At this time, the capacitance of the multilayer ceramic capacitor 100 is proportional to the overlap area of ​​the first internal electrode 121 and the second internal electrode 122 that overlap each other along the T-axis direction in the active region.

[0083] The first external electrode 131 and the second external electrode 132 may each include first and second connection portions arranged on the third and fourth surfaces of the capacitor body 110 and connected to the first internal electrode 121 and the second internal electrode 122, respectively, and first and second band portions arranged at corners where the third and fourth surfaces of the capacitor body 110 meet the first and second surfaces or the fifth and sixth surfaces.

[0084] The first and second band portions may extend to parts of the first and second faces or the fifth and sixth faces of the capacitor body 110 at the first and second connection portions, respectively. The first and second band portions may serve to improve the bonding strength between the first external electrode 131 and the second external electrode 132.

[0085] The first external electrode 131 and the second external electrode 132 may each include a sintered metal layer in contact with the capacitor body 110, a conductive resin layer arranged to cover the sintered metal layer, and a plating layer arranged to cover the conductive resin layer.

[0086] The sintered metal layer can include a conductive metal and glass.

[0087] The conductive metal may include copper (Cu), nickel (Ni), silver (Ag), palladium (Pd), gold (Au), platinum (Pt), tin (Sn), tungsten (W), titanium (Ti), lead (Pb), alloys thereof, or combinations thereof, for example, copper (Cu) may include copper (Cu) alloys. When the conductive metal includes copper, the metal other than copper is included in an amount of 5 molar parts or less per 100 molar parts of copper.

[0088] The glass may include a mixed oxide composition, such as one or more selected from the group consisting of silicon oxide, boron oxide, aluminum oxide, transition metal oxide, alkali metal oxide, and alkaline earth metal oxide. The transition metal may be selected from the group consisting of zinc (Zn), titanium (Ti), copper (Cu), vanadium (V), manganese (Mn), iron (Fe), and nickel (Ni), the alkali metal may be selected from the group consisting of lithium (Li), sodium (Na), and potassium (K), and the alkaline earth metal may be one or more selected from the group consisting of magnesium (Mg), calcium (Ca), strontium (Sr), and barium (Ba).

[0089] Alternatively, the conductive resin layer may be formed on the sintered metal layer, for example, to completely cover the sintered metal layer. Meanwhile, the first external electrode 131 and the second external electrode 132 may not include a sintered metal layer, in which case the conductive resin layer may be in direct contact with the capacitor body 110.

[0090] The conductive resin layer extends on the first and second surfaces or the fifth and sixth surfaces of the capacitor body 110, and the length of the region (i.e., band portion) where the conductive resin layer is arranged extending on the first and second surfaces or the fifth and sixth surfaces of the capacitor body 110 is longer than the length of the region (i.e., band portion) where the sintered metal layer is arranged extending on the first and second surfaces or the fifth and sixth surfaces of the capacitor body 110. In other words, the conductive resin layer is formed on the sintered metal layer to completely cover the sintered metal layer.

[0091] The conductive resin layer includes a resin and a conductive metal.

[0092] The resin contained in the conductive resin layer is not particularly limited as long as it has bonding and impact absorbing properties and can be mixed with the conductive metal powder to form a paste, and may include, for example, a phenolic resin, an acrylic resin, a silicone resin, an epoxy resin, or a polyimide resin.

[0093] The conductive metal contained in the conductive resin layer serves to electrically connect with the first internal electrode 121 and the second internal electrode 122 or the sintered metal layer.

[0094] The conductive metal contained in the conductive resin layer may have a spherical shape, a flake shape, or a combination thereof, that is, the conductive metal may be only flake-shaped, only spherical, or a mixture of flake-shaped and spherical shapes.

[0095] Here, the term "spherical" may include shapes that are not completely spherical, and may include shapes in which the ratio of the major axis to the minor axis (major axis / minor axis) is 1.45 or less. The term "flaky powder" refers to a powder having a flat and elongated shape, and is not particularly limited, and may include shapes in which the ratio of the major axis to the minor axis (major axis / minor axis) is 1.95 or more, for example.

[0096] The first external electrode 131 and the second external electrode 132 may further include a plating layer disposed on the outer side of the conductive resin layer.

[0097] The plating layer may include nickel (Ni), copper (Cu), tin (Sn), palladium (Pd), platinum (Pt), gold (Au), silver (Ag), tungsten (W), titanium (Ti), or lead (Pb) alone or in combination with an alloy thereof. For example, the plating layer may be a nickel (Ni) plating layer or a tin (Sn) plating layer, or may be a layer in which a nickel (Ni) plating layer and a tin (Sn) plating layer are sequentially laminated, or a layer in which a tin (Sn) plating layer, a nickel (Ni) plating layer, and a tin (Sn) plating layer are sequentially laminated. The plating layer may include a plurality of nickel (Ni) plating layers and / or a plurality of tin (Sn) plating layers.

[0098] The plating layer can improve the mountability of the multilayer ceramic capacitor 100 to a substrate, structural reliability, durability against the outside, heat resistance, and equivalent series resistance (ESR).

[0099] A method for manufacturing the multilayer ceramic capacitor 100 according to an embodiment will now be described.

[0100] The multilayer ceramic capacitor 100 according to one embodiment is manufactured through the steps of: mixing raw materials including nickel (Ni) and cerium oxide (CeO2) to prepare a conductive paste; preparing a dielectric green sheet using a dielectric slurry and printing the conductive paste on a surface of the dielectric green sheet to form a conductive paste layer; laminating the dielectric green sheets on which the conductive paste layer is formed to prepare a dielectric green sheet laminate; sintering the dielectric green sheet laminate to prepare a capacitor body including a dielectric layer and an internal electrode layer; and forming an external electrode on one surface of the capacitor body.

[0101] Cerium oxide (CeO2) is mixed in an amount of 0.01 to 5 parts by weight, for example, 0.05 to 3 parts by weight, or 0.08 to 2.5 parts by weight, relative to 100 parts by weight of nickel (Ni). When cerium oxide (CeO2) is mixed within the above content range, it is possible to reduce sintering mismatch between the dielectric layer and the internal electrode layer by increasing the thermal stability of the internal electrode layer during high-temperature firing, and also, cerium (Ce) diffuses into the dielectric layer during firing to improve deterioration due to oxygen vacancies.

[0102] The raw material containing nickel (Ni) and cerium oxide (CeO2) may further contain a conductive metal such as copper (Cu), silver (Ag), palladium (Pd), gold (Au), an alloy thereof, or a combination thereof. The conductive metal is mixed in an amount of 0.01 to 5 parts by weight per 100 parts by weight of nickel (Ni).

[0103] The conductive paste can be prepared by mixing the raw materials with a conductive powder, a binder and a solvent.

[0104] The dielectric slurry can be produced by mixing a barium titanate-based main component powder with a selected auxiliary component powder. The auxiliary component powder may be used in the form of a sol dispersed in an organic solvent.

[0105] The auxiliary component powder may be an oxide of the metal that is the aforementioned auxiliary component. For reference, the cerium (Ce) contained in the dielectric layer 111 according to one embodiment is not obtained from the dielectric slurry, but is a component derived from cerium oxide (CeO2) added during the manufacture of the internal electrode layers 121 and 122, and is diffused into the dielectric layer 111 by firing.

[0106] The dielectric slurry may be prepared by additionally mixing additives such as a dispersant, a binder, a plasticizer, a lubricant, an antistatic agent, and a solvent.

[0107] The dispersant may include, for example, a phosphate-based dispersant, a polycarboxylic acid-based dispersant, or a combination thereof. The dispersant is mixed in an amount of 0.1 to 5 parts by weight, for example, 0.3 to 3 parts by weight, relative to 100 parts by weight of the total amount of the barium titanate and the gallium (Ga) complex compound. When the dispersant is mixed within the above content range, the dispersibility of the dielectric slurry is excellent, and the amount of impurities contained in the manufactured dielectric layer can be reduced.

[0108] The binder may be, for example, an acrylic resin, a polyvinyl butyl resin, a polyvinyl acetal resin, an ethyl cellulose resin, etc. The binder is added in an amount of 0.1 to 50 parts by weight, for example, 3 to 30 parts by weight, relative to 100 parts by weight of the total amount of the barium titanate and the gallium (Ga) complex compound. When the binder is mixed within the above content range, the dispersibility of the dielectric slurry is excellent, and the amount of impurities contained in the manufactured dielectric layer can be reduced.

[0109] The plasticizer may be, for example, a phthalic acid compound such as dioctyl phthalate, benzyl butyl phthalate, dibutyl phthalate, dihexyl phthalate, di(2-ethylhexyl) phthalate, or di(2-ethylbutyl) phthalate; an adipic acid compound such as dihexyl adipate or di(2-ethylhexyl) adipate; a glycol compound such as ethylene glycol, diethylene glycol, or triethylene glycol; or a glycol ester compound such as triethylene glycol dibutyrate, triethylene glycol di(2-ethylbutyrate), or triethylene glycol di(2-ethylhexanoate). The plasticizer is added in an amount of 0.1 to 20 parts by weight, for example, 1 to 10 parts by weight, relative to 100 parts by weight of the total amount of the barium titanate and the gallium (Ga) complex compound. When the plasticizer is mixed within the above content range, the dispersibility of the dielectric slurry is excellent, and the amount of impurities contained in the manufactured dielectric layer can be reduced.

[0110] The solvent may be an aqueous solvent such as water; an alcoholic solvent such as ethanol, methanol, benzyl alcohol, or methoxyethanol; a glycol solvent such as ethylene glycol or diethylene glycol; a ketone solvent such as acetone, methyl ethyl ketone, methyl isobutyl ketone, or cyclohexanone; an ester solvent such as butyl acetate, ethyl acetate, carbitol acetate, or butyl carbitol acetate; an ether solvent such as methyl cellosolve, ethyl cellosolve, butyl ether, or tetrahydrofuran; or an aromatic solvent such as benzene, toluene, or xylene. The solvent may be an alcoholic solvent or an aromatic solvent, for example, taking into consideration the solubility and dispersibility of various additives contained in the dielectric slurry. The solvent is mixed in an amount of 50 parts by weight to 1000 parts by weight, for example, 100 parts by weight to 500 parts by weight, relative to 100 parts by weight of the total amount of barium titanate and gallium (Ga) complex compound. When the solvent is mixed within the above content range, the dielectric slurry components are sufficiently mixed, and the solvent can be easily removed thereafter.

[0111] A wet ball mill or stirring mill can be used to mix the barium titanate-based main component and optional subcomponents. When using zirconia balls in a wet ball mill, wet mixing can be performed for 8 to 48 hours or 10 to 24 hours using multiple zirconia balls with diameters of 0.1 mm to 10 mm.

[0112] The prepared dielectric slurry is formed into a dielectric layer after sintering.

[0113] The produced dielectric slurry can be molded into a sheet shape using a tape molding method such as a doctor blade method or a calendar roll method, for example, a head-discharging on-roll molding coater, and then the molded body can be dried to obtain a dielectric green sheet.

[0114] The conductive paste thus prepared is applied in a predetermined pattern to the surface of the dielectric green sheet by various printing methods such as screen printing or transfer printing to form a conductive paste layer. The conductive paste layer thus prepared is formed into an internal electrode layer after sintering.

[0115] Next, the dielectric green sheets on which the internal electrode patterns are formed are laminated in a plurality of layers, and then pressed in the lamination direction to manufacture a dielectric green sheet laminate. At this time, the dielectric green sheets and the internal electrode patterns can be laminated so that the dielectric green sheets are located on the upper and lower surfaces of the dielectric green sheet laminate in the lamination direction.

[0116] The manufactured dielectric green sheet laminate may be selectively cut into a predetermined size by dicing or the like.

[0117] Furthermore, the dielectric green sheet laminate can be solidified and dried to remove plasticizers, etc., as necessary, and after solidification and drying, can be barrel polished using a horizontal centrifugal barrel machine, etc. In barrel polishing, the dielectric green sheet laminate is placed in a barrel container together with media and polishing liquid, and unnecessary parts such as burrs generated during cutting can be polished by applying rotational motion, vibration, etc. to the barrel container. Furthermore, after barrel polishing, the dielectric green sheet laminate can be washed with a cleaning liquid such as water and dried.

[0118] The dielectric greensheet stack can then be debindered and sintered to produce a capacitor body.

[0119] The binder removal treatment conditions can be appropriately adjusted depending on the components of the dielectric layers and the internal electrode layers. For example, the temperature rise rate during the binder removal treatment may be 5°C / hour to 300°C / hour, the support temperature may be 180°C to 400°C, and the temperature maintenance time may be 0.5 hours to 24 hours. The atmosphere during the binder removal treatment may be air or a reducing atmosphere.

[0120] The dielectric green sheet laminate is sintered at a temperature of 1000° C. to 1400° C., for example, at a temperature of 1100° C. to 1350° C. When the sintering is performed at a temperature within the above range, sintering mismatch between the dielectric layers and the internal electrode layers is reduced, thereby improving the connectivity of the internal electrodes.

[0121] The sintering is performed for 0.5 to 8 hours, for example, 1 to 3 hours. The sintering is performed in a reducing atmosphere, for example, an atmosphere of a humidified mixed gas of nitrogen and hydrogen. When the internal electrode contains nickel (Ni) or a nickel (Ni) alloy, the oxygen partial pressure in the sintering atmosphere is 1.0×10 -14 MPa~1.0×10 -10 It may be MPa.

[0122] After sintering, annealing can be carried out as necessary. Annealing is a process for reoxidizing the dielectric layer, and can be carried out when sintering is carried out in a reducing atmosphere. The conditions of the annealing process can also be appropriately adjusted depending on the components of the dielectric layer. For example, the annealing temperature may be 950°C to 1150°C, the annealing time may be 0 hours to 20 hours, and the heating rate may be 50°C / hour to 500°C / hour. The annealing atmosphere may be a humidified nitrogen gas (N2) atmosphere, and the oxygen partial pressure may be 1.0×10 -9 MPa~1.0×10 -5 It may be MPa.

[0123] In the binder removal treatment, sintering treatment, or annealing treatment, for example, a wetter can be used to moisten the nitrogen gas or mixed gas, and in this case, the water temperature may be 5° C. to 75° C. The binder removal treatment, sintering treatment, and annealing treatment may be performed consecutively or independently.

[0124] Optionally, surface treatment such as sandblasting, laser irradiation, barrel polishing, etc. may be performed on the third and fourth faces of the manufactured capacitor body 110. By performing such surface treatment, the ends of the first and second internal electrodes are exposed on the outermost surfaces of the third and fourth faces, which improves the electrical connection between the first and second external electrodes and the first and second internal electrodes, making it easier to form an alloy part.

[0125] Next, an external electrode is formed on one surface of the manufactured capacitor body 110 .

[0126] As an example, a paste for forming a sintered metal layer can be applied to the external electrodes and then sintered to form a sintered metal layer.

[0127] The paste for forming the sintered metal layer may include a conductive metal and glass. The conductive metal and glass have been described above, and therefore will not be described again. The paste for forming the sintered metal layer may selectively include a binder, a solvent, a dispersant, a plasticizer, an oxide powder, and the like. The binder may be, for example, ethyl cellulose, acrylic, butyral, and the solvent may be, for example, an organic solvent or an aqueous solvent such as terpineol, butyl carbitol, alcohol, methyl ethyl ketone, acetone, or toluene.

[0128] The method of applying the sintered metal layer forming paste to the outer surface of the capacitor body 110 can be a dipping method, various printing methods such as screen printing, an application method using a dispenser, a spraying method using a spray, etc. The sintered metal layer forming paste is applied to at least the third and fourth surfaces of the capacitor body 110, and is selectively applied to parts of the first, second, fifth, or sixth surfaces on which the band portions of the first and second external electrodes are formed.

[0129] Thereafter, the capacitor body 110 on which the paste for forming a sintered metal layer is applied is dried and sintered at a temperature of 700° C. to 1000° C. for 0.1 to 3 hours to form a sintered metal layer.

[0130] Alternatively, a conductive resin layer forming paste may be applied to the outer surface of the obtained capacitor body 110 and then cured to form a conductive resin layer.

[0131] The paste for forming the conductive resin layer may include a resin, and optionally a conductive metal or a non-conductive filler. The conductive metal and the resin have been described above, and therefore will not be described again. The paste for forming the conductive resin layer may optionally include a binder, a solvent, a dispersant, a plasticizer, an oxide powder, and the like. Examples of the binder include ethyl cellulose, acrylic, butyral, and the like, and examples of the solvent include organic solvents or aqueous solvents such as terpineol, butyl carbitol, alcohol, methyl ethyl ketone, acetone, and toluene.

[0132] As an example, the conductive resin layer may be formed by dipping the capacitor body 110 in a paste for forming the conductive resin layer and then curing it, or by printing the paste for forming the conductive resin layer on the surface of the capacitor body 110 using a screen printing method or a gravure printing method, or by applying the paste for forming the conductive resin layer on the surface of the capacitor body 110 and then curing it.

[0133] Next, a plating layer is formed on the outside of the conductive resin layer.

[0134] As an example, the plating layer is formed by a plating method, and may be formed by sputtering or electric deposition.

[0135] The above-mentioned embodiments will be described in more detail with reference to the following examples, which are merely for illustrative purposes and are not intended to limit the scope of the invention.

[0136] (Manufacturing of multilayer ceramic capacitors) Example 1 A conductive paste was prepared by mixing raw materials containing nickel (Ni) and cerium oxide (CeO2). At this time, 0.1 parts by weight of CeO2 was mixed with 100 parts by weight of Ni.

[0137] Next, barium titanate (BaTiO3) powder was mixed to prepare a dielectric slurry. At this time, the mixture was mechanically milled after adding ethanol / toluene, a dispersant, and a binder to a zirconium ball (ZrO2 ball) as a dispersion medium.

[0138] Next, the prepared dielectric slurry was applied to a head-discharging on-roll forming coater to prepare a dielectric green sheet. The prepared conductive paste was printed on the surface of the dielectric green sheet to form a conductive paste layer. The dielectric green sheets (width x length x height = 3.2 mm x 2.5 mm x 2.5 mm) on which the conductive paste layer was formed were stacked and pressed to prepare a dielectric green sheet laminate. The dielectric green sheet laminate was subjected to a plasticization process in a nitrogen atmosphere at 400°C or less, and sintered under conditions of a sintering temperature of 1300°C and a hydrogen concentration of 1.0% H2 or less.

[0139] Next, a multilayer ceramic capacitor was manufactured through processes such as forming external electrodes and plating.

[0140] Example 2 A multilayer ceramic capacitor was manufactured in the same manner as in Example 1, except that 0.2 parts by weight of CeO2 was mixed with 100 parts by weight of Ni to manufacture a conductive paste.

[0141] Example 3 A multilayer ceramic capacitor was manufactured in the same manner as in Example 1, except that 0.3 parts by weight of CeO2 was mixed with 100 parts by weight of Ni to manufacture a conductive paste.

[0142] Example 4 A multilayer ceramic capacitor was manufactured in the same manner as in Example 1, except that 0.4 parts by weight of CeO2 was mixed with 100 parts by weight of Ni to manufacture a conductive paste.

[0143] Example 5 A multilayer ceramic capacitor was manufactured in the same manner as in Example 1, except that 0.6 parts by weight of CeO2 was mixed with 100 parts by weight of Ni to manufacture a conductive paste.

[0144] Example 6 A multilayer ceramic capacitor was manufactured in the same manner as in Example 1, except that 1.0 part by weight of CeO2 was mixed with 100 parts by weight of Ni to manufacture a conductive paste.

[0145] Example 7 A multilayer ceramic capacitor was manufactured in the same manner as in Example 4, except that sintering was performed at 1320°C.

[0146] Comparative Example 1 A multilayer ceramic capacitor was manufactured in the same manner as in Example 1, except that the conductive paste was manufactured without using CeO2.

[0147] Evaluation 1: SEM-EDS analysis of multilayer ceramic capacitors The multilayer ceramic capacitor manufactured in Example 1 was subjected to SEM-EDS (scanning electron microscope-energy dispersive spectroscopy) analysis, and the results are shown in FIG.

[0148] The SEM-EDS analysis was performed as follows. The multilayer ceramic capacitor manufactured in Example 1 was placed in an epoxy mixture and cured, and then the W-axis and T-axis faces (WT faces) of the capacitor body were polished to 1 / 2 points in the L-axis direction, and then fixed and maintained in a vacuum atmosphere chamber to obtain a cross-sectional sample so that the active area where the dielectric layer and the internal electrode layer intersect can be observed. The center part (area C in FIG. 3) of the active area of ​​the cross-sectional sample was measured by SEM. The SEM used was a Verios G4 product from Thermofisher Scientific, and the measurement conditions were 10 kV, 0.2 nA, and the analysis magnification was 50 k times, and the measurement was performed so that at least five dielectric layers and internal electrode layers were exposed. The content and composition of cerium (Ce) were confirmed by Point-EDS analysis in the SEM image of the measured cross-sectional sample. In the Point-EDS analysis, five points were designated at intervals of 500 nm in each of the central region A and interface region B of the internal electrode layer, and the interface region B' of the dielectric layer, and the cerium (Ce) content at each point was measured and the arithmetic average value was calculated.

[0149] FIG. 6 shows SEM-EDS analysis images of the active area of ​​the multilayer ceramic capacitor according to Example 1, where (b) shows an enlarged view of the area shown in (a).

[0150] Referring to FIG. 6, in the case of Example 1, it can be seen that cerium (Ce) is present in the internal electrode layer. Specifically, it can be seen that cerium (Ce) is present in all of the central region and interface region in the internal electrode layer, and is contained at a higher content in the interface region than in the central region. It can also be seen that cerium (Ce) is present in the dielectric layer, specifically, in the interface region of the dielectric layer. Here, when the internal electrode layer is divided into three equal parts in the thickness direction into an upper part, a middle part, and a lower part, the middle part is defined as the central region, and at least one of the upper part and the lower part having an interface with the dielectric layer is defined as the interface region. Also, when the dielectric layer is divided into three equal parts in the thickness direction into an upper part, a middle part, and a lower part, the middle part is defined as the central region, and at least one of the upper part and the lower part having an interface with the internal electrode layer is defined as the interface region.

[0151] Evaluation 2: TMA analysis of internal electrode layer materials In order to confirm the thermal stability of the internal electrode layers of the multilayer ceramic capacitors manufactured in Example 6 and Comparative Example 1, thermomechanical analysis (TMA) was performed on the internal electrode layer materials, and the results are shown in FIG. 7 and Table 1 below.

[0152] The TMA measurement was performed as follows. The thermal shrinkage behavior during heating was measured using a TMA device (i-tube's TMA 450 EM / RH) for pellet-shaped samples made by pressing the mixed powder of the materials for forming the internal electrode layers according to Example 6 and Comparative Example 1. The measurement conditions were H2 gas 3% and a heating rate of 10K / min.

[0153] FIG. 7 is a thermomechanical analysis (TMA) graph for the internal electrode layer materials according to Example 6 and Comparative Example 1.

[0154] [Table 1]

[0155] 7 and Table 1 below, comparing the temperatures at which the internal electrode layer materials shrink by 5%, Comparative Example 1 using only Ni is 452°C, whereas Example 6 containing Ni and Ce is 515°C, confirming that a shrinkage delay of about 63°C occurs. This shows that the internal electrode layer containing Ni and Ce according to one embodiment has a thermal shrinkage delay effect.

[0156] Evaluation 3: SEM analysis of dielectric layers The dielectric layers of the multilayer ceramic capacitors manufactured in Examples 1, 2, 4, 5 and 7 were subjected to SEM (scanning electron microscope) analysis, and the results are shown in FIGS. 8A to 8E.

[0157] The SEM analysis was performed as follows. The multilayer ceramic capacitors manufactured in Examples 1, 2, 4, 5, and 7 were placed in an epoxy mixture and cured, and then the W-axis and T-axis faces (WT faces) of the capacitor body were polished to 1 / 2 points in the L-axis direction, and then fixed and maintained in a vacuum atmosphere chamber to obtain a cross-sectional sample so that the active area where the dielectric layer and the internal electrode layer intersect can be observed. SEM analysis was performed on the interface area of ​​the dielectric layer in the center of the active area of ​​the cross-sectional sample. At this time, when the dielectric layer is divided into three equal parts in the thickness direction into an upper part, a middle part, and a lower part, at least one of the upper part and the lower part having an interface with the internal electrode layer corresponds to the interface area. The SEM used was a Verios G4 product from Thermofisher Scientific, and the measurement conditions were 10 kV, 0.2 nA, and the analysis magnification was 50 k times.

[0158] 8A to 8E are scanning electron microscope (SEM) analysis images of the interfacial regions of the dielectric layers according to Examples 1, 2, 4, 5 and 7, respectively.

[0159] 8A to 8E, in the case of Examples 1, 2, 4, 5, and 7 according to an embodiment, cerium (Ce) is added to the internal electrode layer, and the cerium (Ce) diffuses into the dielectric layer during firing, increasing the size of the dielectric crystal grains present in the interface region between the internal electrode layer and the dielectric layer, thereby improving the dielectric constant and reliability.

[0160] Evaluation 4: Reliability of multilayer ceramic capacitors The multilayer ceramic capacitors manufactured in Examples 1 to 5 and Comparative Example 1 were measured for reliability in the following items, and the results are shown in Table 2 and FIG.

[0161] Each value shown in Table 2 below corresponds to a respective ratio based on the result value of Comparative Example 1.

[0162] (1) Connectivity of internal electrodes: After obtaining a cross-sectional sample in the same manner as in Evaluation 3, the central part of the active region of the cross-sectional sample was measured by SEM. The SEM used was a Verios G4 product from Thermofisher Scientific, the measurement conditions were 10 kV, 0.2 nA, the analysis magnification was 10k times, and the measurement was performed so that approximately 30 internal electrode layers were obtained per photograph. After obtaining a total of three photographic images, the average value of the connectivity of each internal electrode was calculated. The connectivity of each internal electrode was calculated by the following Equation 1.

[0163] [Formula 1] Connectivity of internal electrodes (%) = (total length of connected parts excluding discontinuous parts in multiple internal electrode layers / total length of multiple internal electrode layers) x 100

[0164] (2) Dielectric constant of dielectric: The capacitance of a sample chip, the thickness of the dielectric, and the effective surface area of ​​the internal electrode layer were measured and calculated from these.

[0165] Fig. 9 is a graph showing the dielectric constant of the dielectrics according to Examples 1, 2, 4, and 5. Referring to Fig. 9, it can be seen that the dielectric constant of the dielectrics is improved in Examples 1, 2, 4, and 5 according to an embodiment.

[0166] (3) Capacitance: The capacitance (F) was measured at a frequency of 1 kHz and a voltage of 0.5 V.

[0167] (4) BDV (break down voltage): Each sample chip was connected to a circuit, and the maximum voltage (V) at which the chip was broken was measured by increasing the voltage stepwise at a rate of 20 V / s.

[0168] (5) MTTF (mean time to failure): The mean time to failure (hr) was calculated for each sample chip under conditions of a temperature of 125° C., a voltage of 9.45 V, and a time of 48 hours.

[0169] [Table 2]

[0170] Referring to Table 2, in the case of Examples 1 to 5 in which cerium (Ce) is included in the internal electrode layer, specifically, in which cerium (Ce) is included at a higher content in the interface region than in the central region in the internal electrode layer, the internal electrodes have excellent connectivity, and are excellent in dielectric constant, capacity, and voltage resistance characteristics, and thus have improved reliability, compared to Comparative Example 1 in which cerium (Ce) is not included.

[0171] Although the preferred embodiment of the present invention has been described above, the present invention is not limited thereto, and various modifications can be made within the scope of the claims, the description of the invention, and the accompanying drawings, which of course also fall within the scope of the present invention. [Explanation of symbols]

[0172] 100: Multilayer ceramic capacitor 110: Capacitor body 111: Dielectric layer 121: 1st internal electrode 122:Second internal electrode 131: 1st external electrode 132:Second external electrode

Claims

1. a capacitor body including a dielectric layer and an internal electrode layer; an external electrode disposed on an outer side of the capacitor body; The internal electrode layers include nickel (Ni) and cerium (Ce), When the internal electrode layer is divided into three equal parts in the thickness direction into an upper part, a middle part and a lower part, the middle part is defined as a central region, and at least one of the upper part and the lower part having an interface with the dielectric layer is defined as an interface region, the cerium (Ce) is contained in the central region and the interface region, The cerium (Ce) is contained in a higher content in the interface region than in the central region.

2. 2. The multilayer ceramic capacitor according to claim 1, wherein the cerium (Ce) is contained in the interface region at a content 1.5 to 3 times higher than that in the central region.

3. 2. The multilayer ceramic capacitor according to claim 1, wherein the cerium (Ce) is contained in the internal electrode layer in an amount of 0.01 to 5 parts by weight relative to 100 parts by weight of the nickel (Ni).

4. The multilayer ceramic capacitor according to claim 1 , wherein the internal electrode layers further include copper (Cu), silver (Ag), palladium (Pd), gold (Au), an alloy thereof, or a combination thereof.

5. 2. The multilayer ceramic capacitor according to claim 1, wherein the dielectric layers contain a barium titanate-based main component containing barium (Ba) and titanium (Ti), and cerium (Ce).

6. 6. The multilayer ceramic capacitor according to claim 5, wherein when the dielectric layer is divided into three equal parts in a thickness direction into an upper part, a middle part and a lower part, the middle part is defined as a central region, and at least one of the upper part and the lower part having an interface with the internal electrode layer is defined as an interface region, the cerium (Ce) is contained in the interface region of the dielectric layer.

7. 7. The multilayer ceramic capacitor according to claim 6, wherein the cerium (Ce) is contained in an amount of 0.05 to 1 part by mol relative to 100 parts by mol of the barium (Ba) in the interface region of the dielectric layer.

8. The cerium (Ce) is contained in an interfacial region of the dielectric layer in an amount of 0.05 mol part to 1 mol part relative to 100 mol parts of the barium (Ba) in a region from an interface with the internal electrode layer to a depth of 10 nm to 100 nm. The multilayer ceramic capacitor according to claim 7.

9. the interface region of the dielectric layer includes a plurality of dielectric crystal grains; At least one of the dielectric crystal grains has a structure including a core and a shell surrounding the core, The multilayer ceramic capacitor according to claim 6 , wherein the shell contains the cerium (Ce).

10. 10. The multilayer ceramic capacitor according to claim 9, wherein the size (D50) of the dielectric crystal grains is 50 nm to 250 nm.

11. The cerium (Ce) contained in the dielectric layer is cerium oxide (CeO ２ 6. The multilayer ceramic capacitor according to claim 5, wherein the dielectric layer is a component that is derived from the dielectric layer and diffuses from the dielectric layer after sintering.

12. Nickel (Ni) and cerium oxide (CeO ２ ) to prepare a conductive paste; preparing a dielectric green sheet using the dielectric slurry, and printing the conductive paste on a surface of the dielectric green sheet to form a conductive paste layer; laminating the dielectric green sheets on which the conductive paste layers are formed to manufacture a dielectric green sheet laminate; sintering the dielectric green sheet laminate to manufacture a capacitor body including dielectric layers and internal electrode layers; forming an external electrode on one surface of the capacitor body; The internal electrode layers include nickel (Ni) and cerium (Ce), A method for manufacturing a multilayer ceramic capacitor, wherein when the internal electrode layer is divided into three equal parts in a thickness direction into an upper part, a middle part and a lower part, the middle part is defined as a central region, and at least one of the upper part and the lower part having an interface with the dielectric layer is defined as an interface region, the cerium (Ce) is contained in the central region and the interface region, and the cerium (Ce) is contained in a higher content in the interface region than in the central region.

13. The cerium oxide (CeO ２ 13. The method for manufacturing a multilayer ceramic capacitor according to claim 12, wherein the amount of the nickel (Ni) is 0.01 to 5 parts by weight based on 100 parts by weight of the nickel (Ni).

14. The method for producing a multilayer ceramic capacitor according to claim 12, wherein the raw material further includes copper (Cu), silver (Ag), palladium (Pd), gold (Au), an alloy thereof, or a combination thereof.

15. The method for manufacturing a multilayer ceramic capacitor according to claim 12, wherein the dielectric slurry is manufactured by mixing a barium titanate-based main component powder and, optionally, a subcomponent powder.

16. The method for producing a multilayer ceramic capacitor according to claim 12, wherein the sintering is performed at a temperature of 1000°C to 1400°C.

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